fsl_soc.c 18 KB

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  1. /*
  2. * FSL SoC setup code
  3. *
  4. * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5. *
  6. * 2006 (c) MontaVista Software, Inc.
  7. * Vitaly Bordug <vbordug@ru.mvista.com>
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. */
  14. #include <linux/stddef.h>
  15. #include <linux/kernel.h>
  16. #include <linux/init.h>
  17. #include <linux/errno.h>
  18. #include <linux/major.h>
  19. #include <linux/delay.h>
  20. #include <linux/irq.h>
  21. #include <linux/module.h>
  22. #include <linux/device.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/phy.h>
  26. #include <linux/phy_fixed.h>
  27. #include <linux/spi/spi.h>
  28. #include <linux/fsl_devices.h>
  29. #include <linux/fs_enet_pd.h>
  30. #include <linux/fs_uart_pd.h>
  31. #include <asm/system.h>
  32. #include <asm/atomic.h>
  33. #include <asm/io.h>
  34. #include <asm/irq.h>
  35. #include <asm/time.h>
  36. #include <asm/prom.h>
  37. #include <sysdev/fsl_soc.h>
  38. #include <mm/mmu_decl.h>
  39. #include <asm/cpm2.h>
  40. extern void init_fcc_ioports(struct fs_platform_info*);
  41. extern void init_fec_ioports(struct fs_platform_info*);
  42. extern void init_smc_ioports(struct fs_uart_platform_info*);
  43. static phys_addr_t immrbase = -1;
  44. phys_addr_t get_immrbase(void)
  45. {
  46. struct device_node *soc;
  47. if (immrbase != -1)
  48. return immrbase;
  49. soc = of_find_node_by_type(NULL, "soc");
  50. if (soc) {
  51. int size;
  52. u32 naddr;
  53. const u32 *prop = of_get_property(soc, "#address-cells", &size);
  54. if (prop && size == 4)
  55. naddr = *prop;
  56. else
  57. naddr = 2;
  58. prop = of_get_property(soc, "ranges", &size);
  59. if (prop)
  60. immrbase = of_translate_address(soc, prop + naddr);
  61. of_node_put(soc);
  62. }
  63. return immrbase;
  64. }
  65. EXPORT_SYMBOL(get_immrbase);
  66. static u32 sysfreq = -1;
  67. u32 fsl_get_sys_freq(void)
  68. {
  69. struct device_node *soc;
  70. const u32 *prop;
  71. int size;
  72. if (sysfreq != -1)
  73. return sysfreq;
  74. soc = of_find_node_by_type(NULL, "soc");
  75. if (!soc)
  76. return -1;
  77. prop = of_get_property(soc, "clock-frequency", &size);
  78. if (!prop || size != sizeof(*prop) || *prop == 0)
  79. prop = of_get_property(soc, "bus-frequency", &size);
  80. if (prop && size == sizeof(*prop))
  81. sysfreq = *prop;
  82. of_node_put(soc);
  83. return sysfreq;
  84. }
  85. EXPORT_SYMBOL(fsl_get_sys_freq);
  86. #if defined(CONFIG_CPM2) || defined(CONFIG_QUICC_ENGINE) || defined(CONFIG_8xx)
  87. static u32 brgfreq = -1;
  88. u32 get_brgfreq(void)
  89. {
  90. struct device_node *node;
  91. const unsigned int *prop;
  92. int size;
  93. if (brgfreq != -1)
  94. return brgfreq;
  95. node = of_find_compatible_node(NULL, NULL, "fsl,cpm-brg");
  96. if (node) {
  97. prop = of_get_property(node, "clock-frequency", &size);
  98. if (prop && size == 4)
  99. brgfreq = *prop;
  100. of_node_put(node);
  101. return brgfreq;
  102. }
  103. /* Legacy device binding -- will go away when no users are left. */
  104. node = of_find_node_by_type(NULL, "cpm");
  105. if (!node)
  106. node = of_find_compatible_node(NULL, NULL, "fsl,qe");
  107. if (!node)
  108. node = of_find_node_by_type(NULL, "qe");
  109. if (node) {
  110. prop = of_get_property(node, "brg-frequency", &size);
  111. if (prop && size == 4)
  112. brgfreq = *prop;
  113. if (brgfreq == -1 || brgfreq == 0) {
  114. prop = of_get_property(node, "bus-frequency", &size);
  115. if (prop && size == 4)
  116. brgfreq = *prop / 2;
  117. }
  118. of_node_put(node);
  119. }
  120. return brgfreq;
  121. }
  122. EXPORT_SYMBOL(get_brgfreq);
  123. static u32 fs_baudrate = -1;
  124. u32 get_baudrate(void)
  125. {
  126. struct device_node *node;
  127. if (fs_baudrate != -1)
  128. return fs_baudrate;
  129. node = of_find_node_by_type(NULL, "serial");
  130. if (node) {
  131. int size;
  132. const unsigned int *prop = of_get_property(node,
  133. "current-speed", &size);
  134. if (prop)
  135. fs_baudrate = *prop;
  136. of_node_put(node);
  137. }
  138. return fs_baudrate;
  139. }
  140. EXPORT_SYMBOL(get_baudrate);
  141. #endif /* CONFIG_CPM2 */
  142. #ifdef CONFIG_FIXED_PHY
  143. static int __init of_add_fixed_phys(void)
  144. {
  145. int ret;
  146. struct device_node *np;
  147. u32 *fixed_link;
  148. struct fixed_phy_status status = {};
  149. for_each_node_by_name(np, "ethernet") {
  150. fixed_link = (u32 *)of_get_property(np, "fixed-link", NULL);
  151. if (!fixed_link)
  152. continue;
  153. status.link = 1;
  154. status.duplex = fixed_link[1];
  155. status.speed = fixed_link[2];
  156. status.pause = fixed_link[3];
  157. status.asym_pause = fixed_link[4];
  158. ret = fixed_phy_add(PHY_POLL, fixed_link[0], &status);
  159. if (ret) {
  160. of_node_put(np);
  161. return ret;
  162. }
  163. }
  164. return 0;
  165. }
  166. arch_initcall(of_add_fixed_phys);
  167. #endif /* CONFIG_FIXED_PHY */
  168. static int __init gfar_mdio_of_init(void)
  169. {
  170. struct device_node *np = NULL;
  171. struct platform_device *mdio_dev;
  172. struct resource res;
  173. int ret;
  174. np = of_find_compatible_node(np, NULL, "fsl,gianfar-mdio");
  175. /* try the deprecated version */
  176. if (!np)
  177. np = of_find_compatible_node(np, "mdio", "gianfar");
  178. if (np) {
  179. int k;
  180. struct device_node *child = NULL;
  181. struct gianfar_mdio_data mdio_data;
  182. memset(&res, 0, sizeof(res));
  183. memset(&mdio_data, 0, sizeof(mdio_data));
  184. ret = of_address_to_resource(np, 0, &res);
  185. if (ret)
  186. goto err;
  187. mdio_dev =
  188. platform_device_register_simple("fsl-gianfar_mdio",
  189. res.start, &res, 1);
  190. if (IS_ERR(mdio_dev)) {
  191. ret = PTR_ERR(mdio_dev);
  192. goto err;
  193. }
  194. for (k = 0; k < 32; k++)
  195. mdio_data.irq[k] = PHY_POLL;
  196. while ((child = of_get_next_child(np, child)) != NULL) {
  197. int irq = irq_of_parse_and_map(child, 0);
  198. if (irq != NO_IRQ) {
  199. const u32 *id = of_get_property(child,
  200. "reg", NULL);
  201. mdio_data.irq[*id] = irq;
  202. }
  203. }
  204. ret =
  205. platform_device_add_data(mdio_dev, &mdio_data,
  206. sizeof(struct gianfar_mdio_data));
  207. if (ret)
  208. goto unreg;
  209. }
  210. of_node_put(np);
  211. return 0;
  212. unreg:
  213. platform_device_unregister(mdio_dev);
  214. err:
  215. of_node_put(np);
  216. return ret;
  217. }
  218. arch_initcall(gfar_mdio_of_init);
  219. static const char *gfar_tx_intr = "tx";
  220. static const char *gfar_rx_intr = "rx";
  221. static const char *gfar_err_intr = "error";
  222. static int __init gfar_of_init(void)
  223. {
  224. struct device_node *np;
  225. unsigned int i;
  226. struct platform_device *gfar_dev;
  227. struct resource res;
  228. int ret;
  229. for (np = NULL, i = 0;
  230. (np = of_find_compatible_node(np, "network", "gianfar")) != NULL;
  231. i++) {
  232. struct resource r[4];
  233. struct device_node *phy, *mdio;
  234. struct gianfar_platform_data gfar_data;
  235. const unsigned int *id;
  236. const char *model;
  237. const char *ctype;
  238. const void *mac_addr;
  239. const phandle *ph;
  240. int n_res = 2;
  241. memset(r, 0, sizeof(r));
  242. memset(&gfar_data, 0, sizeof(gfar_data));
  243. ret = of_address_to_resource(np, 0, &r[0]);
  244. if (ret)
  245. goto err;
  246. of_irq_to_resource(np, 0, &r[1]);
  247. model = of_get_property(np, "model", NULL);
  248. /* If we aren't the FEC we have multiple interrupts */
  249. if (model && strcasecmp(model, "FEC")) {
  250. r[1].name = gfar_tx_intr;
  251. r[2].name = gfar_rx_intr;
  252. of_irq_to_resource(np, 1, &r[2]);
  253. r[3].name = gfar_err_intr;
  254. of_irq_to_resource(np, 2, &r[3]);
  255. n_res += 2;
  256. }
  257. gfar_dev =
  258. platform_device_register_simple("fsl-gianfar", i, &r[0],
  259. n_res);
  260. if (IS_ERR(gfar_dev)) {
  261. ret = PTR_ERR(gfar_dev);
  262. goto err;
  263. }
  264. mac_addr = of_get_mac_address(np);
  265. if (mac_addr)
  266. memcpy(gfar_data.mac_addr, mac_addr, 6);
  267. if (model && !strcasecmp(model, "TSEC"))
  268. gfar_data.device_flags =
  269. FSL_GIANFAR_DEV_HAS_GIGABIT |
  270. FSL_GIANFAR_DEV_HAS_COALESCE |
  271. FSL_GIANFAR_DEV_HAS_RMON |
  272. FSL_GIANFAR_DEV_HAS_MULTI_INTR;
  273. if (model && !strcasecmp(model, "eTSEC"))
  274. gfar_data.device_flags =
  275. FSL_GIANFAR_DEV_HAS_GIGABIT |
  276. FSL_GIANFAR_DEV_HAS_COALESCE |
  277. FSL_GIANFAR_DEV_HAS_RMON |
  278. FSL_GIANFAR_DEV_HAS_MULTI_INTR |
  279. FSL_GIANFAR_DEV_HAS_CSUM |
  280. FSL_GIANFAR_DEV_HAS_VLAN |
  281. FSL_GIANFAR_DEV_HAS_EXTENDED_HASH;
  282. ctype = of_get_property(np, "phy-connection-type", NULL);
  283. /* We only care about rgmii-id. The rest are autodetected */
  284. if (ctype && !strcmp(ctype, "rgmii-id"))
  285. gfar_data.interface = PHY_INTERFACE_MODE_RGMII_ID;
  286. else
  287. gfar_data.interface = PHY_INTERFACE_MODE_MII;
  288. ph = of_get_property(np, "phy-handle", NULL);
  289. if (ph == NULL) {
  290. u32 *fixed_link;
  291. fixed_link = (u32 *)of_get_property(np, "fixed-link",
  292. NULL);
  293. if (!fixed_link) {
  294. ret = -ENODEV;
  295. goto unreg;
  296. }
  297. snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "0");
  298. gfar_data.phy_id = fixed_link[0];
  299. } else {
  300. phy = of_find_node_by_phandle(*ph);
  301. if (phy == NULL) {
  302. ret = -ENODEV;
  303. goto unreg;
  304. }
  305. mdio = of_get_parent(phy);
  306. id = of_get_property(phy, "reg", NULL);
  307. ret = of_address_to_resource(mdio, 0, &res);
  308. if (ret) {
  309. of_node_put(phy);
  310. of_node_put(mdio);
  311. goto unreg;
  312. }
  313. gfar_data.phy_id = *id;
  314. snprintf(gfar_data.bus_id, MII_BUS_ID_SIZE, "%llx",
  315. (unsigned long long)res.start);
  316. of_node_put(phy);
  317. of_node_put(mdio);
  318. }
  319. ret =
  320. platform_device_add_data(gfar_dev, &gfar_data,
  321. sizeof(struct
  322. gianfar_platform_data));
  323. if (ret)
  324. goto unreg;
  325. }
  326. return 0;
  327. unreg:
  328. platform_device_unregister(gfar_dev);
  329. err:
  330. return ret;
  331. }
  332. arch_initcall(gfar_of_init);
  333. #ifdef CONFIG_PPC_83xx
  334. static int __init mpc83xx_wdt_init(void)
  335. {
  336. struct resource r;
  337. struct device_node *np;
  338. struct platform_device *dev;
  339. u32 freq = fsl_get_sys_freq();
  340. int ret;
  341. np = of_find_compatible_node(NULL, "watchdog", "mpc83xx_wdt");
  342. if (!np) {
  343. ret = -ENODEV;
  344. goto nodev;
  345. }
  346. memset(&r, 0, sizeof(r));
  347. ret = of_address_to_resource(np, 0, &r);
  348. if (ret)
  349. goto err;
  350. dev = platform_device_register_simple("mpc83xx_wdt", 0, &r, 1);
  351. if (IS_ERR(dev)) {
  352. ret = PTR_ERR(dev);
  353. goto err;
  354. }
  355. ret = platform_device_add_data(dev, &freq, sizeof(freq));
  356. if (ret)
  357. goto unreg;
  358. of_node_put(np);
  359. return 0;
  360. unreg:
  361. platform_device_unregister(dev);
  362. err:
  363. of_node_put(np);
  364. nodev:
  365. return ret;
  366. }
  367. arch_initcall(mpc83xx_wdt_init);
  368. #endif
  369. static enum fsl_usb2_phy_modes determine_usb_phy(const char *phy_type)
  370. {
  371. if (!phy_type)
  372. return FSL_USB2_PHY_NONE;
  373. if (!strcasecmp(phy_type, "ulpi"))
  374. return FSL_USB2_PHY_ULPI;
  375. if (!strcasecmp(phy_type, "utmi"))
  376. return FSL_USB2_PHY_UTMI;
  377. if (!strcasecmp(phy_type, "utmi_wide"))
  378. return FSL_USB2_PHY_UTMI_WIDE;
  379. if (!strcasecmp(phy_type, "serial"))
  380. return FSL_USB2_PHY_SERIAL;
  381. return FSL_USB2_PHY_NONE;
  382. }
  383. static int __init fsl_usb_of_init(void)
  384. {
  385. struct device_node *np;
  386. unsigned int i = 0;
  387. struct platform_device *usb_dev_mph = NULL, *usb_dev_dr_host = NULL,
  388. *usb_dev_dr_client = NULL;
  389. int ret;
  390. for_each_compatible_node(np, NULL, "fsl-usb2-mph") {
  391. struct resource r[2];
  392. struct fsl_usb2_platform_data usb_data;
  393. const unsigned char *prop = NULL;
  394. memset(&r, 0, sizeof(r));
  395. memset(&usb_data, 0, sizeof(usb_data));
  396. ret = of_address_to_resource(np, 0, &r[0]);
  397. if (ret)
  398. goto err;
  399. of_irq_to_resource(np, 0, &r[1]);
  400. usb_dev_mph =
  401. platform_device_register_simple("fsl-ehci", i, r, 2);
  402. if (IS_ERR(usb_dev_mph)) {
  403. ret = PTR_ERR(usb_dev_mph);
  404. goto err;
  405. }
  406. usb_dev_mph->dev.coherent_dma_mask = 0xffffffffUL;
  407. usb_dev_mph->dev.dma_mask = &usb_dev_mph->dev.coherent_dma_mask;
  408. usb_data.operating_mode = FSL_USB2_MPH_HOST;
  409. prop = of_get_property(np, "port0", NULL);
  410. if (prop)
  411. usb_data.port_enables |= FSL_USB2_PORT0_ENABLED;
  412. prop = of_get_property(np, "port1", NULL);
  413. if (prop)
  414. usb_data.port_enables |= FSL_USB2_PORT1_ENABLED;
  415. prop = of_get_property(np, "phy_type", NULL);
  416. usb_data.phy_mode = determine_usb_phy(prop);
  417. ret =
  418. platform_device_add_data(usb_dev_mph, &usb_data,
  419. sizeof(struct
  420. fsl_usb2_platform_data));
  421. if (ret)
  422. goto unreg_mph;
  423. i++;
  424. }
  425. for_each_compatible_node(np, NULL, "fsl-usb2-dr") {
  426. struct resource r[2];
  427. struct fsl_usb2_platform_data usb_data;
  428. const unsigned char *prop = NULL;
  429. memset(&r, 0, sizeof(r));
  430. memset(&usb_data, 0, sizeof(usb_data));
  431. ret = of_address_to_resource(np, 0, &r[0]);
  432. if (ret)
  433. goto unreg_mph;
  434. of_irq_to_resource(np, 0, &r[1]);
  435. prop = of_get_property(np, "dr_mode", NULL);
  436. if (!prop || !strcmp(prop, "host")) {
  437. usb_data.operating_mode = FSL_USB2_DR_HOST;
  438. usb_dev_dr_host = platform_device_register_simple(
  439. "fsl-ehci", i, r, 2);
  440. if (IS_ERR(usb_dev_dr_host)) {
  441. ret = PTR_ERR(usb_dev_dr_host);
  442. goto err;
  443. }
  444. } else if (prop && !strcmp(prop, "peripheral")) {
  445. usb_data.operating_mode = FSL_USB2_DR_DEVICE;
  446. usb_dev_dr_client = platform_device_register_simple(
  447. "fsl-usb2-udc", i, r, 2);
  448. if (IS_ERR(usb_dev_dr_client)) {
  449. ret = PTR_ERR(usb_dev_dr_client);
  450. goto err;
  451. }
  452. } else if (prop && !strcmp(prop, "otg")) {
  453. usb_data.operating_mode = FSL_USB2_DR_OTG;
  454. usb_dev_dr_host = platform_device_register_simple(
  455. "fsl-ehci", i, r, 2);
  456. if (IS_ERR(usb_dev_dr_host)) {
  457. ret = PTR_ERR(usb_dev_dr_host);
  458. goto err;
  459. }
  460. usb_dev_dr_client = platform_device_register_simple(
  461. "fsl-usb2-udc", i, r, 2);
  462. if (IS_ERR(usb_dev_dr_client)) {
  463. ret = PTR_ERR(usb_dev_dr_client);
  464. goto err;
  465. }
  466. } else {
  467. ret = -EINVAL;
  468. goto err;
  469. }
  470. prop = of_get_property(np, "phy_type", NULL);
  471. usb_data.phy_mode = determine_usb_phy(prop);
  472. if (usb_dev_dr_host) {
  473. usb_dev_dr_host->dev.coherent_dma_mask = 0xffffffffUL;
  474. usb_dev_dr_host->dev.dma_mask = &usb_dev_dr_host->
  475. dev.coherent_dma_mask;
  476. if ((ret = platform_device_add_data(usb_dev_dr_host,
  477. &usb_data, sizeof(struct
  478. fsl_usb2_platform_data))))
  479. goto unreg_dr;
  480. }
  481. if (usb_dev_dr_client) {
  482. usb_dev_dr_client->dev.coherent_dma_mask = 0xffffffffUL;
  483. usb_dev_dr_client->dev.dma_mask = &usb_dev_dr_client->
  484. dev.coherent_dma_mask;
  485. if ((ret = platform_device_add_data(usb_dev_dr_client,
  486. &usb_data, sizeof(struct
  487. fsl_usb2_platform_data))))
  488. goto unreg_dr;
  489. }
  490. i++;
  491. }
  492. return 0;
  493. unreg_dr:
  494. if (usb_dev_dr_host)
  495. platform_device_unregister(usb_dev_dr_host);
  496. if (usb_dev_dr_client)
  497. platform_device_unregister(usb_dev_dr_client);
  498. unreg_mph:
  499. if (usb_dev_mph)
  500. platform_device_unregister(usb_dev_mph);
  501. err:
  502. return ret;
  503. }
  504. arch_initcall(fsl_usb_of_init);
  505. static int __init of_fsl_spi_probe(char *type, char *compatible, u32 sysclk,
  506. struct spi_board_info *board_infos,
  507. unsigned int num_board_infos,
  508. void (*activate_cs)(u8 cs, u8 polarity),
  509. void (*deactivate_cs)(u8 cs, u8 polarity))
  510. {
  511. struct device_node *np;
  512. unsigned int i = 0;
  513. for_each_compatible_node(np, type, compatible) {
  514. int ret;
  515. unsigned int j;
  516. const void *prop;
  517. struct resource res[2];
  518. struct platform_device *pdev;
  519. struct fsl_spi_platform_data pdata = {
  520. .activate_cs = activate_cs,
  521. .deactivate_cs = deactivate_cs,
  522. };
  523. memset(res, 0, sizeof(res));
  524. pdata.sysclk = sysclk;
  525. prop = of_get_property(np, "reg", NULL);
  526. if (!prop)
  527. goto err;
  528. pdata.bus_num = *(u32 *)prop;
  529. prop = of_get_property(np, "cell-index", NULL);
  530. if (prop)
  531. i = *(u32 *)prop;
  532. prop = of_get_property(np, "mode", NULL);
  533. if (prop && !strcmp(prop, "cpu-qe"))
  534. pdata.qe_mode = 1;
  535. for (j = 0; j < num_board_infos; j++) {
  536. if (board_infos[j].bus_num == pdata.bus_num)
  537. pdata.max_chipselect++;
  538. }
  539. if (!pdata.max_chipselect)
  540. continue;
  541. ret = of_address_to_resource(np, 0, &res[0]);
  542. if (ret)
  543. goto err;
  544. ret = of_irq_to_resource(np, 0, &res[1]);
  545. if (ret == NO_IRQ)
  546. goto err;
  547. pdev = platform_device_alloc("mpc83xx_spi", i);
  548. if (!pdev)
  549. goto err;
  550. ret = platform_device_add_data(pdev, &pdata, sizeof(pdata));
  551. if (ret)
  552. goto unreg;
  553. ret = platform_device_add_resources(pdev, res,
  554. ARRAY_SIZE(res));
  555. if (ret)
  556. goto unreg;
  557. ret = platform_device_add(pdev);
  558. if (ret)
  559. goto unreg;
  560. goto next;
  561. unreg:
  562. platform_device_del(pdev);
  563. err:
  564. pr_err("%s: registration failed\n", np->full_name);
  565. next:
  566. i++;
  567. }
  568. return i;
  569. }
  570. int __init fsl_spi_init(struct spi_board_info *board_infos,
  571. unsigned int num_board_infos,
  572. void (*activate_cs)(u8 cs, u8 polarity),
  573. void (*deactivate_cs)(u8 cs, u8 polarity))
  574. {
  575. u32 sysclk = -1;
  576. int ret;
  577. #ifdef CONFIG_QUICC_ENGINE
  578. /* SPI controller is either clocked from QE or SoC clock */
  579. sysclk = get_brgfreq();
  580. #endif
  581. if (sysclk == -1) {
  582. sysclk = fsl_get_sys_freq();
  583. if (sysclk == -1)
  584. return -ENODEV;
  585. }
  586. ret = of_fsl_spi_probe(NULL, "fsl,spi", sysclk, board_infos,
  587. num_board_infos, activate_cs, deactivate_cs);
  588. if (!ret)
  589. of_fsl_spi_probe("spi", "fsl_spi", sysclk, board_infos,
  590. num_board_infos, activate_cs, deactivate_cs);
  591. return spi_register_board_info(board_infos, num_board_infos);
  592. }
  593. #if defined(CONFIG_PPC_85xx) || defined(CONFIG_PPC_86xx)
  594. static __be32 __iomem *rstcr;
  595. static int __init setup_rstcr(void)
  596. {
  597. struct device_node *np;
  598. np = of_find_node_by_name(NULL, "global-utilities");
  599. if ((np && of_get_property(np, "fsl,has-rstcr", NULL))) {
  600. const u32 *prop = of_get_property(np, "reg", NULL);
  601. if (prop) {
  602. /* map reset control register
  603. * 0xE00B0 is offset of reset control register
  604. */
  605. rstcr = ioremap(get_immrbase() + *prop + 0xB0, 0xff);
  606. if (!rstcr)
  607. printk (KERN_EMERG "Error: reset control "
  608. "register not mapped!\n");
  609. }
  610. } else
  611. printk (KERN_INFO "rstcr compatible register does not exist!\n");
  612. if (np)
  613. of_node_put(np);
  614. return 0;
  615. }
  616. arch_initcall(setup_rstcr);
  617. void fsl_rstcr_restart(char *cmd)
  618. {
  619. local_irq_disable();
  620. if (rstcr)
  621. /* set reset control register */
  622. out_be32(rstcr, 0x2); /* HRESET_REQ */
  623. while (1) ;
  624. }
  625. #endif
  626. #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
  627. struct platform_diu_data_ops diu_ops = {
  628. .diu_size = 1280 * 1024 * 4, /* default one 1280x1024 buffer */
  629. };
  630. EXPORT_SYMBOL(diu_ops);
  631. int __init preallocate_diu_videomemory(void)
  632. {
  633. pr_debug("diu_size=%lu\n", diu_ops.diu_size);
  634. diu_ops.diu_mem = __alloc_bootmem(diu_ops.diu_size, 8, 0);
  635. if (!diu_ops.diu_mem) {
  636. printk(KERN_ERR "fsl-diu: cannot allocate %lu bytes\n",
  637. diu_ops.diu_size);
  638. return -ENOMEM;
  639. }
  640. pr_debug("diu_mem=%p\n", diu_ops.diu_mem);
  641. rh_init(&diu_ops.diu_rh_info, 4096, ARRAY_SIZE(diu_ops.diu_rh_block),
  642. diu_ops.diu_rh_block);
  643. return rh_attach_region(&diu_ops.diu_rh_info,
  644. (unsigned long) diu_ops.diu_mem,
  645. diu_ops.diu_size);
  646. }
  647. static int __init early_parse_diufb(char *p)
  648. {
  649. if (!p)
  650. return 1;
  651. diu_ops.diu_size = _ALIGN_UP(memparse(p, &p), 8);
  652. pr_debug("diu_size=%lu\n", diu_ops.diu_size);
  653. return 0;
  654. }
  655. early_param("diufb", early_parse_diufb);
  656. #endif