mpc8349emitx.dts 6.9 KB

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  1. /*
  2. * MPC8349E-mITX Device Tree Source
  3. *
  4. * Copyright 2006 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8349EMITX";
  14. compatible = "MPC8349EMITX", "MPC834xMITX", "MPC83xxMITX";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. };
  25. cpus {
  26. #address-cells = <1>;
  27. #size-cells = <0>;
  28. PowerPC,8349@0 {
  29. device_type = "cpu";
  30. reg = <0x0>;
  31. d-cache-line-size = <32>;
  32. i-cache-line-size = <32>;
  33. d-cache-size = <32768>;
  34. i-cache-size = <32768>;
  35. timebase-frequency = <0>; // from bootloader
  36. bus-frequency = <0>; // from bootloader
  37. clock-frequency = <0>; // from bootloader
  38. };
  39. };
  40. memory {
  41. device_type = "memory";
  42. reg = <0x00000000 0x10000000>;
  43. };
  44. soc8349@e0000000 {
  45. #address-cells = <1>;
  46. #size-cells = <1>;
  47. device_type = "soc";
  48. ranges = <0x0 0xe0000000 0x00100000>;
  49. reg = <0xe0000000 0x00000200>;
  50. bus-frequency = <0>; // from bootloader
  51. wdt@200 {
  52. device_type = "watchdog";
  53. compatible = "mpc83xx_wdt";
  54. reg = <0x200 0x100>;
  55. };
  56. i2c@3000 {
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. cell-index = <0>;
  60. compatible = "fsl-i2c";
  61. reg = <0x3000 0x100>;
  62. interrupts = <14 0x8>;
  63. interrupt-parent = <&ipic>;
  64. dfsrr;
  65. };
  66. i2c@3100 {
  67. #address-cells = <1>;
  68. #size-cells = <0>;
  69. cell-index = <1>;
  70. compatible = "fsl-i2c";
  71. reg = <0x3100 0x100>;
  72. interrupts = <15 0x8>;
  73. interrupt-parent = <&ipic>;
  74. dfsrr;
  75. };
  76. spi@7000 {
  77. cell-index = <0>;
  78. compatible = "fsl,spi";
  79. reg = <0x7000 0x1000>;
  80. interrupts = <16 0x8>;
  81. interrupt-parent = <&ipic>;
  82. mode = "cpu";
  83. };
  84. dma@82a8 {
  85. #address-cells = <1>;
  86. #size-cells = <1>;
  87. compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
  88. reg = <0x82a8 4>;
  89. ranges = <0 0x8100 0x1a8>;
  90. interrupt-parent = <&ipic>;
  91. interrupts = <71 8>;
  92. cell-index = <0>;
  93. dma-channel@0 {
  94. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  95. reg = <0 0x80>;
  96. interrupt-parent = <&ipic>;
  97. interrupts = <71 8>;
  98. };
  99. dma-channel@80 {
  100. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  101. reg = <0x80 0x80>;
  102. interrupt-parent = <&ipic>;
  103. interrupts = <71 8>;
  104. };
  105. dma-channel@100 {
  106. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  107. reg = <0x100 0x80>;
  108. interrupt-parent = <&ipic>;
  109. interrupts = <71 8>;
  110. };
  111. dma-channel@180 {
  112. compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
  113. reg = <0x180 0x28>;
  114. interrupt-parent = <&ipic>;
  115. interrupts = <71 8>;
  116. };
  117. };
  118. usb@22000 {
  119. compatible = "fsl-usb2-mph";
  120. reg = <0x22000 0x1000>;
  121. #address-cells = <1>;
  122. #size-cells = <0>;
  123. interrupt-parent = <&ipic>;
  124. interrupts = <39 0x8>;
  125. phy_type = "ulpi";
  126. port1;
  127. };
  128. usb@23000 {
  129. compatible = "fsl-usb2-dr";
  130. reg = <0x23000 0x1000>;
  131. #address-cells = <1>;
  132. #size-cells = <0>;
  133. interrupt-parent = <&ipic>;
  134. interrupts = <38 0x8>;
  135. dr_mode = "peripheral";
  136. phy_type = "ulpi";
  137. };
  138. mdio@24520 {
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. compatible = "fsl,gianfar-mdio";
  142. reg = <0x24520 0x20>;
  143. /* Vitesse 8201 */
  144. phy1c: ethernet-phy@1c {
  145. interrupt-parent = <&ipic>;
  146. interrupts = <18 0x8>;
  147. reg = <0x1c>;
  148. device_type = "ethernet-phy";
  149. };
  150. };
  151. enet0: ethernet@24000 {
  152. cell-index = <0>;
  153. device_type = "network";
  154. model = "TSEC";
  155. compatible = "gianfar";
  156. reg = <0x24000 0x1000>;
  157. local-mac-address = [ 00 00 00 00 00 00 ];
  158. interrupts = <32 0x8 33 0x8 34 0x8>;
  159. interrupt-parent = <&ipic>;
  160. phy-handle = <&phy1c>;
  161. linux,network-index = <0>;
  162. };
  163. enet1: ethernet@25000 {
  164. cell-index = <1>;
  165. device_type = "network";
  166. model = "TSEC";
  167. compatible = "gianfar";
  168. reg = <0x25000 0x1000>;
  169. local-mac-address = [ 00 00 00 00 00 00 ];
  170. interrupts = <35 0x8 36 0x8 37 0x8>;
  171. interrupt-parent = <&ipic>;
  172. /* Vitesse 7385 isn't on the MDIO bus */
  173. fixed-link = <1 1 1000 0 0>;
  174. linux,network-index = <1>;
  175. };
  176. serial0: serial@4500 {
  177. cell-index = <0>;
  178. device_type = "serial";
  179. compatible = "ns16550";
  180. reg = <0x4500 0x100>;
  181. clock-frequency = <0>; // from bootloader
  182. interrupts = <9 0x8>;
  183. interrupt-parent = <&ipic>;
  184. };
  185. serial1: serial@4600 {
  186. cell-index = <1>;
  187. device_type = "serial";
  188. compatible = "ns16550";
  189. reg = <0x4600 0x100>;
  190. clock-frequency = <0>; // from bootloader
  191. interrupts = <10 0x8>;
  192. interrupt-parent = <&ipic>;
  193. };
  194. crypto@30000 {
  195. compatible = "fsl,sec2.0";
  196. reg = <0x30000 0x10000>;
  197. interrupts = <11 0x8>;
  198. interrupt-parent = <&ipic>;
  199. fsl,num-channels = <4>;
  200. fsl,channel-fifo-len = <24>;
  201. fsl,exec-units-mask = <0x7e>;
  202. fsl,descriptor-types-mask = <0x01010ebf>;
  203. };
  204. ipic: pic@700 {
  205. interrupt-controller;
  206. #address-cells = <0>;
  207. #interrupt-cells = <2>;
  208. reg = <0x700 0x100>;
  209. device_type = "ipic";
  210. };
  211. };
  212. pci0: pci@e0008500 {
  213. cell-index = <1>;
  214. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  215. interrupt-map = <
  216. /* IDSEL 0x10 - SATA */
  217. 0x8000 0x0 0x0 0x1 &ipic 22 0x8 /* SATA_INTA */
  218. >;
  219. interrupt-parent = <&ipic>;
  220. interrupts = <66 0x8>;
  221. bus-range = <0x0 0x0>;
  222. ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  223. 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  224. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
  225. clock-frequency = <66666666>;
  226. #interrupt-cells = <1>;
  227. #size-cells = <2>;
  228. #address-cells = <3>;
  229. reg = <0xe0008500 0x100>;
  230. compatible = "fsl,mpc8349-pci";
  231. device_type = "pci";
  232. };
  233. pci1: pci@e0008600 {
  234. cell-index = <2>;
  235. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  236. interrupt-map = <
  237. /* IDSEL 0x0E - MiniPCI Slot */
  238. 0x7000 0x0 0x0 0x1 &ipic 21 0x8 /* PCI_INTA */
  239. /* IDSEL 0x0F - PCI Slot */
  240. 0x7800 0x0 0x0 0x1 &ipic 20 0x8 /* PCI_INTA */
  241. 0x7800 0x0 0x0 0x2 &ipic 21 0x8 /* PCI_INTB */
  242. >;
  243. interrupt-parent = <&ipic>;
  244. interrupts = <67 0x8>;
  245. bus-range = <0x0 0x0>;
  246. ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  247. 0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
  248. 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x01000000>;
  249. clock-frequency = <66666666>;
  250. #interrupt-cells = <1>;
  251. #size-cells = <2>;
  252. #address-cells = <3>;
  253. reg = <0xe0008600 0x100>;
  254. compatible = "fsl,mpc8349-pci";
  255. device_type = "pci";
  256. };
  257. localbus@e0005000 {
  258. #address-cells = <2>;
  259. #size-cells = <1>;
  260. compatible = "fsl,mpc8349e-localbus",
  261. "fsl,pq2pro-localbus";
  262. reg = <0xe0005000 0xd8>;
  263. ranges = <0x3 0x0 0xf0000000 0x210>;
  264. pata@3,0 {
  265. compatible = "fsl,mpc8349emitx-pata", "ata-generic";
  266. reg = <0x3 0x0 0x10 0x3 0x20c 0x4>;
  267. reg-shift = <1>;
  268. pio-mode = <6>;
  269. interrupts = <23 0x8>;
  270. interrupt-parent = <&ipic>;
  271. };
  272. };
  273. };