head.S 8.9 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf548/head.S
  3. * Based on: arch/blackfin/mach-bf537/head.S
  4. * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
  5. *
  6. * Created: 1998
  7. * Description: Startup code for Blackfin BF548
  8. *
  9. * Modified:
  10. * Copyright 2004-2007 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/linkage.h>
  30. #include <linux/init.h>
  31. #include <asm/blackfin.h>
  32. #include <asm/trace.h>
  33. #if CONFIG_BFIN_KERNEL_CLOCK
  34. #include <asm/mach-common/clocks.h>
  35. #include <asm/mach/mem_init.h>
  36. #endif
  37. .extern ___bss_stop
  38. .extern ___bss_start
  39. .extern _bf53x_relocate_l1_mem
  40. #define INITIAL_STACK 0xFFB01000
  41. __INIT
  42. ENTRY(__start)
  43. /* R0: argument of command line string, passed from uboot, save it */
  44. R7 = R0;
  45. /* Enable Cycle Counter and Nesting Of Interrupts */
  46. #ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
  47. R0 = SYSCFG_SNEN;
  48. #else
  49. R0 = SYSCFG_SNEN | SYSCFG_CCEN;
  50. #endif
  51. SYSCFG = R0;
  52. R0 = 0;
  53. /* Clear Out All the data and pointer Registers*/
  54. R1 = R0;
  55. R2 = R0;
  56. R3 = R0;
  57. R4 = R0;
  58. R5 = R0;
  59. R6 = R0;
  60. P0 = R0;
  61. P1 = R0;
  62. P2 = R0;
  63. P3 = R0;
  64. P4 = R0;
  65. P5 = R0;
  66. LC0 = r0;
  67. LC1 = r0;
  68. L0 = r0;
  69. L1 = r0;
  70. L2 = r0;
  71. L3 = r0;
  72. /* Clear Out All the DAG Registers*/
  73. B0 = r0;
  74. B1 = r0;
  75. B2 = r0;
  76. B3 = r0;
  77. I0 = r0;
  78. I1 = r0;
  79. I2 = r0;
  80. I3 = r0;
  81. M0 = r0;
  82. M1 = r0;
  83. M2 = r0;
  84. M3 = r0;
  85. trace_buffer_init(p0,r0);
  86. P0 = R1;
  87. R0 = R1;
  88. /* Turn off the icache */
  89. p0.l = LO(IMEM_CONTROL);
  90. p0.h = HI(IMEM_CONTROL);
  91. R1 = [p0];
  92. R0 = ~ENICPLB;
  93. R0 = R0 & R1;
  94. [p0] = R0;
  95. SSYNC;
  96. /* Turn off the dcache */
  97. p0.l = LO(DMEM_CONTROL);
  98. p0.h = HI(DMEM_CONTROL);
  99. R1 = [p0];
  100. R0 = ~ENDCPLB;
  101. R0 = R0 & R1;
  102. [p0] = R0;
  103. SSYNC;
  104. /* Initialize stack pointer */
  105. SP.L = LO(INITIAL_STACK);
  106. SP.H = HI(INITIAL_STACK);
  107. FP = SP;
  108. USP = SP;
  109. #ifdef CONFIG_EARLY_PRINTK
  110. SP += -12;
  111. call _init_early_exception_vectors;
  112. SP += 12;
  113. #endif
  114. /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
  115. call _bf53x_relocate_l1_mem;
  116. #if CONFIG_BFIN_KERNEL_CLOCK
  117. call _start_dma_code;
  118. #endif
  119. /* Code for initializing Async memory banks */
  120. p2.h = hi(EBIU_AMBCTL1);
  121. p2.l = lo(EBIU_AMBCTL1);
  122. r0.h = hi(AMBCTL1VAL);
  123. r0.l = lo(AMBCTL1VAL);
  124. [p2] = r0;
  125. ssync;
  126. p2.h = hi(EBIU_AMBCTL0);
  127. p2.l = lo(EBIU_AMBCTL0);
  128. r0.h = hi(AMBCTL0VAL);
  129. r0.l = lo(AMBCTL0VAL);
  130. [p2] = r0;
  131. ssync;
  132. p2.h = hi(EBIU_AMGCTL);
  133. p2.l = lo(EBIU_AMGCTL);
  134. r0 = AMGCTLVAL;
  135. w[p2] = r0;
  136. ssync;
  137. p2.h = hi(EBIU_MBSCTL);
  138. p2.l = lo(EBIU_MBSCTL);
  139. r0.h = hi(CONFIG_EBIU_MBSCTLVAL);
  140. r0.l = lo(CONFIG_EBIU_MBSCTLVAL);
  141. [p2] = r0;
  142. ssync;
  143. p2.h = hi(EBIU_MODE);
  144. p2.l = lo(EBIU_MODE);
  145. r0.h = hi(CONFIG_EBIU_MODEVAL);
  146. r0.l = lo(CONFIG_EBIU_MODEVAL);
  147. [p2] = r0;
  148. ssync;
  149. p2.h = hi(EBIU_FCTL);
  150. p2.l = lo(EBIU_FCTL);
  151. r0.h = hi(CONFIG_EBIU_FCTLVAL);
  152. r0.l = lo(CONFIG_EBIU_FCTLVAL);
  153. [p2] = r0;
  154. ssync;
  155. /* This section keeps the processor in supervisor mode
  156. * during kernel boot. Switches to user mode at end of boot.
  157. * See page 3-9 of Hardware Reference manual for documentation.
  158. */
  159. /* EVT15 = _real_start */
  160. p0.l = lo(EVT15);
  161. p0.h = hi(EVT15);
  162. p1.l = _real_start;
  163. p1.h = _real_start;
  164. [p0] = p1;
  165. csync;
  166. p0.l = lo(IMASK);
  167. p0.h = hi(IMASK);
  168. p1.l = IMASK_IVG15;
  169. p1.h = 0x0;
  170. [p0] = p1;
  171. csync;
  172. raise 15;
  173. p0.l = .LWAIT_HERE;
  174. p0.h = .LWAIT_HERE;
  175. reti = p0;
  176. #if ANOMALY_05000281
  177. nop;
  178. nop;
  179. nop;
  180. #endif
  181. rti;
  182. .LWAIT_HERE:
  183. jump .LWAIT_HERE;
  184. ENDPROC(__start)
  185. ENTRY(_real_start)
  186. [ -- sp ] = reti;
  187. p0.l = lo(WDOG_CTL);
  188. p0.h = hi(WDOG_CTL);
  189. r0 = 0xAD6(z);
  190. w[p0] = r0; /* watchdog off for now */
  191. ssync;
  192. /* Code update for BSS size == 0
  193. * Zero out the bss region.
  194. */
  195. p1.l = ___bss_start;
  196. p1.h = ___bss_start;
  197. p2.l = ___bss_stop;
  198. p2.h = ___bss_stop;
  199. r0 = 0;
  200. p2 -= p1;
  201. lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
  202. .L_clear_bss:
  203. B[p1++] = r0;
  204. /* In case there is a NULL pointer reference
  205. * Zero out region before stext
  206. */
  207. p1.l = 0x0;
  208. p1.h = 0x0;
  209. r0.l = __stext;
  210. r0.h = __stext;
  211. r0 = r0 >> 1;
  212. p2 = r0;
  213. r0 = 0;
  214. lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
  215. .L_clear_zero:
  216. W[p1++] = r0;
  217. /* pass the uboot arguments to the global value command line */
  218. R0 = R7;
  219. call _cmdline_init;
  220. p1.l = __rambase;
  221. p1.h = __rambase;
  222. r0.l = __sdata;
  223. r0.h = __sdata;
  224. [p1] = r0;
  225. p1.l = __ramstart;
  226. p1.h = __ramstart;
  227. p3.l = ___bss_stop;
  228. p3.h = ___bss_stop;
  229. r1 = p3;
  230. [p1] = r1;
  231. /*
  232. * load the current thread pointer and stack
  233. */
  234. r1.l = _init_thread_union;
  235. r1.h = _init_thread_union;
  236. r2.l = 0x2000;
  237. r2.h = 0x0000;
  238. r1 = r1 + r2;
  239. sp = r1;
  240. usp = sp;
  241. fp = sp;
  242. call _start_kernel;
  243. .L_exit:
  244. jump.s .L_exit;
  245. ENDPROC(_real_start)
  246. __FINIT
  247. .section .l1.text
  248. #if CONFIG_BFIN_KERNEL_CLOCK
  249. ENTRY(_start_dma_code)
  250. /* Enable PHY CLK buffer output */
  251. p0.h = hi(VR_CTL);
  252. p0.l = lo(VR_CTL);
  253. r0.l = w[p0];
  254. bitset(r0, 14);
  255. w[p0] = r0.l;
  256. ssync;
  257. p0.h = hi(SIC_IWR0);
  258. p0.l = lo(SIC_IWR0);
  259. r0.l = 0x1;
  260. r0.h = 0x0;
  261. [p0] = r0;
  262. SSYNC;
  263. /*
  264. * Set PLL_CTL
  265. * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
  266. * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
  267. * - [7] = output delay (add 200ps of delay to mem signals)
  268. * - [6] = input delay (add 200ps of input delay to mem signals)
  269. * - [5] = PDWN : 1=All Clocks off
  270. * - [3] = STOPCK : 1=Core Clock off
  271. * - [1] = PLL_OFF : 1=Disable Power to PLL
  272. * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
  273. * all other bits set to zero
  274. */
  275. p0.h = hi(PLL_LOCKCNT);
  276. p0.l = lo(PLL_LOCKCNT);
  277. r0 = 0x300(Z);
  278. w[p0] = r0.l;
  279. ssync;
  280. #if defined(CONFIG_BF54x)
  281. P2.H = hi(EBIU_RSTCTL);
  282. P2.L = lo(EBIU_RSTCTL);
  283. R0 = [P2];
  284. BITSET (R0, 3);
  285. #else
  286. P2.H = hi(EBIU_SDGCTL);
  287. P2.L = lo(EBIU_SDGCTL);
  288. R0 = [P2];
  289. BITSET (R0, 24);
  290. #endif
  291. [P2] = R0;
  292. SSYNC;
  293. #if defined(CONFIG_BF54x)
  294. .LSRR_MODE:
  295. R0 = [P2];
  296. CC = BITTST(R0, 4);
  297. if !CC JUMP .LSRR_MODE;
  298. #endif
  299. r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
  300. r0 = r0 << 9; /* Shift it over, */
  301. r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
  302. r0 = r1 | r0;
  303. r1 = PLL_BYPASS; /* Bypass the PLL? */
  304. r1 = r1 << 8; /* Shift it over */
  305. r0 = r1 | r0; /* add them all together */
  306. p0.h = hi(PLL_CTL);
  307. p0.l = lo(PLL_CTL); /* Load the address */
  308. cli r2; /* Disable interrupts */
  309. ssync;
  310. w[p0] = r0.l; /* Set the value */
  311. idle; /* Wait for the PLL to stablize */
  312. sti r2; /* Enable interrupts */
  313. .Lcheck_again:
  314. p0.h = hi(PLL_STAT);
  315. p0.l = lo(PLL_STAT);
  316. R0 = W[P0](Z);
  317. CC = BITTST(R0,5);
  318. if ! CC jump .Lcheck_again;
  319. /* Configure SCLK & CCLK Dividers */
  320. r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
  321. p0.h = hi(PLL_DIV);
  322. p0.l = lo(PLL_DIV);
  323. w[p0] = r0.l;
  324. ssync;
  325. #if defined(CONFIG_BF54x)
  326. P2.H = hi(EBIU_RSTCTL);
  327. P2.L = lo(EBIU_RSTCTL);
  328. R0 = [P2];
  329. CC = BITTST(R0, 0);
  330. if CC jump .Lskipddrrst;
  331. BITSET (R0, 0);
  332. .Lskipddrrst:
  333. BITCLR (R0, 3);
  334. [P2] = R0;
  335. SSYNC;
  336. p0.l = lo(EBIU_DDRCTL0);
  337. p0.h = hi(EBIU_DDRCTL0);
  338. r0.l = lo(mem_DDRCTL0);
  339. r0.h = hi(mem_DDRCTL0);
  340. [p0] = r0;
  341. ssync;
  342. p0.l = lo(EBIU_DDRCTL1);
  343. p0.h = hi(EBIU_DDRCTL1);
  344. r0.l = lo(mem_DDRCTL1);
  345. r0.h = hi(mem_DDRCTL1);
  346. [p0] = r0;
  347. ssync;
  348. p0.l = lo(EBIU_DDRCTL2);
  349. p0.h = hi(EBIU_DDRCTL2);
  350. r0.l = lo(mem_DDRCTL2);
  351. r0.h = hi(mem_DDRCTL2);
  352. [p0] = r0;
  353. ssync;
  354. #else
  355. p0.l = lo(EBIU_SDRRC);
  356. p0.h = hi(EBIU_SDRRC);
  357. r0 = mem_SDRRC;
  358. w[p0] = r0.l;
  359. ssync;
  360. p0.l = LO(EBIU_SDBCTL);
  361. p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
  362. r0 = mem_SDBCTL;
  363. w[p0] = r0.l;
  364. ssync;
  365. P2.H = hi(EBIU_SDGCTL);
  366. P2.L = lo(EBIU_SDGCTL);
  367. R0 = [P2];
  368. BITCLR (R0, 24);
  369. p0.h = hi(EBIU_SDSTAT);
  370. p0.l = lo(EBIU_SDSTAT);
  371. r2.l = w[p0];
  372. cc = bittst(r2,3);
  373. if !cc jump .Lskip;
  374. NOP;
  375. BITSET (R0, 23);
  376. .Lskip:
  377. [P2] = R0;
  378. SSYNC;
  379. R0.L = lo(mem_SDGCTL);
  380. R0.H = hi(mem_SDGCTL);
  381. R1 = [p2];
  382. R1 = R1 | R0;
  383. [P2] = R1;
  384. SSYNC;
  385. #endif
  386. p0.h = hi(SIC_IWR0);
  387. p0.l = lo(SIC_IWR0);
  388. r0.l = lo(IWR_ENABLE_ALL);
  389. r0.h = hi(IWR_ENABLE_ALL);
  390. [p0] = r0;
  391. SSYNC;
  392. RTS;
  393. ENDPROC(_start_dma_code)
  394. #endif /* CONFIG_BFIN_KERNEL_CLOCK */