setup.c 22 KB

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  1. /*
  2. * Copyright (C) 2009 Renesas Solutions Corp.
  3. *
  4. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/device.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/mtd/physmap.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/io.h>
  17. #include <linux/delay.h>
  18. #include <linux/usb/r8a66597.h>
  19. #include <linux/i2c.h>
  20. #include <linux/i2c/tsc2007.h>
  21. #include <linux/spi/spi.h>
  22. #include <linux/spi/sh_msiof.h>
  23. #include <linux/spi/mmc_spi.h>
  24. #include <linux/mmc/host.h>
  25. #include <linux/input.h>
  26. #include <linux/input/sh_keysc.h>
  27. #include <linux/mfd/sh_mobile_sdhi.h>
  28. #include <video/sh_mobile_lcdc.h>
  29. #include <media/sh_mobile_ceu.h>
  30. #include <asm/heartbeat.h>
  31. #include <asm/sh_eth.h>
  32. #include <asm/clock.h>
  33. #include <asm/suspend.h>
  34. #include <cpu/sh7724.h>
  35. /*
  36. * Address Interface BusWidth
  37. *-----------------------------------------
  38. * 0x0000_0000 uboot 16bit
  39. * 0x0004_0000 Linux romImage 16bit
  40. * 0x0014_0000 MTD for Linux 16bit
  41. * 0x0400_0000 Internal I/O 16/32bit
  42. * 0x0800_0000 DRAM 32bit
  43. * 0x1800_0000 MFI 16bit
  44. */
  45. /* SWITCH
  46. *------------------------------
  47. * DS2[1] = FlashROM write protect ON : write protect
  48. * OFF : No write protect
  49. * DS2[2] = RMII / TS, SCIF ON : RMII
  50. * OFF : TS, SCIF3
  51. * DS2[3] = Camera / Video ON : Camera
  52. * OFF : NTSC/PAL (IN)
  53. * DS2[5] = NTSC_OUT Clock ON : On board OSC
  54. * OFF : SH7724 DV_CLK
  55. * DS2[6-7] = MMC / SD ON-OFF : SD
  56. * OFF-ON : MMC
  57. */
  58. /* Heartbeat */
  59. static unsigned char led_pos[] = { 0, 1, 2, 3 };
  60. static struct heartbeat_data heartbeat_data = {
  61. .regsize = 8,
  62. .nr_bits = 4,
  63. .bit_pos = led_pos,
  64. };
  65. static struct resource heartbeat_resources[] = {
  66. [0] = {
  67. .start = 0xA405012C, /* PTG */
  68. .end = 0xA405012E - 1,
  69. .flags = IORESOURCE_MEM,
  70. },
  71. };
  72. static struct platform_device heartbeat_device = {
  73. .name = "heartbeat",
  74. .id = -1,
  75. .dev = {
  76. .platform_data = &heartbeat_data,
  77. },
  78. .num_resources = ARRAY_SIZE(heartbeat_resources),
  79. .resource = heartbeat_resources,
  80. };
  81. /* MTD */
  82. static struct mtd_partition nor_flash_partitions[] = {
  83. {
  84. .name = "boot loader",
  85. .offset = 0,
  86. .size = (5 * 1024 * 1024),
  87. .mask_flags = MTD_WRITEABLE, /* force read-only */
  88. }, {
  89. .name = "free-area",
  90. .offset = MTDPART_OFS_APPEND,
  91. .size = MTDPART_SIZ_FULL,
  92. },
  93. };
  94. static struct physmap_flash_data nor_flash_data = {
  95. .width = 2,
  96. .parts = nor_flash_partitions,
  97. .nr_parts = ARRAY_SIZE(nor_flash_partitions),
  98. };
  99. static struct resource nor_flash_resources[] = {
  100. [0] = {
  101. .name = "NOR Flash",
  102. .start = 0x00000000,
  103. .end = 0x03ffffff,
  104. .flags = IORESOURCE_MEM,
  105. }
  106. };
  107. static struct platform_device nor_flash_device = {
  108. .name = "physmap-flash",
  109. .resource = nor_flash_resources,
  110. .num_resources = ARRAY_SIZE(nor_flash_resources),
  111. .dev = {
  112. .platform_data = &nor_flash_data,
  113. },
  114. };
  115. /* SH Eth */
  116. #define SH_ETH_ADDR (0xA4600000)
  117. #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
  118. #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
  119. static struct resource sh_eth_resources[] = {
  120. [0] = {
  121. .start = SH_ETH_ADDR,
  122. .end = SH_ETH_ADDR + 0x1FC,
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = 91,
  127. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  128. },
  129. };
  130. struct sh_eth_plat_data sh_eth_plat = {
  131. .phy = 0x1f, /* SMSC LAN8700 */
  132. .edmac_endian = EDMAC_LITTLE_ENDIAN,
  133. .ether_link_active_low = 1
  134. };
  135. static struct platform_device sh_eth_device = {
  136. .name = "sh-eth",
  137. .id = 0,
  138. .dev = {
  139. .platform_data = &sh_eth_plat,
  140. },
  141. .num_resources = ARRAY_SIZE(sh_eth_resources),
  142. .resource = sh_eth_resources,
  143. .archdata = {
  144. .hwblk_id = HWBLK_ETHER,
  145. },
  146. };
  147. /* USB0 host */
  148. void usb0_port_power(int port, int power)
  149. {
  150. gpio_set_value(GPIO_PTB4, power);
  151. }
  152. static struct r8a66597_platdata usb0_host_data = {
  153. .on_chip = 1,
  154. .port_power = usb0_port_power,
  155. };
  156. static struct resource usb0_host_resources[] = {
  157. [0] = {
  158. .start = 0xa4d80000,
  159. .end = 0xa4d80124 - 1,
  160. .flags = IORESOURCE_MEM,
  161. },
  162. [1] = {
  163. .start = 65,
  164. .end = 65,
  165. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  166. },
  167. };
  168. static struct platform_device usb0_host_device = {
  169. .name = "r8a66597_hcd",
  170. .id = 0,
  171. .dev = {
  172. .dma_mask = NULL, /* not use dma */
  173. .coherent_dma_mask = 0xffffffff,
  174. .platform_data = &usb0_host_data,
  175. },
  176. .num_resources = ARRAY_SIZE(usb0_host_resources),
  177. .resource = usb0_host_resources,
  178. };
  179. /* USB1 host/function */
  180. void usb1_port_power(int port, int power)
  181. {
  182. gpio_set_value(GPIO_PTB5, power);
  183. }
  184. static struct r8a66597_platdata usb1_common_data = {
  185. .on_chip = 1,
  186. .port_power = usb1_port_power,
  187. };
  188. static struct resource usb1_common_resources[] = {
  189. [0] = {
  190. .start = 0xa4d90000,
  191. .end = 0xa4d90124 - 1,
  192. .flags = IORESOURCE_MEM,
  193. },
  194. [1] = {
  195. .start = 66,
  196. .end = 66,
  197. .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
  198. },
  199. };
  200. static struct platform_device usb1_common_device = {
  201. /* .name will be added in arch_setup */
  202. .id = 1,
  203. .dev = {
  204. .dma_mask = NULL, /* not use dma */
  205. .coherent_dma_mask = 0xffffffff,
  206. .platform_data = &usb1_common_data,
  207. },
  208. .num_resources = ARRAY_SIZE(usb1_common_resources),
  209. .resource = usb1_common_resources,
  210. };
  211. /* LCDC */
  212. static struct sh_mobile_lcdc_info lcdc_info = {
  213. .ch[0] = {
  214. .interface_type = RGB18,
  215. .chan = LCDC_CHAN_MAINLCD,
  216. .bpp = 16,
  217. .lcd_cfg = {
  218. .sync = 0, /* hsync and vsync are active low */
  219. },
  220. .lcd_size_cfg = { /* 7.0 inch */
  221. .width = 152,
  222. .height = 91,
  223. },
  224. .board_cfg = {
  225. },
  226. }
  227. };
  228. static struct resource lcdc_resources[] = {
  229. [0] = {
  230. .name = "LCDC",
  231. .start = 0xfe940000,
  232. .end = 0xfe942fff,
  233. .flags = IORESOURCE_MEM,
  234. },
  235. [1] = {
  236. .start = 106,
  237. .flags = IORESOURCE_IRQ,
  238. },
  239. };
  240. static struct platform_device lcdc_device = {
  241. .name = "sh_mobile_lcdc_fb",
  242. .num_resources = ARRAY_SIZE(lcdc_resources),
  243. .resource = lcdc_resources,
  244. .dev = {
  245. .platform_data = &lcdc_info,
  246. },
  247. .archdata = {
  248. .hwblk_id = HWBLK_LCDC,
  249. },
  250. };
  251. /* CEU0 */
  252. static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
  253. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  254. };
  255. static struct resource ceu0_resources[] = {
  256. [0] = {
  257. .name = "CEU0",
  258. .start = 0xfe910000,
  259. .end = 0xfe91009f,
  260. .flags = IORESOURCE_MEM,
  261. },
  262. [1] = {
  263. .start = 52,
  264. .flags = IORESOURCE_IRQ,
  265. },
  266. [2] = {
  267. /* place holder for contiguous memory */
  268. },
  269. };
  270. static struct platform_device ceu0_device = {
  271. .name = "sh_mobile_ceu",
  272. .id = 0, /* "ceu0" clock */
  273. .num_resources = ARRAY_SIZE(ceu0_resources),
  274. .resource = ceu0_resources,
  275. .dev = {
  276. .platform_data = &sh_mobile_ceu0_info,
  277. },
  278. .archdata = {
  279. .hwblk_id = HWBLK_CEU0,
  280. },
  281. };
  282. /* CEU1 */
  283. static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
  284. .flags = SH_CEU_FLAG_USE_8BIT_BUS,
  285. };
  286. static struct resource ceu1_resources[] = {
  287. [0] = {
  288. .name = "CEU1",
  289. .start = 0xfe914000,
  290. .end = 0xfe91409f,
  291. .flags = IORESOURCE_MEM,
  292. },
  293. [1] = {
  294. .start = 63,
  295. .flags = IORESOURCE_IRQ,
  296. },
  297. [2] = {
  298. /* place holder for contiguous memory */
  299. },
  300. };
  301. static struct platform_device ceu1_device = {
  302. .name = "sh_mobile_ceu",
  303. .id = 1, /* "ceu1" clock */
  304. .num_resources = ARRAY_SIZE(ceu1_resources),
  305. .resource = ceu1_resources,
  306. .dev = {
  307. .platform_data = &sh_mobile_ceu1_info,
  308. },
  309. .archdata = {
  310. .hwblk_id = HWBLK_CEU1,
  311. },
  312. };
  313. /* I2C device */
  314. static struct i2c_board_info i2c1_devices[] = {
  315. {
  316. I2C_BOARD_INFO("r2025sd", 0x32),
  317. },
  318. };
  319. /* KEYSC */
  320. static struct sh_keysc_info keysc_info = {
  321. .mode = SH_KEYSC_MODE_1,
  322. .scan_timing = 3,
  323. .delay = 50,
  324. .kycr2_delay = 100,
  325. .keycodes = { KEY_1, 0, 0, 0, 0,
  326. KEY_2, 0, 0, 0, 0,
  327. KEY_3, 0, 0, 0, 0,
  328. KEY_4, 0, 0, 0, 0,
  329. KEY_5, 0, 0, 0, 0,
  330. KEY_6, 0, 0, 0, 0, },
  331. };
  332. static struct resource keysc_resources[] = {
  333. [0] = {
  334. .name = "KEYSC",
  335. .start = 0x044b0000,
  336. .end = 0x044b000f,
  337. .flags = IORESOURCE_MEM,
  338. },
  339. [1] = {
  340. .start = 79,
  341. .flags = IORESOURCE_IRQ,
  342. },
  343. };
  344. static struct platform_device keysc_device = {
  345. .name = "sh_keysc",
  346. .id = 0, /* keysc0 clock */
  347. .num_resources = ARRAY_SIZE(keysc_resources),
  348. .resource = keysc_resources,
  349. .dev = {
  350. .platform_data = &keysc_info,
  351. },
  352. .archdata = {
  353. .hwblk_id = HWBLK_KEYSC,
  354. },
  355. };
  356. /* TouchScreen */
  357. #define IRQ0 32
  358. static int ts_get_pendown_state(void)
  359. {
  360. int val = 0;
  361. gpio_free(GPIO_FN_INTC_IRQ0);
  362. gpio_request(GPIO_PTZ0, NULL);
  363. gpio_direction_input(GPIO_PTZ0);
  364. val = gpio_get_value(GPIO_PTZ0);
  365. gpio_free(GPIO_PTZ0);
  366. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  367. return val ? 0 : 1;
  368. }
  369. static int ts_init(void)
  370. {
  371. gpio_request(GPIO_FN_INTC_IRQ0, NULL);
  372. return 0;
  373. }
  374. struct tsc2007_platform_data tsc2007_info = {
  375. .model = 2007,
  376. .x_plate_ohms = 180,
  377. .get_pendown_state = ts_get_pendown_state,
  378. .init_platform_hw = ts_init,
  379. };
  380. static struct i2c_board_info ts_i2c_clients = {
  381. I2C_BOARD_INFO("tsc2007", 0x48),
  382. .type = "tsc2007",
  383. .platform_data = &tsc2007_info,
  384. .irq = IRQ0,
  385. };
  386. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  387. /* SHDI0 */
  388. static void sdhi0_set_pwr(struct platform_device *pdev, int state)
  389. {
  390. gpio_set_value(GPIO_PTB6, state);
  391. }
  392. static struct sh_mobile_sdhi_info sdhi0_info = {
  393. .set_pwr = sdhi0_set_pwr,
  394. };
  395. static struct resource sdhi0_resources[] = {
  396. [0] = {
  397. .name = "SDHI0",
  398. .start = 0x04ce0000,
  399. .end = 0x04ce01ff,
  400. .flags = IORESOURCE_MEM,
  401. },
  402. [1] = {
  403. .start = 101,
  404. .flags = IORESOURCE_IRQ,
  405. },
  406. };
  407. static struct platform_device sdhi0_device = {
  408. .name = "sh_mobile_sdhi",
  409. .num_resources = ARRAY_SIZE(sdhi0_resources),
  410. .resource = sdhi0_resources,
  411. .id = 0,
  412. .dev = {
  413. .platform_data = &sdhi0_info,
  414. },
  415. .archdata = {
  416. .hwblk_id = HWBLK_SDHI0,
  417. },
  418. };
  419. /* SHDI1 */
  420. static void sdhi1_set_pwr(struct platform_device *pdev, int state)
  421. {
  422. gpio_set_value(GPIO_PTB7, state);
  423. }
  424. static struct sh_mobile_sdhi_info sdhi1_info = {
  425. .set_pwr = sdhi1_set_pwr,
  426. };
  427. static struct resource sdhi1_resources[] = {
  428. [0] = {
  429. .name = "SDHI1",
  430. .start = 0x04cf0000,
  431. .end = 0x04cf01ff,
  432. .flags = IORESOURCE_MEM,
  433. },
  434. [1] = {
  435. .start = 24,
  436. .flags = IORESOURCE_IRQ,
  437. },
  438. };
  439. static struct platform_device sdhi1_device = {
  440. .name = "sh_mobile_sdhi",
  441. .num_resources = ARRAY_SIZE(sdhi1_resources),
  442. .resource = sdhi1_resources,
  443. .id = 1,
  444. .dev = {
  445. .platform_data = &sdhi1_info,
  446. },
  447. .archdata = {
  448. .hwblk_id = HWBLK_SDHI1,
  449. },
  450. };
  451. #else
  452. static int mmc_spi_get_ro(struct device *dev)
  453. {
  454. return gpio_get_value(GPIO_PTY6);
  455. }
  456. static int mmc_spi_get_cd(struct device *dev)
  457. {
  458. return !gpio_get_value(GPIO_PTY7);
  459. }
  460. static void mmc_spi_setpower(struct device *dev, unsigned int maskval)
  461. {
  462. gpio_set_value(GPIO_PTB6, maskval ? 1 : 0);
  463. }
  464. static struct mmc_spi_platform_data mmc_spi_info = {
  465. .get_ro = mmc_spi_get_ro,
  466. .get_cd = mmc_spi_get_cd,
  467. .caps = MMC_CAP_NEEDS_POLL,
  468. .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3.3V only */
  469. .setpower = mmc_spi_setpower,
  470. };
  471. static struct spi_board_info spi_bus[] = {
  472. {
  473. .modalias = "mmc_spi",
  474. .platform_data = &mmc_spi_info,
  475. .max_speed_hz = 5000000,
  476. .mode = SPI_MODE_0,
  477. .controller_data = (void *) GPIO_PTM4,
  478. },
  479. };
  480. static struct sh_msiof_spi_info msiof0_data = {
  481. .num_chipselect = 1,
  482. };
  483. static struct resource msiof0_resources[] = {
  484. [0] = {
  485. .name = "MSIOF0",
  486. .start = 0xa4c40000,
  487. .end = 0xa4c40063,
  488. .flags = IORESOURCE_MEM,
  489. },
  490. [1] = {
  491. .start = 84,
  492. .flags = IORESOURCE_IRQ,
  493. },
  494. };
  495. static struct platform_device msiof0_device = {
  496. .name = "spi_sh_msiof",
  497. .id = 0, /* MSIOF0 */
  498. .dev = {
  499. .platform_data = &msiof0_data,
  500. },
  501. .num_resources = ARRAY_SIZE(msiof0_resources),
  502. .resource = msiof0_resources,
  503. .archdata = {
  504. .hwblk_id = HWBLK_MSIOF0,
  505. },
  506. };
  507. #endif
  508. static struct platform_device *ecovec_devices[] __initdata = {
  509. &heartbeat_device,
  510. &nor_flash_device,
  511. &sh_eth_device,
  512. &usb0_host_device,
  513. &usb1_common_device,
  514. &lcdc_device,
  515. &ceu0_device,
  516. &ceu1_device,
  517. &keysc_device,
  518. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  519. &sdhi0_device,
  520. &sdhi1_device,
  521. #else
  522. &msiof0_device,
  523. #endif
  524. };
  525. #define EEPROM_ADDR 0x50
  526. static u8 mac_read(struct i2c_adapter *a, u8 command)
  527. {
  528. struct i2c_msg msg[2];
  529. u8 buf;
  530. int ret;
  531. msg[0].addr = EEPROM_ADDR;
  532. msg[0].flags = 0;
  533. msg[0].len = 1;
  534. msg[0].buf = &command;
  535. msg[1].addr = EEPROM_ADDR;
  536. msg[1].flags = I2C_M_RD;
  537. msg[1].len = 1;
  538. msg[1].buf = &buf;
  539. ret = i2c_transfer(a, msg, 2);
  540. if (ret < 0) {
  541. printk(KERN_ERR "error %d\n", ret);
  542. buf = 0xff;
  543. }
  544. return buf;
  545. }
  546. static void __init sh_eth_init(struct sh_eth_plat_data *pd)
  547. {
  548. struct i2c_adapter *a = i2c_get_adapter(1);
  549. int i;
  550. if (!a) {
  551. pr_err("can not get I2C 1\n");
  552. return;
  553. }
  554. /* read MAC address frome EEPROM */
  555. for (i = 0; i < sizeof(pd->mac_addr); i++) {
  556. pd->mac_addr[i] = mac_read(a, 0x10 + i);
  557. msleep(10);
  558. }
  559. }
  560. #define PORT_HIZA 0xA4050158
  561. #define IODRIVEA 0xA405018A
  562. extern char ecovec24_sdram_enter_start;
  563. extern char ecovec24_sdram_enter_end;
  564. extern char ecovec24_sdram_leave_start;
  565. extern char ecovec24_sdram_leave_end;
  566. static int __init arch_setup(void)
  567. {
  568. /* register board specific self-refresh code */
  569. sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
  570. &ecovec24_sdram_enter_start,
  571. &ecovec24_sdram_enter_end,
  572. &ecovec24_sdram_leave_start,
  573. &ecovec24_sdram_leave_end);
  574. /* enable STATUS0, STATUS2 and PDSTATUS */
  575. gpio_request(GPIO_FN_STATUS0, NULL);
  576. gpio_request(GPIO_FN_STATUS2, NULL);
  577. gpio_request(GPIO_FN_PDSTATUS, NULL);
  578. /* enable SCIFA0 */
  579. gpio_request(GPIO_FN_SCIF0_TXD, NULL);
  580. gpio_request(GPIO_FN_SCIF0_RXD, NULL);
  581. /* enable debug LED */
  582. gpio_request(GPIO_PTG0, NULL);
  583. gpio_request(GPIO_PTG1, NULL);
  584. gpio_request(GPIO_PTG2, NULL);
  585. gpio_request(GPIO_PTG3, NULL);
  586. gpio_direction_output(GPIO_PTG0, 0);
  587. gpio_direction_output(GPIO_PTG1, 0);
  588. gpio_direction_output(GPIO_PTG2, 0);
  589. gpio_direction_output(GPIO_PTG3, 0);
  590. ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
  591. /* enable SH-Eth */
  592. gpio_request(GPIO_PTA1, NULL);
  593. gpio_direction_output(GPIO_PTA1, 1);
  594. mdelay(20);
  595. gpio_request(GPIO_FN_RMII_RXD0, NULL);
  596. gpio_request(GPIO_FN_RMII_RXD1, NULL);
  597. gpio_request(GPIO_FN_RMII_TXD0, NULL);
  598. gpio_request(GPIO_FN_RMII_TXD1, NULL);
  599. gpio_request(GPIO_FN_RMII_REF_CLK, NULL);
  600. gpio_request(GPIO_FN_RMII_TX_EN, NULL);
  601. gpio_request(GPIO_FN_RMII_RX_ER, NULL);
  602. gpio_request(GPIO_FN_RMII_CRS_DV, NULL);
  603. gpio_request(GPIO_FN_MDIO, NULL);
  604. gpio_request(GPIO_FN_MDC, NULL);
  605. gpio_request(GPIO_FN_LNKSTA, NULL);
  606. /* enable USB */
  607. ctrl_outw(0x0000, 0xA4D80000);
  608. ctrl_outw(0x0000, 0xA4D90000);
  609. gpio_request(GPIO_PTB3, NULL);
  610. gpio_request(GPIO_PTB4, NULL);
  611. gpio_request(GPIO_PTB5, NULL);
  612. gpio_direction_input(GPIO_PTB3);
  613. gpio_direction_output(GPIO_PTB4, 0);
  614. gpio_direction_output(GPIO_PTB5, 0);
  615. ctrl_outw(0x0600, 0xa40501d4);
  616. ctrl_outw(0x0600, 0xa4050192);
  617. if (gpio_get_value(GPIO_PTB3)) {
  618. printk(KERN_INFO "USB1 function is selected\n");
  619. usb1_common_device.name = "r8a66597_udc";
  620. } else {
  621. printk(KERN_INFO "USB1 host is selected\n");
  622. usb1_common_device.name = "r8a66597_hcd";
  623. }
  624. /* enable LCDC */
  625. gpio_request(GPIO_FN_LCDD23, NULL);
  626. gpio_request(GPIO_FN_LCDD22, NULL);
  627. gpio_request(GPIO_FN_LCDD21, NULL);
  628. gpio_request(GPIO_FN_LCDD20, NULL);
  629. gpio_request(GPIO_FN_LCDD19, NULL);
  630. gpio_request(GPIO_FN_LCDD18, NULL);
  631. gpio_request(GPIO_FN_LCDD17, NULL);
  632. gpio_request(GPIO_FN_LCDD16, NULL);
  633. gpio_request(GPIO_FN_LCDD15, NULL);
  634. gpio_request(GPIO_FN_LCDD14, NULL);
  635. gpio_request(GPIO_FN_LCDD13, NULL);
  636. gpio_request(GPIO_FN_LCDD12, NULL);
  637. gpio_request(GPIO_FN_LCDD11, NULL);
  638. gpio_request(GPIO_FN_LCDD10, NULL);
  639. gpio_request(GPIO_FN_LCDD9, NULL);
  640. gpio_request(GPIO_FN_LCDD8, NULL);
  641. gpio_request(GPIO_FN_LCDD7, NULL);
  642. gpio_request(GPIO_FN_LCDD6, NULL);
  643. gpio_request(GPIO_FN_LCDD5, NULL);
  644. gpio_request(GPIO_FN_LCDD4, NULL);
  645. gpio_request(GPIO_FN_LCDD3, NULL);
  646. gpio_request(GPIO_FN_LCDD2, NULL);
  647. gpio_request(GPIO_FN_LCDD1, NULL);
  648. gpio_request(GPIO_FN_LCDD0, NULL);
  649. gpio_request(GPIO_FN_LCDDISP, NULL);
  650. gpio_request(GPIO_FN_LCDHSYN, NULL);
  651. gpio_request(GPIO_FN_LCDDCK, NULL);
  652. gpio_request(GPIO_FN_LCDVSYN, NULL);
  653. gpio_request(GPIO_FN_LCDDON, NULL);
  654. gpio_request(GPIO_FN_LCDLCLK, NULL);
  655. ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
  656. gpio_request(GPIO_PTE6, NULL);
  657. gpio_request(GPIO_PTU1, NULL);
  658. gpio_request(GPIO_PTR1, NULL);
  659. gpio_request(GPIO_PTA2, NULL);
  660. gpio_direction_input(GPIO_PTE6);
  661. gpio_direction_output(GPIO_PTU1, 0);
  662. gpio_direction_output(GPIO_PTR1, 0);
  663. gpio_direction_output(GPIO_PTA2, 0);
  664. /* I/O buffer drive ability is high */
  665. ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
  666. if (gpio_get_value(GPIO_PTE6)) {
  667. /* DVI */
  668. lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
  669. lcdc_info.ch[0].clock_divider = 1,
  670. lcdc_info.ch[0].lcd_cfg.name = "DVI";
  671. lcdc_info.ch[0].lcd_cfg.xres = 1280;
  672. lcdc_info.ch[0].lcd_cfg.yres = 720;
  673. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  674. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  675. lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
  676. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  677. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  678. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  679. gpio_set_value(GPIO_PTA2, 1);
  680. gpio_set_value(GPIO_PTU1, 1);
  681. } else {
  682. /* Panel */
  683. lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
  684. lcdc_info.ch[0].clock_divider = 2,
  685. lcdc_info.ch[0].lcd_cfg.name = "Panel";
  686. lcdc_info.ch[0].lcd_cfg.xres = 800;
  687. lcdc_info.ch[0].lcd_cfg.yres = 480;
  688. lcdc_info.ch[0].lcd_cfg.left_margin = 220;
  689. lcdc_info.ch[0].lcd_cfg.right_margin = 110;
  690. lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
  691. lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
  692. lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
  693. lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
  694. gpio_set_value(GPIO_PTR1, 1);
  695. /* FIXME
  696. *
  697. * LCDDON control is needed for Panel,
  698. * but current sh_mobile_lcdc driver doesn't control it.
  699. * It is temporary correspondence
  700. */
  701. gpio_request(GPIO_PTF4, NULL);
  702. gpio_direction_output(GPIO_PTF4, 1);
  703. /* enable TouchScreen */
  704. i2c_register_board_info(0, &ts_i2c_clients, 1);
  705. set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
  706. }
  707. /* enable CEU0 */
  708. gpio_request(GPIO_FN_VIO0_D15, NULL);
  709. gpio_request(GPIO_FN_VIO0_D14, NULL);
  710. gpio_request(GPIO_FN_VIO0_D13, NULL);
  711. gpio_request(GPIO_FN_VIO0_D12, NULL);
  712. gpio_request(GPIO_FN_VIO0_D11, NULL);
  713. gpio_request(GPIO_FN_VIO0_D10, NULL);
  714. gpio_request(GPIO_FN_VIO0_D9, NULL);
  715. gpio_request(GPIO_FN_VIO0_D8, NULL);
  716. gpio_request(GPIO_FN_VIO0_D7, NULL);
  717. gpio_request(GPIO_FN_VIO0_D6, NULL);
  718. gpio_request(GPIO_FN_VIO0_D5, NULL);
  719. gpio_request(GPIO_FN_VIO0_D4, NULL);
  720. gpio_request(GPIO_FN_VIO0_D3, NULL);
  721. gpio_request(GPIO_FN_VIO0_D2, NULL);
  722. gpio_request(GPIO_FN_VIO0_D1, NULL);
  723. gpio_request(GPIO_FN_VIO0_D0, NULL);
  724. gpio_request(GPIO_FN_VIO0_VD, NULL);
  725. gpio_request(GPIO_FN_VIO0_CLK, NULL);
  726. gpio_request(GPIO_FN_VIO0_FLD, NULL);
  727. gpio_request(GPIO_FN_VIO0_HD, NULL);
  728. platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20);
  729. /* enable CEU1 */
  730. gpio_request(GPIO_FN_VIO1_D7, NULL);
  731. gpio_request(GPIO_FN_VIO1_D6, NULL);
  732. gpio_request(GPIO_FN_VIO1_D5, NULL);
  733. gpio_request(GPIO_FN_VIO1_D4, NULL);
  734. gpio_request(GPIO_FN_VIO1_D3, NULL);
  735. gpio_request(GPIO_FN_VIO1_D2, NULL);
  736. gpio_request(GPIO_FN_VIO1_D1, NULL);
  737. gpio_request(GPIO_FN_VIO1_D0, NULL);
  738. gpio_request(GPIO_FN_VIO1_FLD, NULL);
  739. gpio_request(GPIO_FN_VIO1_HD, NULL);
  740. gpio_request(GPIO_FN_VIO1_VD, NULL);
  741. gpio_request(GPIO_FN_VIO1_CLK, NULL);
  742. platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20);
  743. /* enable KEYSC */
  744. gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
  745. gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
  746. gpio_request(GPIO_FN_KEYOUT3, NULL);
  747. gpio_request(GPIO_FN_KEYOUT2, NULL);
  748. gpio_request(GPIO_FN_KEYOUT1, NULL);
  749. gpio_request(GPIO_FN_KEYOUT0, NULL);
  750. gpio_request(GPIO_FN_KEYIN0, NULL);
  751. /* enable user debug switch */
  752. gpio_request(GPIO_PTR0, NULL);
  753. gpio_request(GPIO_PTR4, NULL);
  754. gpio_request(GPIO_PTR5, NULL);
  755. gpio_request(GPIO_PTR6, NULL);
  756. gpio_direction_input(GPIO_PTR0);
  757. gpio_direction_input(GPIO_PTR4);
  758. gpio_direction_input(GPIO_PTR5);
  759. gpio_direction_input(GPIO_PTR6);
  760. #ifdef CONFIG_MFD_SH_MOBILE_SDHI
  761. /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
  762. gpio_request(GPIO_FN_SDHI0CD, NULL);
  763. gpio_request(GPIO_FN_SDHI0WP, NULL);
  764. gpio_request(GPIO_FN_SDHI0CMD, NULL);
  765. gpio_request(GPIO_FN_SDHI0CLK, NULL);
  766. gpio_request(GPIO_FN_SDHI0D3, NULL);
  767. gpio_request(GPIO_FN_SDHI0D2, NULL);
  768. gpio_request(GPIO_FN_SDHI0D1, NULL);
  769. gpio_request(GPIO_FN_SDHI0D0, NULL);
  770. gpio_request(GPIO_PTB6, NULL);
  771. gpio_direction_output(GPIO_PTB6, 0);
  772. /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
  773. gpio_request(GPIO_FN_SDHI1CD, NULL);
  774. gpio_request(GPIO_FN_SDHI1WP, NULL);
  775. gpio_request(GPIO_FN_SDHI1CMD, NULL);
  776. gpio_request(GPIO_FN_SDHI1CLK, NULL);
  777. gpio_request(GPIO_FN_SDHI1D3, NULL);
  778. gpio_request(GPIO_FN_SDHI1D2, NULL);
  779. gpio_request(GPIO_FN_SDHI1D1, NULL);
  780. gpio_request(GPIO_FN_SDHI1D0, NULL);
  781. gpio_request(GPIO_PTB7, NULL);
  782. gpio_direction_output(GPIO_PTB7, 0);
  783. /* I/O buffer drive ability is high for SDHI1 */
  784. ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
  785. #else
  786. /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
  787. gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
  788. gpio_request(GPIO_FN_MSIOF0_RXD, NULL);
  789. gpio_request(GPIO_FN_MSIOF0_TSCK, NULL);
  790. gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */
  791. gpio_direction_output(GPIO_PTM4, 1); /* active low CS */
  792. gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */
  793. gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */
  794. gpio_request(GPIO_PTY6, NULL); /* write protect */
  795. gpio_direction_input(GPIO_PTY6);
  796. gpio_request(GPIO_PTY7, NULL); /* card detect */
  797. gpio_direction_input(GPIO_PTY7);
  798. spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
  799. #endif
  800. /* enable I2C device */
  801. i2c_register_board_info(1, i2c1_devices,
  802. ARRAY_SIZE(i2c1_devices));
  803. return platform_add_devices(ecovec_devices,
  804. ARRAY_SIZE(ecovec_devices));
  805. }
  806. arch_initcall(arch_setup);
  807. static int __init devices_setup(void)
  808. {
  809. sh_eth_init(&sh_eth_plat);
  810. return 0;
  811. }
  812. device_initcall(devices_setup);
  813. static struct sh_machine_vector mv_ecovec __initmv = {
  814. .mv_name = "R0P7724 (EcoVec)",
  815. };