pm8001_hwi.c 144 KB

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  1. /*
  2. * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
  3. *
  4. * Copyright (c) 2008-2009 USI Co., Ltd.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. */
  40. #include "pm8001_sas.h"
  41. #include "pm8001_hwi.h"
  42. #include "pm8001_chips.h"
  43. #include "pm8001_ctl.h"
  44. /**
  45. * read_main_config_table - read the configure table and save it.
  46. * @pm8001_ha: our hba card information
  47. */
  48. static void __devinit read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  49. {
  50. void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  51. pm8001_ha->main_cfg_tbl.signature = pm8001_mr32(address, 0x00);
  52. pm8001_ha->main_cfg_tbl.interface_rev = pm8001_mr32(address, 0x04);
  53. pm8001_ha->main_cfg_tbl.firmware_rev = pm8001_mr32(address, 0x08);
  54. pm8001_ha->main_cfg_tbl.max_out_io = pm8001_mr32(address, 0x0C);
  55. pm8001_ha->main_cfg_tbl.max_sgl = pm8001_mr32(address, 0x10);
  56. pm8001_ha->main_cfg_tbl.ctrl_cap_flag = pm8001_mr32(address, 0x14);
  57. pm8001_ha->main_cfg_tbl.gst_offset = pm8001_mr32(address, 0x18);
  58. pm8001_ha->main_cfg_tbl.inbound_queue_offset =
  59. pm8001_mr32(address, MAIN_IBQ_OFFSET);
  60. pm8001_ha->main_cfg_tbl.outbound_queue_offset =
  61. pm8001_mr32(address, MAIN_OBQ_OFFSET);
  62. pm8001_ha->main_cfg_tbl.hda_mode_flag =
  63. pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  64. /* read analog Setting offset from the configuration table */
  65. pm8001_ha->main_cfg_tbl.anolog_setup_table_offset =
  66. pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  67. /* read Error Dump Offset and Length */
  68. pm8001_ha->main_cfg_tbl.fatal_err_dump_offset0 =
  69. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  70. pm8001_ha->main_cfg_tbl.fatal_err_dump_length0 =
  71. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  72. pm8001_ha->main_cfg_tbl.fatal_err_dump_offset1 =
  73. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  74. pm8001_ha->main_cfg_tbl.fatal_err_dump_length1 =
  75. pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  76. }
  77. /**
  78. * read_general_status_table - read the general status table and save it.
  79. * @pm8001_ha: our hba card information
  80. */
  81. static void __devinit
  82. read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  83. {
  84. void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  85. pm8001_ha->gs_tbl.gst_len_mpistate = pm8001_mr32(address, 0x00);
  86. pm8001_ha->gs_tbl.iq_freeze_state0 = pm8001_mr32(address, 0x04);
  87. pm8001_ha->gs_tbl.iq_freeze_state1 = pm8001_mr32(address, 0x08);
  88. pm8001_ha->gs_tbl.msgu_tcnt = pm8001_mr32(address, 0x0C);
  89. pm8001_ha->gs_tbl.iop_tcnt = pm8001_mr32(address, 0x10);
  90. pm8001_ha->gs_tbl.reserved = pm8001_mr32(address, 0x14);
  91. pm8001_ha->gs_tbl.phy_state[0] = pm8001_mr32(address, 0x18);
  92. pm8001_ha->gs_tbl.phy_state[1] = pm8001_mr32(address, 0x1C);
  93. pm8001_ha->gs_tbl.phy_state[2] = pm8001_mr32(address, 0x20);
  94. pm8001_ha->gs_tbl.phy_state[3] = pm8001_mr32(address, 0x24);
  95. pm8001_ha->gs_tbl.phy_state[4] = pm8001_mr32(address, 0x28);
  96. pm8001_ha->gs_tbl.phy_state[5] = pm8001_mr32(address, 0x2C);
  97. pm8001_ha->gs_tbl.phy_state[6] = pm8001_mr32(address, 0x30);
  98. pm8001_ha->gs_tbl.phy_state[7] = pm8001_mr32(address, 0x34);
  99. pm8001_ha->gs_tbl.reserved1 = pm8001_mr32(address, 0x38);
  100. pm8001_ha->gs_tbl.reserved2 = pm8001_mr32(address, 0x3C);
  101. pm8001_ha->gs_tbl.reserved3 = pm8001_mr32(address, 0x40);
  102. pm8001_ha->gs_tbl.recover_err_info[0] = pm8001_mr32(address, 0x44);
  103. pm8001_ha->gs_tbl.recover_err_info[1] = pm8001_mr32(address, 0x48);
  104. pm8001_ha->gs_tbl.recover_err_info[2] = pm8001_mr32(address, 0x4C);
  105. pm8001_ha->gs_tbl.recover_err_info[3] = pm8001_mr32(address, 0x50);
  106. pm8001_ha->gs_tbl.recover_err_info[4] = pm8001_mr32(address, 0x54);
  107. pm8001_ha->gs_tbl.recover_err_info[5] = pm8001_mr32(address, 0x58);
  108. pm8001_ha->gs_tbl.recover_err_info[6] = pm8001_mr32(address, 0x5C);
  109. pm8001_ha->gs_tbl.recover_err_info[7] = pm8001_mr32(address, 0x60);
  110. }
  111. /**
  112. * read_inbnd_queue_table - read the inbound queue table and save it.
  113. * @pm8001_ha: our hba card information
  114. */
  115. static void __devinit
  116. read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
  117. {
  118. int inbQ_num = 1;
  119. int i;
  120. void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
  121. for (i = 0; i < inbQ_num; i++) {
  122. u32 offset = i * 0x20;
  123. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
  124. get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
  125. pm8001_ha->inbnd_q_tbl[i].pi_offset =
  126. pm8001_mr32(address, (offset + 0x18));
  127. }
  128. }
  129. /**
  130. * read_outbnd_queue_table - read the outbound queue table and save it.
  131. * @pm8001_ha: our hba card information
  132. */
  133. static void __devinit
  134. read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
  135. {
  136. int outbQ_num = 1;
  137. int i;
  138. void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
  139. for (i = 0; i < outbQ_num; i++) {
  140. u32 offset = i * 0x24;
  141. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
  142. get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
  143. pm8001_ha->outbnd_q_tbl[i].ci_offset =
  144. pm8001_mr32(address, (offset + 0x18));
  145. }
  146. }
  147. /**
  148. * init_default_table_values - init the default table.
  149. * @pm8001_ha: our hba card information
  150. */
  151. static void __devinit
  152. init_default_table_values(struct pm8001_hba_info *pm8001_ha)
  153. {
  154. int qn = 1;
  155. int i;
  156. u32 offsetib, offsetob;
  157. void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
  158. void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
  159. pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd = 0;
  160. pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3 = 0;
  161. pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7 = 0;
  162. pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3 = 0;
  163. pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7 = 0;
  164. pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3 = 0;
  165. pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7 = 0;
  166. pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
  167. pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
  168. pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3 = 0;
  169. pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7 = 0;
  170. pm8001_ha->main_cfg_tbl.upper_event_log_addr =
  171. pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
  172. pm8001_ha->main_cfg_tbl.lower_event_log_addr =
  173. pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
  174. pm8001_ha->main_cfg_tbl.event_log_size = PM8001_EVENT_LOG_SIZE;
  175. pm8001_ha->main_cfg_tbl.event_log_option = 0x01;
  176. pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr =
  177. pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
  178. pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr =
  179. pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
  180. pm8001_ha->main_cfg_tbl.iop_event_log_size = PM8001_EVENT_LOG_SIZE;
  181. pm8001_ha->main_cfg_tbl.iop_event_log_option = 0x01;
  182. pm8001_ha->main_cfg_tbl.fatal_err_interrupt = 0x01;
  183. for (i = 0; i < qn; i++) {
  184. pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
  185. 0x00000100 | (0x00000040 << 16) | (0x00<<30);
  186. pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
  187. pm8001_ha->memoryMap.region[IB].phys_addr_hi;
  188. pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
  189. pm8001_ha->memoryMap.region[IB].phys_addr_lo;
  190. pm8001_ha->inbnd_q_tbl[i].base_virt =
  191. (u8 *)pm8001_ha->memoryMap.region[IB].virt_ptr;
  192. pm8001_ha->inbnd_q_tbl[i].total_length =
  193. pm8001_ha->memoryMap.region[IB].total_len;
  194. pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
  195. pm8001_ha->memoryMap.region[CI].phys_addr_hi;
  196. pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
  197. pm8001_ha->memoryMap.region[CI].phys_addr_lo;
  198. pm8001_ha->inbnd_q_tbl[i].ci_virt =
  199. pm8001_ha->memoryMap.region[CI].virt_ptr;
  200. offsetib = i * 0x20;
  201. pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
  202. get_pci_bar_index(pm8001_mr32(addressib,
  203. (offsetib + 0x14)));
  204. pm8001_ha->inbnd_q_tbl[i].pi_offset =
  205. pm8001_mr32(addressib, (offsetib + 0x18));
  206. pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
  207. pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
  208. }
  209. for (i = 0; i < qn; i++) {
  210. pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
  211. 256 | (64 << 16) | (1<<30);
  212. pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
  213. pm8001_ha->memoryMap.region[OB].phys_addr_hi;
  214. pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
  215. pm8001_ha->memoryMap.region[OB].phys_addr_lo;
  216. pm8001_ha->outbnd_q_tbl[i].base_virt =
  217. (u8 *)pm8001_ha->memoryMap.region[OB].virt_ptr;
  218. pm8001_ha->outbnd_q_tbl[i].total_length =
  219. pm8001_ha->memoryMap.region[OB].total_len;
  220. pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
  221. pm8001_ha->memoryMap.region[PI].phys_addr_hi;
  222. pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
  223. pm8001_ha->memoryMap.region[PI].phys_addr_lo;
  224. pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay =
  225. 0 | (10 << 16) | (0 << 24);
  226. pm8001_ha->outbnd_q_tbl[i].pi_virt =
  227. pm8001_ha->memoryMap.region[PI].virt_ptr;
  228. offsetob = i * 0x24;
  229. pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
  230. get_pci_bar_index(pm8001_mr32(addressob,
  231. offsetob + 0x14));
  232. pm8001_ha->outbnd_q_tbl[i].ci_offset =
  233. pm8001_mr32(addressob, (offsetob + 0x18));
  234. pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
  235. pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
  236. }
  237. }
  238. /**
  239. * update_main_config_table - update the main default table to the HBA.
  240. * @pm8001_ha: our hba card information
  241. */
  242. static void __devinit
  243. update_main_config_table(struct pm8001_hba_info *pm8001_ha)
  244. {
  245. void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  246. pm8001_mw32(address, 0x24,
  247. pm8001_ha->main_cfg_tbl.inbound_q_nppd_hppd);
  248. pm8001_mw32(address, 0x28,
  249. pm8001_ha->main_cfg_tbl.outbound_hw_event_pid0_3);
  250. pm8001_mw32(address, 0x2C,
  251. pm8001_ha->main_cfg_tbl.outbound_hw_event_pid4_7);
  252. pm8001_mw32(address, 0x30,
  253. pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid0_3);
  254. pm8001_mw32(address, 0x34,
  255. pm8001_ha->main_cfg_tbl.outbound_ncq_event_pid4_7);
  256. pm8001_mw32(address, 0x38,
  257. pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid0_3);
  258. pm8001_mw32(address, 0x3C,
  259. pm8001_ha->main_cfg_tbl.outbound_tgt_ITNexus_event_pid4_7);
  260. pm8001_mw32(address, 0x40,
  261. pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid0_3);
  262. pm8001_mw32(address, 0x44,
  263. pm8001_ha->main_cfg_tbl.outbound_tgt_ssp_event_pid4_7);
  264. pm8001_mw32(address, 0x48,
  265. pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid0_3);
  266. pm8001_mw32(address, 0x4C,
  267. pm8001_ha->main_cfg_tbl.outbound_tgt_smp_event_pid4_7);
  268. pm8001_mw32(address, 0x50,
  269. pm8001_ha->main_cfg_tbl.upper_event_log_addr);
  270. pm8001_mw32(address, 0x54,
  271. pm8001_ha->main_cfg_tbl.lower_event_log_addr);
  272. pm8001_mw32(address, 0x58, pm8001_ha->main_cfg_tbl.event_log_size);
  273. pm8001_mw32(address, 0x5C, pm8001_ha->main_cfg_tbl.event_log_option);
  274. pm8001_mw32(address, 0x60,
  275. pm8001_ha->main_cfg_tbl.upper_iop_event_log_addr);
  276. pm8001_mw32(address, 0x64,
  277. pm8001_ha->main_cfg_tbl.lower_iop_event_log_addr);
  278. pm8001_mw32(address, 0x68, pm8001_ha->main_cfg_tbl.iop_event_log_size);
  279. pm8001_mw32(address, 0x6C,
  280. pm8001_ha->main_cfg_tbl.iop_event_log_option);
  281. pm8001_mw32(address, 0x70,
  282. pm8001_ha->main_cfg_tbl.fatal_err_interrupt);
  283. }
  284. /**
  285. * update_inbnd_queue_table - update the inbound queue table to the HBA.
  286. * @pm8001_ha: our hba card information
  287. */
  288. static void __devinit
  289. update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
  290. {
  291. void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
  292. u16 offset = number * 0x20;
  293. pm8001_mw32(address, offset + 0x00,
  294. pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
  295. pm8001_mw32(address, offset + 0x04,
  296. pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
  297. pm8001_mw32(address, offset + 0x08,
  298. pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
  299. pm8001_mw32(address, offset + 0x0C,
  300. pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
  301. pm8001_mw32(address, offset + 0x10,
  302. pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
  303. }
  304. /**
  305. * update_outbnd_queue_table - update the outbound queue table to the HBA.
  306. * @pm8001_ha: our hba card information
  307. */
  308. static void __devinit
  309. update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha, int number)
  310. {
  311. void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
  312. u16 offset = number * 0x24;
  313. pm8001_mw32(address, offset + 0x00,
  314. pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
  315. pm8001_mw32(address, offset + 0x04,
  316. pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
  317. pm8001_mw32(address, offset + 0x08,
  318. pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
  319. pm8001_mw32(address, offset + 0x0C,
  320. pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
  321. pm8001_mw32(address, offset + 0x10,
  322. pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
  323. pm8001_mw32(address, offset + 0x1C,
  324. pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
  325. }
  326. /**
  327. * bar4_shift - function is called to shift BAR base address
  328. * @pm8001_ha : our hba card infomation
  329. * @shiftValue : shifting value in memory bar.
  330. */
  331. static int bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
  332. {
  333. u32 regVal;
  334. u32 max_wait_count;
  335. /* program the inbound AXI translation Lower Address */
  336. pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
  337. /* confirm the setting is written */
  338. max_wait_count = 1 * 1000 * 1000; /* 1 sec */
  339. do {
  340. udelay(1);
  341. regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
  342. } while ((regVal != shiftValue) && (--max_wait_count));
  343. if (!max_wait_count) {
  344. PM8001_INIT_DBG(pm8001_ha,
  345. pm8001_printk("TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW"
  346. " = 0x%x\n", regVal));
  347. return -1;
  348. }
  349. return 0;
  350. }
  351. /**
  352. * mpi_set_phys_g3_with_ssc
  353. * @pm8001_ha: our hba card information
  354. * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
  355. */
  356. static void __devinit
  357. mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha, u32 SSCbit)
  358. {
  359. u32 offset;
  360. u32 value;
  361. u32 i, j;
  362. u32 bit_cnt;
  363. #define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
  364. #define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
  365. #define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
  366. #define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
  367. #define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
  368. #define PHY_G3_WITH_SSC_BIT_SHIFT 13
  369. #define SNW3_PHY_CAPABILITIES_PARITY 31
  370. /*
  371. * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
  372. * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
  373. */
  374. if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR))
  375. return;
  376. /* set SSC bit of PHY 0 - 3 */
  377. for (i = 0; i < 4; i++) {
  378. offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
  379. value = pm8001_cr32(pm8001_ha, 2, offset);
  380. if (SSCbit) {
  381. value |= 0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT;
  382. value &= ~(0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT);
  383. } else {
  384. value |= 0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT;
  385. value &= ~(0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT);
  386. }
  387. bit_cnt = 0;
  388. for (j = 0; j < 31; j++)
  389. if ((value >> j) & 0x00000001)
  390. bit_cnt++;
  391. if (bit_cnt % 2)
  392. value &= ~(0x00000001 << SNW3_PHY_CAPABILITIES_PARITY);
  393. else
  394. value |= 0x00000001 << SNW3_PHY_CAPABILITIES_PARITY;
  395. pm8001_cw32(pm8001_ha, 2, offset, value);
  396. }
  397. /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
  398. if (-1 == bar4_shift(pm8001_ha, SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR))
  399. return;
  400. /* set SSC bit of PHY 4 - 7 */
  401. for (i = 4; i < 8; i++) {
  402. offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
  403. value = pm8001_cr32(pm8001_ha, 2, offset);
  404. if (SSCbit) {
  405. value |= 0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT;
  406. value &= ~(0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT);
  407. } else {
  408. value |= 0x00000001 << PHY_G3_WITHOUT_SSC_BIT_SHIFT;
  409. value &= ~(0x00000001 << PHY_G3_WITH_SSC_BIT_SHIFT);
  410. }
  411. bit_cnt = 0;
  412. for (j = 0; j < 31; j++)
  413. if ((value >> j) & 0x00000001)
  414. bit_cnt++;
  415. if (bit_cnt % 2)
  416. value &= ~(0x00000001 << SNW3_PHY_CAPABILITIES_PARITY);
  417. else
  418. value |= 0x00000001 << SNW3_PHY_CAPABILITIES_PARITY;
  419. pm8001_cw32(pm8001_ha, 2, offset, value);
  420. }
  421. /*set the shifted destination address to 0x0 to avoid error operation */
  422. bar4_shift(pm8001_ha, 0x0);
  423. return;
  424. }
  425. /**
  426. * mpi_set_open_retry_interval_reg
  427. * @pm8001_ha: our hba card information
  428. * @interval - interval time for each OPEN_REJECT (RETRY). The units are in 1us.
  429. */
  430. static void __devinit
  431. mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
  432. u32 interval)
  433. {
  434. u32 offset;
  435. u32 value;
  436. u32 i;
  437. #define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
  438. #define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
  439. #define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
  440. #define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
  441. #define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
  442. value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
  443. /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
  444. if (-1 == bar4_shift(pm8001_ha,
  445. OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR))
  446. return;
  447. for (i = 0; i < 4; i++) {
  448. offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
  449. pm8001_cw32(pm8001_ha, 2, offset, value);
  450. }
  451. if (-1 == bar4_shift(pm8001_ha,
  452. OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR))
  453. return;
  454. for (i = 4; i < 8; i++) {
  455. offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
  456. pm8001_cw32(pm8001_ha, 2, offset, value);
  457. }
  458. /*set the shifted destination address to 0x0 to avoid error operation */
  459. bar4_shift(pm8001_ha, 0x0);
  460. return;
  461. }
  462. /**
  463. * mpi_init_check - check firmware initialization status.
  464. * @pm8001_ha: our hba card information
  465. */
  466. static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
  467. {
  468. u32 max_wait_count;
  469. u32 value;
  470. u32 gst_len_mpistate;
  471. /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
  472. table is updated */
  473. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
  474. /* wait until Inbound DoorBell Clear Register toggled */
  475. max_wait_count = 1 * 1000 * 1000;/* 1 sec */
  476. do {
  477. udelay(1);
  478. value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
  479. value &= SPC_MSGU_CFG_TABLE_UPDATE;
  480. } while ((value != 0) && (--max_wait_count));
  481. if (!max_wait_count)
  482. return -1;
  483. /* check the MPI-State for initialization */
  484. gst_len_mpistate =
  485. pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
  486. GST_GSTLEN_MPIS_OFFSET);
  487. if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
  488. return -1;
  489. /* check MPI Initialization error */
  490. gst_len_mpistate = gst_len_mpistate >> 16;
  491. if (0x0000 != gst_len_mpistate)
  492. return -1;
  493. return 0;
  494. }
  495. /**
  496. * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
  497. * @pm8001_ha: our hba card information
  498. */
  499. static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
  500. {
  501. u32 value, value1;
  502. u32 max_wait_count;
  503. /* check error state */
  504. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  505. value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  506. /* check AAP error */
  507. if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
  508. /* error state */
  509. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
  510. return -1;
  511. }
  512. /* check IOP error */
  513. if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
  514. /* error state */
  515. value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
  516. return -1;
  517. }
  518. /* bit 4-31 of scratch pad1 should be zeros if it is not
  519. in error state*/
  520. if (value & SCRATCH_PAD1_STATE_MASK) {
  521. /* error case */
  522. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
  523. return -1;
  524. }
  525. /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
  526. in error state */
  527. if (value1 & SCRATCH_PAD2_STATE_MASK) {
  528. /* error case */
  529. return -1;
  530. }
  531. max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
  532. /* wait until scratch pad 1 and 2 registers in ready state */
  533. do {
  534. udelay(1);
  535. value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
  536. & SCRATCH_PAD1_RDY;
  537. value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
  538. & SCRATCH_PAD2_RDY;
  539. if ((--max_wait_count) == 0)
  540. return -1;
  541. } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
  542. return 0;
  543. }
  544. static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
  545. {
  546. void __iomem *base_addr;
  547. u32 value;
  548. u32 offset;
  549. u32 pcibar;
  550. u32 pcilogic;
  551. value = pm8001_cr32(pm8001_ha, 0, 0x44);
  552. offset = value & 0x03FFFFFF;
  553. PM8001_INIT_DBG(pm8001_ha,
  554. pm8001_printk("Scratchpad 0 Offset: %x \n", offset));
  555. pcilogic = (value & 0xFC000000) >> 26;
  556. pcibar = get_pci_bar_index(pcilogic);
  557. PM8001_INIT_DBG(pm8001_ha,
  558. pm8001_printk("Scratchpad 0 PCI BAR: %d \n", pcibar));
  559. pm8001_ha->main_cfg_tbl_addr = base_addr =
  560. pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
  561. pm8001_ha->general_stat_tbl_addr =
  562. base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
  563. pm8001_ha->inbnd_q_tbl_addr =
  564. base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
  565. pm8001_ha->outbnd_q_tbl_addr =
  566. base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
  567. }
  568. /**
  569. * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
  570. * @pm8001_ha: our hba card information
  571. */
  572. static int __devinit pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
  573. {
  574. /* check the firmware status */
  575. if (-1 == check_fw_ready(pm8001_ha)) {
  576. PM8001_FAIL_DBG(pm8001_ha,
  577. pm8001_printk("Firmware is not ready!\n"));
  578. return -EBUSY;
  579. }
  580. /* Initialize pci space address eg: mpi offset */
  581. init_pci_device_addresses(pm8001_ha);
  582. init_default_table_values(pm8001_ha);
  583. read_main_config_table(pm8001_ha);
  584. read_general_status_table(pm8001_ha);
  585. read_inbnd_queue_table(pm8001_ha);
  586. read_outbnd_queue_table(pm8001_ha);
  587. /* update main config table ,inbound table and outbound table */
  588. update_main_config_table(pm8001_ha);
  589. update_inbnd_queue_table(pm8001_ha, 0);
  590. update_outbnd_queue_table(pm8001_ha, 0);
  591. mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
  592. mpi_set_open_retry_interval_reg(pm8001_ha, 7);
  593. /* notify firmware update finished and check initialization status */
  594. if (0 == mpi_init_check(pm8001_ha)) {
  595. PM8001_INIT_DBG(pm8001_ha,
  596. pm8001_printk("MPI initialize successful!\n"));
  597. } else
  598. return -EBUSY;
  599. /*This register is a 16-bit timer with a resolution of 1us. This is the
  600. timer used for interrupt delay/coalescing in the PCIe Application Layer.
  601. Zero is not a valid value. A value of 1 in the register will cause the
  602. interrupts to be normal. A value greater than 1 will cause coalescing
  603. delays.*/
  604. pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
  605. pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
  606. return 0;
  607. }
  608. static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
  609. {
  610. u32 max_wait_count;
  611. u32 value;
  612. u32 gst_len_mpistate;
  613. init_pci_device_addresses(pm8001_ha);
  614. /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
  615. table is stop */
  616. pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
  617. /* wait until Inbound DoorBell Clear Register toggled */
  618. max_wait_count = 1 * 1000 * 1000;/* 1 sec */
  619. do {
  620. udelay(1);
  621. value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
  622. value &= SPC_MSGU_CFG_TABLE_RESET;
  623. } while ((value != 0) && (--max_wait_count));
  624. if (!max_wait_count) {
  625. PM8001_FAIL_DBG(pm8001_ha,
  626. pm8001_printk("TIMEOUT:IBDB value/=0x%x\n", value));
  627. return -1;
  628. }
  629. /* check the MPI-State for termination in progress */
  630. /* wait until Inbound DoorBell Clear Register toggled */
  631. max_wait_count = 1 * 1000 * 1000; /* 1 sec */
  632. do {
  633. udelay(1);
  634. gst_len_mpistate =
  635. pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
  636. GST_GSTLEN_MPIS_OFFSET);
  637. if (GST_MPI_STATE_UNINIT ==
  638. (gst_len_mpistate & GST_MPI_STATE_MASK))
  639. break;
  640. } while (--max_wait_count);
  641. if (!max_wait_count) {
  642. PM8001_FAIL_DBG(pm8001_ha,
  643. pm8001_printk(" TIME OUT MPI State = 0x%x\n",
  644. gst_len_mpistate & GST_MPI_STATE_MASK));
  645. return -1;
  646. }
  647. return 0;
  648. }
  649. /**
  650. * soft_reset_ready_check - Function to check FW is ready for soft reset.
  651. * @pm8001_ha: our hba card information
  652. */
  653. static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
  654. {
  655. u32 regVal, regVal1, regVal2;
  656. if (mpi_uninit_check(pm8001_ha) != 0) {
  657. PM8001_FAIL_DBG(pm8001_ha,
  658. pm8001_printk("MPI state is not ready\n"));
  659. return -1;
  660. }
  661. /* read the scratch pad 2 register bit 2 */
  662. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
  663. & SCRATCH_PAD2_FWRDY_RST;
  664. if (regVal == SCRATCH_PAD2_FWRDY_RST) {
  665. PM8001_INIT_DBG(pm8001_ha,
  666. pm8001_printk("Firmware is ready for reset .\n"));
  667. } else {
  668. /* Trigger NMI twice via RB6 */
  669. if (-1 == bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
  670. PM8001_FAIL_DBG(pm8001_ha,
  671. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  672. RB6_ACCESS_REG));
  673. return -1;
  674. }
  675. pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
  676. RB6_MAGIC_NUMBER_RST);
  677. pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
  678. /* wait for 100 ms */
  679. mdelay(100);
  680. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
  681. SCRATCH_PAD2_FWRDY_RST;
  682. if (regVal != SCRATCH_PAD2_FWRDY_RST) {
  683. regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  684. regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  685. PM8001_FAIL_DBG(pm8001_ha,
  686. pm8001_printk("TIMEOUT:MSGU_SCRATCH_PAD1"
  687. "=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
  688. regVal1, regVal2));
  689. PM8001_FAIL_DBG(pm8001_ha,
  690. pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
  691. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0)));
  692. PM8001_FAIL_DBG(pm8001_ha,
  693. pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
  694. pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3)));
  695. return -1;
  696. }
  697. }
  698. return 0;
  699. }
  700. /**
  701. * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
  702. * the FW register status to the originated status.
  703. * @pm8001_ha: our hba card information
  704. * @signature: signature in host scratch pad0 register.
  705. */
  706. static int
  707. pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha, u32 signature)
  708. {
  709. u32 regVal, toggleVal;
  710. u32 max_wait_count;
  711. u32 regVal1, regVal2, regVal3;
  712. /* step1: Check FW is ready for soft reset */
  713. if (soft_reset_ready_check(pm8001_ha) != 0) {
  714. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("FW is not ready\n"));
  715. return -1;
  716. }
  717. /* step 2: clear NMI status register on AAP1 and IOP, write the same
  718. value to clear */
  719. /* map 0x60000 to BAR4(0x20), BAR2(win) */
  720. if (-1 == bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
  721. PM8001_FAIL_DBG(pm8001_ha,
  722. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  723. MBIC_AAP1_ADDR_BASE));
  724. return -1;
  725. }
  726. regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
  727. PM8001_INIT_DBG(pm8001_ha,
  728. pm8001_printk("MBIC - NMI Enable VPE0 (IOP)= 0x%x\n", regVal));
  729. pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
  730. /* map 0x70000 to BAR4(0x20), BAR2(win) */
  731. if (-1 == bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
  732. PM8001_FAIL_DBG(pm8001_ha,
  733. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  734. MBIC_IOP_ADDR_BASE));
  735. return -1;
  736. }
  737. regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
  738. PM8001_INIT_DBG(pm8001_ha,
  739. pm8001_printk("MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n", regVal));
  740. pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
  741. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
  742. PM8001_INIT_DBG(pm8001_ha,
  743. pm8001_printk("PCIE -Event Interrupt Enable = 0x%x\n", regVal));
  744. pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
  745. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
  746. PM8001_INIT_DBG(pm8001_ha,
  747. pm8001_printk("PCIE - Event Interrupt = 0x%x\n", regVal));
  748. pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
  749. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
  750. PM8001_INIT_DBG(pm8001_ha,
  751. pm8001_printk("PCIE -Error Interrupt Enable = 0x%x\n", regVal));
  752. pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
  753. regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
  754. PM8001_INIT_DBG(pm8001_ha,
  755. pm8001_printk("PCIE - Error Interrupt = 0x%x\n", regVal));
  756. pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
  757. /* read the scratch pad 1 register bit 2 */
  758. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
  759. & SCRATCH_PAD1_RST;
  760. toggleVal = regVal ^ SCRATCH_PAD1_RST;
  761. /* set signature in host scratch pad0 register to tell SPC that the
  762. host performs the soft reset */
  763. pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
  764. /* read required registers for confirmming */
  765. /* map 0x0700000 to BAR4(0x20), BAR2(win) */
  766. if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
  767. PM8001_FAIL_DBG(pm8001_ha,
  768. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  769. GSM_ADDR_BASE));
  770. return -1;
  771. }
  772. PM8001_INIT_DBG(pm8001_ha,
  773. pm8001_printk("GSM 0x0(0x00007b88)-GSM Configuration and"
  774. " Reset = 0x%x\n",
  775. pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  776. /* step 3: host read GSM Configuration and Reset register */
  777. regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
  778. /* Put those bits to low */
  779. /* GSM XCBI offset = 0x70 0000
  780. 0x00 Bit 13 COM_SLV_SW_RSTB 1
  781. 0x00 Bit 12 QSSP_SW_RSTB 1
  782. 0x00 Bit 11 RAAE_SW_RSTB 1
  783. 0x00 Bit 9 RB_1_SW_RSTB 1
  784. 0x00 Bit 8 SM_SW_RSTB 1
  785. */
  786. regVal &= ~(0x00003b00);
  787. /* host write GSM Configuration and Reset register */
  788. pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
  789. PM8001_INIT_DBG(pm8001_ha,
  790. pm8001_printk("GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM "
  791. "Configuration and Reset is set to = 0x%x\n",
  792. pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  793. /* step 4: */
  794. /* disable GSM - Read Address Parity Check */
  795. regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
  796. PM8001_INIT_DBG(pm8001_ha,
  797. pm8001_printk("GSM 0x700038 - Read Address Parity Check "
  798. "Enable = 0x%x\n", regVal1));
  799. pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
  800. PM8001_INIT_DBG(pm8001_ha,
  801. pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
  802. "is set to = 0x%x\n",
  803. pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
  804. /* disable GSM - Write Address Parity Check */
  805. regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
  806. PM8001_INIT_DBG(pm8001_ha,
  807. pm8001_printk("GSM 0x700040 - Write Address Parity Check"
  808. " Enable = 0x%x\n", regVal2));
  809. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
  810. PM8001_INIT_DBG(pm8001_ha,
  811. pm8001_printk("GSM 0x700040 - Write Address Parity Check "
  812. "Enable is set to = 0x%x\n",
  813. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
  814. /* disable GSM - Write Data Parity Check */
  815. regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
  816. PM8001_INIT_DBG(pm8001_ha,
  817. pm8001_printk("GSM 0x300048 - Write Data Parity Check"
  818. " Enable = 0x%x\n", regVal3));
  819. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
  820. PM8001_INIT_DBG(pm8001_ha,
  821. pm8001_printk("GSM 0x300048 - Write Data Parity Check Enable"
  822. "is set to = 0x%x\n",
  823. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
  824. /* step 5: delay 10 usec */
  825. udelay(10);
  826. /* step 5-b: set GPIO-0 output control to tristate anyway */
  827. if (-1 == bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
  828. PM8001_INIT_DBG(pm8001_ha,
  829. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  830. GPIO_ADDR_BASE));
  831. return -1;
  832. }
  833. regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
  834. PM8001_INIT_DBG(pm8001_ha,
  835. pm8001_printk("GPIO Output Control Register:"
  836. " = 0x%x\n", regVal));
  837. /* set GPIO-0 output control to tri-state */
  838. regVal &= 0xFFFFFFFC;
  839. pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
  840. /* Step 6: Reset the IOP and AAP1 */
  841. /* map 0x00000 to BAR4(0x20), BAR2(win) */
  842. if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
  843. PM8001_FAIL_DBG(pm8001_ha,
  844. pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
  845. SPC_TOP_LEVEL_ADDR_BASE));
  846. return -1;
  847. }
  848. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  849. PM8001_INIT_DBG(pm8001_ha,
  850. pm8001_printk("Top Register before resetting IOP/AAP1"
  851. ":= 0x%x\n", regVal));
  852. regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
  853. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  854. /* step 7: Reset the BDMA/OSSP */
  855. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  856. PM8001_INIT_DBG(pm8001_ha,
  857. pm8001_printk("Top Register before resetting BDMA/OSSP"
  858. ": = 0x%x\n", regVal));
  859. regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
  860. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  861. /* step 8: delay 10 usec */
  862. udelay(10);
  863. /* step 9: bring the BDMA and OSSP out of reset */
  864. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  865. PM8001_INIT_DBG(pm8001_ha,
  866. pm8001_printk("Top Register before bringing up BDMA/OSSP"
  867. ":= 0x%x\n", regVal));
  868. regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
  869. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  870. /* step 10: delay 10 usec */
  871. udelay(10);
  872. /* step 11: reads and sets the GSM Configuration and Reset Register */
  873. /* map 0x0700000 to BAR4(0x20), BAR2(win) */
  874. if (-1 == bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
  875. PM8001_FAIL_DBG(pm8001_ha,
  876. pm8001_printk("SPC Shift Bar4 to 0x%x failed\n",
  877. GSM_ADDR_BASE));
  878. return -1;
  879. }
  880. PM8001_INIT_DBG(pm8001_ha,
  881. pm8001_printk("GSM 0x0 (0x00007b88)-GSM Configuration and "
  882. "Reset = 0x%x\n", pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  883. regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
  884. /* Put those bits to high */
  885. /* GSM XCBI offset = 0x70 0000
  886. 0x00 Bit 13 COM_SLV_SW_RSTB 1
  887. 0x00 Bit 12 QSSP_SW_RSTB 1
  888. 0x00 Bit 11 RAAE_SW_RSTB 1
  889. 0x00 Bit 9 RB_1_SW_RSTB 1
  890. 0x00 Bit 8 SM_SW_RSTB 1
  891. */
  892. regVal |= (GSM_CONFIG_RESET_VALUE);
  893. pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
  894. PM8001_INIT_DBG(pm8001_ha,
  895. pm8001_printk("GSM (0x00004088 ==> 0x00007b88) - GSM"
  896. " Configuration and Reset is set to = 0x%x\n",
  897. pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET)));
  898. /* step 12: Restore GSM - Read Address Parity Check */
  899. regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
  900. /* just for debugging */
  901. PM8001_INIT_DBG(pm8001_ha,
  902. pm8001_printk("GSM 0x700038 - Read Address Parity Check Enable"
  903. " = 0x%x\n", regVal));
  904. pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
  905. PM8001_INIT_DBG(pm8001_ha,
  906. pm8001_printk("GSM 0x700038 - Read Address Parity"
  907. " Check Enable is set to = 0x%x\n",
  908. pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK)));
  909. /* Restore GSM - Write Address Parity Check */
  910. regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
  911. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
  912. PM8001_INIT_DBG(pm8001_ha,
  913. pm8001_printk("GSM 0x700040 - Write Address Parity Check"
  914. " Enable is set to = 0x%x\n",
  915. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK)));
  916. /* Restore GSM - Write Data Parity Check */
  917. regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
  918. pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
  919. PM8001_INIT_DBG(pm8001_ha,
  920. pm8001_printk("GSM 0x700048 - Write Data Parity Check Enable"
  921. "is set to = 0x%x\n",
  922. pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK)));
  923. /* step 13: bring the IOP and AAP1 out of reset */
  924. /* map 0x00000 to BAR4(0x20), BAR2(win) */
  925. if (-1 == bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
  926. PM8001_FAIL_DBG(pm8001_ha,
  927. pm8001_printk("Shift Bar4 to 0x%x failed\n",
  928. SPC_TOP_LEVEL_ADDR_BASE));
  929. return -1;
  930. }
  931. regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
  932. regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
  933. pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
  934. /* step 14: delay 10 usec - Normal Mode */
  935. udelay(10);
  936. /* check Soft Reset Normal mode or Soft Reset HDA mode */
  937. if (signature == SPC_SOFT_RESET_SIGNATURE) {
  938. /* step 15 (Normal Mode): wait until scratch pad1 register
  939. bit 2 toggled */
  940. max_wait_count = 2 * 1000 * 1000;/* 2 sec */
  941. do {
  942. udelay(1);
  943. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
  944. SCRATCH_PAD1_RST;
  945. } while ((regVal != toggleVal) && (--max_wait_count));
  946. if (!max_wait_count) {
  947. regVal = pm8001_cr32(pm8001_ha, 0,
  948. MSGU_SCRATCH_PAD_1);
  949. PM8001_FAIL_DBG(pm8001_ha,
  950. pm8001_printk("TIMEOUT : ToggleVal 0x%x,"
  951. "MSGU_SCRATCH_PAD1 = 0x%x\n",
  952. toggleVal, regVal));
  953. PM8001_FAIL_DBG(pm8001_ha,
  954. pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
  955. pm8001_cr32(pm8001_ha, 0,
  956. MSGU_SCRATCH_PAD_0)));
  957. PM8001_FAIL_DBG(pm8001_ha,
  958. pm8001_printk("SCRATCH_PAD2 value = 0x%x\n",
  959. pm8001_cr32(pm8001_ha, 0,
  960. MSGU_SCRATCH_PAD_2)));
  961. PM8001_FAIL_DBG(pm8001_ha,
  962. pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
  963. pm8001_cr32(pm8001_ha, 0,
  964. MSGU_SCRATCH_PAD_3)));
  965. return -1;
  966. }
  967. /* step 16 (Normal) - Clear ODMR and ODCR */
  968. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
  969. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
  970. /* step 17 (Normal Mode): wait for the FW and IOP to get
  971. ready - 1 sec timeout */
  972. /* Wait for the SPC Configuration Table to be ready */
  973. if (check_fw_ready(pm8001_ha) == -1) {
  974. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
  975. /* return error if MPI Configuration Table not ready */
  976. PM8001_INIT_DBG(pm8001_ha,
  977. pm8001_printk("FW not ready SCRATCH_PAD1"
  978. " = 0x%x\n", regVal));
  979. regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
  980. /* return error if MPI Configuration Table not ready */
  981. PM8001_INIT_DBG(pm8001_ha,
  982. pm8001_printk("FW not ready SCRATCH_PAD2"
  983. " = 0x%x\n", regVal));
  984. PM8001_INIT_DBG(pm8001_ha,
  985. pm8001_printk("SCRATCH_PAD0 value = 0x%x\n",
  986. pm8001_cr32(pm8001_ha, 0,
  987. MSGU_SCRATCH_PAD_0)));
  988. PM8001_INIT_DBG(pm8001_ha,
  989. pm8001_printk("SCRATCH_PAD3 value = 0x%x\n",
  990. pm8001_cr32(pm8001_ha, 0,
  991. MSGU_SCRATCH_PAD_3)));
  992. return -1;
  993. }
  994. }
  995. PM8001_INIT_DBG(pm8001_ha,
  996. pm8001_printk("SPC soft reset Complete\n"));
  997. return 0;
  998. }
  999. static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
  1000. {
  1001. u32 i;
  1002. u32 regVal;
  1003. PM8001_INIT_DBG(pm8001_ha,
  1004. pm8001_printk("chip reset start\n"));
  1005. /* do SPC chip reset. */
  1006. regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
  1007. regVal &= ~(SPC_REG_RESET_DEVICE);
  1008. pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
  1009. /* delay 10 usec */
  1010. udelay(10);
  1011. /* bring chip reset out of reset */
  1012. regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
  1013. regVal |= SPC_REG_RESET_DEVICE;
  1014. pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
  1015. /* delay 10 usec */
  1016. udelay(10);
  1017. /* wait for 20 msec until the firmware gets reloaded */
  1018. i = 20;
  1019. do {
  1020. mdelay(1);
  1021. } while ((--i) != 0);
  1022. PM8001_INIT_DBG(pm8001_ha,
  1023. pm8001_printk("chip reset finished\n"));
  1024. }
  1025. /**
  1026. * pm8001_chip_iounmap - which maped when initilized.
  1027. * @pm8001_ha: our hba card information
  1028. */
  1029. static void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
  1030. {
  1031. s8 bar, logical = 0;
  1032. for (bar = 0; bar < 6; bar++) {
  1033. /*
  1034. ** logical BARs for SPC:
  1035. ** bar 0 and 1 - logical BAR0
  1036. ** bar 2 and 3 - logical BAR1
  1037. ** bar4 - logical BAR2
  1038. ** bar5 - logical BAR3
  1039. ** Skip the appropriate assignments:
  1040. */
  1041. if ((bar == 1) || (bar == 3))
  1042. continue;
  1043. if (pm8001_ha->io_mem[logical].memvirtaddr) {
  1044. iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
  1045. logical++;
  1046. }
  1047. }
  1048. }
  1049. /**
  1050. * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
  1051. * @pm8001_ha: our hba card information
  1052. */
  1053. static void
  1054. pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
  1055. {
  1056. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
  1057. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
  1058. }
  1059. /**
  1060. * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
  1061. * @pm8001_ha: our hba card information
  1062. */
  1063. static void
  1064. pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
  1065. {
  1066. pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
  1067. }
  1068. /**
  1069. * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
  1070. * @pm8001_ha: our hba card information
  1071. */
  1072. static void
  1073. pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
  1074. u32 int_vec_idx)
  1075. {
  1076. u32 msi_index;
  1077. u32 value;
  1078. msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
  1079. msi_index += MSIX_TABLE_BASE;
  1080. pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
  1081. value = (1 << int_vec_idx);
  1082. pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, value);
  1083. }
  1084. /**
  1085. * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
  1086. * @pm8001_ha: our hba card information
  1087. */
  1088. static void
  1089. pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
  1090. u32 int_vec_idx)
  1091. {
  1092. u32 msi_index;
  1093. msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
  1094. msi_index += MSIX_TABLE_BASE;
  1095. pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_DISABLE);
  1096. }
  1097. /**
  1098. * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
  1099. * @pm8001_ha: our hba card information
  1100. */
  1101. static void
  1102. pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
  1103. {
  1104. #ifdef PM8001_USE_MSIX
  1105. pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
  1106. return;
  1107. #endif
  1108. pm8001_chip_intx_interrupt_enable(pm8001_ha);
  1109. }
  1110. /**
  1111. * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
  1112. * @pm8001_ha: our hba card information
  1113. */
  1114. static void
  1115. pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
  1116. {
  1117. #ifdef PM8001_USE_MSIX
  1118. pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
  1119. return;
  1120. #endif
  1121. pm8001_chip_intx_interrupt_disable(pm8001_ha);
  1122. }
  1123. /**
  1124. * mpi_msg_free_get- get the free message buffer for transfer inbound queue.
  1125. * @circularQ: the inbound queue we want to transfer to HBA.
  1126. * @messageSize: the message size of this transfer, normally it is 64 bytes
  1127. * @messagePtr: the pointer to message.
  1128. */
  1129. static int mpi_msg_free_get(struct inbound_queue_table *circularQ,
  1130. u16 messageSize, void **messagePtr)
  1131. {
  1132. u32 offset, consumer_index;
  1133. struct mpi_msg_hdr *msgHeader;
  1134. u8 bcCount = 1; /* only support single buffer */
  1135. /* Checks is the requested message size can be allocated in this queue*/
  1136. if (messageSize > 64) {
  1137. *messagePtr = NULL;
  1138. return -1;
  1139. }
  1140. /* Stores the new consumer index */
  1141. consumer_index = pm8001_read_32(circularQ->ci_virt);
  1142. circularQ->consumer_index = cpu_to_le32(consumer_index);
  1143. if (((circularQ->producer_idx + bcCount) % 256) ==
  1144. circularQ->consumer_index) {
  1145. *messagePtr = NULL;
  1146. return -1;
  1147. }
  1148. /* get memory IOMB buffer address */
  1149. offset = circularQ->producer_idx * 64;
  1150. /* increment to next bcCount element */
  1151. circularQ->producer_idx = (circularQ->producer_idx + bcCount) % 256;
  1152. /* Adds that distance to the base of the region virtual address plus
  1153. the message header size*/
  1154. msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
  1155. *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
  1156. return 0;
  1157. }
  1158. /**
  1159. * mpi_build_cmd- build the message queue for transfer, update the PI to FW
  1160. * to tell the fw to get this message from IOMB.
  1161. * @pm8001_ha: our hba card information
  1162. * @circularQ: the inbound queue we want to transfer to HBA.
  1163. * @opCode: the operation code represents commands which LLDD and fw recognized.
  1164. * @payload: the command payload of each operation command.
  1165. */
  1166. static int mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
  1167. struct inbound_queue_table *circularQ,
  1168. u32 opCode, void *payload)
  1169. {
  1170. u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
  1171. u32 responseQueue = 0;
  1172. void *pMessage;
  1173. if (mpi_msg_free_get(circularQ, 64, &pMessage) < 0) {
  1174. PM8001_IO_DBG(pm8001_ha,
  1175. pm8001_printk("No free mpi buffer \n"));
  1176. return -1;
  1177. }
  1178. BUG_ON(!payload);
  1179. /*Copy to the payload*/
  1180. memcpy(pMessage, payload, (64 - sizeof(struct mpi_msg_hdr)));
  1181. /*Build the header*/
  1182. Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
  1183. | ((responseQueue & 0x3F) << 16)
  1184. | ((category & 0xF) << 12) | (opCode & 0xFFF));
  1185. pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
  1186. /*Update the PI to the firmware*/
  1187. pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
  1188. circularQ->pi_offset, circularQ->producer_idx);
  1189. PM8001_IO_DBG(pm8001_ha,
  1190. pm8001_printk("after PI= %d CI= %d \n", circularQ->producer_idx,
  1191. circularQ->consumer_index));
  1192. return 0;
  1193. }
  1194. static u32 mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
  1195. struct outbound_queue_table *circularQ, u8 bc)
  1196. {
  1197. u32 producer_index;
  1198. struct mpi_msg_hdr *msgHeader;
  1199. struct mpi_msg_hdr *pOutBoundMsgHeader;
  1200. msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
  1201. pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
  1202. circularQ->consumer_idx * 64);
  1203. if (pOutBoundMsgHeader != msgHeader) {
  1204. PM8001_FAIL_DBG(pm8001_ha,
  1205. pm8001_printk("consumer_idx = %d msgHeader = %p\n",
  1206. circularQ->consumer_idx, msgHeader));
  1207. /* Update the producer index from SPC */
  1208. producer_index = pm8001_read_32(circularQ->pi_virt);
  1209. circularQ->producer_index = cpu_to_le32(producer_index);
  1210. PM8001_FAIL_DBG(pm8001_ha,
  1211. pm8001_printk("consumer_idx = %d producer_index = %d"
  1212. "msgHeader = %p\n", circularQ->consumer_idx,
  1213. circularQ->producer_index, msgHeader));
  1214. return 0;
  1215. }
  1216. /* free the circular queue buffer elements associated with the message*/
  1217. circularQ->consumer_idx = (circularQ->consumer_idx + bc) % 256;
  1218. /* update the CI of outbound queue */
  1219. pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
  1220. circularQ->consumer_idx);
  1221. /* Update the producer index from SPC*/
  1222. producer_index = pm8001_read_32(circularQ->pi_virt);
  1223. circularQ->producer_index = cpu_to_le32(producer_index);
  1224. PM8001_IO_DBG(pm8001_ha,
  1225. pm8001_printk(" CI=%d PI=%d\n", circularQ->consumer_idx,
  1226. circularQ->producer_index));
  1227. return 0;
  1228. }
  1229. /**
  1230. * mpi_msg_consume- get the MPI message from outbound queue message table.
  1231. * @pm8001_ha: our hba card information
  1232. * @circularQ: the outbound queue table.
  1233. * @messagePtr1: the message contents of this outbound message.
  1234. * @pBC: the message size.
  1235. */
  1236. static u32 mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
  1237. struct outbound_queue_table *circularQ,
  1238. void **messagePtr1, u8 *pBC)
  1239. {
  1240. struct mpi_msg_hdr *msgHeader;
  1241. __le32 msgHeader_tmp;
  1242. u32 header_tmp;
  1243. do {
  1244. /* If there are not-yet-delivered messages ... */
  1245. if (circularQ->producer_index != circularQ->consumer_idx) {
  1246. /*Get the pointer to the circular queue buffer element*/
  1247. msgHeader = (struct mpi_msg_hdr *)
  1248. (circularQ->base_virt +
  1249. circularQ->consumer_idx * 64);
  1250. /* read header */
  1251. header_tmp = pm8001_read_32(msgHeader);
  1252. msgHeader_tmp = cpu_to_le32(header_tmp);
  1253. if (0 != (msgHeader_tmp & 0x80000000)) {
  1254. if (OPC_OUB_SKIP_ENTRY !=
  1255. (msgHeader_tmp & 0xfff)) {
  1256. *messagePtr1 =
  1257. ((u8 *)msgHeader) +
  1258. sizeof(struct mpi_msg_hdr);
  1259. *pBC = (u8)((msgHeader_tmp >> 24) &
  1260. 0x1f);
  1261. PM8001_IO_DBG(pm8001_ha,
  1262. pm8001_printk(": CI=%d PI=%d "
  1263. "msgHeader=%x\n",
  1264. circularQ->consumer_idx,
  1265. circularQ->producer_index,
  1266. msgHeader_tmp));
  1267. return MPI_IO_STATUS_SUCCESS;
  1268. } else {
  1269. circularQ->consumer_idx =
  1270. (circularQ->consumer_idx +
  1271. ((msgHeader_tmp >> 24) & 0x1f))
  1272. % 256;
  1273. msgHeader_tmp = 0;
  1274. pm8001_write_32(msgHeader, 0, 0);
  1275. /* update the CI of outbound queue */
  1276. pm8001_cw32(pm8001_ha,
  1277. circularQ->ci_pci_bar,
  1278. circularQ->ci_offset,
  1279. circularQ->consumer_idx);
  1280. }
  1281. } else {
  1282. circularQ->consumer_idx =
  1283. (circularQ->consumer_idx +
  1284. ((msgHeader_tmp >> 24) & 0x1f)) % 256;
  1285. msgHeader_tmp = 0;
  1286. pm8001_write_32(msgHeader, 0, 0);
  1287. /* update the CI of outbound queue */
  1288. pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
  1289. circularQ->ci_offset,
  1290. circularQ->consumer_idx);
  1291. return MPI_IO_STATUS_FAIL;
  1292. }
  1293. } else {
  1294. u32 producer_index;
  1295. void *pi_virt = circularQ->pi_virt;
  1296. /* Update the producer index from SPC */
  1297. producer_index = pm8001_read_32(pi_virt);
  1298. circularQ->producer_index = cpu_to_le32(producer_index);
  1299. }
  1300. } while (circularQ->producer_index != circularQ->consumer_idx);
  1301. /* while we don't have any more not-yet-delivered message */
  1302. /* report empty */
  1303. return MPI_IO_STATUS_BUSY;
  1304. }
  1305. static void pm8001_work_queue(struct work_struct *work)
  1306. {
  1307. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1308. struct pm8001_wq *wq = container_of(dw, struct pm8001_wq, work_q);
  1309. struct pm8001_device *pm8001_dev;
  1310. struct domain_device *dev;
  1311. switch (wq->handler) {
  1312. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1313. pm8001_dev = wq->data;
  1314. dev = pm8001_dev->sas_device;
  1315. pm8001_I_T_nexus_reset(dev);
  1316. break;
  1317. case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
  1318. pm8001_dev = wq->data;
  1319. dev = pm8001_dev->sas_device;
  1320. pm8001_I_T_nexus_reset(dev);
  1321. break;
  1322. case IO_DS_IN_ERROR:
  1323. pm8001_dev = wq->data;
  1324. dev = pm8001_dev->sas_device;
  1325. pm8001_I_T_nexus_reset(dev);
  1326. break;
  1327. case IO_DS_NON_OPERATIONAL:
  1328. pm8001_dev = wq->data;
  1329. dev = pm8001_dev->sas_device;
  1330. pm8001_I_T_nexus_reset(dev);
  1331. break;
  1332. }
  1333. list_del(&wq->entry);
  1334. kfree(wq);
  1335. }
  1336. static int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
  1337. int handler)
  1338. {
  1339. struct pm8001_wq *wq;
  1340. int ret = 0;
  1341. wq = kmalloc(sizeof(struct pm8001_wq), GFP_ATOMIC);
  1342. if (wq) {
  1343. wq->pm8001_ha = pm8001_ha;
  1344. wq->data = data;
  1345. wq->handler = handler;
  1346. INIT_DELAYED_WORK(&wq->work_q, pm8001_work_queue);
  1347. list_add_tail(&wq->entry, &pm8001_ha->wq_list);
  1348. schedule_delayed_work(&wq->work_q, 0);
  1349. } else
  1350. ret = -ENOMEM;
  1351. return ret;
  1352. }
  1353. /**
  1354. * mpi_ssp_completion- process the event that FW response to the SSP request.
  1355. * @pm8001_ha: our hba card information
  1356. * @piomb: the message contents of this outbound message.
  1357. *
  1358. * When FW has completed a ssp request for example a IO request, after it has
  1359. * filled the SG data with the data, it will trigger this event represent
  1360. * that he has finished the job,please check the coresponding buffer.
  1361. * So we will tell the caller who maybe waiting the result to tell upper layer
  1362. * that the task has been finished.
  1363. */
  1364. static void
  1365. mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
  1366. {
  1367. struct sas_task *t;
  1368. struct pm8001_ccb_info *ccb;
  1369. unsigned long flags;
  1370. u32 status;
  1371. u32 param;
  1372. u32 tag;
  1373. struct ssp_completion_resp *psspPayload;
  1374. struct task_status_struct *ts;
  1375. struct ssp_response_iu *iu;
  1376. struct pm8001_device *pm8001_dev;
  1377. psspPayload = (struct ssp_completion_resp *)(piomb + 4);
  1378. status = le32_to_cpu(psspPayload->status);
  1379. tag = le32_to_cpu(psspPayload->tag);
  1380. ccb = &pm8001_ha->ccb_info[tag];
  1381. pm8001_dev = ccb->device;
  1382. param = le32_to_cpu(psspPayload->param);
  1383. t = ccb->task;
  1384. if (status && status != IO_UNDERFLOW)
  1385. PM8001_FAIL_DBG(pm8001_ha,
  1386. pm8001_printk("sas IO status 0x%x\n", status));
  1387. if (unlikely(!t || !t->lldd_task || !t->dev))
  1388. return;
  1389. ts = &t->task_status;
  1390. switch (status) {
  1391. case IO_SUCCESS:
  1392. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS"
  1393. ",param = %d \n", param));
  1394. if (param == 0) {
  1395. ts->resp = SAS_TASK_COMPLETE;
  1396. ts->stat = SAM_GOOD;
  1397. } else {
  1398. ts->resp = SAS_TASK_COMPLETE;
  1399. ts->stat = SAS_PROTO_RESPONSE;
  1400. ts->residual = param;
  1401. iu = &psspPayload->ssp_resp_iu;
  1402. sas_ssp_task_response(pm8001_ha->dev, t, iu);
  1403. }
  1404. if (pm8001_dev)
  1405. pm8001_dev->running_req--;
  1406. break;
  1407. case IO_ABORTED:
  1408. PM8001_IO_DBG(pm8001_ha,
  1409. pm8001_printk("IO_ABORTED IOMB Tag \n"));
  1410. ts->resp = SAS_TASK_COMPLETE;
  1411. ts->stat = SAS_ABORTED_TASK;
  1412. break;
  1413. case IO_UNDERFLOW:
  1414. /* SSP Completion with error */
  1415. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW"
  1416. ",param = %d \n", param));
  1417. ts->resp = SAS_TASK_COMPLETE;
  1418. ts->stat = SAS_DATA_UNDERRUN;
  1419. ts->residual = param;
  1420. if (pm8001_dev)
  1421. pm8001_dev->running_req--;
  1422. break;
  1423. case IO_NO_DEVICE:
  1424. PM8001_IO_DBG(pm8001_ha,
  1425. pm8001_printk("IO_NO_DEVICE\n"));
  1426. ts->resp = SAS_TASK_UNDELIVERED;
  1427. ts->stat = SAS_PHY_DOWN;
  1428. break;
  1429. case IO_XFER_ERROR_BREAK:
  1430. PM8001_IO_DBG(pm8001_ha,
  1431. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  1432. ts->resp = SAS_TASK_COMPLETE;
  1433. ts->stat = SAS_OPEN_REJECT;
  1434. break;
  1435. case IO_XFER_ERROR_PHY_NOT_READY:
  1436. PM8001_IO_DBG(pm8001_ha,
  1437. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  1438. ts->resp = SAS_TASK_COMPLETE;
  1439. ts->stat = SAS_OPEN_REJECT;
  1440. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1441. break;
  1442. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  1443. PM8001_IO_DBG(pm8001_ha,
  1444. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
  1445. ts->resp = SAS_TASK_COMPLETE;
  1446. ts->stat = SAS_OPEN_REJECT;
  1447. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1448. break;
  1449. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  1450. PM8001_IO_DBG(pm8001_ha,
  1451. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  1452. ts->resp = SAS_TASK_COMPLETE;
  1453. ts->stat = SAS_OPEN_REJECT;
  1454. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1455. break;
  1456. case IO_OPEN_CNX_ERROR_BREAK:
  1457. PM8001_IO_DBG(pm8001_ha,
  1458. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  1459. ts->resp = SAS_TASK_COMPLETE;
  1460. ts->stat = SAS_OPEN_REJECT;
  1461. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1462. break;
  1463. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1464. PM8001_IO_DBG(pm8001_ha,
  1465. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  1466. ts->resp = SAS_TASK_COMPLETE;
  1467. ts->stat = SAS_OPEN_REJECT;
  1468. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1469. if (!t->uldd_task)
  1470. pm8001_handle_event(pm8001_ha,
  1471. pm8001_dev,
  1472. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  1473. break;
  1474. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  1475. PM8001_IO_DBG(pm8001_ha,
  1476. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  1477. ts->resp = SAS_TASK_COMPLETE;
  1478. ts->stat = SAS_OPEN_REJECT;
  1479. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  1480. break;
  1481. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  1482. PM8001_IO_DBG(pm8001_ha,
  1483. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  1484. "NOT_SUPPORTED\n"));
  1485. ts->resp = SAS_TASK_COMPLETE;
  1486. ts->stat = SAS_OPEN_REJECT;
  1487. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1488. break;
  1489. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  1490. PM8001_IO_DBG(pm8001_ha,
  1491. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  1492. ts->resp = SAS_TASK_UNDELIVERED;
  1493. ts->stat = SAS_OPEN_REJECT;
  1494. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1495. break;
  1496. case IO_XFER_ERROR_NAK_RECEIVED:
  1497. PM8001_IO_DBG(pm8001_ha,
  1498. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  1499. ts->resp = SAS_TASK_COMPLETE;
  1500. ts->stat = SAS_OPEN_REJECT;
  1501. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1502. break;
  1503. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  1504. PM8001_IO_DBG(pm8001_ha,
  1505. pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
  1506. ts->resp = SAS_TASK_COMPLETE;
  1507. ts->stat = SAS_NAK_R_ERR;
  1508. break;
  1509. case IO_XFER_ERROR_DMA:
  1510. PM8001_IO_DBG(pm8001_ha,
  1511. pm8001_printk("IO_XFER_ERROR_DMA\n"));
  1512. ts->resp = SAS_TASK_COMPLETE;
  1513. ts->stat = SAS_OPEN_REJECT;
  1514. break;
  1515. case IO_XFER_OPEN_RETRY_TIMEOUT:
  1516. PM8001_IO_DBG(pm8001_ha,
  1517. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  1518. ts->resp = SAS_TASK_COMPLETE;
  1519. ts->stat = SAS_OPEN_REJECT;
  1520. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1521. break;
  1522. case IO_XFER_ERROR_OFFSET_MISMATCH:
  1523. PM8001_IO_DBG(pm8001_ha,
  1524. pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
  1525. ts->resp = SAS_TASK_COMPLETE;
  1526. ts->stat = SAS_OPEN_REJECT;
  1527. break;
  1528. case IO_PORT_IN_RESET:
  1529. PM8001_IO_DBG(pm8001_ha,
  1530. pm8001_printk("IO_PORT_IN_RESET\n"));
  1531. ts->resp = SAS_TASK_COMPLETE;
  1532. ts->stat = SAS_OPEN_REJECT;
  1533. break;
  1534. case IO_DS_NON_OPERATIONAL:
  1535. PM8001_IO_DBG(pm8001_ha,
  1536. pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
  1537. ts->resp = SAS_TASK_COMPLETE;
  1538. ts->stat = SAS_OPEN_REJECT;
  1539. if (!t->uldd_task)
  1540. pm8001_handle_event(pm8001_ha,
  1541. pm8001_dev,
  1542. IO_DS_NON_OPERATIONAL);
  1543. break;
  1544. case IO_DS_IN_RECOVERY:
  1545. PM8001_IO_DBG(pm8001_ha,
  1546. pm8001_printk("IO_DS_IN_RECOVERY\n"));
  1547. ts->resp = SAS_TASK_COMPLETE;
  1548. ts->stat = SAS_OPEN_REJECT;
  1549. break;
  1550. case IO_TM_TAG_NOT_FOUND:
  1551. PM8001_IO_DBG(pm8001_ha,
  1552. pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
  1553. ts->resp = SAS_TASK_COMPLETE;
  1554. ts->stat = SAS_OPEN_REJECT;
  1555. break;
  1556. case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
  1557. PM8001_IO_DBG(pm8001_ha,
  1558. pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
  1559. ts->resp = SAS_TASK_COMPLETE;
  1560. ts->stat = SAS_OPEN_REJECT;
  1561. break;
  1562. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  1563. PM8001_IO_DBG(pm8001_ha,
  1564. pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
  1565. ts->resp = SAS_TASK_COMPLETE;
  1566. ts->stat = SAS_OPEN_REJECT;
  1567. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1568. default:
  1569. PM8001_IO_DBG(pm8001_ha,
  1570. pm8001_printk("Unknown status 0x%x\n", status));
  1571. /* not allowed case. Therefore, return failed status */
  1572. ts->resp = SAS_TASK_COMPLETE;
  1573. ts->stat = SAS_OPEN_REJECT;
  1574. break;
  1575. }
  1576. PM8001_IO_DBG(pm8001_ha,
  1577. pm8001_printk("scsi_status = %x \n ",
  1578. psspPayload->ssp_resp_iu.status));
  1579. spin_lock_irqsave(&t->task_state_lock, flags);
  1580. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1581. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  1582. t->task_state_flags |= SAS_TASK_STATE_DONE;
  1583. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  1584. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1585. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
  1586. " io_status 0x%x resp 0x%x "
  1587. "stat 0x%x but aborted by upper layer!\n",
  1588. t, status, ts->resp, ts->stat));
  1589. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1590. } else {
  1591. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1592. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1593. mb();/* in order to force CPU ordering */
  1594. t->task_done(t);
  1595. }
  1596. }
  1597. /*See the comments for mpi_ssp_completion */
  1598. static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  1599. {
  1600. struct sas_task *t;
  1601. unsigned long flags;
  1602. struct task_status_struct *ts;
  1603. struct pm8001_ccb_info *ccb;
  1604. struct pm8001_device *pm8001_dev;
  1605. struct ssp_event_resp *psspPayload =
  1606. (struct ssp_event_resp *)(piomb + 4);
  1607. u32 event = le32_to_cpu(psspPayload->event);
  1608. u32 tag = le32_to_cpu(psspPayload->tag);
  1609. u32 port_id = le32_to_cpu(psspPayload->port_id);
  1610. u32 dev_id = le32_to_cpu(psspPayload->device_id);
  1611. ccb = &pm8001_ha->ccb_info[tag];
  1612. t = ccb->task;
  1613. pm8001_dev = ccb->device;
  1614. if (event)
  1615. PM8001_FAIL_DBG(pm8001_ha,
  1616. pm8001_printk("sas IO status 0x%x\n", event));
  1617. if (unlikely(!t || !t->lldd_task || !t->dev))
  1618. return;
  1619. ts = &t->task_status;
  1620. PM8001_IO_DBG(pm8001_ha,
  1621. pm8001_printk("port_id = %x,device_id = %x\n",
  1622. port_id, dev_id));
  1623. switch (event) {
  1624. case IO_OVERFLOW:
  1625. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
  1626. ts->resp = SAS_TASK_COMPLETE;
  1627. ts->stat = SAS_DATA_OVERRUN;
  1628. ts->residual = 0;
  1629. if (pm8001_dev)
  1630. pm8001_dev->running_req--;
  1631. break;
  1632. case IO_XFER_ERROR_BREAK:
  1633. PM8001_IO_DBG(pm8001_ha,
  1634. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  1635. ts->resp = SAS_TASK_COMPLETE;
  1636. ts->stat = SAS_INTERRUPTED;
  1637. break;
  1638. case IO_XFER_ERROR_PHY_NOT_READY:
  1639. PM8001_IO_DBG(pm8001_ha,
  1640. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  1641. ts->resp = SAS_TASK_COMPLETE;
  1642. ts->stat = SAS_OPEN_REJECT;
  1643. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1644. break;
  1645. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  1646. PM8001_IO_DBG(pm8001_ha,
  1647. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
  1648. "_SUPPORTED\n"));
  1649. ts->resp = SAS_TASK_COMPLETE;
  1650. ts->stat = SAS_OPEN_REJECT;
  1651. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1652. break;
  1653. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  1654. PM8001_IO_DBG(pm8001_ha,
  1655. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  1656. ts->resp = SAS_TASK_COMPLETE;
  1657. ts->stat = SAS_OPEN_REJECT;
  1658. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1659. break;
  1660. case IO_OPEN_CNX_ERROR_BREAK:
  1661. PM8001_IO_DBG(pm8001_ha,
  1662. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  1663. ts->resp = SAS_TASK_COMPLETE;
  1664. ts->stat = SAS_OPEN_REJECT;
  1665. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1666. break;
  1667. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1668. PM8001_IO_DBG(pm8001_ha,
  1669. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  1670. ts->resp = SAS_TASK_COMPLETE;
  1671. ts->stat = SAS_OPEN_REJECT;
  1672. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1673. if (!t->uldd_task)
  1674. pm8001_handle_event(pm8001_ha,
  1675. pm8001_dev,
  1676. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  1677. break;
  1678. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  1679. PM8001_IO_DBG(pm8001_ha,
  1680. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  1681. ts->resp = SAS_TASK_COMPLETE;
  1682. ts->stat = SAS_OPEN_REJECT;
  1683. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  1684. break;
  1685. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  1686. PM8001_IO_DBG(pm8001_ha,
  1687. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  1688. "NOT_SUPPORTED\n"));
  1689. ts->resp = SAS_TASK_COMPLETE;
  1690. ts->stat = SAS_OPEN_REJECT;
  1691. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1692. break;
  1693. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  1694. PM8001_IO_DBG(pm8001_ha,
  1695. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  1696. ts->resp = SAS_TASK_COMPLETE;
  1697. ts->stat = SAS_OPEN_REJECT;
  1698. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1699. break;
  1700. case IO_XFER_ERROR_NAK_RECEIVED:
  1701. PM8001_IO_DBG(pm8001_ha,
  1702. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  1703. ts->resp = SAS_TASK_COMPLETE;
  1704. ts->stat = SAS_OPEN_REJECT;
  1705. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1706. break;
  1707. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  1708. PM8001_IO_DBG(pm8001_ha,
  1709. pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
  1710. ts->resp = SAS_TASK_COMPLETE;
  1711. ts->stat = SAS_NAK_R_ERR;
  1712. break;
  1713. case IO_XFER_OPEN_RETRY_TIMEOUT:
  1714. PM8001_IO_DBG(pm8001_ha,
  1715. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  1716. ts->resp = SAS_TASK_COMPLETE;
  1717. ts->stat = SAS_OPEN_REJECT;
  1718. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1719. break;
  1720. case IO_XFER_ERROR_UNEXPECTED_PHASE:
  1721. PM8001_IO_DBG(pm8001_ha,
  1722. pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
  1723. ts->resp = SAS_TASK_COMPLETE;
  1724. ts->stat = SAS_DATA_OVERRUN;
  1725. break;
  1726. case IO_XFER_ERROR_XFER_RDY_OVERRUN:
  1727. PM8001_IO_DBG(pm8001_ha,
  1728. pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
  1729. ts->resp = SAS_TASK_COMPLETE;
  1730. ts->stat = SAS_DATA_OVERRUN;
  1731. break;
  1732. case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
  1733. PM8001_IO_DBG(pm8001_ha,
  1734. pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
  1735. ts->resp = SAS_TASK_COMPLETE;
  1736. ts->stat = SAS_DATA_OVERRUN;
  1737. break;
  1738. case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
  1739. PM8001_IO_DBG(pm8001_ha,
  1740. pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
  1741. ts->resp = SAS_TASK_COMPLETE;
  1742. ts->stat = SAS_DATA_OVERRUN;
  1743. break;
  1744. case IO_XFER_ERROR_OFFSET_MISMATCH:
  1745. PM8001_IO_DBG(pm8001_ha,
  1746. pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
  1747. ts->resp = SAS_TASK_COMPLETE;
  1748. ts->stat = SAS_DATA_OVERRUN;
  1749. break;
  1750. case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
  1751. PM8001_IO_DBG(pm8001_ha,
  1752. pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
  1753. ts->resp = SAS_TASK_COMPLETE;
  1754. ts->stat = SAS_DATA_OVERRUN;
  1755. break;
  1756. case IO_XFER_CMD_FRAME_ISSUED:
  1757. PM8001_IO_DBG(pm8001_ha,
  1758. pm8001_printk(" IO_XFER_CMD_FRAME_ISSUED\n"));
  1759. return;
  1760. default:
  1761. PM8001_IO_DBG(pm8001_ha,
  1762. pm8001_printk("Unknown status 0x%x\n", event));
  1763. /* not allowed case. Therefore, return failed status */
  1764. ts->resp = SAS_TASK_COMPLETE;
  1765. ts->stat = SAS_DATA_OVERRUN;
  1766. break;
  1767. }
  1768. spin_lock_irqsave(&t->task_state_lock, flags);
  1769. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  1770. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  1771. t->task_state_flags |= SAS_TASK_STATE_DONE;
  1772. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  1773. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1774. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
  1775. " event 0x%x resp 0x%x "
  1776. "stat 0x%x but aborted by upper layer!\n",
  1777. t, event, ts->resp, ts->stat));
  1778. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1779. } else {
  1780. spin_unlock_irqrestore(&t->task_state_lock, flags);
  1781. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1782. mb();/* in order to force CPU ordering */
  1783. t->task_done(t);
  1784. }
  1785. }
  1786. /*See the comments for mpi_ssp_completion */
  1787. static void
  1788. mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
  1789. {
  1790. struct sas_task *t;
  1791. struct pm8001_ccb_info *ccb;
  1792. unsigned long flags = 0;
  1793. u32 param;
  1794. u32 status;
  1795. u32 tag;
  1796. struct sata_completion_resp *psataPayload;
  1797. struct task_status_struct *ts;
  1798. struct ata_task_resp *resp ;
  1799. u32 *sata_resp;
  1800. struct pm8001_device *pm8001_dev;
  1801. psataPayload = (struct sata_completion_resp *)(piomb + 4);
  1802. status = le32_to_cpu(psataPayload->status);
  1803. tag = le32_to_cpu(psataPayload->tag);
  1804. ccb = &pm8001_ha->ccb_info[tag];
  1805. param = le32_to_cpu(psataPayload->param);
  1806. t = ccb->task;
  1807. ts = &t->task_status;
  1808. pm8001_dev = ccb->device;
  1809. if (status)
  1810. PM8001_FAIL_DBG(pm8001_ha,
  1811. pm8001_printk("sata IO status 0x%x\n", status));
  1812. if (unlikely(!t || !t->lldd_task || !t->dev))
  1813. return;
  1814. switch (status) {
  1815. case IO_SUCCESS:
  1816. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
  1817. if (param == 0) {
  1818. ts->resp = SAS_TASK_COMPLETE;
  1819. ts->stat = SAM_GOOD;
  1820. } else {
  1821. u8 len;
  1822. ts->resp = SAS_TASK_COMPLETE;
  1823. ts->stat = SAS_PROTO_RESPONSE;
  1824. ts->residual = param;
  1825. PM8001_IO_DBG(pm8001_ha,
  1826. pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
  1827. param));
  1828. sata_resp = &psataPayload->sata_resp[0];
  1829. resp = (struct ata_task_resp *)ts->buf;
  1830. if (t->ata_task.dma_xfer == 0 &&
  1831. t->data_dir == PCI_DMA_FROMDEVICE) {
  1832. len = sizeof(struct pio_setup_fis);
  1833. PM8001_IO_DBG(pm8001_ha,
  1834. pm8001_printk("PIO read len = %d\n", len));
  1835. } else if (t->ata_task.use_ncq) {
  1836. len = sizeof(struct set_dev_bits_fis);
  1837. PM8001_IO_DBG(pm8001_ha,
  1838. pm8001_printk("FPDMA len = %d\n", len));
  1839. } else {
  1840. len = sizeof(struct dev_to_host_fis);
  1841. PM8001_IO_DBG(pm8001_ha,
  1842. pm8001_printk("other len = %d\n", len));
  1843. }
  1844. if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
  1845. resp->frame_len = len;
  1846. memcpy(&resp->ending_fis[0], sata_resp, len);
  1847. ts->buf_valid_size = sizeof(*resp);
  1848. } else
  1849. PM8001_IO_DBG(pm8001_ha,
  1850. pm8001_printk("response to large \n"));
  1851. }
  1852. if (pm8001_dev)
  1853. pm8001_dev->running_req--;
  1854. break;
  1855. case IO_ABORTED:
  1856. PM8001_IO_DBG(pm8001_ha,
  1857. pm8001_printk("IO_ABORTED IOMB Tag \n"));
  1858. ts->resp = SAS_TASK_COMPLETE;
  1859. ts->stat = SAS_ABORTED_TASK;
  1860. if (pm8001_dev)
  1861. pm8001_dev->running_req--;
  1862. break;
  1863. /* following cases are to do cases */
  1864. case IO_UNDERFLOW:
  1865. /* SATA Completion with error */
  1866. PM8001_IO_DBG(pm8001_ha,
  1867. pm8001_printk("IO_UNDERFLOW param = %d\n", param));
  1868. ts->resp = SAS_TASK_COMPLETE;
  1869. ts->stat = SAS_DATA_UNDERRUN;
  1870. ts->residual = param;
  1871. if (pm8001_dev)
  1872. pm8001_dev->running_req--;
  1873. break;
  1874. case IO_NO_DEVICE:
  1875. PM8001_IO_DBG(pm8001_ha,
  1876. pm8001_printk("IO_NO_DEVICE\n"));
  1877. ts->resp = SAS_TASK_UNDELIVERED;
  1878. ts->stat = SAS_PHY_DOWN;
  1879. break;
  1880. case IO_XFER_ERROR_BREAK:
  1881. PM8001_IO_DBG(pm8001_ha,
  1882. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  1883. ts->resp = SAS_TASK_COMPLETE;
  1884. ts->stat = SAS_INTERRUPTED;
  1885. break;
  1886. case IO_XFER_ERROR_PHY_NOT_READY:
  1887. PM8001_IO_DBG(pm8001_ha,
  1888. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  1889. ts->resp = SAS_TASK_COMPLETE;
  1890. ts->stat = SAS_OPEN_REJECT;
  1891. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  1892. break;
  1893. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  1894. PM8001_IO_DBG(pm8001_ha,
  1895. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
  1896. "_SUPPORTED\n"));
  1897. ts->resp = SAS_TASK_COMPLETE;
  1898. ts->stat = SAS_OPEN_REJECT;
  1899. ts->open_rej_reason = SAS_OREJ_EPROTO;
  1900. break;
  1901. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  1902. PM8001_IO_DBG(pm8001_ha,
  1903. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  1904. ts->resp = SAS_TASK_COMPLETE;
  1905. ts->stat = SAS_OPEN_REJECT;
  1906. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  1907. break;
  1908. case IO_OPEN_CNX_ERROR_BREAK:
  1909. PM8001_IO_DBG(pm8001_ha,
  1910. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  1911. ts->resp = SAS_TASK_COMPLETE;
  1912. ts->stat = SAS_OPEN_REJECT;
  1913. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  1914. break;
  1915. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  1916. PM8001_IO_DBG(pm8001_ha,
  1917. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  1918. ts->resp = SAS_TASK_COMPLETE;
  1919. ts->stat = SAS_DEV_NO_RESPONSE;
  1920. if (!t->uldd_task) {
  1921. pm8001_handle_event(pm8001_ha,
  1922. pm8001_dev,
  1923. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  1924. ts->resp = SAS_TASK_UNDELIVERED;
  1925. ts->stat = SAS_QUEUE_FULL;
  1926. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1927. mb();/*in order to force CPU ordering*/
  1928. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1929. t->task_done(t);
  1930. spin_lock_irqsave(&pm8001_ha->lock, flags);
  1931. return;
  1932. }
  1933. break;
  1934. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  1935. PM8001_IO_DBG(pm8001_ha,
  1936. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  1937. ts->resp = SAS_TASK_UNDELIVERED;
  1938. ts->stat = SAS_OPEN_REJECT;
  1939. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  1940. if (!t->uldd_task) {
  1941. pm8001_handle_event(pm8001_ha,
  1942. pm8001_dev,
  1943. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  1944. ts->resp = SAS_TASK_UNDELIVERED;
  1945. ts->stat = SAS_QUEUE_FULL;
  1946. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1947. mb();/*ditto*/
  1948. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1949. t->task_done(t);
  1950. spin_lock_irqsave(&pm8001_ha->lock, flags);
  1951. return;
  1952. }
  1953. break;
  1954. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  1955. PM8001_IO_DBG(pm8001_ha,
  1956. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  1957. "NOT_SUPPORTED\n"));
  1958. ts->resp = SAS_TASK_COMPLETE;
  1959. ts->stat = SAS_OPEN_REJECT;
  1960. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  1961. break;
  1962. case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
  1963. PM8001_IO_DBG(pm8001_ha,
  1964. pm8001_printk("IO_OPEN_CNX_ERROR_STP_RESOURCES"
  1965. "_BUSY\n"));
  1966. ts->resp = SAS_TASK_COMPLETE;
  1967. ts->stat = SAS_DEV_NO_RESPONSE;
  1968. if (!t->uldd_task) {
  1969. pm8001_handle_event(pm8001_ha,
  1970. pm8001_dev,
  1971. IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
  1972. ts->resp = SAS_TASK_UNDELIVERED;
  1973. ts->stat = SAS_QUEUE_FULL;
  1974. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  1975. mb();/* ditto*/
  1976. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  1977. t->task_done(t);
  1978. spin_lock_irqsave(&pm8001_ha->lock, flags);
  1979. return;
  1980. }
  1981. break;
  1982. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  1983. PM8001_IO_DBG(pm8001_ha,
  1984. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  1985. ts->resp = SAS_TASK_COMPLETE;
  1986. ts->stat = SAS_OPEN_REJECT;
  1987. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  1988. break;
  1989. case IO_XFER_ERROR_NAK_RECEIVED:
  1990. PM8001_IO_DBG(pm8001_ha,
  1991. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  1992. ts->resp = SAS_TASK_COMPLETE;
  1993. ts->stat = SAS_NAK_R_ERR;
  1994. break;
  1995. case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
  1996. PM8001_IO_DBG(pm8001_ha,
  1997. pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
  1998. ts->resp = SAS_TASK_COMPLETE;
  1999. ts->stat = SAS_NAK_R_ERR;
  2000. break;
  2001. case IO_XFER_ERROR_DMA:
  2002. PM8001_IO_DBG(pm8001_ha,
  2003. pm8001_printk("IO_XFER_ERROR_DMA\n"));
  2004. ts->resp = SAS_TASK_COMPLETE;
  2005. ts->stat = SAS_ABORTED_TASK;
  2006. break;
  2007. case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
  2008. PM8001_IO_DBG(pm8001_ha,
  2009. pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
  2010. ts->resp = SAS_TASK_UNDELIVERED;
  2011. ts->stat = SAS_DEV_NO_RESPONSE;
  2012. break;
  2013. case IO_XFER_ERROR_REJECTED_NCQ_MODE:
  2014. PM8001_IO_DBG(pm8001_ha,
  2015. pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
  2016. ts->resp = SAS_TASK_COMPLETE;
  2017. ts->stat = SAS_DATA_UNDERRUN;
  2018. break;
  2019. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2020. PM8001_IO_DBG(pm8001_ha,
  2021. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2022. ts->resp = SAS_TASK_COMPLETE;
  2023. ts->stat = SAS_OPEN_TO;
  2024. break;
  2025. case IO_PORT_IN_RESET:
  2026. PM8001_IO_DBG(pm8001_ha,
  2027. pm8001_printk("IO_PORT_IN_RESET\n"));
  2028. ts->resp = SAS_TASK_COMPLETE;
  2029. ts->stat = SAS_DEV_NO_RESPONSE;
  2030. break;
  2031. case IO_DS_NON_OPERATIONAL:
  2032. PM8001_IO_DBG(pm8001_ha,
  2033. pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
  2034. ts->resp = SAS_TASK_COMPLETE;
  2035. ts->stat = SAS_DEV_NO_RESPONSE;
  2036. if (!t->uldd_task) {
  2037. pm8001_handle_event(pm8001_ha, pm8001_dev,
  2038. IO_DS_NON_OPERATIONAL);
  2039. ts->resp = SAS_TASK_UNDELIVERED;
  2040. ts->stat = SAS_QUEUE_FULL;
  2041. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2042. mb();/*ditto*/
  2043. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2044. t->task_done(t);
  2045. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2046. return;
  2047. }
  2048. break;
  2049. case IO_DS_IN_RECOVERY:
  2050. PM8001_IO_DBG(pm8001_ha,
  2051. pm8001_printk(" IO_DS_IN_RECOVERY\n"));
  2052. ts->resp = SAS_TASK_COMPLETE;
  2053. ts->stat = SAS_DEV_NO_RESPONSE;
  2054. break;
  2055. case IO_DS_IN_ERROR:
  2056. PM8001_IO_DBG(pm8001_ha,
  2057. pm8001_printk("IO_DS_IN_ERROR\n"));
  2058. ts->resp = SAS_TASK_COMPLETE;
  2059. ts->stat = SAS_DEV_NO_RESPONSE;
  2060. if (!t->uldd_task) {
  2061. pm8001_handle_event(pm8001_ha, pm8001_dev,
  2062. IO_DS_IN_ERROR);
  2063. ts->resp = SAS_TASK_UNDELIVERED;
  2064. ts->stat = SAS_QUEUE_FULL;
  2065. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2066. mb();/*ditto*/
  2067. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2068. t->task_done(t);
  2069. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2070. return;
  2071. }
  2072. break;
  2073. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  2074. PM8001_IO_DBG(pm8001_ha,
  2075. pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
  2076. ts->resp = SAS_TASK_COMPLETE;
  2077. ts->stat = SAS_OPEN_REJECT;
  2078. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2079. default:
  2080. PM8001_IO_DBG(pm8001_ha,
  2081. pm8001_printk("Unknown status 0x%x\n", status));
  2082. /* not allowed case. Therefore, return failed status */
  2083. ts->resp = SAS_TASK_COMPLETE;
  2084. ts->stat = SAS_DEV_NO_RESPONSE;
  2085. break;
  2086. }
  2087. spin_lock_irqsave(&t->task_state_lock, flags);
  2088. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2089. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2090. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2091. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2092. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2093. PM8001_FAIL_DBG(pm8001_ha,
  2094. pm8001_printk("task 0x%p done with io_status 0x%x"
  2095. " resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2096. t, status, ts->resp, ts->stat));
  2097. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2098. } else if (t->uldd_task) {
  2099. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2100. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2101. mb();/* ditto */
  2102. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2103. t->task_done(t);
  2104. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2105. } else if (!t->uldd_task) {
  2106. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2107. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2108. mb();/*ditto*/
  2109. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2110. t->task_done(t);
  2111. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2112. }
  2113. }
  2114. /*See the comments for mpi_ssp_completion */
  2115. static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  2116. {
  2117. struct sas_task *t;
  2118. unsigned long flags = 0;
  2119. struct task_status_struct *ts;
  2120. struct pm8001_ccb_info *ccb;
  2121. struct pm8001_device *pm8001_dev;
  2122. struct sata_event_resp *psataPayload =
  2123. (struct sata_event_resp *)(piomb + 4);
  2124. u32 event = le32_to_cpu(psataPayload->event);
  2125. u32 tag = le32_to_cpu(psataPayload->tag);
  2126. u32 port_id = le32_to_cpu(psataPayload->port_id);
  2127. u32 dev_id = le32_to_cpu(psataPayload->device_id);
  2128. ccb = &pm8001_ha->ccb_info[tag];
  2129. t = ccb->task;
  2130. pm8001_dev = ccb->device;
  2131. if (event)
  2132. PM8001_FAIL_DBG(pm8001_ha,
  2133. pm8001_printk("sata IO status 0x%x\n", event));
  2134. if (unlikely(!t || !t->lldd_task || !t->dev))
  2135. return;
  2136. ts = &t->task_status;
  2137. PM8001_IO_DBG(pm8001_ha,
  2138. pm8001_printk("port_id = %x,device_id = %x\n",
  2139. port_id, dev_id));
  2140. switch (event) {
  2141. case IO_OVERFLOW:
  2142. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
  2143. ts->resp = SAS_TASK_COMPLETE;
  2144. ts->stat = SAS_DATA_OVERRUN;
  2145. ts->residual = 0;
  2146. if (pm8001_dev)
  2147. pm8001_dev->running_req--;
  2148. break;
  2149. case IO_XFER_ERROR_BREAK:
  2150. PM8001_IO_DBG(pm8001_ha,
  2151. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  2152. ts->resp = SAS_TASK_COMPLETE;
  2153. ts->stat = SAS_INTERRUPTED;
  2154. break;
  2155. case IO_XFER_ERROR_PHY_NOT_READY:
  2156. PM8001_IO_DBG(pm8001_ha,
  2157. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  2158. ts->resp = SAS_TASK_COMPLETE;
  2159. ts->stat = SAS_OPEN_REJECT;
  2160. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2161. break;
  2162. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2163. PM8001_IO_DBG(pm8001_ha,
  2164. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT"
  2165. "_SUPPORTED\n"));
  2166. ts->resp = SAS_TASK_COMPLETE;
  2167. ts->stat = SAS_OPEN_REJECT;
  2168. ts->open_rej_reason = SAS_OREJ_EPROTO;
  2169. break;
  2170. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2171. PM8001_IO_DBG(pm8001_ha,
  2172. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  2173. ts->resp = SAS_TASK_COMPLETE;
  2174. ts->stat = SAS_OPEN_REJECT;
  2175. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2176. break;
  2177. case IO_OPEN_CNX_ERROR_BREAK:
  2178. PM8001_IO_DBG(pm8001_ha,
  2179. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  2180. ts->resp = SAS_TASK_COMPLETE;
  2181. ts->stat = SAS_OPEN_REJECT;
  2182. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2183. break;
  2184. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2185. PM8001_IO_DBG(pm8001_ha,
  2186. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  2187. ts->resp = SAS_TASK_UNDELIVERED;
  2188. ts->stat = SAS_DEV_NO_RESPONSE;
  2189. if (!t->uldd_task) {
  2190. pm8001_handle_event(pm8001_ha,
  2191. pm8001_dev,
  2192. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2193. ts->resp = SAS_TASK_COMPLETE;
  2194. ts->stat = SAS_QUEUE_FULL;
  2195. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2196. mb();/*ditto*/
  2197. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2198. t->task_done(t);
  2199. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2200. return;
  2201. }
  2202. break;
  2203. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2204. PM8001_IO_DBG(pm8001_ha,
  2205. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  2206. ts->resp = SAS_TASK_UNDELIVERED;
  2207. ts->stat = SAS_OPEN_REJECT;
  2208. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2209. break;
  2210. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2211. PM8001_IO_DBG(pm8001_ha,
  2212. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  2213. "NOT_SUPPORTED\n"));
  2214. ts->resp = SAS_TASK_COMPLETE;
  2215. ts->stat = SAS_OPEN_REJECT;
  2216. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2217. break;
  2218. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2219. PM8001_IO_DBG(pm8001_ha,
  2220. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  2221. ts->resp = SAS_TASK_COMPLETE;
  2222. ts->stat = SAS_OPEN_REJECT;
  2223. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2224. break;
  2225. case IO_XFER_ERROR_NAK_RECEIVED:
  2226. PM8001_IO_DBG(pm8001_ha,
  2227. pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
  2228. ts->resp = SAS_TASK_COMPLETE;
  2229. ts->stat = SAS_NAK_R_ERR;
  2230. break;
  2231. case IO_XFER_ERROR_PEER_ABORTED:
  2232. PM8001_IO_DBG(pm8001_ha,
  2233. pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
  2234. ts->resp = SAS_TASK_COMPLETE;
  2235. ts->stat = SAS_NAK_R_ERR;
  2236. break;
  2237. case IO_XFER_ERROR_REJECTED_NCQ_MODE:
  2238. PM8001_IO_DBG(pm8001_ha,
  2239. pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
  2240. ts->resp = SAS_TASK_COMPLETE;
  2241. ts->stat = SAS_DATA_UNDERRUN;
  2242. break;
  2243. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2244. PM8001_IO_DBG(pm8001_ha,
  2245. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2246. ts->resp = SAS_TASK_COMPLETE;
  2247. ts->stat = SAS_OPEN_TO;
  2248. break;
  2249. case IO_XFER_ERROR_UNEXPECTED_PHASE:
  2250. PM8001_IO_DBG(pm8001_ha,
  2251. pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
  2252. ts->resp = SAS_TASK_COMPLETE;
  2253. ts->stat = SAS_OPEN_TO;
  2254. break;
  2255. case IO_XFER_ERROR_XFER_RDY_OVERRUN:
  2256. PM8001_IO_DBG(pm8001_ha,
  2257. pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
  2258. ts->resp = SAS_TASK_COMPLETE;
  2259. ts->stat = SAS_OPEN_TO;
  2260. break;
  2261. case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
  2262. PM8001_IO_DBG(pm8001_ha,
  2263. pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
  2264. ts->resp = SAS_TASK_COMPLETE;
  2265. ts->stat = SAS_OPEN_TO;
  2266. break;
  2267. case IO_XFER_ERROR_OFFSET_MISMATCH:
  2268. PM8001_IO_DBG(pm8001_ha,
  2269. pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
  2270. ts->resp = SAS_TASK_COMPLETE;
  2271. ts->stat = SAS_OPEN_TO;
  2272. break;
  2273. case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
  2274. PM8001_IO_DBG(pm8001_ha,
  2275. pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
  2276. ts->resp = SAS_TASK_COMPLETE;
  2277. ts->stat = SAS_OPEN_TO;
  2278. break;
  2279. case IO_XFER_CMD_FRAME_ISSUED:
  2280. PM8001_IO_DBG(pm8001_ha,
  2281. pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
  2282. break;
  2283. case IO_XFER_PIO_SETUP_ERROR:
  2284. PM8001_IO_DBG(pm8001_ha,
  2285. pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
  2286. ts->resp = SAS_TASK_COMPLETE;
  2287. ts->stat = SAS_OPEN_TO;
  2288. break;
  2289. default:
  2290. PM8001_IO_DBG(pm8001_ha,
  2291. pm8001_printk("Unknown status 0x%x\n", event));
  2292. /* not allowed case. Therefore, return failed status */
  2293. ts->resp = SAS_TASK_COMPLETE;
  2294. ts->stat = SAS_OPEN_TO;
  2295. break;
  2296. }
  2297. spin_lock_irqsave(&t->task_state_lock, flags);
  2298. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2299. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2300. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2301. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2302. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2303. PM8001_FAIL_DBG(pm8001_ha,
  2304. pm8001_printk("task 0x%p done with io_status 0x%x"
  2305. " resp 0x%x stat 0x%x but aborted by upper layer!\n",
  2306. t, event, ts->resp, ts->stat));
  2307. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2308. } else if (t->uldd_task) {
  2309. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2310. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2311. mb();/* ditto */
  2312. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2313. t->task_done(t);
  2314. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2315. } else if (!t->uldd_task) {
  2316. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2317. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2318. mb();/*ditto*/
  2319. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  2320. t->task_done(t);
  2321. spin_lock_irqsave(&pm8001_ha->lock, flags);
  2322. }
  2323. }
  2324. /*See the comments for mpi_ssp_completion */
  2325. static void
  2326. mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2327. {
  2328. u32 param;
  2329. struct sas_task *t;
  2330. struct pm8001_ccb_info *ccb;
  2331. unsigned long flags;
  2332. u32 status;
  2333. u32 tag;
  2334. struct smp_completion_resp *psmpPayload;
  2335. struct task_status_struct *ts;
  2336. struct pm8001_device *pm8001_dev;
  2337. psmpPayload = (struct smp_completion_resp *)(piomb + 4);
  2338. status = le32_to_cpu(psmpPayload->status);
  2339. tag = le32_to_cpu(psmpPayload->tag);
  2340. ccb = &pm8001_ha->ccb_info[tag];
  2341. param = le32_to_cpu(psmpPayload->param);
  2342. t = ccb->task;
  2343. ts = &t->task_status;
  2344. pm8001_dev = ccb->device;
  2345. if (status)
  2346. PM8001_FAIL_DBG(pm8001_ha,
  2347. pm8001_printk("smp IO status 0x%x\n", status));
  2348. if (unlikely(!t || !t->lldd_task || !t->dev))
  2349. return;
  2350. switch (status) {
  2351. case IO_SUCCESS:
  2352. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
  2353. ts->resp = SAS_TASK_COMPLETE;
  2354. ts->stat = SAM_GOOD;
  2355. if (pm8001_dev)
  2356. pm8001_dev->running_req--;
  2357. break;
  2358. case IO_ABORTED:
  2359. PM8001_IO_DBG(pm8001_ha,
  2360. pm8001_printk("IO_ABORTED IOMB\n"));
  2361. ts->resp = SAS_TASK_COMPLETE;
  2362. ts->stat = SAS_ABORTED_TASK;
  2363. if (pm8001_dev)
  2364. pm8001_dev->running_req--;
  2365. break;
  2366. case IO_OVERFLOW:
  2367. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
  2368. ts->resp = SAS_TASK_COMPLETE;
  2369. ts->stat = SAS_DATA_OVERRUN;
  2370. ts->residual = 0;
  2371. if (pm8001_dev)
  2372. pm8001_dev->running_req--;
  2373. break;
  2374. case IO_NO_DEVICE:
  2375. PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
  2376. ts->resp = SAS_TASK_COMPLETE;
  2377. ts->stat = SAS_PHY_DOWN;
  2378. break;
  2379. case IO_ERROR_HW_TIMEOUT:
  2380. PM8001_IO_DBG(pm8001_ha,
  2381. pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
  2382. ts->resp = SAS_TASK_COMPLETE;
  2383. ts->stat = SAM_BUSY;
  2384. break;
  2385. case IO_XFER_ERROR_BREAK:
  2386. PM8001_IO_DBG(pm8001_ha,
  2387. pm8001_printk("IO_XFER_ERROR_BREAK\n"));
  2388. ts->resp = SAS_TASK_COMPLETE;
  2389. ts->stat = SAM_BUSY;
  2390. break;
  2391. case IO_XFER_ERROR_PHY_NOT_READY:
  2392. PM8001_IO_DBG(pm8001_ha,
  2393. pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
  2394. ts->resp = SAS_TASK_COMPLETE;
  2395. ts->stat = SAM_BUSY;
  2396. break;
  2397. case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
  2398. PM8001_IO_DBG(pm8001_ha,
  2399. pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
  2400. ts->resp = SAS_TASK_COMPLETE;
  2401. ts->stat = SAS_OPEN_REJECT;
  2402. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2403. break;
  2404. case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
  2405. PM8001_IO_DBG(pm8001_ha,
  2406. pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
  2407. ts->resp = SAS_TASK_COMPLETE;
  2408. ts->stat = SAS_OPEN_REJECT;
  2409. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2410. break;
  2411. case IO_OPEN_CNX_ERROR_BREAK:
  2412. PM8001_IO_DBG(pm8001_ha,
  2413. pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
  2414. ts->resp = SAS_TASK_COMPLETE;
  2415. ts->stat = SAS_OPEN_REJECT;
  2416. ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
  2417. break;
  2418. case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
  2419. PM8001_IO_DBG(pm8001_ha,
  2420. pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
  2421. ts->resp = SAS_TASK_COMPLETE;
  2422. ts->stat = SAS_OPEN_REJECT;
  2423. ts->open_rej_reason = SAS_OREJ_UNKNOWN;
  2424. pm8001_handle_event(pm8001_ha,
  2425. pm8001_dev,
  2426. IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
  2427. break;
  2428. case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
  2429. PM8001_IO_DBG(pm8001_ha,
  2430. pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
  2431. ts->resp = SAS_TASK_COMPLETE;
  2432. ts->stat = SAS_OPEN_REJECT;
  2433. ts->open_rej_reason = SAS_OREJ_BAD_DEST;
  2434. break;
  2435. case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
  2436. PM8001_IO_DBG(pm8001_ha,
  2437. pm8001_printk("IO_OPEN_CNX_ERROR_CONNECTION_RATE_"
  2438. "NOT_SUPPORTED\n"));
  2439. ts->resp = SAS_TASK_COMPLETE;
  2440. ts->stat = SAS_OPEN_REJECT;
  2441. ts->open_rej_reason = SAS_OREJ_CONN_RATE;
  2442. break;
  2443. case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
  2444. PM8001_IO_DBG(pm8001_ha,
  2445. pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
  2446. ts->resp = SAS_TASK_COMPLETE;
  2447. ts->stat = SAS_OPEN_REJECT;
  2448. ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
  2449. break;
  2450. case IO_XFER_ERROR_RX_FRAME:
  2451. PM8001_IO_DBG(pm8001_ha,
  2452. pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
  2453. ts->resp = SAS_TASK_COMPLETE;
  2454. ts->stat = SAS_DEV_NO_RESPONSE;
  2455. break;
  2456. case IO_XFER_OPEN_RETRY_TIMEOUT:
  2457. PM8001_IO_DBG(pm8001_ha,
  2458. pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
  2459. ts->resp = SAS_TASK_COMPLETE;
  2460. ts->stat = SAS_OPEN_REJECT;
  2461. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2462. break;
  2463. case IO_ERROR_INTERNAL_SMP_RESOURCE:
  2464. PM8001_IO_DBG(pm8001_ha,
  2465. pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
  2466. ts->resp = SAS_TASK_COMPLETE;
  2467. ts->stat = SAS_QUEUE_FULL;
  2468. break;
  2469. case IO_PORT_IN_RESET:
  2470. PM8001_IO_DBG(pm8001_ha,
  2471. pm8001_printk("IO_PORT_IN_RESET\n"));
  2472. ts->resp = SAS_TASK_COMPLETE;
  2473. ts->stat = SAS_OPEN_REJECT;
  2474. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2475. break;
  2476. case IO_DS_NON_OPERATIONAL:
  2477. PM8001_IO_DBG(pm8001_ha,
  2478. pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
  2479. ts->resp = SAS_TASK_COMPLETE;
  2480. ts->stat = SAS_DEV_NO_RESPONSE;
  2481. break;
  2482. case IO_DS_IN_RECOVERY:
  2483. PM8001_IO_DBG(pm8001_ha,
  2484. pm8001_printk("IO_DS_IN_RECOVERY\n"));
  2485. ts->resp = SAS_TASK_COMPLETE;
  2486. ts->stat = SAS_OPEN_REJECT;
  2487. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2488. break;
  2489. case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
  2490. PM8001_IO_DBG(pm8001_ha,
  2491. pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
  2492. ts->resp = SAS_TASK_COMPLETE;
  2493. ts->stat = SAS_OPEN_REJECT;
  2494. ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
  2495. break;
  2496. default:
  2497. PM8001_IO_DBG(pm8001_ha,
  2498. pm8001_printk("Unknown status 0x%x\n", status));
  2499. ts->resp = SAS_TASK_COMPLETE;
  2500. ts->stat = SAS_DEV_NO_RESPONSE;
  2501. /* not allowed case. Therefore, return failed status */
  2502. break;
  2503. }
  2504. spin_lock_irqsave(&t->task_state_lock, flags);
  2505. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  2506. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  2507. t->task_state_flags |= SAS_TASK_STATE_DONE;
  2508. if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
  2509. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2510. PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("task 0x%p done with"
  2511. " io_status 0x%x resp 0x%x "
  2512. "stat 0x%x but aborted by upper layer!\n",
  2513. t, status, ts->resp, ts->stat));
  2514. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2515. } else {
  2516. spin_unlock_irqrestore(&t->task_state_lock, flags);
  2517. pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
  2518. mb();/* in order to force CPU ordering */
  2519. t->task_done(t);
  2520. }
  2521. }
  2522. static void
  2523. mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2524. {
  2525. struct set_dev_state_resp *pPayload =
  2526. (struct set_dev_state_resp *)(piomb + 4);
  2527. u32 tag = le32_to_cpu(pPayload->tag);
  2528. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  2529. struct pm8001_device *pm8001_dev = ccb->device;
  2530. u32 status = le32_to_cpu(pPayload->status);
  2531. u32 device_id = le32_to_cpu(pPayload->device_id);
  2532. u8 pds = le32_to_cpu(pPayload->pds_nds) | PDS_BITS;
  2533. u8 nds = le32_to_cpu(pPayload->pds_nds) | NDS_BITS;
  2534. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set device id = 0x%x state "
  2535. "from 0x%x to 0x%x status = 0x%x!\n",
  2536. device_id, pds, nds, status));
  2537. complete(pm8001_dev->setds_completion);
  2538. ccb->task = NULL;
  2539. ccb->ccb_tag = 0xFFFFFFFF;
  2540. pm8001_ccb_free(pm8001_ha, tag);
  2541. }
  2542. static void
  2543. mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2544. {
  2545. struct get_nvm_data_resp *pPayload =
  2546. (struct get_nvm_data_resp *)(piomb + 4);
  2547. u32 tag = le32_to_cpu(pPayload->tag);
  2548. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  2549. u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
  2550. complete(pm8001_ha->nvmd_completion);
  2551. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Set nvm data complete!\n"));
  2552. if ((dlen_status & NVMD_STAT) != 0) {
  2553. PM8001_FAIL_DBG(pm8001_ha,
  2554. pm8001_printk("Set nvm data error!\n"));
  2555. return;
  2556. }
  2557. ccb->task = NULL;
  2558. ccb->ccb_tag = 0xFFFFFFFF;
  2559. pm8001_ccb_free(pm8001_ha, tag);
  2560. }
  2561. static void
  2562. mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2563. {
  2564. struct fw_control_ex *fw_control_context;
  2565. struct get_nvm_data_resp *pPayload =
  2566. (struct get_nvm_data_resp *)(piomb + 4);
  2567. u32 tag = le32_to_cpu(pPayload->tag);
  2568. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  2569. u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
  2570. u32 ir_tds_bn_dps_das_nvm =
  2571. le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
  2572. void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
  2573. fw_control_context = ccb->fw_control_context;
  2574. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("Get nvm data complete!\n"));
  2575. if ((dlen_status & NVMD_STAT) != 0) {
  2576. PM8001_FAIL_DBG(pm8001_ha,
  2577. pm8001_printk("Get nvm data error!\n"));
  2578. complete(pm8001_ha->nvmd_completion);
  2579. return;
  2580. }
  2581. if (ir_tds_bn_dps_das_nvm & IPMode) {
  2582. /* indirect mode - IR bit set */
  2583. PM8001_MSG_DBG(pm8001_ha,
  2584. pm8001_printk("Get NVMD success, IR=1\n"));
  2585. if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
  2586. if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
  2587. memcpy(pm8001_ha->sas_addr,
  2588. ((u8 *)virt_addr + 4),
  2589. SAS_ADDR_SIZE);
  2590. PM8001_MSG_DBG(pm8001_ha,
  2591. pm8001_printk("Get SAS address"
  2592. " from VPD successfully!\n"));
  2593. }
  2594. } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
  2595. || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
  2596. ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
  2597. ;
  2598. } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
  2599. || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
  2600. ;
  2601. } else {
  2602. /* Should not be happened*/
  2603. PM8001_MSG_DBG(pm8001_ha,
  2604. pm8001_printk("(IR=1)Wrong Device type 0x%x\n",
  2605. ir_tds_bn_dps_das_nvm));
  2606. }
  2607. } else /* direct mode */{
  2608. PM8001_MSG_DBG(pm8001_ha,
  2609. pm8001_printk("Get NVMD success, IR=0, dataLen=%d\n",
  2610. (dlen_status & NVMD_LEN) >> 24));
  2611. }
  2612. memcpy(fw_control_context->usrAddr,
  2613. pm8001_ha->memoryMap.region[NVMD].virt_ptr,
  2614. fw_control_context->len);
  2615. complete(pm8001_ha->nvmd_completion);
  2616. ccb->task = NULL;
  2617. ccb->ccb_tag = 0xFFFFFFFF;
  2618. pm8001_ccb_free(pm8001_ha, tag);
  2619. }
  2620. static int mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2621. {
  2622. struct local_phy_ctl_resp *pPayload =
  2623. (struct local_phy_ctl_resp *)(piomb + 4);
  2624. u32 status = le32_to_cpu(pPayload->status);
  2625. u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
  2626. u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
  2627. if (status != 0) {
  2628. PM8001_MSG_DBG(pm8001_ha,
  2629. pm8001_printk("%x phy execute %x phy op failed! \n",
  2630. phy_id, phy_op));
  2631. } else
  2632. PM8001_MSG_DBG(pm8001_ha,
  2633. pm8001_printk("%x phy execute %x phy op success! \n",
  2634. phy_id, phy_op));
  2635. return 0;
  2636. }
  2637. /**
  2638. * pm8001_bytes_dmaed - one of the interface function communication with libsas
  2639. * @pm8001_ha: our hba card information
  2640. * @i: which phy that received the event.
  2641. *
  2642. * when HBA driver received the identify done event or initiate FIS received
  2643. * event(for SATA), it will invoke this function to notify the sas layer that
  2644. * the sas toplogy has formed, please discover the the whole sas domain,
  2645. * while receive a broadcast(change) primitive just tell the sas
  2646. * layer to discover the changed domain rather than the whole domain.
  2647. */
  2648. static void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
  2649. {
  2650. struct pm8001_phy *phy = &pm8001_ha->phy[i];
  2651. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  2652. struct sas_ha_struct *sas_ha;
  2653. if (!phy->phy_attached)
  2654. return;
  2655. sas_ha = pm8001_ha->sas;
  2656. if (sas_phy->phy) {
  2657. struct sas_phy *sphy = sas_phy->phy;
  2658. sphy->negotiated_linkrate = sas_phy->linkrate;
  2659. sphy->minimum_linkrate = phy->minimum_linkrate;
  2660. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  2661. sphy->maximum_linkrate = phy->maximum_linkrate;
  2662. sphy->maximum_linkrate_hw = phy->maximum_linkrate;
  2663. }
  2664. if (phy->phy_type & PORT_TYPE_SAS) {
  2665. struct sas_identify_frame *id;
  2666. id = (struct sas_identify_frame *)phy->frame_rcvd;
  2667. id->dev_type = phy->identify.device_type;
  2668. id->initiator_bits = SAS_PROTOCOL_ALL;
  2669. id->target_bits = phy->identify.target_port_protocols;
  2670. } else if (phy->phy_type & PORT_TYPE_SATA) {
  2671. /*Nothing*/
  2672. }
  2673. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("phy %d byte dmaded.\n", i));
  2674. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  2675. pm8001_ha->sas->notify_port_event(sas_phy, PORTE_BYTES_DMAED);
  2676. }
  2677. /* Get the link rate speed */
  2678. static void get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
  2679. {
  2680. struct sas_phy *sas_phy = phy->sas_phy.phy;
  2681. switch (link_rate) {
  2682. case PHY_SPEED_60:
  2683. phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
  2684. phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
  2685. break;
  2686. case PHY_SPEED_30:
  2687. phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
  2688. phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
  2689. break;
  2690. case PHY_SPEED_15:
  2691. phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
  2692. phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
  2693. break;
  2694. }
  2695. sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
  2696. sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
  2697. sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  2698. sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
  2699. sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
  2700. }
  2701. /**
  2702. * asd_get_attached_sas_addr -- extract/generate attached SAS address
  2703. * @phy: pointer to asd_phy
  2704. * @sas_addr: pointer to buffer where the SAS address is to be written
  2705. *
  2706. * This function extracts the SAS address from an IDENTIFY frame
  2707. * received. If OOB is SATA, then a SAS address is generated from the
  2708. * HA tables.
  2709. *
  2710. * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
  2711. * buffer.
  2712. */
  2713. static void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
  2714. u8 *sas_addr)
  2715. {
  2716. if (phy->sas_phy.frame_rcvd[0] == 0x34
  2717. && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
  2718. struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
  2719. /* FIS device-to-host */
  2720. u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
  2721. addr += phy->sas_phy.id;
  2722. *(__be64 *)sas_addr = cpu_to_be64(addr);
  2723. } else {
  2724. struct sas_identify_frame *idframe =
  2725. (void *) phy->sas_phy.frame_rcvd;
  2726. memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
  2727. }
  2728. }
  2729. /**
  2730. * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
  2731. * @pm8001_ha: our hba card information
  2732. * @Qnum: the outbound queue message number.
  2733. * @SEA: source of event to ack
  2734. * @port_id: port id.
  2735. * @phyId: phy id.
  2736. * @param0: parameter 0.
  2737. * @param1: parameter 1.
  2738. */
  2739. static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
  2740. u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
  2741. {
  2742. struct hw_event_ack_req payload;
  2743. u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
  2744. struct inbound_queue_table *circularQ;
  2745. memset((u8 *)&payload, 0, sizeof(payload));
  2746. circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
  2747. payload.tag = 1;
  2748. payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
  2749. ((phyId & 0x0F) << 4) | (port_id & 0x0F));
  2750. payload.param0 = cpu_to_le32(param0);
  2751. payload.param1 = cpu_to_le32(param1);
  2752. mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  2753. }
  2754. static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
  2755. u32 phyId, u32 phy_op);
  2756. /**
  2757. * hw_event_sas_phy_up -FW tells me a SAS phy up event.
  2758. * @pm8001_ha: our hba card information
  2759. * @piomb: IO message buffer
  2760. */
  2761. static void
  2762. hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2763. {
  2764. struct hw_event_resp *pPayload =
  2765. (struct hw_event_resp *)(piomb + 4);
  2766. u32 lr_evt_status_phyid_portid =
  2767. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  2768. u8 link_rate =
  2769. (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
  2770. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  2771. u8 phy_id =
  2772. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  2773. u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
  2774. u8 portstate = (u8)(npip_portstate & 0x0000000F);
  2775. struct pm8001_port *port = &pm8001_ha->port[port_id];
  2776. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  2777. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  2778. unsigned long flags;
  2779. u8 deviceType = pPayload->sas_identify.dev_type;
  2780. port->port_state = portstate;
  2781. PM8001_MSG_DBG(pm8001_ha,
  2782. pm8001_printk("HW_EVENT_SAS_PHY_UP \n"));
  2783. switch (deviceType) {
  2784. case SAS_PHY_UNUSED:
  2785. PM8001_MSG_DBG(pm8001_ha,
  2786. pm8001_printk("device type no device.\n"));
  2787. break;
  2788. case SAS_END_DEVICE:
  2789. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
  2790. pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
  2791. PHY_NOTIFY_ENABLE_SPINUP);
  2792. port->port_attached = 1;
  2793. get_lrate_mode(phy, link_rate);
  2794. break;
  2795. case SAS_EDGE_EXPANDER_DEVICE:
  2796. PM8001_MSG_DBG(pm8001_ha,
  2797. pm8001_printk("expander device.\n"));
  2798. port->port_attached = 1;
  2799. get_lrate_mode(phy, link_rate);
  2800. break;
  2801. case SAS_FANOUT_EXPANDER_DEVICE:
  2802. PM8001_MSG_DBG(pm8001_ha,
  2803. pm8001_printk("fanout expander device.\n"));
  2804. port->port_attached = 1;
  2805. get_lrate_mode(phy, link_rate);
  2806. break;
  2807. default:
  2808. PM8001_MSG_DBG(pm8001_ha,
  2809. pm8001_printk("unkown device type(%x)\n", deviceType));
  2810. break;
  2811. }
  2812. phy->phy_type |= PORT_TYPE_SAS;
  2813. phy->identify.device_type = deviceType;
  2814. phy->phy_attached = 1;
  2815. if (phy->identify.device_type == SAS_END_DEV)
  2816. phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
  2817. else if (phy->identify.device_type != NO_DEVICE)
  2818. phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
  2819. phy->sas_phy.oob_mode = SAS_OOB_MODE;
  2820. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
  2821. spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
  2822. memcpy(phy->frame_rcvd, &pPayload->sas_identify,
  2823. sizeof(struct sas_identify_frame)-4);
  2824. phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
  2825. pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
  2826. spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
  2827. if (pm8001_ha->flags == PM8001F_RUN_TIME)
  2828. mdelay(200);/*delay a moment to wait disk to spinup*/
  2829. pm8001_bytes_dmaed(pm8001_ha, phy_id);
  2830. }
  2831. /**
  2832. * hw_event_sata_phy_up -FW tells me a SATA phy up event.
  2833. * @pm8001_ha: our hba card information
  2834. * @piomb: IO message buffer
  2835. */
  2836. static void
  2837. hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2838. {
  2839. struct hw_event_resp *pPayload =
  2840. (struct hw_event_resp *)(piomb + 4);
  2841. u32 lr_evt_status_phyid_portid =
  2842. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  2843. u8 link_rate =
  2844. (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
  2845. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  2846. u8 phy_id =
  2847. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  2848. u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
  2849. u8 portstate = (u8)(npip_portstate & 0x0000000F);
  2850. struct pm8001_port *port = &pm8001_ha->port[port_id];
  2851. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  2852. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  2853. unsigned long flags;
  2854. port->port_state = portstate;
  2855. port->port_attached = 1;
  2856. get_lrate_mode(phy, link_rate);
  2857. phy->phy_type |= PORT_TYPE_SATA;
  2858. phy->phy_attached = 1;
  2859. phy->sas_phy.oob_mode = SATA_OOB_MODE;
  2860. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
  2861. spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
  2862. memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
  2863. sizeof(struct dev_to_host_fis));
  2864. phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
  2865. phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
  2866. phy->identify.device_type = SATA_DEV;
  2867. pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
  2868. spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
  2869. pm8001_bytes_dmaed(pm8001_ha, phy_id);
  2870. }
  2871. /**
  2872. * hw_event_phy_down -we should notify the libsas the phy is down.
  2873. * @pm8001_ha: our hba card information
  2874. * @piomb: IO message buffer
  2875. */
  2876. static void
  2877. hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2878. {
  2879. struct hw_event_resp *pPayload =
  2880. (struct hw_event_resp *)(piomb + 4);
  2881. u32 lr_evt_status_phyid_portid =
  2882. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  2883. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  2884. u8 phy_id =
  2885. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  2886. u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
  2887. u8 portstate = (u8)(npip_portstate & 0x0000000F);
  2888. struct pm8001_port *port = &pm8001_ha->port[port_id];
  2889. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  2890. port->port_state = portstate;
  2891. phy->phy_type = 0;
  2892. phy->identify.device_type = 0;
  2893. phy->phy_attached = 0;
  2894. memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
  2895. switch (portstate) {
  2896. case PORT_VALID:
  2897. break;
  2898. case PORT_INVALID:
  2899. PM8001_MSG_DBG(pm8001_ha,
  2900. pm8001_printk(" PortInvalid portID %d \n", port_id));
  2901. PM8001_MSG_DBG(pm8001_ha,
  2902. pm8001_printk(" Last phy Down and port invalid\n"));
  2903. port->port_attached = 0;
  2904. pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  2905. port_id, phy_id, 0, 0);
  2906. break;
  2907. case PORT_IN_RESET:
  2908. PM8001_MSG_DBG(pm8001_ha,
  2909. pm8001_printk(" Port In Reset portID %d \n", port_id));
  2910. break;
  2911. case PORT_NOT_ESTABLISHED:
  2912. PM8001_MSG_DBG(pm8001_ha,
  2913. pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
  2914. port->port_attached = 0;
  2915. break;
  2916. case PORT_LOSTCOMM:
  2917. PM8001_MSG_DBG(pm8001_ha,
  2918. pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
  2919. PM8001_MSG_DBG(pm8001_ha,
  2920. pm8001_printk(" Last phy Down and port invalid\n"));
  2921. port->port_attached = 0;
  2922. pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
  2923. port_id, phy_id, 0, 0);
  2924. break;
  2925. default:
  2926. port->port_attached = 0;
  2927. PM8001_MSG_DBG(pm8001_ha,
  2928. pm8001_printk(" phy Down and(default) = %x\n",
  2929. portstate));
  2930. break;
  2931. }
  2932. }
  2933. /**
  2934. * mpi_reg_resp -process register device ID response.
  2935. * @pm8001_ha: our hba card information
  2936. * @piomb: IO message buffer
  2937. *
  2938. * when sas layer find a device it will notify LLDD, then the driver register
  2939. * the domain device to FW, this event is the return device ID which the FW
  2940. * has assigned, from now,inter-communication with FW is no longer using the
  2941. * SAS address, use device ID which FW assigned.
  2942. */
  2943. static int mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  2944. {
  2945. u32 status;
  2946. u32 device_id;
  2947. u32 htag;
  2948. struct pm8001_ccb_info *ccb;
  2949. struct pm8001_device *pm8001_dev;
  2950. struct dev_reg_resp *registerRespPayload =
  2951. (struct dev_reg_resp *)(piomb + 4);
  2952. htag = le32_to_cpu(registerRespPayload->tag);
  2953. ccb = &pm8001_ha->ccb_info[registerRespPayload->tag];
  2954. pm8001_dev = ccb->device;
  2955. status = le32_to_cpu(registerRespPayload->status);
  2956. device_id = le32_to_cpu(registerRespPayload->device_id);
  2957. PM8001_MSG_DBG(pm8001_ha,
  2958. pm8001_printk(" register device is status = %d\n", status));
  2959. switch (status) {
  2960. case DEVREG_SUCCESS:
  2961. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("DEVREG_SUCCESS\n"));
  2962. pm8001_dev->device_id = device_id;
  2963. break;
  2964. case DEVREG_FAILURE_OUT_OF_RESOURCE:
  2965. PM8001_MSG_DBG(pm8001_ha,
  2966. pm8001_printk("DEVREG_FAILURE_OUT_OF_RESOURCE\n"));
  2967. break;
  2968. case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
  2969. PM8001_MSG_DBG(pm8001_ha,
  2970. pm8001_printk("DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n"));
  2971. break;
  2972. case DEVREG_FAILURE_INVALID_PHY_ID:
  2973. PM8001_MSG_DBG(pm8001_ha,
  2974. pm8001_printk("DEVREG_FAILURE_INVALID_PHY_ID\n"));
  2975. break;
  2976. case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
  2977. PM8001_MSG_DBG(pm8001_ha,
  2978. pm8001_printk("DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n"));
  2979. break;
  2980. case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
  2981. PM8001_MSG_DBG(pm8001_ha,
  2982. pm8001_printk("DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n"));
  2983. break;
  2984. case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
  2985. PM8001_MSG_DBG(pm8001_ha,
  2986. pm8001_printk("DEVREG_FAILURE_PORT_NOT_VALID_STATE\n"));
  2987. break;
  2988. case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
  2989. PM8001_MSG_DBG(pm8001_ha,
  2990. pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n"));
  2991. break;
  2992. default:
  2993. PM8001_MSG_DBG(pm8001_ha,
  2994. pm8001_printk("DEVREG_FAILURE_DEVICE_TYPE_NOT_UNSORPORTED\n"));
  2995. break;
  2996. }
  2997. complete(pm8001_dev->dcompletion);
  2998. ccb->task = NULL;
  2999. ccb->ccb_tag = 0xFFFFFFFF;
  3000. pm8001_ccb_free(pm8001_ha, htag);
  3001. return 0;
  3002. }
  3003. static int mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3004. {
  3005. u32 status;
  3006. u32 device_id;
  3007. struct dev_reg_resp *registerRespPayload =
  3008. (struct dev_reg_resp *)(piomb + 4);
  3009. status = le32_to_cpu(registerRespPayload->status);
  3010. device_id = le32_to_cpu(registerRespPayload->device_id);
  3011. if (status != 0)
  3012. PM8001_MSG_DBG(pm8001_ha,
  3013. pm8001_printk(" deregister device failed ,status = %x"
  3014. ", device_id = %x\n", status, device_id));
  3015. return 0;
  3016. }
  3017. static int
  3018. mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3019. {
  3020. u32 status;
  3021. struct fw_control_ex fw_control_context;
  3022. struct fw_flash_Update_resp *ppayload =
  3023. (struct fw_flash_Update_resp *)(piomb + 4);
  3024. u32 tag = le32_to_cpu(ppayload->tag);
  3025. struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
  3026. status = le32_to_cpu(ppayload->status);
  3027. memcpy(&fw_control_context,
  3028. ccb->fw_control_context,
  3029. sizeof(fw_control_context));
  3030. switch (status) {
  3031. case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
  3032. PM8001_MSG_DBG(pm8001_ha,
  3033. pm8001_printk(": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n"));
  3034. break;
  3035. case FLASH_UPDATE_IN_PROGRESS:
  3036. PM8001_MSG_DBG(pm8001_ha,
  3037. pm8001_printk(": FLASH_UPDATE_IN_PROGRESS\n"));
  3038. break;
  3039. case FLASH_UPDATE_HDR_ERR:
  3040. PM8001_MSG_DBG(pm8001_ha,
  3041. pm8001_printk(": FLASH_UPDATE_HDR_ERR\n"));
  3042. break;
  3043. case FLASH_UPDATE_OFFSET_ERR:
  3044. PM8001_MSG_DBG(pm8001_ha,
  3045. pm8001_printk(": FLASH_UPDATE_OFFSET_ERR\n"));
  3046. break;
  3047. case FLASH_UPDATE_CRC_ERR:
  3048. PM8001_MSG_DBG(pm8001_ha,
  3049. pm8001_printk(": FLASH_UPDATE_CRC_ERR\n"));
  3050. break;
  3051. case FLASH_UPDATE_LENGTH_ERR:
  3052. PM8001_MSG_DBG(pm8001_ha,
  3053. pm8001_printk(": FLASH_UPDATE_LENGTH_ERR\n"));
  3054. break;
  3055. case FLASH_UPDATE_HW_ERR:
  3056. PM8001_MSG_DBG(pm8001_ha,
  3057. pm8001_printk(": FLASH_UPDATE_HW_ERR\n"));
  3058. break;
  3059. case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
  3060. PM8001_MSG_DBG(pm8001_ha,
  3061. pm8001_printk(": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n"));
  3062. break;
  3063. case FLASH_UPDATE_DISABLED:
  3064. PM8001_MSG_DBG(pm8001_ha,
  3065. pm8001_printk(": FLASH_UPDATE_DISABLED\n"));
  3066. break;
  3067. default:
  3068. PM8001_MSG_DBG(pm8001_ha,
  3069. pm8001_printk("No matched status = %d\n", status));
  3070. break;
  3071. }
  3072. ccb->fw_control_context->fw_control->retcode = status;
  3073. pci_free_consistent(pm8001_ha->pdev,
  3074. fw_control_context.len,
  3075. fw_control_context.virtAddr,
  3076. fw_control_context.phys_addr);
  3077. complete(pm8001_ha->nvmd_completion);
  3078. ccb->task = NULL;
  3079. ccb->ccb_tag = 0xFFFFFFFF;
  3080. pm8001_ccb_free(pm8001_ha, tag);
  3081. return 0;
  3082. }
  3083. static int
  3084. mpi_general_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
  3085. {
  3086. u32 status;
  3087. int i;
  3088. struct general_event_resp *pPayload =
  3089. (struct general_event_resp *)(piomb + 4);
  3090. status = le32_to_cpu(pPayload->status);
  3091. PM8001_MSG_DBG(pm8001_ha,
  3092. pm8001_printk(" status = 0x%x\n", status));
  3093. for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
  3094. PM8001_MSG_DBG(pm8001_ha,
  3095. pm8001_printk("inb_IOMB_payload[0x%x] 0x%x, \n", i,
  3096. pPayload->inb_IOMB_payload[i]));
  3097. return 0;
  3098. }
  3099. static int
  3100. mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3101. {
  3102. struct sas_task *t;
  3103. struct pm8001_ccb_info *ccb;
  3104. unsigned long flags;
  3105. u32 status ;
  3106. u32 tag, scp;
  3107. struct task_status_struct *ts;
  3108. struct task_abort_resp *pPayload =
  3109. (struct task_abort_resp *)(piomb + 4);
  3110. ccb = &pm8001_ha->ccb_info[pPayload->tag];
  3111. t = ccb->task;
  3112. status = le32_to_cpu(pPayload->status);
  3113. tag = le32_to_cpu(pPayload->tag);
  3114. scp = le32_to_cpu(pPayload->scp);
  3115. PM8001_IO_DBG(pm8001_ha,
  3116. pm8001_printk(" status = 0x%x\n", status));
  3117. if (t == NULL)
  3118. return -1;
  3119. ts = &t->task_status;
  3120. if (status != 0)
  3121. PM8001_FAIL_DBG(pm8001_ha,
  3122. pm8001_printk("task abort failed status 0x%x ,"
  3123. "tag = 0x%x, scp= 0x%x\n", status, tag, scp));
  3124. switch (status) {
  3125. case IO_SUCCESS:
  3126. PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
  3127. ts->resp = SAS_TASK_COMPLETE;
  3128. ts->stat = SAM_GOOD;
  3129. break;
  3130. case IO_NOT_VALID:
  3131. PM8001_EH_DBG(pm8001_ha, pm8001_printk("IO_NOT_VALID\n"));
  3132. ts->resp = TMF_RESP_FUNC_FAILED;
  3133. break;
  3134. }
  3135. spin_lock_irqsave(&t->task_state_lock, flags);
  3136. t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
  3137. t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
  3138. t->task_state_flags |= SAS_TASK_STATE_DONE;
  3139. spin_unlock_irqrestore(&t->task_state_lock, flags);
  3140. pm8001_ccb_task_free(pm8001_ha, t, ccb, pPayload->tag);
  3141. mb();
  3142. t->task_done(t);
  3143. return 0;
  3144. }
  3145. /**
  3146. * mpi_hw_event -The hw event has come.
  3147. * @pm8001_ha: our hba card information
  3148. * @piomb: IO message buffer
  3149. */
  3150. static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void* piomb)
  3151. {
  3152. unsigned long flags;
  3153. struct hw_event_resp *pPayload =
  3154. (struct hw_event_resp *)(piomb + 4);
  3155. u32 lr_evt_status_phyid_portid =
  3156. le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
  3157. u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
  3158. u8 phy_id =
  3159. (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
  3160. u16 eventType =
  3161. (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
  3162. u8 status =
  3163. (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
  3164. struct sas_ha_struct *sas_ha = pm8001_ha->sas;
  3165. struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
  3166. struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
  3167. PM8001_MSG_DBG(pm8001_ha,
  3168. pm8001_printk("outbound queue HW event & event type : "));
  3169. switch (eventType) {
  3170. case HW_EVENT_PHY_START_STATUS:
  3171. PM8001_MSG_DBG(pm8001_ha,
  3172. pm8001_printk("HW_EVENT_PHY_START_STATUS"
  3173. " status = %x\n", status));
  3174. if (status == 0) {
  3175. phy->phy_state = 1;
  3176. if (pm8001_ha->flags == PM8001F_RUN_TIME)
  3177. complete(phy->enable_completion);
  3178. }
  3179. break;
  3180. case HW_EVENT_SAS_PHY_UP:
  3181. PM8001_MSG_DBG(pm8001_ha,
  3182. pm8001_printk("HW_EVENT_PHY_START_STATUS \n"));
  3183. hw_event_sas_phy_up(pm8001_ha, piomb);
  3184. break;
  3185. case HW_EVENT_SATA_PHY_UP:
  3186. PM8001_MSG_DBG(pm8001_ha,
  3187. pm8001_printk("HW_EVENT_SATA_PHY_UP \n"));
  3188. hw_event_sata_phy_up(pm8001_ha, piomb);
  3189. break;
  3190. case HW_EVENT_PHY_STOP_STATUS:
  3191. PM8001_MSG_DBG(pm8001_ha,
  3192. pm8001_printk("HW_EVENT_PHY_STOP_STATUS "
  3193. "status = %x\n", status));
  3194. if (status == 0)
  3195. phy->phy_state = 0;
  3196. break;
  3197. case HW_EVENT_SATA_SPINUP_HOLD:
  3198. PM8001_MSG_DBG(pm8001_ha,
  3199. pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD \n"));
  3200. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
  3201. break;
  3202. case HW_EVENT_PHY_DOWN:
  3203. PM8001_MSG_DBG(pm8001_ha,
  3204. pm8001_printk("HW_EVENT_PHY_DOWN \n"));
  3205. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
  3206. phy->phy_attached = 0;
  3207. phy->phy_state = 0;
  3208. hw_event_phy_down(pm8001_ha, piomb);
  3209. break;
  3210. case HW_EVENT_PORT_INVALID:
  3211. PM8001_MSG_DBG(pm8001_ha,
  3212. pm8001_printk("HW_EVENT_PORT_INVALID\n"));
  3213. sas_phy_disconnected(sas_phy);
  3214. phy->phy_attached = 0;
  3215. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3216. break;
  3217. /* the broadcast change primitive received, tell the LIBSAS this event
  3218. to revalidate the sas domain*/
  3219. case HW_EVENT_BROADCAST_CHANGE:
  3220. PM8001_MSG_DBG(pm8001_ha,
  3221. pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
  3222. pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
  3223. port_id, phy_id, 1, 0);
  3224. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3225. sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
  3226. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3227. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3228. break;
  3229. case HW_EVENT_PHY_ERROR:
  3230. PM8001_MSG_DBG(pm8001_ha,
  3231. pm8001_printk("HW_EVENT_PHY_ERROR\n"));
  3232. sas_phy_disconnected(&phy->sas_phy);
  3233. phy->phy_attached = 0;
  3234. sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
  3235. break;
  3236. case HW_EVENT_BROADCAST_EXP:
  3237. PM8001_MSG_DBG(pm8001_ha,
  3238. pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
  3239. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3240. sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
  3241. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3242. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3243. break;
  3244. case HW_EVENT_LINK_ERR_INVALID_DWORD:
  3245. PM8001_MSG_DBG(pm8001_ha,
  3246. pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
  3247. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3248. HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
  3249. sas_phy_disconnected(sas_phy);
  3250. phy->phy_attached = 0;
  3251. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3252. break;
  3253. case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
  3254. PM8001_MSG_DBG(pm8001_ha,
  3255. pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
  3256. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3257. HW_EVENT_LINK_ERR_DISPARITY_ERROR,
  3258. port_id, phy_id, 0, 0);
  3259. sas_phy_disconnected(sas_phy);
  3260. phy->phy_attached = 0;
  3261. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3262. break;
  3263. case HW_EVENT_LINK_ERR_CODE_VIOLATION:
  3264. PM8001_MSG_DBG(pm8001_ha,
  3265. pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
  3266. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3267. HW_EVENT_LINK_ERR_CODE_VIOLATION,
  3268. port_id, phy_id, 0, 0);
  3269. sas_phy_disconnected(sas_phy);
  3270. phy->phy_attached = 0;
  3271. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3272. break;
  3273. case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
  3274. PM8001_MSG_DBG(pm8001_ha,
  3275. pm8001_printk("HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
  3276. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3277. HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
  3278. port_id, phy_id, 0, 0);
  3279. sas_phy_disconnected(sas_phy);
  3280. phy->phy_attached = 0;
  3281. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3282. break;
  3283. case HW_EVENT_MALFUNCTION:
  3284. PM8001_MSG_DBG(pm8001_ha,
  3285. pm8001_printk("HW_EVENT_MALFUNCTION\n"));
  3286. break;
  3287. case HW_EVENT_BROADCAST_SES:
  3288. PM8001_MSG_DBG(pm8001_ha,
  3289. pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
  3290. spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
  3291. sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
  3292. spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
  3293. sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
  3294. break;
  3295. case HW_EVENT_INBOUND_CRC_ERROR:
  3296. PM8001_MSG_DBG(pm8001_ha,
  3297. pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
  3298. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3299. HW_EVENT_INBOUND_CRC_ERROR,
  3300. port_id, phy_id, 0, 0);
  3301. break;
  3302. case HW_EVENT_HARD_RESET_RECEIVED:
  3303. PM8001_MSG_DBG(pm8001_ha,
  3304. pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
  3305. sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
  3306. break;
  3307. case HW_EVENT_ID_FRAME_TIMEOUT:
  3308. PM8001_MSG_DBG(pm8001_ha,
  3309. pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
  3310. sas_phy_disconnected(sas_phy);
  3311. phy->phy_attached = 0;
  3312. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3313. break;
  3314. case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
  3315. PM8001_MSG_DBG(pm8001_ha,
  3316. pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED \n"));
  3317. pm8001_hw_event_ack_req(pm8001_ha, 0,
  3318. HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
  3319. port_id, phy_id, 0, 0);
  3320. sas_phy_disconnected(sas_phy);
  3321. phy->phy_attached = 0;
  3322. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3323. break;
  3324. case HW_EVENT_PORT_RESET_TIMER_TMO:
  3325. PM8001_MSG_DBG(pm8001_ha,
  3326. pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO \n"));
  3327. sas_phy_disconnected(sas_phy);
  3328. phy->phy_attached = 0;
  3329. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3330. break;
  3331. case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
  3332. PM8001_MSG_DBG(pm8001_ha,
  3333. pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO \n"));
  3334. sas_phy_disconnected(sas_phy);
  3335. phy->phy_attached = 0;
  3336. sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
  3337. break;
  3338. case HW_EVENT_PORT_RECOVER:
  3339. PM8001_MSG_DBG(pm8001_ha,
  3340. pm8001_printk("HW_EVENT_PORT_RECOVER \n"));
  3341. break;
  3342. case HW_EVENT_PORT_RESET_COMPLETE:
  3343. PM8001_MSG_DBG(pm8001_ha,
  3344. pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE \n"));
  3345. break;
  3346. case EVENT_BROADCAST_ASYNCH_EVENT:
  3347. PM8001_MSG_DBG(pm8001_ha,
  3348. pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
  3349. break;
  3350. default:
  3351. PM8001_MSG_DBG(pm8001_ha,
  3352. pm8001_printk("Unknown event type = %x\n", eventType));
  3353. break;
  3354. }
  3355. return 0;
  3356. }
  3357. /**
  3358. * process_one_iomb - process one outbound Queue memory block
  3359. * @pm8001_ha: our hba card information
  3360. * @piomb: IO message buffer
  3361. */
  3362. static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
  3363. {
  3364. u32 pHeader = (u32)*(u32 *)piomb;
  3365. u8 opc = (u8)((le32_to_cpu(pHeader)) & 0xFFF);
  3366. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("process_one_iomb:"));
  3367. switch (opc) {
  3368. case OPC_OUB_ECHO:
  3369. PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO \n"));
  3370. break;
  3371. case OPC_OUB_HW_EVENT:
  3372. PM8001_MSG_DBG(pm8001_ha,
  3373. pm8001_printk("OPC_OUB_HW_EVENT \n"));
  3374. mpi_hw_event(pm8001_ha, piomb);
  3375. break;
  3376. case OPC_OUB_SSP_COMP:
  3377. PM8001_MSG_DBG(pm8001_ha,
  3378. pm8001_printk("OPC_OUB_SSP_COMP \n"));
  3379. mpi_ssp_completion(pm8001_ha, piomb);
  3380. break;
  3381. case OPC_OUB_SMP_COMP:
  3382. PM8001_MSG_DBG(pm8001_ha,
  3383. pm8001_printk("OPC_OUB_SMP_COMP \n"));
  3384. mpi_smp_completion(pm8001_ha, piomb);
  3385. break;
  3386. case OPC_OUB_LOCAL_PHY_CNTRL:
  3387. PM8001_MSG_DBG(pm8001_ha,
  3388. pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
  3389. mpi_local_phy_ctl(pm8001_ha, piomb);
  3390. break;
  3391. case OPC_OUB_DEV_REGIST:
  3392. PM8001_MSG_DBG(pm8001_ha,
  3393. pm8001_printk("OPC_OUB_DEV_REGIST \n"));
  3394. mpi_reg_resp(pm8001_ha, piomb);
  3395. break;
  3396. case OPC_OUB_DEREG_DEV:
  3397. PM8001_MSG_DBG(pm8001_ha,
  3398. pm8001_printk("unresgister the deviece \n"));
  3399. mpi_dereg_resp(pm8001_ha, piomb);
  3400. break;
  3401. case OPC_OUB_GET_DEV_HANDLE:
  3402. PM8001_MSG_DBG(pm8001_ha,
  3403. pm8001_printk("OPC_OUB_GET_DEV_HANDLE \n"));
  3404. break;
  3405. case OPC_OUB_SATA_COMP:
  3406. PM8001_MSG_DBG(pm8001_ha,
  3407. pm8001_printk("OPC_OUB_SATA_COMP \n"));
  3408. mpi_sata_completion(pm8001_ha, piomb);
  3409. break;
  3410. case OPC_OUB_SATA_EVENT:
  3411. PM8001_MSG_DBG(pm8001_ha,
  3412. pm8001_printk("OPC_OUB_SATA_EVENT \n"));
  3413. mpi_sata_event(pm8001_ha, piomb);
  3414. break;
  3415. case OPC_OUB_SSP_EVENT:
  3416. PM8001_MSG_DBG(pm8001_ha,
  3417. pm8001_printk("OPC_OUB_SSP_EVENT\n"));
  3418. mpi_ssp_event(pm8001_ha, piomb);
  3419. break;
  3420. case OPC_OUB_DEV_HANDLE_ARRIV:
  3421. PM8001_MSG_DBG(pm8001_ha,
  3422. pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
  3423. /*This is for target*/
  3424. break;
  3425. case OPC_OUB_SSP_RECV_EVENT:
  3426. PM8001_MSG_DBG(pm8001_ha,
  3427. pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
  3428. /*This is for target*/
  3429. break;
  3430. case OPC_OUB_DEV_INFO:
  3431. PM8001_MSG_DBG(pm8001_ha,
  3432. pm8001_printk("OPC_OUB_DEV_INFO\n"));
  3433. break;
  3434. case OPC_OUB_FW_FLASH_UPDATE:
  3435. PM8001_MSG_DBG(pm8001_ha,
  3436. pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
  3437. mpi_fw_flash_update_resp(pm8001_ha, piomb);
  3438. break;
  3439. case OPC_OUB_GPIO_RESPONSE:
  3440. PM8001_MSG_DBG(pm8001_ha,
  3441. pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
  3442. break;
  3443. case OPC_OUB_GPIO_EVENT:
  3444. PM8001_MSG_DBG(pm8001_ha,
  3445. pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
  3446. break;
  3447. case OPC_OUB_GENERAL_EVENT:
  3448. PM8001_MSG_DBG(pm8001_ha,
  3449. pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
  3450. mpi_general_event(pm8001_ha, piomb);
  3451. break;
  3452. case OPC_OUB_SSP_ABORT_RSP:
  3453. PM8001_MSG_DBG(pm8001_ha,
  3454. pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
  3455. mpi_task_abort_resp(pm8001_ha, piomb);
  3456. break;
  3457. case OPC_OUB_SATA_ABORT_RSP:
  3458. PM8001_MSG_DBG(pm8001_ha,
  3459. pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
  3460. mpi_task_abort_resp(pm8001_ha, piomb);
  3461. break;
  3462. case OPC_OUB_SAS_DIAG_MODE_START_END:
  3463. PM8001_MSG_DBG(pm8001_ha,
  3464. pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
  3465. break;
  3466. case OPC_OUB_SAS_DIAG_EXECUTE:
  3467. PM8001_MSG_DBG(pm8001_ha,
  3468. pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
  3469. break;
  3470. case OPC_OUB_GET_TIME_STAMP:
  3471. PM8001_MSG_DBG(pm8001_ha,
  3472. pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
  3473. break;
  3474. case OPC_OUB_SAS_HW_EVENT_ACK:
  3475. PM8001_MSG_DBG(pm8001_ha,
  3476. pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
  3477. break;
  3478. case OPC_OUB_PORT_CONTROL:
  3479. PM8001_MSG_DBG(pm8001_ha,
  3480. pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
  3481. break;
  3482. case OPC_OUB_SMP_ABORT_RSP:
  3483. PM8001_MSG_DBG(pm8001_ha,
  3484. pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
  3485. mpi_task_abort_resp(pm8001_ha, piomb);
  3486. break;
  3487. case OPC_OUB_GET_NVMD_DATA:
  3488. PM8001_MSG_DBG(pm8001_ha,
  3489. pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
  3490. mpi_get_nvmd_resp(pm8001_ha, piomb);
  3491. break;
  3492. case OPC_OUB_SET_NVMD_DATA:
  3493. PM8001_MSG_DBG(pm8001_ha,
  3494. pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
  3495. mpi_set_nvmd_resp(pm8001_ha, piomb);
  3496. break;
  3497. case OPC_OUB_DEVICE_HANDLE_REMOVAL:
  3498. PM8001_MSG_DBG(pm8001_ha,
  3499. pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
  3500. break;
  3501. case OPC_OUB_SET_DEVICE_STATE:
  3502. PM8001_MSG_DBG(pm8001_ha,
  3503. pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
  3504. mpi_set_dev_state_resp(pm8001_ha, piomb);
  3505. break;
  3506. case OPC_OUB_GET_DEVICE_STATE:
  3507. PM8001_MSG_DBG(pm8001_ha,
  3508. pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
  3509. break;
  3510. case OPC_OUB_SET_DEV_INFO:
  3511. PM8001_MSG_DBG(pm8001_ha,
  3512. pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
  3513. break;
  3514. case OPC_OUB_SAS_RE_INITIALIZE:
  3515. PM8001_MSG_DBG(pm8001_ha,
  3516. pm8001_printk("OPC_OUB_SAS_RE_INITIALIZE\n"));
  3517. break;
  3518. default:
  3519. PM8001_MSG_DBG(pm8001_ha,
  3520. pm8001_printk("Unknown outbound Queue IOMB OPC = %x\n",
  3521. opc));
  3522. break;
  3523. }
  3524. }
  3525. static int process_oq(struct pm8001_hba_info *pm8001_ha)
  3526. {
  3527. struct outbound_queue_table *circularQ;
  3528. void *pMsg1 = NULL;
  3529. u8 bc = 0;
  3530. u32 ret = MPI_IO_STATUS_FAIL;
  3531. circularQ = &pm8001_ha->outbnd_q_tbl[0];
  3532. do {
  3533. ret = mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
  3534. if (MPI_IO_STATUS_SUCCESS == ret) {
  3535. /* process the outbound message */
  3536. process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
  3537. /* free the message from the outbound circular buffer */
  3538. mpi_msg_free_set(pm8001_ha, pMsg1, circularQ, bc);
  3539. }
  3540. if (MPI_IO_STATUS_BUSY == ret) {
  3541. u32 producer_idx;
  3542. /* Update the producer index from SPC */
  3543. producer_idx = pm8001_read_32(circularQ->pi_virt);
  3544. circularQ->producer_index = cpu_to_le32(producer_idx);
  3545. if (circularQ->producer_index ==
  3546. circularQ->consumer_idx)
  3547. /* OQ is empty */
  3548. break;
  3549. }
  3550. } while (1);
  3551. return ret;
  3552. }
  3553. /* PCI_DMA_... to our direction translation. */
  3554. static const u8 data_dir_flags[] = {
  3555. [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
  3556. [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
  3557. [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
  3558. [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
  3559. };
  3560. static void
  3561. pm8001_chip_make_sg(struct scatterlist *scatter, int nr, void *prd)
  3562. {
  3563. int i;
  3564. struct scatterlist *sg;
  3565. struct pm8001_prd *buf_prd = prd;
  3566. for_each_sg(scatter, sg, nr, i) {
  3567. buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
  3568. buf_prd->im_len.len = cpu_to_le32(sg_dma_len(sg));
  3569. buf_prd->im_len.e = 0;
  3570. buf_prd++;
  3571. }
  3572. }
  3573. static void build_smp_cmd(u32 deviceID, u32 hTag, struct smp_req *psmp_cmd)
  3574. {
  3575. psmp_cmd->tag = cpu_to_le32(hTag);
  3576. psmp_cmd->device_id = cpu_to_le32(deviceID);
  3577. psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
  3578. }
  3579. /**
  3580. * pm8001_chip_smp_req - send a SMP task to FW
  3581. * @pm8001_ha: our hba card information.
  3582. * @ccb: the ccb information this request used.
  3583. */
  3584. static int pm8001_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
  3585. struct pm8001_ccb_info *ccb)
  3586. {
  3587. int elem, rc;
  3588. struct sas_task *task = ccb->task;
  3589. struct domain_device *dev = task->dev;
  3590. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  3591. struct scatterlist *sg_req, *sg_resp;
  3592. u32 req_len, resp_len;
  3593. struct smp_req smp_cmd;
  3594. u32 opc;
  3595. struct inbound_queue_table *circularQ;
  3596. memset(&smp_cmd, 0, sizeof(smp_cmd));
  3597. /*
  3598. * DMA-map SMP request, response buffers
  3599. */
  3600. sg_req = &task->smp_task.smp_req;
  3601. elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
  3602. if (!elem)
  3603. return -ENOMEM;
  3604. req_len = sg_dma_len(sg_req);
  3605. sg_resp = &task->smp_task.smp_resp;
  3606. elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  3607. if (!elem) {
  3608. rc = -ENOMEM;
  3609. goto err_out;
  3610. }
  3611. resp_len = sg_dma_len(sg_resp);
  3612. /* must be in dwords */
  3613. if ((req_len & 0x3) || (resp_len & 0x3)) {
  3614. rc = -EINVAL;
  3615. goto err_out_2;
  3616. }
  3617. opc = OPC_INB_SMP_REQUEST;
  3618. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3619. smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
  3620. smp_cmd.long_smp_req.long_req_addr =
  3621. cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
  3622. smp_cmd.long_smp_req.long_req_size =
  3623. cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
  3624. smp_cmd.long_smp_req.long_resp_addr =
  3625. cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_resp));
  3626. smp_cmd.long_smp_req.long_resp_size =
  3627. cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
  3628. build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag, &smp_cmd);
  3629. mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd);
  3630. return 0;
  3631. err_out_2:
  3632. dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
  3633. PCI_DMA_FROMDEVICE);
  3634. err_out:
  3635. dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
  3636. PCI_DMA_TODEVICE);
  3637. return rc;
  3638. }
  3639. /**
  3640. * pm8001_chip_ssp_io_req - send a SSP task to FW
  3641. * @pm8001_ha: our hba card information.
  3642. * @ccb: the ccb information this request used.
  3643. */
  3644. static int pm8001_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
  3645. struct pm8001_ccb_info *ccb)
  3646. {
  3647. struct sas_task *task = ccb->task;
  3648. struct domain_device *dev = task->dev;
  3649. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  3650. struct ssp_ini_io_start_req ssp_cmd;
  3651. u32 tag = ccb->ccb_tag;
  3652. int ret;
  3653. __le64 phys_addr;
  3654. struct inbound_queue_table *circularQ;
  3655. u32 opc = OPC_INB_SSPINIIOSTART;
  3656. memset(&ssp_cmd, 0, sizeof(ssp_cmd));
  3657. memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
  3658. ssp_cmd.dir_m_tlr = data_dir_flags[task->data_dir] << 8 | 0x0;/*0 for
  3659. SAS 1.1 compatible TLR*/
  3660. ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
  3661. ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
  3662. ssp_cmd.tag = cpu_to_le32(tag);
  3663. if (task->ssp_task.enable_first_burst)
  3664. ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
  3665. ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
  3666. ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
  3667. memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cdb, 16);
  3668. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3669. /* fill in PRD (scatter/gather) table, if any */
  3670. if (task->num_scatter > 1) {
  3671. pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
  3672. phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
  3673. offsetof(struct pm8001_ccb_info, buf_prd[0]));
  3674. ssp_cmd.addr_low = lower_32_bits(phys_addr);
  3675. ssp_cmd.addr_high = upper_32_bits(phys_addr);
  3676. ssp_cmd.esgl = cpu_to_le32(1<<31);
  3677. } else if (task->num_scatter == 1) {
  3678. __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
  3679. ssp_cmd.addr_low = lower_32_bits(dma_addr);
  3680. ssp_cmd.addr_high = upper_32_bits(dma_addr);
  3681. ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
  3682. ssp_cmd.esgl = 0;
  3683. } else if (task->num_scatter == 0) {
  3684. ssp_cmd.addr_low = 0;
  3685. ssp_cmd.addr_high = 0;
  3686. ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
  3687. ssp_cmd.esgl = 0;
  3688. }
  3689. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &ssp_cmd);
  3690. return ret;
  3691. }
  3692. static int pm8001_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
  3693. struct pm8001_ccb_info *ccb)
  3694. {
  3695. struct sas_task *task = ccb->task;
  3696. struct domain_device *dev = task->dev;
  3697. struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
  3698. u32 tag = ccb->ccb_tag;
  3699. int ret;
  3700. struct sata_start_req sata_cmd;
  3701. u32 hdr_tag, ncg_tag = 0;
  3702. __le64 phys_addr;
  3703. u32 ATAP = 0x0;
  3704. u32 dir;
  3705. struct inbound_queue_table *circularQ;
  3706. u32 opc = OPC_INB_SATA_HOST_OPSTART;
  3707. memset(&sata_cmd, 0, sizeof(sata_cmd));
  3708. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3709. if (task->data_dir == PCI_DMA_NONE) {
  3710. ATAP = 0x04; /* no data*/
  3711. PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data \n"));
  3712. } else if (likely(!task->ata_task.device_control_reg_update)) {
  3713. if (task->ata_task.dma_xfer) {
  3714. ATAP = 0x06; /* DMA */
  3715. PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA \n"));
  3716. } else {
  3717. ATAP = 0x05; /* PIO*/
  3718. PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO \n"));
  3719. }
  3720. if (task->ata_task.use_ncq &&
  3721. dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
  3722. ATAP = 0x07; /* FPDMA */
  3723. PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA \n"));
  3724. }
  3725. }
  3726. if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag))
  3727. ncg_tag = cpu_to_le32(hdr_tag);
  3728. dir = data_dir_flags[task->data_dir] << 8;
  3729. sata_cmd.tag = cpu_to_le32(tag);
  3730. sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
  3731. sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
  3732. sata_cmd.ncqtag_atap_dir_m =
  3733. cpu_to_le32(((ncg_tag & 0xff)<<16)|((ATAP & 0x3f) << 10) | dir);
  3734. sata_cmd.sata_fis = task->ata_task.fis;
  3735. if (likely(!task->ata_task.device_control_reg_update))
  3736. sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
  3737. sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
  3738. /* fill in PRD (scatter/gather) table, if any */
  3739. if (task->num_scatter > 1) {
  3740. pm8001_chip_make_sg(task->scatter, ccb->n_elem, ccb->buf_prd);
  3741. phys_addr = cpu_to_le64(ccb->ccb_dma_handle +
  3742. offsetof(struct pm8001_ccb_info, buf_prd[0]));
  3743. sata_cmd.addr_low = lower_32_bits(phys_addr);
  3744. sata_cmd.addr_high = upper_32_bits(phys_addr);
  3745. sata_cmd.esgl = cpu_to_le32(1 << 31);
  3746. } else if (task->num_scatter == 1) {
  3747. __le64 dma_addr = cpu_to_le64(sg_dma_address(task->scatter));
  3748. sata_cmd.addr_low = lower_32_bits(dma_addr);
  3749. sata_cmd.addr_high = upper_32_bits(dma_addr);
  3750. sata_cmd.len = cpu_to_le32(task->total_xfer_len);
  3751. sata_cmd.esgl = 0;
  3752. } else if (task->num_scatter == 0) {
  3753. sata_cmd.addr_low = 0;
  3754. sata_cmd.addr_high = 0;
  3755. sata_cmd.len = cpu_to_le32(task->total_xfer_len);
  3756. sata_cmd.esgl = 0;
  3757. }
  3758. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd);
  3759. return ret;
  3760. }
  3761. /**
  3762. * pm8001_chip_phy_start_req - start phy via PHY_START COMMAND
  3763. * @pm8001_ha: our hba card information.
  3764. * @num: the inbound queue number
  3765. * @phy_id: the phy id which we wanted to start up.
  3766. */
  3767. static int
  3768. pm8001_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
  3769. {
  3770. struct phy_start_req payload;
  3771. struct inbound_queue_table *circularQ;
  3772. int ret;
  3773. u32 tag = 0x01;
  3774. u32 opcode = OPC_INB_PHYSTART;
  3775. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3776. memset(&payload, 0, sizeof(payload));
  3777. payload.tag = cpu_to_le32(tag);
  3778. /*
  3779. ** [0:7] PHY Identifier
  3780. ** [8:11] link rate 1.5G, 3G, 6G
  3781. ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b both
  3782. ** [14] 0b disable spin up hold; 1b enable spin up hold
  3783. */
  3784. payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
  3785. LINKMODE_AUTO | LINKRATE_15 |
  3786. LINKRATE_30 | LINKRATE_60 | phy_id);
  3787. payload.sas_identify.dev_type = SAS_END_DEV;
  3788. payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
  3789. memcpy(payload.sas_identify.sas_addr,
  3790. pm8001_ha->sas_addr, SAS_ADDR_SIZE);
  3791. payload.sas_identify.phy_id = phy_id;
  3792. ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
  3793. return ret;
  3794. }
  3795. /**
  3796. * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
  3797. * @pm8001_ha: our hba card information.
  3798. * @num: the inbound queue number
  3799. * @phy_id: the phy id which we wanted to start up.
  3800. */
  3801. static int pm8001_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
  3802. u8 phy_id)
  3803. {
  3804. struct phy_stop_req payload;
  3805. struct inbound_queue_table *circularQ;
  3806. int ret;
  3807. u32 tag = 0x01;
  3808. u32 opcode = OPC_INB_PHYSTOP;
  3809. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3810. memset(&payload, 0, sizeof(payload));
  3811. payload.tag = cpu_to_le32(tag);
  3812. payload.phy_id = cpu_to_le32(phy_id);
  3813. ret = mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload);
  3814. return ret;
  3815. }
  3816. /**
  3817. * see comments on mpi_reg_resp.
  3818. */
  3819. static int pm8001_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
  3820. struct pm8001_device *pm8001_dev, u32 flag)
  3821. {
  3822. struct reg_dev_req payload;
  3823. u32 opc;
  3824. u32 stp_sspsmp_sata = 0x4;
  3825. struct inbound_queue_table *circularQ;
  3826. u32 linkrate, phy_id;
  3827. int rc, tag = 0xdeadbeef;
  3828. struct pm8001_ccb_info *ccb;
  3829. u8 retryFlag = 0x1;
  3830. u16 firstBurstSize = 0;
  3831. u16 ITNT = 2000;
  3832. struct domain_device *dev = pm8001_dev->sas_device;
  3833. struct domain_device *parent_dev = dev->parent;
  3834. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3835. memset(&payload, 0, sizeof(payload));
  3836. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  3837. if (rc)
  3838. return rc;
  3839. ccb = &pm8001_ha->ccb_info[tag];
  3840. ccb->device = pm8001_dev;
  3841. ccb->ccb_tag = tag;
  3842. payload.tag = cpu_to_le32(tag);
  3843. if (flag == 1)
  3844. stp_sspsmp_sata = 0x02; /*direct attached sata */
  3845. else {
  3846. if (pm8001_dev->dev_type == SATA_DEV)
  3847. stp_sspsmp_sata = 0x00; /* stp*/
  3848. else if (pm8001_dev->dev_type == SAS_END_DEV ||
  3849. pm8001_dev->dev_type == EDGE_DEV ||
  3850. pm8001_dev->dev_type == FANOUT_DEV)
  3851. stp_sspsmp_sata = 0x01; /*ssp or smp*/
  3852. }
  3853. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
  3854. phy_id = parent_dev->ex_dev.ex_phy->phy_id;
  3855. else
  3856. phy_id = pm8001_dev->attached_phy;
  3857. opc = OPC_INB_REG_DEV;
  3858. linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
  3859. pm8001_dev->sas_device->linkrate : dev->port->linkrate;
  3860. payload.phyid_portid =
  3861. cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0x0F) |
  3862. ((phy_id & 0x0F) << 4));
  3863. payload.dtype_dlr_retry = cpu_to_le32((retryFlag & 0x01) |
  3864. ((linkrate & 0x0F) * 0x1000000) |
  3865. ((stp_sspsmp_sata & 0x03) * 0x10000000));
  3866. payload.firstburstsize_ITNexustimeout =
  3867. cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
  3868. memcpy(&payload.sas_addr_hi, pm8001_dev->sas_device->sas_addr,
  3869. SAS_ADDR_SIZE);
  3870. rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  3871. return rc;
  3872. }
  3873. /**
  3874. * see comments on mpi_reg_resp.
  3875. */
  3876. static int pm8001_chip_dereg_dev_req(struct pm8001_hba_info *pm8001_ha,
  3877. u32 device_id)
  3878. {
  3879. struct dereg_dev_req payload;
  3880. u32 opc = OPC_INB_DEREG_DEV_HANDLE;
  3881. int ret;
  3882. struct inbound_queue_table *circularQ;
  3883. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3884. memset(&payload, 0, sizeof(payload));
  3885. payload.tag = 1;
  3886. payload.device_id = cpu_to_le32(device_id);
  3887. PM8001_MSG_DBG(pm8001_ha,
  3888. pm8001_printk("unregister device device_id = %d\n", device_id));
  3889. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  3890. return ret;
  3891. }
  3892. /**
  3893. * pm8001_chip_phy_ctl_req - support the local phy operation
  3894. * @pm8001_ha: our hba card information.
  3895. * @num: the inbound queue number
  3896. * @phy_id: the phy id which we wanted to operate
  3897. * @phy_op:
  3898. */
  3899. static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
  3900. u32 phyId, u32 phy_op)
  3901. {
  3902. struct local_phy_ctl_req payload;
  3903. struct inbound_queue_table *circularQ;
  3904. int ret;
  3905. u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
  3906. memset((u8 *)&payload, 0, sizeof(payload));
  3907. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3908. payload.tag = 1;
  3909. payload.phyop_phyid =
  3910. cpu_to_le32(((phy_op & 0xff) << 8) | (phyId & 0x0F));
  3911. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  3912. return ret;
  3913. }
  3914. static u32 pm8001_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
  3915. {
  3916. u32 value;
  3917. #ifdef PM8001_USE_MSIX
  3918. return 1;
  3919. #endif
  3920. value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
  3921. if (value)
  3922. return 1;
  3923. return 0;
  3924. }
  3925. /**
  3926. * pm8001_chip_isr - PM8001 isr handler.
  3927. * @pm8001_ha: our hba card information.
  3928. * @irq: irq number.
  3929. * @stat: stat.
  3930. */
  3931. static irqreturn_t
  3932. pm8001_chip_isr(struct pm8001_hba_info *pm8001_ha)
  3933. {
  3934. unsigned long flags;
  3935. spin_lock_irqsave(&pm8001_ha->lock, flags);
  3936. pm8001_chip_interrupt_disable(pm8001_ha);
  3937. process_oq(pm8001_ha);
  3938. pm8001_chip_interrupt_enable(pm8001_ha);
  3939. spin_unlock_irqrestore(&pm8001_ha->lock, flags);
  3940. return IRQ_HANDLED;
  3941. }
  3942. static int send_task_abort(struct pm8001_hba_info *pm8001_ha, u32 opc,
  3943. u32 dev_id, u8 flag, u32 task_tag, u32 cmd_tag)
  3944. {
  3945. struct task_abort_req task_abort;
  3946. struct inbound_queue_table *circularQ;
  3947. int ret;
  3948. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  3949. memset(&task_abort, 0, sizeof(task_abort));
  3950. if (ABORT_SINGLE == (flag & ABORT_MASK)) {
  3951. task_abort.abort_all = 0;
  3952. task_abort.device_id = cpu_to_le32(dev_id);
  3953. task_abort.tag_to_abort = cpu_to_le32(task_tag);
  3954. task_abort.tag = cpu_to_le32(cmd_tag);
  3955. } else if (ABORT_ALL == (flag & ABORT_MASK)) {
  3956. task_abort.abort_all = cpu_to_le32(1);
  3957. task_abort.device_id = cpu_to_le32(dev_id);
  3958. task_abort.tag = cpu_to_le32(cmd_tag);
  3959. }
  3960. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort);
  3961. return ret;
  3962. }
  3963. /**
  3964. * pm8001_chip_abort_task - SAS abort task when error or exception happened.
  3965. * @task: the task we wanted to aborted.
  3966. * @flag: the abort flag.
  3967. */
  3968. static int pm8001_chip_abort_task(struct pm8001_hba_info *pm8001_ha,
  3969. struct pm8001_device *pm8001_dev, u8 flag, u32 task_tag, u32 cmd_tag)
  3970. {
  3971. u32 opc, device_id;
  3972. int rc = TMF_RESP_FUNC_FAILED;
  3973. PM8001_EH_DBG(pm8001_ha, pm8001_printk("cmd_tag = %x, abort task tag"
  3974. " = %x", cmd_tag, task_tag));
  3975. if (pm8001_dev->dev_type == SAS_END_DEV)
  3976. opc = OPC_INB_SSP_ABORT;
  3977. else if (pm8001_dev->dev_type == SATA_DEV)
  3978. opc = OPC_INB_SATA_ABORT;
  3979. else
  3980. opc = OPC_INB_SMP_ABORT;/* SMP */
  3981. device_id = pm8001_dev->device_id;
  3982. rc = send_task_abort(pm8001_ha, opc, device_id, flag,
  3983. task_tag, cmd_tag);
  3984. if (rc != TMF_RESP_FUNC_COMPLETE)
  3985. PM8001_EH_DBG(pm8001_ha, pm8001_printk("rc= %d\n", rc));
  3986. return rc;
  3987. }
  3988. /**
  3989. * pm8001_chip_ssp_tm_req - built the task managment command.
  3990. * @pm8001_ha: our hba card information.
  3991. * @ccb: the ccb information.
  3992. * @tmf: task management function.
  3993. */
  3994. static int pm8001_chip_ssp_tm_req(struct pm8001_hba_info *pm8001_ha,
  3995. struct pm8001_ccb_info *ccb, struct pm8001_tmf_task *tmf)
  3996. {
  3997. struct sas_task *task = ccb->task;
  3998. struct domain_device *dev = task->dev;
  3999. struct pm8001_device *pm8001_dev = dev->lldd_dev;
  4000. u32 opc = OPC_INB_SSPINITMSTART;
  4001. struct inbound_queue_table *circularQ;
  4002. struct ssp_ini_tm_start_req sspTMCmd;
  4003. int ret;
  4004. memset(&sspTMCmd, 0, sizeof(sspTMCmd));
  4005. sspTMCmd.device_id = cpu_to_le32(pm8001_dev->device_id);
  4006. sspTMCmd.relate_tag = cpu_to_le32(tmf->tag_of_task_to_be_managed);
  4007. sspTMCmd.tmf = cpu_to_le32(tmf->tmf);
  4008. memcpy(sspTMCmd.lun, task->ssp_task.LUN, 8);
  4009. sspTMCmd.tag = cpu_to_le32(ccb->ccb_tag);
  4010. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4011. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &sspTMCmd);
  4012. return ret;
  4013. }
  4014. static int pm8001_chip_get_nvmd_req(struct pm8001_hba_info *pm8001_ha,
  4015. void *payload)
  4016. {
  4017. u32 opc = OPC_INB_GET_NVMD_DATA;
  4018. u32 nvmd_type;
  4019. int rc;
  4020. u32 tag;
  4021. struct pm8001_ccb_info *ccb;
  4022. struct inbound_queue_table *circularQ;
  4023. struct get_nvm_data_req nvmd_req;
  4024. struct fw_control_ex *fw_control_context;
  4025. struct pm8001_ioctl_payload *ioctl_payload = payload;
  4026. nvmd_type = ioctl_payload->minor_function;
  4027. fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
  4028. fw_control_context->usrAddr = (u8 *)&ioctl_payload->func_specific[0];
  4029. fw_control_context->len = ioctl_payload->length;
  4030. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4031. memset(&nvmd_req, 0, sizeof(nvmd_req));
  4032. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4033. if (rc)
  4034. return rc;
  4035. ccb = &pm8001_ha->ccb_info[tag];
  4036. ccb->ccb_tag = tag;
  4037. ccb->fw_control_context = fw_control_context;
  4038. nvmd_req.tag = cpu_to_le32(tag);
  4039. switch (nvmd_type) {
  4040. case TWI_DEVICE: {
  4041. u32 twi_addr, twi_page_size;
  4042. twi_addr = 0xa8;
  4043. twi_page_size = 2;
  4044. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
  4045. twi_page_size << 8 | TWI_DEVICE);
  4046. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4047. nvmd_req.resp_addr_hi =
  4048. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4049. nvmd_req.resp_addr_lo =
  4050. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4051. break;
  4052. }
  4053. case C_SEEPROM: {
  4054. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
  4055. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4056. nvmd_req.resp_addr_hi =
  4057. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4058. nvmd_req.resp_addr_lo =
  4059. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4060. break;
  4061. }
  4062. case VPD_FLASH: {
  4063. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
  4064. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4065. nvmd_req.resp_addr_hi =
  4066. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4067. nvmd_req.resp_addr_lo =
  4068. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4069. break;
  4070. }
  4071. case EXPAN_ROM: {
  4072. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
  4073. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4074. nvmd_req.resp_addr_hi =
  4075. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4076. nvmd_req.resp_addr_lo =
  4077. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4078. break;
  4079. }
  4080. default:
  4081. break;
  4082. }
  4083. rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
  4084. return rc;
  4085. }
  4086. static int pm8001_chip_set_nvmd_req(struct pm8001_hba_info *pm8001_ha,
  4087. void *payload)
  4088. {
  4089. u32 opc = OPC_INB_SET_NVMD_DATA;
  4090. u32 nvmd_type;
  4091. int rc;
  4092. u32 tag;
  4093. struct pm8001_ccb_info *ccb;
  4094. struct inbound_queue_table *circularQ;
  4095. struct set_nvm_data_req nvmd_req;
  4096. struct fw_control_ex *fw_control_context;
  4097. struct pm8001_ioctl_payload *ioctl_payload = payload;
  4098. nvmd_type = ioctl_payload->minor_function;
  4099. fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
  4100. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4101. memcpy(pm8001_ha->memoryMap.region[NVMD].virt_ptr,
  4102. ioctl_payload->func_specific,
  4103. ioctl_payload->length);
  4104. memset(&nvmd_req, 0, sizeof(nvmd_req));
  4105. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4106. if (rc)
  4107. return rc;
  4108. ccb = &pm8001_ha->ccb_info[tag];
  4109. ccb->fw_control_context = fw_control_context;
  4110. ccb->ccb_tag = tag;
  4111. nvmd_req.tag = cpu_to_le32(tag);
  4112. switch (nvmd_type) {
  4113. case TWI_DEVICE: {
  4114. u32 twi_addr, twi_page_size;
  4115. twi_addr = 0xa8;
  4116. twi_page_size = 2;
  4117. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4118. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | twi_addr << 16 |
  4119. twi_page_size << 8 | TWI_DEVICE);
  4120. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4121. nvmd_req.resp_addr_hi =
  4122. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4123. nvmd_req.resp_addr_lo =
  4124. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4125. break;
  4126. }
  4127. case C_SEEPROM:
  4128. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | C_SEEPROM);
  4129. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4130. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4131. nvmd_req.resp_addr_hi =
  4132. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4133. nvmd_req.resp_addr_lo =
  4134. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4135. break;
  4136. case VPD_FLASH:
  4137. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | VPD_FLASH);
  4138. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4139. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4140. nvmd_req.resp_addr_hi =
  4141. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4142. nvmd_req.resp_addr_lo =
  4143. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4144. break;
  4145. case EXPAN_ROM:
  4146. nvmd_req.len_ir_vpdd = cpu_to_le32(IPMode | EXPAN_ROM);
  4147. nvmd_req.resp_len = cpu_to_le32(ioctl_payload->length);
  4148. nvmd_req.reserved[0] = cpu_to_le32(0xFEDCBA98);
  4149. nvmd_req.resp_addr_hi =
  4150. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_hi);
  4151. nvmd_req.resp_addr_lo =
  4152. cpu_to_le32(pm8001_ha->memoryMap.region[NVMD].phys_addr_lo);
  4153. break;
  4154. default:
  4155. break;
  4156. }
  4157. rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &nvmd_req);
  4158. return rc;
  4159. }
  4160. /**
  4161. * pm8001_chip_fw_flash_update_build - support the firmware update operation
  4162. * @pm8001_ha: our hba card information.
  4163. * @fw_flash_updata_info: firmware flash update param
  4164. */
  4165. static int
  4166. pm8001_chip_fw_flash_update_build(struct pm8001_hba_info *pm8001_ha,
  4167. void *fw_flash_updata_info, u32 tag)
  4168. {
  4169. struct fw_flash_Update_req payload;
  4170. struct fw_flash_updata_info *info;
  4171. struct inbound_queue_table *circularQ;
  4172. int ret;
  4173. u32 opc = OPC_INB_FW_FLASH_UPDATE;
  4174. memset(&payload, 0, sizeof(struct fw_flash_Update_req));
  4175. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4176. info = fw_flash_updata_info;
  4177. payload.tag = cpu_to_le32(tag);
  4178. payload.cur_image_len = cpu_to_le32(info->cur_image_len);
  4179. payload.cur_image_offset = cpu_to_le32(info->cur_image_offset);
  4180. payload.total_image_len = cpu_to_le32(info->total_image_len);
  4181. payload.len = info->sgl.im_len.len ;
  4182. payload.sgl_addr_lo = lower_32_bits(info->sgl.addr);
  4183. payload.sgl_addr_hi = upper_32_bits(info->sgl.addr);
  4184. ret = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  4185. return ret;
  4186. }
  4187. static int
  4188. pm8001_chip_fw_flash_update_req(struct pm8001_hba_info *pm8001_ha,
  4189. void *payload)
  4190. {
  4191. struct fw_flash_updata_info flash_update_info;
  4192. struct fw_control_info *fw_control;
  4193. struct fw_control_ex *fw_control_context;
  4194. int rc;
  4195. u32 tag;
  4196. struct pm8001_ccb_info *ccb;
  4197. void *buffer = NULL;
  4198. dma_addr_t phys_addr;
  4199. u32 phys_addr_hi;
  4200. u32 phys_addr_lo;
  4201. struct pm8001_ioctl_payload *ioctl_payload = payload;
  4202. fw_control_context = kzalloc(sizeof(struct fw_control_ex), GFP_KERNEL);
  4203. fw_control = (struct fw_control_info *)&ioctl_payload->func_specific[0];
  4204. if (fw_control->len != 0) {
  4205. if (pm8001_mem_alloc(pm8001_ha->pdev,
  4206. (void **)&buffer,
  4207. &phys_addr,
  4208. &phys_addr_hi,
  4209. &phys_addr_lo,
  4210. fw_control->len, 0) != 0) {
  4211. PM8001_FAIL_DBG(pm8001_ha,
  4212. pm8001_printk("Mem alloc failure\n"));
  4213. return -ENOMEM;
  4214. }
  4215. }
  4216. memset(buffer, 0, fw_control->len);
  4217. memcpy(buffer, fw_control->buffer, fw_control->len);
  4218. flash_update_info.sgl.addr = cpu_to_le64(phys_addr);
  4219. flash_update_info.sgl.im_len.len = cpu_to_le32(fw_control->len);
  4220. flash_update_info.sgl.im_len.e = 0;
  4221. flash_update_info.cur_image_offset = fw_control->offset;
  4222. flash_update_info.cur_image_len = fw_control->len;
  4223. flash_update_info.total_image_len = fw_control->size;
  4224. fw_control_context->fw_control = fw_control;
  4225. fw_control_context->virtAddr = buffer;
  4226. fw_control_context->len = fw_control->len;
  4227. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4228. if (rc)
  4229. return rc;
  4230. ccb = &pm8001_ha->ccb_info[tag];
  4231. ccb->fw_control_context = fw_control_context;
  4232. ccb->ccb_tag = tag;
  4233. rc = pm8001_chip_fw_flash_update_build(pm8001_ha, &flash_update_info,
  4234. tag);
  4235. return rc;
  4236. }
  4237. static int
  4238. pm8001_chip_set_dev_state_req(struct pm8001_hba_info *pm8001_ha,
  4239. struct pm8001_device *pm8001_dev, u32 state)
  4240. {
  4241. struct set_dev_state_req payload;
  4242. struct inbound_queue_table *circularQ;
  4243. struct pm8001_ccb_info *ccb;
  4244. int rc;
  4245. u32 tag;
  4246. u32 opc = OPC_INB_SET_DEVICE_STATE;
  4247. memset(&payload, 0, sizeof(payload));
  4248. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4249. if (rc)
  4250. return -1;
  4251. ccb = &pm8001_ha->ccb_info[tag];
  4252. ccb->ccb_tag = tag;
  4253. ccb->device = pm8001_dev;
  4254. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4255. payload.tag = cpu_to_le32(tag);
  4256. payload.device_id = cpu_to_le32(pm8001_dev->device_id);
  4257. payload.nds = cpu_to_le32(state);
  4258. rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  4259. return rc;
  4260. }
  4261. static int
  4262. pm8001_chip_sas_re_initialization(struct pm8001_hba_info *pm8001_ha)
  4263. {
  4264. struct sas_re_initialization_req payload;
  4265. struct inbound_queue_table *circularQ;
  4266. struct pm8001_ccb_info *ccb;
  4267. int rc;
  4268. u32 tag;
  4269. u32 opc = OPC_INB_SAS_RE_INITIALIZE;
  4270. memset(&payload, 0, sizeof(payload));
  4271. rc = pm8001_tag_alloc(pm8001_ha, &tag);
  4272. if (rc)
  4273. return -1;
  4274. ccb = &pm8001_ha->ccb_info[tag];
  4275. ccb->ccb_tag = tag;
  4276. circularQ = &pm8001_ha->inbnd_q_tbl[0];
  4277. payload.tag = cpu_to_le32(tag);
  4278. payload.SSAHOLT = cpu_to_le32(0xd << 25);
  4279. payload.sata_hol_tmo = cpu_to_le32(80);
  4280. payload.open_reject_cmdretries_data_retries = cpu_to_le32(0xff00ff);
  4281. rc = mpi_build_cmd(pm8001_ha, circularQ, opc, &payload);
  4282. return rc;
  4283. }
  4284. const struct pm8001_dispatch pm8001_8001_dispatch = {
  4285. .name = "pmc8001",
  4286. .chip_init = pm8001_chip_init,
  4287. .chip_soft_rst = pm8001_chip_soft_rst,
  4288. .chip_rst = pm8001_hw_chip_rst,
  4289. .chip_iounmap = pm8001_chip_iounmap,
  4290. .isr = pm8001_chip_isr,
  4291. .is_our_interupt = pm8001_chip_is_our_interupt,
  4292. .isr_process_oq = process_oq,
  4293. .interrupt_enable = pm8001_chip_interrupt_enable,
  4294. .interrupt_disable = pm8001_chip_interrupt_disable,
  4295. .make_prd = pm8001_chip_make_sg,
  4296. .smp_req = pm8001_chip_smp_req,
  4297. .ssp_io_req = pm8001_chip_ssp_io_req,
  4298. .sata_req = pm8001_chip_sata_req,
  4299. .phy_start_req = pm8001_chip_phy_start_req,
  4300. .phy_stop_req = pm8001_chip_phy_stop_req,
  4301. .reg_dev_req = pm8001_chip_reg_dev_req,
  4302. .dereg_dev_req = pm8001_chip_dereg_dev_req,
  4303. .phy_ctl_req = pm8001_chip_phy_ctl_req,
  4304. .task_abort = pm8001_chip_abort_task,
  4305. .ssp_tm_req = pm8001_chip_ssp_tm_req,
  4306. .get_nvmd_req = pm8001_chip_get_nvmd_req,
  4307. .set_nvmd_req = pm8001_chip_set_nvmd_req,
  4308. .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
  4309. .set_dev_state_req = pm8001_chip_set_dev_state_req,
  4310. .sas_re_init_req = pm8001_chip_sas_re_initialization,
  4311. };