Kconfig 29 KB

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  1. config SYMBOL_PREFIX
  2. string
  3. default "_"
  4. config MMU
  5. def_bool n
  6. config FPU
  7. def_bool n
  8. config RWSEM_GENERIC_SPINLOCK
  9. def_bool y
  10. config RWSEM_XCHGADD_ALGORITHM
  11. def_bool n
  12. config BLACKFIN
  13. def_bool y
  14. select HAVE_ARCH_KGDB
  15. select HAVE_ARCH_TRACEHOOK
  16. select HAVE_DYNAMIC_FTRACE
  17. select HAVE_FTRACE_MCOUNT_RECORD
  18. select HAVE_FUNCTION_GRAPH_TRACER
  19. select HAVE_FUNCTION_TRACER
  20. select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  21. select HAVE_IDE
  22. select HAVE_KERNEL_GZIP if RAMKERNEL
  23. select HAVE_KERNEL_BZIP2 if RAMKERNEL
  24. select HAVE_KERNEL_LZMA if RAMKERNEL
  25. select HAVE_KERNEL_LZO if RAMKERNEL
  26. select HAVE_OPROFILE
  27. select ARCH_WANT_OPTIONAL_GPIOLIB
  28. config GENERIC_CSUM
  29. def_bool y
  30. config GENERIC_BUG
  31. def_bool y
  32. depends on BUG
  33. config ZONE_DMA
  34. def_bool y
  35. config GENERIC_FIND_NEXT_BIT
  36. def_bool y
  37. config GENERIC_HARDIRQS
  38. def_bool y
  39. config GENERIC_IRQ_PROBE
  40. def_bool y
  41. config GENERIC_GPIO
  42. def_bool y
  43. config FORCE_MAX_ZONEORDER
  44. int
  45. default "14"
  46. config GENERIC_CALIBRATE_DELAY
  47. def_bool y
  48. config LOCKDEP_SUPPORT
  49. def_bool y
  50. config STACKTRACE_SUPPORT
  51. def_bool y
  52. config TRACE_IRQFLAGS_SUPPORT
  53. def_bool y
  54. source "init/Kconfig"
  55. source "kernel/Kconfig.preempt"
  56. source "kernel/Kconfig.freezer"
  57. menu "Blackfin Processor Options"
  58. comment "Processor and Board Settings"
  59. choice
  60. prompt "CPU"
  61. default BF533
  62. config BF512
  63. bool "BF512"
  64. help
  65. BF512 Processor Support.
  66. config BF514
  67. bool "BF514"
  68. help
  69. BF514 Processor Support.
  70. config BF516
  71. bool "BF516"
  72. help
  73. BF516 Processor Support.
  74. config BF518
  75. bool "BF518"
  76. help
  77. BF518 Processor Support.
  78. config BF522
  79. bool "BF522"
  80. help
  81. BF522 Processor Support.
  82. config BF523
  83. bool "BF523"
  84. help
  85. BF523 Processor Support.
  86. config BF524
  87. bool "BF524"
  88. help
  89. BF524 Processor Support.
  90. config BF525
  91. bool "BF525"
  92. help
  93. BF525 Processor Support.
  94. config BF526
  95. bool "BF526"
  96. help
  97. BF526 Processor Support.
  98. config BF527
  99. bool "BF527"
  100. help
  101. BF527 Processor Support.
  102. config BF531
  103. bool "BF531"
  104. help
  105. BF531 Processor Support.
  106. config BF532
  107. bool "BF532"
  108. help
  109. BF532 Processor Support.
  110. config BF533
  111. bool "BF533"
  112. help
  113. BF533 Processor Support.
  114. config BF534
  115. bool "BF534"
  116. help
  117. BF534 Processor Support.
  118. config BF536
  119. bool "BF536"
  120. help
  121. BF536 Processor Support.
  122. config BF537
  123. bool "BF537"
  124. help
  125. BF537 Processor Support.
  126. config BF538
  127. bool "BF538"
  128. help
  129. BF538 Processor Support.
  130. config BF539
  131. bool "BF539"
  132. help
  133. BF539 Processor Support.
  134. config BF542_std
  135. bool "BF542"
  136. help
  137. BF542 Processor Support.
  138. config BF542M
  139. bool "BF542m"
  140. help
  141. BF542 Processor Support.
  142. config BF544_std
  143. bool "BF544"
  144. help
  145. BF544 Processor Support.
  146. config BF544M
  147. bool "BF544m"
  148. help
  149. BF544 Processor Support.
  150. config BF547_std
  151. bool "BF547"
  152. help
  153. BF547 Processor Support.
  154. config BF547M
  155. bool "BF547m"
  156. help
  157. BF547 Processor Support.
  158. config BF548_std
  159. bool "BF548"
  160. help
  161. BF548 Processor Support.
  162. config BF548M
  163. bool "BF548m"
  164. help
  165. BF548 Processor Support.
  166. config BF549_std
  167. bool "BF549"
  168. help
  169. BF549 Processor Support.
  170. config BF549M
  171. bool "BF549m"
  172. help
  173. BF549 Processor Support.
  174. config BF561
  175. bool "BF561"
  176. help
  177. BF561 Processor Support.
  178. endchoice
  179. config SMP
  180. depends on BF561
  181. select TICKSOURCE_CORETMR
  182. bool "Symmetric multi-processing support"
  183. ---help---
  184. This enables support for systems with more than one CPU,
  185. like the dual core BF561. If you have a system with only one
  186. CPU, say N. If you have a system with more than one CPU, say Y.
  187. If you don't know what to do here, say N.
  188. config NR_CPUS
  189. int
  190. depends on SMP
  191. default 2 if BF561
  192. config HOTPLUG_CPU
  193. bool "Support for hot-pluggable CPUs"
  194. depends on SMP && HOTPLUG
  195. default y
  196. config IRQ_PER_CPU
  197. bool
  198. depends on SMP
  199. default y
  200. config HAVE_LEGACY_PER_CPU_AREA
  201. def_bool y
  202. depends on SMP
  203. config BF_REV_MIN
  204. int
  205. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  206. default 2 if (BF537 || BF536 || BF534)
  207. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  208. default 4 if (BF538 || BF539)
  209. config BF_REV_MAX
  210. int
  211. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  212. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  213. default 5 if (BF561 || BF538 || BF539)
  214. default 6 if (BF533 || BF532 || BF531)
  215. choice
  216. prompt "Silicon Rev"
  217. default BF_REV_0_0 if (BF51x || BF52x)
  218. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  219. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  220. config BF_REV_0_0
  221. bool "0.0"
  222. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  223. config BF_REV_0_1
  224. bool "0.1"
  225. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  226. config BF_REV_0_2
  227. bool "0.2"
  228. depends on (BF51x || BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  229. config BF_REV_0_3
  230. bool "0.3"
  231. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  232. config BF_REV_0_4
  233. bool "0.4"
  234. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  235. config BF_REV_0_5
  236. bool "0.5"
  237. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  238. config BF_REV_0_6
  239. bool "0.6"
  240. depends on (BF533 || BF532 || BF531)
  241. config BF_REV_ANY
  242. bool "any"
  243. config BF_REV_NONE
  244. bool "none"
  245. endchoice
  246. config BF53x
  247. bool
  248. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  249. default y
  250. config MEM_MT48LC64M4A2FB_7E
  251. bool
  252. depends on (BFIN533_STAMP)
  253. default y
  254. config MEM_MT48LC16M16A2TG_75
  255. bool
  256. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  257. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
  258. || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
  259. || BFIN527_BLUETECHNIX_CM)
  260. default y
  261. config MEM_MT48LC32M8A2_75
  262. bool
  263. depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  264. default y
  265. config MEM_MT48LC8M32B2B5_7
  266. bool
  267. depends on (BFIN561_BLUETECHNIX_CM)
  268. default y
  269. config MEM_MT48LC32M16A2TG_75
  270. bool
  271. depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP || BFIN527_AD7160EVAL)
  272. default y
  273. config MEM_MT48H32M16LFCJ_75
  274. bool
  275. depends on (BFIN526_EZBRD)
  276. default y
  277. source "arch/blackfin/mach-bf518/Kconfig"
  278. source "arch/blackfin/mach-bf527/Kconfig"
  279. source "arch/blackfin/mach-bf533/Kconfig"
  280. source "arch/blackfin/mach-bf561/Kconfig"
  281. source "arch/blackfin/mach-bf537/Kconfig"
  282. source "arch/blackfin/mach-bf538/Kconfig"
  283. source "arch/blackfin/mach-bf548/Kconfig"
  284. menu "Board customizations"
  285. config CMDLINE_BOOL
  286. bool "Default bootloader kernel arguments"
  287. config CMDLINE
  288. string "Initial kernel command string"
  289. depends on CMDLINE_BOOL
  290. default "console=ttyBF0,57600"
  291. help
  292. If you don't have a boot loader capable of passing a command line string
  293. to the kernel, you may specify one here. As a minimum, you should specify
  294. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  295. config BOOT_LOAD
  296. hex "Kernel load address for booting"
  297. default "0x1000"
  298. range 0x1000 0x20000000
  299. help
  300. This option allows you to set the load address of the kernel.
  301. This can be useful if you are on a board which has a small amount
  302. of memory or you wish to reserve some memory at the beginning of
  303. the address space.
  304. Note that you need to keep this value above 4k (0x1000) as this
  305. memory region is used to capture NULL pointer references as well
  306. as some core kernel functions.
  307. config ROM_BASE
  308. hex "Kernel ROM Base"
  309. depends on ROMKERNEL
  310. default "0x20040040"
  311. range 0x20000000 0x20400000 if !(BF54x || BF561)
  312. range 0x20000000 0x30000000 if (BF54x || BF561)
  313. help
  314. Make sure your ROM base does not include any file-header
  315. information that is prepended to the kernel.
  316. For example, the bootable U-Boot format (created with
  317. mkimage) has a 64 byte header (0x40). So while the image
  318. you write to flash might start at say 0x20080000, you have
  319. to add 0x40 to get the kernel's ROM base as it will come
  320. after the header.
  321. comment "Clock/PLL Setup"
  322. config CLKIN_HZ
  323. int "Frequency of the crystal on the board in Hz"
  324. default "10000000" if BFIN532_IP0X
  325. default "11059200" if BFIN533_STAMP
  326. default "24576000" if PNAV10
  327. default "25000000" # most people use this
  328. default "27000000" if BFIN533_EZKIT
  329. default "30000000" if BFIN561_EZKIT
  330. default "24000000" if BFIN527_AD7160EVAL
  331. help
  332. The frequency of CLKIN crystal oscillator on the board in Hz.
  333. Warning: This value should match the crystal on the board. Otherwise,
  334. peripherals won't work properly.
  335. config BFIN_KERNEL_CLOCK
  336. bool "Re-program Clocks while Kernel boots?"
  337. default n
  338. help
  339. This option decides if kernel clocks are re-programed from the
  340. bootloader settings. If the clocks are not set, the SDRAM settings
  341. are also not changed, and the Bootloader does 100% of the hardware
  342. configuration.
  343. config PLL_BYPASS
  344. bool "Bypass PLL"
  345. depends on BFIN_KERNEL_CLOCK
  346. default n
  347. config CLKIN_HALF
  348. bool "Half Clock In"
  349. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  350. default n
  351. help
  352. If this is set the clock will be divided by 2, before it goes to the PLL.
  353. config VCO_MULT
  354. int "VCO Multiplier"
  355. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  356. range 1 64
  357. default "22" if BFIN533_EZKIT
  358. default "45" if BFIN533_STAMP
  359. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  360. default "22" if BFIN533_BLUETECHNIX_CM
  361. default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  362. default "20" if BFIN561_EZKIT
  363. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  364. default "25" if BFIN527_AD7160EVAL
  365. help
  366. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  367. PLL Frequency = (Crystal Frequency) * (this setting)
  368. choice
  369. prompt "Core Clock Divider"
  370. depends on BFIN_KERNEL_CLOCK
  371. default CCLK_DIV_1
  372. help
  373. This sets the frequency of the core. It can be 1, 2, 4 or 8
  374. Core Frequency = (PLL frequency) / (this setting)
  375. config CCLK_DIV_1
  376. bool "1"
  377. config CCLK_DIV_2
  378. bool "2"
  379. config CCLK_DIV_4
  380. bool "4"
  381. config CCLK_DIV_8
  382. bool "8"
  383. endchoice
  384. config SCLK_DIV
  385. int "System Clock Divider"
  386. depends on BFIN_KERNEL_CLOCK
  387. range 1 15
  388. default 5
  389. help
  390. This sets the frequency of the system clock (including SDRAM or DDR).
  391. This can be between 1 and 15
  392. System Clock = (PLL frequency) / (this setting)
  393. choice
  394. prompt "DDR SDRAM Chip Type"
  395. depends on BFIN_KERNEL_CLOCK
  396. depends on BF54x
  397. default MEM_MT46V32M16_5B
  398. config MEM_MT46V32M16_6T
  399. bool "MT46V32M16_6T"
  400. config MEM_MT46V32M16_5B
  401. bool "MT46V32M16_5B"
  402. endchoice
  403. choice
  404. prompt "DDR/SDRAM Timing"
  405. depends on BFIN_KERNEL_CLOCK
  406. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  407. help
  408. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  409. The calculated SDRAM timing parameters may not be 100%
  410. accurate - This option is therefore marked experimental.
  411. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  412. bool "Calculate Timings (EXPERIMENTAL)"
  413. depends on EXPERIMENTAL
  414. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  415. bool "Provide accurate Timings based on target SCLK"
  416. help
  417. Please consult the Blackfin Hardware Reference Manuals as well
  418. as the memory device datasheet.
  419. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  420. endchoice
  421. menu "Memory Init Control"
  422. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  423. config MEM_DDRCTL0
  424. depends on BF54x
  425. hex "DDRCTL0"
  426. default 0x0
  427. config MEM_DDRCTL1
  428. depends on BF54x
  429. hex "DDRCTL1"
  430. default 0x0
  431. config MEM_DDRCTL2
  432. depends on BF54x
  433. hex "DDRCTL2"
  434. default 0x0
  435. config MEM_EBIU_DDRQUE
  436. depends on BF54x
  437. hex "DDRQUE"
  438. default 0x0
  439. config MEM_SDRRC
  440. depends on !BF54x
  441. hex "SDRRC"
  442. default 0x0
  443. config MEM_SDGCTL
  444. depends on !BF54x
  445. hex "SDGCTL"
  446. default 0x0
  447. endmenu
  448. #
  449. # Max & Min Speeds for various Chips
  450. #
  451. config MAX_VCO_HZ
  452. int
  453. default 400000000 if BF512
  454. default 400000000 if BF514
  455. default 400000000 if BF516
  456. default 400000000 if BF518
  457. default 400000000 if BF522
  458. default 600000000 if BF523
  459. default 400000000 if BF524
  460. default 600000000 if BF525
  461. default 400000000 if BF526
  462. default 600000000 if BF527
  463. default 400000000 if BF531
  464. default 400000000 if BF532
  465. default 750000000 if BF533
  466. default 500000000 if BF534
  467. default 400000000 if BF536
  468. default 600000000 if BF537
  469. default 533333333 if BF538
  470. default 533333333 if BF539
  471. default 600000000 if BF542
  472. default 533333333 if BF544
  473. default 600000000 if BF547
  474. default 600000000 if BF548
  475. default 533333333 if BF549
  476. default 600000000 if BF561
  477. config MIN_VCO_HZ
  478. int
  479. default 50000000
  480. config MAX_SCLK_HZ
  481. int
  482. default 133333333
  483. config MIN_SCLK_HZ
  484. int
  485. default 27000000
  486. comment "Kernel Timer/Scheduler"
  487. source kernel/Kconfig.hz
  488. config GENERIC_CLOCKEVENTS
  489. bool "Generic clock events"
  490. default y
  491. menu "Clock event device"
  492. depends on GENERIC_CLOCKEVENTS
  493. config TICKSOURCE_GPTMR0
  494. bool "GPTimer0"
  495. depends on !SMP
  496. select BFIN_GPTIMERS
  497. config TICKSOURCE_CORETMR
  498. bool "Core timer"
  499. default y
  500. endmenu
  501. menu "Clock souce"
  502. depends on GENERIC_CLOCKEVENTS
  503. config CYCLES_CLOCKSOURCE
  504. bool "CYCLES"
  505. default y
  506. depends on !BFIN_SCRATCH_REG_CYCLES
  507. depends on !SMP
  508. help
  509. If you say Y here, you will enable support for using the 'cycles'
  510. registers as a clock source. Doing so means you will be unable to
  511. safely write to the 'cycles' register during runtime. You will
  512. still be able to read it (such as for performance monitoring), but
  513. writing the registers will most likely crash the kernel.
  514. config GPTMR0_CLOCKSOURCE
  515. bool "GPTimer0"
  516. select BFIN_GPTIMERS
  517. depends on !TICKSOURCE_GPTMR0
  518. endmenu
  519. config ARCH_USES_GETTIMEOFFSET
  520. depends on !GENERIC_CLOCKEVENTS
  521. def_bool y
  522. source kernel/time/Kconfig
  523. comment "Misc"
  524. choice
  525. prompt "Blackfin Exception Scratch Register"
  526. default BFIN_SCRATCH_REG_RETN
  527. help
  528. Select the resource to reserve for the Exception handler:
  529. - RETN: Non-Maskable Interrupt (NMI)
  530. - RETE: Exception Return (JTAG/ICE)
  531. - CYCLES: Performance counter
  532. If you are unsure, please select "RETN".
  533. config BFIN_SCRATCH_REG_RETN
  534. bool "RETN"
  535. help
  536. Use the RETN register in the Blackfin exception handler
  537. as a stack scratch register. This means you cannot
  538. safely use NMI on the Blackfin while running Linux, but
  539. you can debug the system with a JTAG ICE and use the
  540. CYCLES performance registers.
  541. If you are unsure, please select "RETN".
  542. config BFIN_SCRATCH_REG_RETE
  543. bool "RETE"
  544. help
  545. Use the RETE register in the Blackfin exception handler
  546. as a stack scratch register. This means you cannot
  547. safely use a JTAG ICE while debugging a Blackfin board,
  548. but you can safely use the CYCLES performance registers
  549. and the NMI.
  550. If you are unsure, please select "RETN".
  551. config BFIN_SCRATCH_REG_CYCLES
  552. bool "CYCLES"
  553. help
  554. Use the CYCLES register in the Blackfin exception handler
  555. as a stack scratch register. This means you cannot
  556. safely use the CYCLES performance registers on a Blackfin
  557. board at anytime, but you can debug the system with a JTAG
  558. ICE and use the NMI.
  559. If you are unsure, please select "RETN".
  560. endchoice
  561. endmenu
  562. menu "Blackfin Kernel Optimizations"
  563. depends on !SMP
  564. comment "Memory Optimizations"
  565. config I_ENTRY_L1
  566. bool "Locate interrupt entry code in L1 Memory"
  567. default y
  568. help
  569. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  570. into L1 instruction memory. (less latency)
  571. config EXCPT_IRQ_SYSC_L1
  572. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  573. default y
  574. help
  575. If enabled, the entire ASM lowlevel exception and interrupt entry code
  576. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  577. (less latency)
  578. config DO_IRQ_L1
  579. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  580. default y
  581. help
  582. If enabled, the frequently called do_irq dispatcher function is linked
  583. into L1 instruction memory. (less latency)
  584. config CORE_TIMER_IRQ_L1
  585. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  586. default y
  587. help
  588. If enabled, the frequently called timer_interrupt() function is linked
  589. into L1 instruction memory. (less latency)
  590. config IDLE_L1
  591. bool "Locate frequently idle function in L1 Memory"
  592. default y
  593. help
  594. If enabled, the frequently called idle function is linked
  595. into L1 instruction memory. (less latency)
  596. config SCHEDULE_L1
  597. bool "Locate kernel schedule function in L1 Memory"
  598. default y
  599. help
  600. If enabled, the frequently called kernel schedule is linked
  601. into L1 instruction memory. (less latency)
  602. config ARITHMETIC_OPS_L1
  603. bool "Locate kernel owned arithmetic functions in L1 Memory"
  604. default y
  605. help
  606. If enabled, arithmetic functions are linked
  607. into L1 instruction memory. (less latency)
  608. config ACCESS_OK_L1
  609. bool "Locate access_ok function in L1 Memory"
  610. default y
  611. help
  612. If enabled, the access_ok function is linked
  613. into L1 instruction memory. (less latency)
  614. config MEMSET_L1
  615. bool "Locate memset function in L1 Memory"
  616. default y
  617. help
  618. If enabled, the memset function is linked
  619. into L1 instruction memory. (less latency)
  620. config MEMCPY_L1
  621. bool "Locate memcpy function in L1 Memory"
  622. default y
  623. help
  624. If enabled, the memcpy function is linked
  625. into L1 instruction memory. (less latency)
  626. config STRCMP_L1
  627. bool "locate strcmp function in L1 Memory"
  628. default y
  629. help
  630. If enabled, the strcmp function is linked
  631. into L1 instruction memory (less latency).
  632. config STRNCMP_L1
  633. bool "locate strncmp function in L1 Memory"
  634. default y
  635. help
  636. If enabled, the strncmp function is linked
  637. into L1 instruction memory (less latency).
  638. config STRCPY_L1
  639. bool "locate strcpy function in L1 Memory"
  640. default y
  641. help
  642. If enabled, the strcpy function is linked
  643. into L1 instruction memory (less latency).
  644. config STRNCPY_L1
  645. bool "locate strncpy function in L1 Memory"
  646. default y
  647. help
  648. If enabled, the strncpy function is linked
  649. into L1 instruction memory (less latency).
  650. config SYS_BFIN_SPINLOCK_L1
  651. bool "Locate sys_bfin_spinlock function in L1 Memory"
  652. default y
  653. help
  654. If enabled, sys_bfin_spinlock function is linked
  655. into L1 instruction memory. (less latency)
  656. config IP_CHECKSUM_L1
  657. bool "Locate IP Checksum function in L1 Memory"
  658. default n
  659. help
  660. If enabled, the IP Checksum function is linked
  661. into L1 instruction memory. (less latency)
  662. config CACHELINE_ALIGNED_L1
  663. bool "Locate cacheline_aligned data to L1 Data Memory"
  664. default y if !BF54x
  665. default n if BF54x
  666. depends on !BF531
  667. help
  668. If enabled, cacheline_aligned data is linked
  669. into L1 data memory. (less latency)
  670. config SYSCALL_TAB_L1
  671. bool "Locate Syscall Table L1 Data Memory"
  672. default n
  673. depends on !BF531
  674. help
  675. If enabled, the Syscall LUT is linked
  676. into L1 data memory. (less latency)
  677. config CPLB_SWITCH_TAB_L1
  678. bool "Locate CPLB Switch Tables L1 Data Memory"
  679. default n
  680. depends on !BF531
  681. help
  682. If enabled, the CPLB Switch Tables are linked
  683. into L1 data memory. (less latency)
  684. config CACHE_FLUSH_L1
  685. bool "Locate cache flush funcs in L1 Inst Memory"
  686. default y
  687. help
  688. If enabled, the Blackfin cache flushing functions are linked
  689. into L1 instruction memory.
  690. Note that this might be required to address anomalies, but
  691. these functions are pretty small, so it shouldn't be too bad.
  692. If you are using a processor affected by an anomaly, the build
  693. system will double check for you and prevent it.
  694. config APP_STACK_L1
  695. bool "Support locating application stack in L1 Scratch Memory"
  696. default y
  697. help
  698. If enabled the application stack can be located in L1
  699. scratch memory (less latency).
  700. Currently only works with FLAT binaries.
  701. config EXCEPTION_L1_SCRATCH
  702. bool "Locate exception stack in L1 Scratch Memory"
  703. default n
  704. depends on !APP_STACK_L1
  705. help
  706. Whenever an exception occurs, use the L1 Scratch memory for
  707. stack storage. You cannot place the stacks of FLAT binaries
  708. in L1 when using this option.
  709. If you don't use L1 Scratch, then you should say Y here.
  710. comment "Speed Optimizations"
  711. config BFIN_INS_LOWOVERHEAD
  712. bool "ins[bwl] low overhead, higher interrupt latency"
  713. default y
  714. help
  715. Reads on the Blackfin are speculative. In Blackfin terms, this means
  716. they can be interrupted at any time (even after they have been issued
  717. on to the external bus), and re-issued after the interrupt occurs.
  718. For memory - this is not a big deal, since memory does not change if
  719. it sees a read.
  720. If a FIFO is sitting on the end of the read, it will see two reads,
  721. when the core only sees one since the FIFO receives both the read
  722. which is cancelled (and not delivered to the core) and the one which
  723. is re-issued (which is delivered to the core).
  724. To solve this, interrupts are turned off before reads occur to
  725. I/O space. This option controls which the overhead/latency of
  726. controlling interrupts during this time
  727. "n" turns interrupts off every read
  728. (higher overhead, but lower interrupt latency)
  729. "y" turns interrupts off every loop
  730. (low overhead, but longer interrupt latency)
  731. default behavior is to leave this set to on (type "Y"). If you are experiencing
  732. interrupt latency issues, it is safe and OK to turn this off.
  733. endmenu
  734. choice
  735. prompt "Kernel executes from"
  736. help
  737. Choose the memory type that the kernel will be running in.
  738. config RAMKERNEL
  739. bool "RAM"
  740. help
  741. The kernel will be resident in RAM when running.
  742. config ROMKERNEL
  743. bool "ROM"
  744. help
  745. The kernel will be resident in FLASH/ROM when running.
  746. endchoice
  747. # Common code uses "ROMKERNEL" or "XIP_KERNEL", so define both
  748. config XIP_KERNEL
  749. bool
  750. default y
  751. depends on ROMKERNEL
  752. source "mm/Kconfig"
  753. config BFIN_GPTIMERS
  754. tristate "Enable Blackfin General Purpose Timers API"
  755. default n
  756. help
  757. Enable support for the General Purpose Timers API. If you
  758. are unsure, say N.
  759. To compile this driver as a module, choose M here: the module
  760. will be called gptimers.
  761. choice
  762. prompt "Uncached DMA region"
  763. default DMA_UNCACHED_1M
  764. config DMA_UNCACHED_4M
  765. bool "Enable 4M DMA region"
  766. config DMA_UNCACHED_2M
  767. bool "Enable 2M DMA region"
  768. config DMA_UNCACHED_1M
  769. bool "Enable 1M DMA region"
  770. config DMA_UNCACHED_512K
  771. bool "Enable 512K DMA region"
  772. config DMA_UNCACHED_256K
  773. bool "Enable 256K DMA region"
  774. config DMA_UNCACHED_128K
  775. bool "Enable 128K DMA region"
  776. config DMA_UNCACHED_NONE
  777. bool "Disable DMA region"
  778. endchoice
  779. comment "Cache Support"
  780. config BFIN_ICACHE
  781. bool "Enable ICACHE"
  782. default y
  783. config BFIN_EXTMEM_ICACHEABLE
  784. bool "Enable ICACHE for external memory"
  785. depends on BFIN_ICACHE
  786. default y
  787. config BFIN_L2_ICACHEABLE
  788. bool "Enable ICACHE for L2 SRAM"
  789. depends on BFIN_ICACHE
  790. depends on BF54x || BF561
  791. default n
  792. config BFIN_DCACHE
  793. bool "Enable DCACHE"
  794. default y
  795. config BFIN_DCACHE_BANKA
  796. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  797. depends on BFIN_DCACHE && !BF531
  798. default n
  799. config BFIN_EXTMEM_DCACHEABLE
  800. bool "Enable DCACHE for external memory"
  801. depends on BFIN_DCACHE
  802. default y
  803. choice
  804. prompt "External memory DCACHE policy"
  805. depends on BFIN_EXTMEM_DCACHEABLE
  806. default BFIN_EXTMEM_WRITEBACK if !SMP
  807. default BFIN_EXTMEM_WRITETHROUGH if SMP
  808. config BFIN_EXTMEM_WRITEBACK
  809. bool "Write back"
  810. depends on !SMP
  811. help
  812. Write Back Policy:
  813. Cached data will be written back to SDRAM only when needed.
  814. This can give a nice increase in performance, but beware of
  815. broken drivers that do not properly invalidate/flush their
  816. cache.
  817. Write Through Policy:
  818. Cached data will always be written back to SDRAM when the
  819. cache is updated. This is a completely safe setting, but
  820. performance is worse than Write Back.
  821. If you are unsure of the options and you want to be safe,
  822. then go with Write Through.
  823. config BFIN_EXTMEM_WRITETHROUGH
  824. bool "Write through"
  825. help
  826. Write Back Policy:
  827. Cached data will be written back to SDRAM only when needed.
  828. This can give a nice increase in performance, but beware of
  829. broken drivers that do not properly invalidate/flush their
  830. cache.
  831. Write Through Policy:
  832. Cached data will always be written back to SDRAM when the
  833. cache is updated. This is a completely safe setting, but
  834. performance is worse than Write Back.
  835. If you are unsure of the options and you want to be safe,
  836. then go with Write Through.
  837. endchoice
  838. config BFIN_L2_DCACHEABLE
  839. bool "Enable DCACHE for L2 SRAM"
  840. depends on BFIN_DCACHE
  841. depends on (BF54x || BF561) && !SMP
  842. default n
  843. choice
  844. prompt "L2 SRAM DCACHE policy"
  845. depends on BFIN_L2_DCACHEABLE
  846. default BFIN_L2_WRITEBACK
  847. config BFIN_L2_WRITEBACK
  848. bool "Write back"
  849. config BFIN_L2_WRITETHROUGH
  850. bool "Write through"
  851. endchoice
  852. comment "Memory Protection Unit"
  853. config MPU
  854. bool "Enable the memory protection unit (EXPERIMENTAL)"
  855. default n
  856. help
  857. Use the processor's MPU to protect applications from accessing
  858. memory they do not own. This comes at a performance penalty
  859. and is recommended only for debugging.
  860. comment "Asynchronous Memory Configuration"
  861. menu "EBIU_AMGCTL Global Control"
  862. config C_AMCKEN
  863. bool "Enable CLKOUT"
  864. default y
  865. config C_CDPRIO
  866. bool "DMA has priority over core for ext. accesses"
  867. default n
  868. config C_B0PEN
  869. depends on BF561
  870. bool "Bank 0 16 bit packing enable"
  871. default y
  872. config C_B1PEN
  873. depends on BF561
  874. bool "Bank 1 16 bit packing enable"
  875. default y
  876. config C_B2PEN
  877. depends on BF561
  878. bool "Bank 2 16 bit packing enable"
  879. default y
  880. config C_B3PEN
  881. depends on BF561
  882. bool "Bank 3 16 bit packing enable"
  883. default n
  884. choice
  885. prompt "Enable Asynchronous Memory Banks"
  886. default C_AMBEN_ALL
  887. config C_AMBEN
  888. bool "Disable All Banks"
  889. config C_AMBEN_B0
  890. bool "Enable Bank 0"
  891. config C_AMBEN_B0_B1
  892. bool "Enable Bank 0 & 1"
  893. config C_AMBEN_B0_B1_B2
  894. bool "Enable Bank 0 & 1 & 2"
  895. config C_AMBEN_ALL
  896. bool "Enable All Banks"
  897. endchoice
  898. endmenu
  899. menu "EBIU_AMBCTL Control"
  900. config BANK_0
  901. hex "Bank 0 (AMBCTL0.L)"
  902. default 0x7BB0
  903. help
  904. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  905. used to control the Asynchronous Memory Bank 0 settings.
  906. config BANK_1
  907. hex "Bank 1 (AMBCTL0.H)"
  908. default 0x7BB0
  909. default 0x5558 if BF54x
  910. help
  911. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  912. used to control the Asynchronous Memory Bank 1 settings.
  913. config BANK_2
  914. hex "Bank 2 (AMBCTL1.L)"
  915. default 0x7BB0
  916. help
  917. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  918. used to control the Asynchronous Memory Bank 2 settings.
  919. config BANK_3
  920. hex "Bank 3 (AMBCTL1.H)"
  921. default 0x99B3
  922. help
  923. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  924. used to control the Asynchronous Memory Bank 3 settings.
  925. endmenu
  926. config EBIU_MBSCTLVAL
  927. hex "EBIU Bank Select Control Register"
  928. depends on BF54x
  929. default 0
  930. config EBIU_MODEVAL
  931. hex "Flash Memory Mode Control Register"
  932. depends on BF54x
  933. default 1
  934. config EBIU_FCTLVAL
  935. hex "Flash Memory Bank Control Register"
  936. depends on BF54x
  937. default 6
  938. endmenu
  939. #############################################################################
  940. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  941. config PCI
  942. bool "PCI support"
  943. depends on BROKEN
  944. help
  945. Support for PCI bus.
  946. source "drivers/pci/Kconfig"
  947. source "drivers/pcmcia/Kconfig"
  948. source "drivers/pci/hotplug/Kconfig"
  949. endmenu
  950. menu "Executable file formats"
  951. source "fs/Kconfig.binfmt"
  952. endmenu
  953. menu "Power management options"
  954. source "kernel/power/Kconfig"
  955. config ARCH_SUSPEND_POSSIBLE
  956. def_bool y
  957. choice
  958. prompt "Standby Power Saving Mode"
  959. depends on PM
  960. default PM_BFIN_SLEEP_DEEPER
  961. config PM_BFIN_SLEEP_DEEPER
  962. bool "Sleep Deeper"
  963. help
  964. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  965. power dissipation by disabling the clock to the processor core (CCLK).
  966. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  967. to 0.85 V to provide the greatest power savings, while preserving the
  968. processor state.
  969. The PLL and system clock (SCLK) continue to operate at a very low
  970. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  971. the SDRAM is put into Self Refresh Mode. Typically an external event
  972. such as GPIO interrupt or RTC activity wakes up the processor.
  973. Various Peripherals such as UART, SPORT, PPI may not function as
  974. normal during Sleep Deeper, due to the reduced SCLK frequency.
  975. When in the sleep mode, system DMA access to L1 memory is not supported.
  976. If unsure, select "Sleep Deeper".
  977. config PM_BFIN_SLEEP
  978. bool "Sleep"
  979. help
  980. Sleep Mode (High Power Savings) - The sleep mode reduces power
  981. dissipation by disabling the clock to the processor core (CCLK).
  982. The PLL and system clock (SCLK), however, continue to operate in
  983. this mode. Typically an external event or RTC activity will wake
  984. up the processor. When in the sleep mode, system DMA access to L1
  985. memory is not supported.
  986. If unsure, select "Sleep Deeper".
  987. endchoice
  988. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  989. depends on PM
  990. config PM_BFIN_WAKE_PH6
  991. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  992. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  993. default n
  994. help
  995. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  996. config PM_BFIN_WAKE_GP
  997. bool "Allow Wake-Up from GPIOs"
  998. depends on PM && BF54x
  999. default n
  1000. help
  1001. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  1002. (all processors, except ADSP-BF549). This option sets
  1003. the general-purpose wake-up enable (GPWE) control bit to enable
  1004. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  1005. On ADSP-BF549 this option enables the the same functionality on the
  1006. /MRXON pin also PH7.
  1007. endmenu
  1008. menu "CPU Frequency scaling"
  1009. source "drivers/cpufreq/Kconfig"
  1010. config BFIN_CPU_FREQ
  1011. bool
  1012. depends on CPU_FREQ
  1013. select CPU_FREQ_TABLE
  1014. default y
  1015. config CPU_VOLTAGE
  1016. bool "CPU Voltage scaling"
  1017. depends on EXPERIMENTAL
  1018. depends on CPU_FREQ
  1019. default n
  1020. help
  1021. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1022. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1023. manuals. There is a theoretical risk that during VDDINT transitions
  1024. the PLL may unlock.
  1025. endmenu
  1026. source "net/Kconfig"
  1027. source "drivers/Kconfig"
  1028. source "drivers/firmware/Kconfig"
  1029. source "fs/Kconfig"
  1030. source "arch/blackfin/Kconfig.debug"
  1031. source "security/Kconfig"
  1032. source "crypto/Kconfig"
  1033. source "lib/Kconfig"