mach-mini6410.c 4.5 KB

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  1. /* linux/arch/arm/mach-s3c64xx/mach-mini6410.c
  2. *
  3. * Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
  4. * Copyright 2008 Openmoko, Inc.
  5. * Copyright 2008 Simtec Electronics
  6. * Ben Dooks <ben@simtec.co.uk>
  7. * http://armlinux.simtec.co.uk/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. */
  14. #include <linux/init.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/gpio.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/dm9000.h>
  20. #include <linux/mtd/mtd.h>
  21. #include <linux/mtd/partitions.h>
  22. #include <linux/serial_core.h>
  23. #include <linux/types.h>
  24. #include <asm/mach-types.h>
  25. #include <asm/mach/arch.h>
  26. #include <asm/mach/map.h>
  27. #include <mach/map.h>
  28. #include <mach/regs-gpio.h>
  29. #include <mach/regs-srom.h>
  30. #include <mach/s3c6410.h>
  31. #include <plat/cpu.h>
  32. #include <plat/devs.h>
  33. #include <plat/nand.h>
  34. #include <plat/regs-serial.h>
  35. #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
  36. #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
  37. #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
  38. static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
  39. [0] = {
  40. .hwport = 0,
  41. .flags = 0,
  42. .ucon = UCON,
  43. .ulcon = ULCON,
  44. .ufcon = UFCON,
  45. },
  46. [1] = {
  47. .hwport = 1,
  48. .flags = 0,
  49. .ucon = UCON,
  50. .ulcon = ULCON,
  51. .ufcon = UFCON,
  52. },
  53. [2] = {
  54. .hwport = 2,
  55. .flags = 0,
  56. .ucon = UCON,
  57. .ulcon = ULCON,
  58. .ufcon = UFCON,
  59. },
  60. [3] = {
  61. .hwport = 3,
  62. .flags = 0,
  63. .ucon = UCON,
  64. .ulcon = ULCON,
  65. .ufcon = UFCON,
  66. },
  67. };
  68. /* DM9000AEP 10/100 ethernet controller */
  69. static struct resource mini6410_dm9k_resource[] = {
  70. [0] = {
  71. .start = S3C64XX_PA_XM0CSN1,
  72. .end = S3C64XX_PA_XM0CSN1 + 1,
  73. .flags = IORESOURCE_MEM
  74. },
  75. [1] = {
  76. .start = S3C64XX_PA_XM0CSN1 + 4,
  77. .end = S3C64XX_PA_XM0CSN1 + 5,
  78. .flags = IORESOURCE_MEM
  79. },
  80. [2] = {
  81. .start = S3C_EINT(7),
  82. .end = S3C_EINT(7),
  83. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL
  84. }
  85. };
  86. static struct dm9000_plat_data mini6410_dm9k_pdata = {
  87. .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
  88. };
  89. static struct platform_device mini6410_device_eth = {
  90. .name = "dm9000",
  91. .id = -1,
  92. .num_resources = ARRAY_SIZE(mini6410_dm9k_resource),
  93. .resource = mini6410_dm9k_resource,
  94. .dev = {
  95. .platform_data = &mini6410_dm9k_pdata,
  96. },
  97. };
  98. static struct mtd_partition mini6410_nand_part[] = {
  99. [0] = {
  100. .name = "uboot",
  101. .size = SZ_1M,
  102. .offset = 0,
  103. },
  104. [1] = {
  105. .name = "kernel",
  106. .size = SZ_2M,
  107. .offset = SZ_1M,
  108. },
  109. [2] = {
  110. .name = "rootfs",
  111. .size = MTDPART_SIZ_FULL,
  112. .offset = SZ_1M + SZ_2M,
  113. },
  114. };
  115. static struct s3c2410_nand_set mini6410_nand_sets[] = {
  116. [0] = {
  117. .name = "nand",
  118. .nr_chips = 1,
  119. .nr_partitions = ARRAY_SIZE(mini6410_nand_part),
  120. .partitions = mini6410_nand_part,
  121. },
  122. };
  123. static struct s3c2410_platform_nand mini6410_nand_info = {
  124. .tacls = 25,
  125. .twrph0 = 55,
  126. .twrph1 = 40,
  127. .nr_sets = ARRAY_SIZE(mini6410_nand_sets),
  128. .sets = mini6410_nand_sets,
  129. };
  130. static struct platform_device *mini6410_devices[] __initdata = {
  131. &mini6410_device_eth,
  132. &s3c_device_hsmmc0,
  133. &s3c_device_hsmmc1,
  134. &s3c_device_ohci,
  135. &s3c_device_nand,
  136. };
  137. static void __init mini6410_map_io(void)
  138. {
  139. s3c64xx_init_io(NULL, 0);
  140. s3c24xx_init_clocks(12000000);
  141. s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
  142. }
  143. static void __init mini6410_machine_init(void)
  144. {
  145. u32 cs1;
  146. s3c_nand_set_platdata(&mini6410_nand_info);
  147. /* configure nCS1 width to 16 bits */
  148. cs1 = __raw_readl(S3C64XX_SROM_BW) &
  149. ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
  150. cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
  151. (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
  152. (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
  153. S3C64XX_SROM_BW__NCS1__SHIFT;
  154. __raw_writel(cs1, S3C64XX_SROM_BW);
  155. /* set timing for nCS1 suitable for ethernet chip */
  156. __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
  157. (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
  158. (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
  159. (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
  160. (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
  161. (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
  162. (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
  163. platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
  164. }
  165. MACHINE_START(MINI6410, "MINI6410")
  166. /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
  167. .boot_params = S3C64XX_PA_SDRAM + 0x100,
  168. .init_irq = s3c6410_init_irq,
  169. .map_io = mini6410_map_io,
  170. .init_machine = mini6410_machine_init,
  171. .timer = &s3c24xx_timer,
  172. MACHINE_END