vmwgfx_kms.c 46 KB

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  1. /**************************************************************************
  2. *
  3. * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
  4. * All Rights Reserved.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the
  8. * "Software"), to deal in the Software without restriction, including
  9. * without limitation the rights to use, copy, modify, merge, publish,
  10. * distribute, sub license, and/or sell copies of the Software, and to
  11. * permit persons to whom the Software is furnished to do so, subject to
  12. * the following conditions:
  13. *
  14. * The above copyright notice and this permission notice (including the
  15. * next paragraph) shall be included in all copies or substantial portions
  16. * of the Software.
  17. *
  18. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20. * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21. * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22. * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23. * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24. * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25. *
  26. **************************************************************************/
  27. #include "vmwgfx_kms.h"
  28. /* Might need a hrtimer here? */
  29. #define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
  30. void vmw_display_unit_cleanup(struct vmw_display_unit *du)
  31. {
  32. if (du->cursor_surface)
  33. vmw_surface_unreference(&du->cursor_surface);
  34. if (du->cursor_dmabuf)
  35. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  36. drm_crtc_cleanup(&du->crtc);
  37. drm_encoder_cleanup(&du->encoder);
  38. drm_connector_cleanup(&du->connector);
  39. }
  40. /*
  41. * Display Unit Cursor functions
  42. */
  43. int vmw_cursor_update_image(struct vmw_private *dev_priv,
  44. u32 *image, u32 width, u32 height,
  45. u32 hotspotX, u32 hotspotY)
  46. {
  47. struct {
  48. u32 cmd;
  49. SVGAFifoCmdDefineAlphaCursor cursor;
  50. } *cmd;
  51. u32 image_size = width * height * 4;
  52. u32 cmd_size = sizeof(*cmd) + image_size;
  53. if (!image)
  54. return -EINVAL;
  55. cmd = vmw_fifo_reserve(dev_priv, cmd_size);
  56. if (unlikely(cmd == NULL)) {
  57. DRM_ERROR("Fifo reserve failed.\n");
  58. return -ENOMEM;
  59. }
  60. memset(cmd, 0, sizeof(*cmd));
  61. memcpy(&cmd[1], image, image_size);
  62. cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
  63. cmd->cursor.id = cpu_to_le32(0);
  64. cmd->cursor.width = cpu_to_le32(width);
  65. cmd->cursor.height = cpu_to_le32(height);
  66. cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
  67. cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
  68. vmw_fifo_commit(dev_priv, cmd_size);
  69. return 0;
  70. }
  71. void vmw_cursor_update_position(struct vmw_private *dev_priv,
  72. bool show, int x, int y)
  73. {
  74. __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  75. uint32_t count;
  76. iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
  77. iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
  78. iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
  79. count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  80. iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
  81. }
  82. int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
  83. uint32_t handle, uint32_t width, uint32_t height)
  84. {
  85. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  86. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  87. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  88. struct vmw_surface *surface = NULL;
  89. struct vmw_dma_buffer *dmabuf = NULL;
  90. int ret;
  91. if (handle) {
  92. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  93. handle, &surface);
  94. if (!ret) {
  95. if (!surface->snooper.image) {
  96. DRM_ERROR("surface not suitable for cursor\n");
  97. return -EINVAL;
  98. }
  99. } else {
  100. ret = vmw_user_dmabuf_lookup(tfile,
  101. handle, &dmabuf);
  102. if (ret) {
  103. DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
  104. return -EINVAL;
  105. }
  106. }
  107. }
  108. /* takedown old cursor */
  109. if (du->cursor_surface) {
  110. du->cursor_surface->snooper.crtc = NULL;
  111. vmw_surface_unreference(&du->cursor_surface);
  112. }
  113. if (du->cursor_dmabuf)
  114. vmw_dmabuf_unreference(&du->cursor_dmabuf);
  115. /* setup new image */
  116. if (surface) {
  117. /* vmw_user_surface_lookup takes one reference */
  118. du->cursor_surface = surface;
  119. du->cursor_surface->snooper.crtc = crtc;
  120. du->cursor_age = du->cursor_surface->snooper.age;
  121. vmw_cursor_update_image(dev_priv, surface->snooper.image,
  122. 64, 64, du->hotspot_x, du->hotspot_y);
  123. } else if (dmabuf) {
  124. struct ttm_bo_kmap_obj map;
  125. unsigned long kmap_offset;
  126. unsigned long kmap_num;
  127. void *virtual;
  128. bool dummy;
  129. /* vmw_user_surface_lookup takes one reference */
  130. du->cursor_dmabuf = dmabuf;
  131. kmap_offset = 0;
  132. kmap_num = (64*64*4) >> PAGE_SHIFT;
  133. ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
  134. if (unlikely(ret != 0)) {
  135. DRM_ERROR("reserve failed\n");
  136. return -EINVAL;
  137. }
  138. ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
  139. if (unlikely(ret != 0))
  140. goto err_unreserve;
  141. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  142. vmw_cursor_update_image(dev_priv, virtual, 64, 64,
  143. du->hotspot_x, du->hotspot_y);
  144. ttm_bo_kunmap(&map);
  145. err_unreserve:
  146. ttm_bo_unreserve(&dmabuf->base);
  147. } else {
  148. vmw_cursor_update_position(dev_priv, false, 0, 0);
  149. return 0;
  150. }
  151. vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
  152. return 0;
  153. }
  154. int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
  155. {
  156. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  157. struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
  158. bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
  159. du->cursor_x = x + crtc->x;
  160. du->cursor_y = y + crtc->y;
  161. vmw_cursor_update_position(dev_priv, shown,
  162. du->cursor_x, du->cursor_y);
  163. return 0;
  164. }
  165. void vmw_kms_cursor_snoop(struct vmw_surface *srf,
  166. struct ttm_object_file *tfile,
  167. struct ttm_buffer_object *bo,
  168. SVGA3dCmdHeader *header)
  169. {
  170. struct ttm_bo_kmap_obj map;
  171. unsigned long kmap_offset;
  172. unsigned long kmap_num;
  173. SVGA3dCopyBox *box;
  174. unsigned box_count;
  175. void *virtual;
  176. bool dummy;
  177. struct vmw_dma_cmd {
  178. SVGA3dCmdHeader header;
  179. SVGA3dCmdSurfaceDMA dma;
  180. } *cmd;
  181. int ret;
  182. cmd = container_of(header, struct vmw_dma_cmd, header);
  183. /* No snooper installed */
  184. if (!srf->snooper.image)
  185. return;
  186. if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
  187. DRM_ERROR("face and mipmap for cursors should never != 0\n");
  188. return;
  189. }
  190. if (cmd->header.size < 64) {
  191. DRM_ERROR("at least one full copy box must be given\n");
  192. return;
  193. }
  194. box = (SVGA3dCopyBox *)&cmd[1];
  195. box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
  196. sizeof(SVGA3dCopyBox);
  197. if (cmd->dma.guest.pitch != (64 * 4) ||
  198. cmd->dma.guest.ptr.offset % PAGE_SIZE ||
  199. box->x != 0 || box->y != 0 || box->z != 0 ||
  200. box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
  201. box->w != 64 || box->h != 64 || box->d != 1 ||
  202. box_count != 1) {
  203. /* TODO handle none page aligned offsets */
  204. /* TODO handle partial uploads and pitch != 256 */
  205. /* TODO handle more then one copy (size != 64) */
  206. DRM_ERROR("lazy programmer, can't handle weird stuff\n");
  207. return;
  208. }
  209. kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
  210. kmap_num = (64*64*4) >> PAGE_SHIFT;
  211. ret = ttm_bo_reserve(bo, true, false, false, 0);
  212. if (unlikely(ret != 0)) {
  213. DRM_ERROR("reserve failed\n");
  214. return;
  215. }
  216. ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
  217. if (unlikely(ret != 0))
  218. goto err_unreserve;
  219. virtual = ttm_kmap_obj_virtual(&map, &dummy);
  220. memcpy(srf->snooper.image, virtual, 64*64*4);
  221. srf->snooper.age++;
  222. /* we can't call this function from this function since execbuf has
  223. * reserved fifo space.
  224. *
  225. * if (srf->snooper.crtc)
  226. * vmw_ldu_crtc_cursor_update_image(dev_priv,
  227. * srf->snooper.image, 64, 64,
  228. * du->hotspot_x, du->hotspot_y);
  229. */
  230. ttm_bo_kunmap(&map);
  231. err_unreserve:
  232. ttm_bo_unreserve(bo);
  233. }
  234. void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
  235. {
  236. struct drm_device *dev = dev_priv->dev;
  237. struct vmw_display_unit *du;
  238. struct drm_crtc *crtc;
  239. mutex_lock(&dev->mode_config.mutex);
  240. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  241. du = vmw_crtc_to_du(crtc);
  242. if (!du->cursor_surface ||
  243. du->cursor_age == du->cursor_surface->snooper.age)
  244. continue;
  245. du->cursor_age = du->cursor_surface->snooper.age;
  246. vmw_cursor_update_image(dev_priv,
  247. du->cursor_surface->snooper.image,
  248. 64, 64, du->hotspot_x, du->hotspot_y);
  249. }
  250. mutex_unlock(&dev->mode_config.mutex);
  251. }
  252. /*
  253. * Generic framebuffer code
  254. */
  255. int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
  256. struct drm_file *file_priv,
  257. unsigned int *handle)
  258. {
  259. if (handle)
  260. handle = 0;
  261. return 0;
  262. }
  263. /*
  264. * Surface framebuffer code
  265. */
  266. #define vmw_framebuffer_to_vfbs(x) \
  267. container_of(x, struct vmw_framebuffer_surface, base.base)
  268. struct vmw_framebuffer_surface {
  269. struct vmw_framebuffer base;
  270. struct vmw_surface *surface;
  271. struct vmw_dma_buffer *buffer;
  272. struct list_head head;
  273. struct drm_master *master;
  274. };
  275. void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
  276. {
  277. struct vmw_framebuffer_surface *vfbs =
  278. vmw_framebuffer_to_vfbs(framebuffer);
  279. struct vmw_master *vmaster = vmw_master(vfbs->master);
  280. mutex_lock(&vmaster->fb_surf_mutex);
  281. list_del(&vfbs->head);
  282. mutex_unlock(&vmaster->fb_surf_mutex);
  283. drm_master_put(&vfbs->master);
  284. drm_framebuffer_cleanup(framebuffer);
  285. vmw_surface_unreference(&vfbs->surface);
  286. ttm_base_object_unref(&vfbs->base.user_obj);
  287. kfree(vfbs);
  288. }
  289. static int do_surface_dirty_sou(struct vmw_private *dev_priv,
  290. struct drm_file *file_priv,
  291. struct vmw_framebuffer *framebuffer,
  292. struct vmw_surface *surf,
  293. unsigned flags, unsigned color,
  294. struct drm_clip_rect *clips,
  295. unsigned num_clips, int inc)
  296. {
  297. struct drm_clip_rect *clips_ptr;
  298. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  299. struct drm_crtc *crtc;
  300. size_t fifo_size;
  301. int i, num_units;
  302. int ret = 0; /* silence warning */
  303. int left, right, top, bottom;
  304. struct {
  305. SVGA3dCmdHeader header;
  306. SVGA3dCmdBlitSurfaceToScreen body;
  307. } *cmd;
  308. SVGASignedRect *blits;
  309. num_units = 0;
  310. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
  311. head) {
  312. if (crtc->fb != &framebuffer->base)
  313. continue;
  314. units[num_units++] = vmw_crtc_to_du(crtc);
  315. }
  316. BUG_ON(surf == NULL);
  317. BUG_ON(!clips || !num_clips);
  318. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  319. cmd = kzalloc(fifo_size, GFP_KERNEL);
  320. if (unlikely(cmd == NULL)) {
  321. DRM_ERROR("Temporary fifo memory alloc failed.\n");
  322. return -ENOMEM;
  323. }
  324. left = clips->x1;
  325. right = clips->x2;
  326. top = clips->y1;
  327. bottom = clips->y2;
  328. clips_ptr = clips;
  329. for (i = 1; i < num_clips; i++, clips_ptr += inc) {
  330. left = min_t(int, left, (int)clips_ptr->x1);
  331. right = max_t(int, right, (int)clips_ptr->x2);
  332. top = min_t(int, top, (int)clips_ptr->y1);
  333. bottom = max_t(int, bottom, (int)clips_ptr->y2);
  334. }
  335. /* only need to do this once */
  336. memset(cmd, 0, fifo_size);
  337. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  338. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  339. cmd->body.srcRect.left = left;
  340. cmd->body.srcRect.right = right;
  341. cmd->body.srcRect.top = top;
  342. cmd->body.srcRect.bottom = bottom;
  343. clips_ptr = clips;
  344. blits = (SVGASignedRect *)&cmd[1];
  345. for (i = 0; i < num_clips; i++, clips_ptr += inc) {
  346. blits[i].left = clips_ptr->x1 - left;
  347. blits[i].right = clips_ptr->x2 - left;
  348. blits[i].top = clips_ptr->y1 - top;
  349. blits[i].bottom = clips_ptr->y2 - top;
  350. }
  351. /* do per unit writing, reuse fifo for each */
  352. for (i = 0; i < num_units; i++) {
  353. struct vmw_display_unit *unit = units[i];
  354. int clip_x1 = left - unit->crtc.x;
  355. int clip_y1 = top - unit->crtc.y;
  356. int clip_x2 = right - unit->crtc.x;
  357. int clip_y2 = bottom - unit->crtc.y;
  358. /* skip any crtcs that misses the clip region */
  359. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  360. clip_y1 >= unit->crtc.mode.vdisplay ||
  361. clip_x2 <= 0 || clip_y2 <= 0)
  362. continue;
  363. /* need to reset sid as it is changed by execbuf */
  364. cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
  365. cmd->body.destScreenId = unit->unit;
  366. /*
  367. * The blit command is a lot more resilient then the
  368. * readback command when it comes to clip rects. So its
  369. * okay to go out of bounds.
  370. */
  371. cmd->body.destRect.left = clip_x1;
  372. cmd->body.destRect.right = clip_x2;
  373. cmd->body.destRect.top = clip_y1;
  374. cmd->body.destRect.bottom = clip_y2;
  375. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  376. fifo_size, 0, NULL);
  377. if (unlikely(ret != 0))
  378. break;
  379. }
  380. kfree(cmd);
  381. return ret;
  382. }
  383. int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
  384. struct drm_file *file_priv,
  385. unsigned flags, unsigned color,
  386. struct drm_clip_rect *clips,
  387. unsigned num_clips)
  388. {
  389. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  390. struct vmw_master *vmaster = vmw_master(file_priv->master);
  391. struct vmw_framebuffer_surface *vfbs =
  392. vmw_framebuffer_to_vfbs(framebuffer);
  393. struct vmw_surface *surf = vfbs->surface;
  394. struct drm_clip_rect norect;
  395. int ret, inc = 1;
  396. if (unlikely(vfbs->master != file_priv->master))
  397. return -EINVAL;
  398. /* Require ScreenObject support for 3D */
  399. if (!dev_priv->sou_priv)
  400. return -EINVAL;
  401. ret = ttm_read_lock(&vmaster->lock, true);
  402. if (unlikely(ret != 0))
  403. return ret;
  404. if (!num_clips) {
  405. num_clips = 1;
  406. clips = &norect;
  407. norect.x1 = norect.y1 = 0;
  408. norect.x2 = framebuffer->width;
  409. norect.y2 = framebuffer->height;
  410. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  411. num_clips /= 2;
  412. inc = 2; /* skip source rects */
  413. }
  414. ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base, surf,
  415. flags, color,
  416. clips, num_clips, inc);
  417. ttm_read_unlock(&vmaster->lock);
  418. return 0;
  419. }
  420. static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
  421. .destroy = vmw_framebuffer_surface_destroy,
  422. .dirty = vmw_framebuffer_surface_dirty,
  423. .create_handle = vmw_framebuffer_create_handle,
  424. };
  425. static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
  426. struct drm_file *file_priv,
  427. struct vmw_surface *surface,
  428. struct vmw_framebuffer **out,
  429. const struct drm_mode_fb_cmd
  430. *mode_cmd)
  431. {
  432. struct drm_device *dev = dev_priv->dev;
  433. struct vmw_framebuffer_surface *vfbs;
  434. enum SVGA3dSurfaceFormat format;
  435. struct vmw_master *vmaster = vmw_master(file_priv->master);
  436. int ret;
  437. /* 3D is only supported on HWv8 hosts which supports screen objects */
  438. if (!dev_priv->sou_priv)
  439. return -ENOSYS;
  440. /*
  441. * Sanity checks.
  442. */
  443. if (unlikely(surface->mip_levels[0] != 1 ||
  444. surface->num_sizes != 1 ||
  445. surface->sizes[0].width < mode_cmd->width ||
  446. surface->sizes[0].height < mode_cmd->height ||
  447. surface->sizes[0].depth != 1)) {
  448. DRM_ERROR("Incompatible surface dimensions "
  449. "for requested mode.\n");
  450. return -EINVAL;
  451. }
  452. switch (mode_cmd->depth) {
  453. case 32:
  454. format = SVGA3D_A8R8G8B8;
  455. break;
  456. case 24:
  457. format = SVGA3D_X8R8G8B8;
  458. break;
  459. case 16:
  460. format = SVGA3D_R5G6B5;
  461. break;
  462. case 15:
  463. format = SVGA3D_A1R5G5B5;
  464. break;
  465. case 8:
  466. format = SVGA3D_LUMINANCE8;
  467. break;
  468. default:
  469. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  470. return -EINVAL;
  471. }
  472. if (unlikely(format != surface->format)) {
  473. DRM_ERROR("Invalid surface format for requested mode.\n");
  474. return -EINVAL;
  475. }
  476. vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
  477. if (!vfbs) {
  478. ret = -ENOMEM;
  479. goto out_err1;
  480. }
  481. ret = drm_framebuffer_init(dev, &vfbs->base.base,
  482. &vmw_framebuffer_surface_funcs);
  483. if (ret)
  484. goto out_err2;
  485. if (!vmw_surface_reference(surface)) {
  486. DRM_ERROR("failed to reference surface %p\n", surface);
  487. goto out_err3;
  488. }
  489. /* XXX get the first 3 from the surface info */
  490. vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
  491. vfbs->base.base.pitch = mode_cmd->pitch;
  492. vfbs->base.base.depth = mode_cmd->depth;
  493. vfbs->base.base.width = mode_cmd->width;
  494. vfbs->base.base.height = mode_cmd->height;
  495. vfbs->surface = surface;
  496. vfbs->base.user_handle = mode_cmd->handle;
  497. vfbs->master = drm_master_get(file_priv->master);
  498. mutex_lock(&vmaster->fb_surf_mutex);
  499. list_add_tail(&vfbs->head, &vmaster->fb_surf);
  500. mutex_unlock(&vmaster->fb_surf_mutex);
  501. *out = &vfbs->base;
  502. return 0;
  503. out_err3:
  504. drm_framebuffer_cleanup(&vfbs->base.base);
  505. out_err2:
  506. kfree(vfbs);
  507. out_err1:
  508. return ret;
  509. }
  510. /*
  511. * Dmabuf framebuffer code
  512. */
  513. #define vmw_framebuffer_to_vfbd(x) \
  514. container_of(x, struct vmw_framebuffer_dmabuf, base.base)
  515. struct vmw_framebuffer_dmabuf {
  516. struct vmw_framebuffer base;
  517. struct vmw_dma_buffer *buffer;
  518. };
  519. void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
  520. {
  521. struct vmw_framebuffer_dmabuf *vfbd =
  522. vmw_framebuffer_to_vfbd(framebuffer);
  523. drm_framebuffer_cleanup(framebuffer);
  524. vmw_dmabuf_unreference(&vfbd->buffer);
  525. ttm_base_object_unref(&vfbd->base.user_obj);
  526. kfree(vfbd);
  527. }
  528. static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
  529. struct vmw_framebuffer *framebuffer,
  530. struct vmw_dma_buffer *buffer,
  531. unsigned flags, unsigned color,
  532. struct drm_clip_rect *clips,
  533. unsigned num_clips, int increment)
  534. {
  535. size_t fifo_size;
  536. int i;
  537. struct {
  538. uint32_t header;
  539. SVGAFifoCmdUpdate body;
  540. } *cmd;
  541. fifo_size = sizeof(*cmd) * num_clips;
  542. cmd = vmw_fifo_reserve(dev_priv, fifo_size);
  543. if (unlikely(cmd == NULL)) {
  544. DRM_ERROR("Fifo reserve failed.\n");
  545. return -ENOMEM;
  546. }
  547. memset(cmd, 0, fifo_size);
  548. for (i = 0; i < num_clips; i++, clips += increment) {
  549. cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
  550. cmd[i].body.x = cpu_to_le32(clips->x1);
  551. cmd[i].body.y = cpu_to_le32(clips->y1);
  552. cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
  553. cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
  554. }
  555. vmw_fifo_commit(dev_priv, fifo_size);
  556. return 0;
  557. }
  558. static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
  559. struct vmw_private *dev_priv,
  560. struct vmw_framebuffer *framebuffer)
  561. {
  562. size_t fifo_size;
  563. int ret;
  564. struct {
  565. uint32_t header;
  566. SVGAFifoCmdDefineGMRFB body;
  567. } *cmd;
  568. fifo_size = sizeof(*cmd);
  569. cmd = kmalloc(fifo_size, GFP_KERNEL);
  570. if (unlikely(cmd == NULL)) {
  571. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  572. return -ENOMEM;
  573. }
  574. memset(cmd, 0, fifo_size);
  575. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  576. cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
  577. cmd->body.format.colorDepth = framebuffer->base.depth;
  578. cmd->body.format.reserved = 0;
  579. cmd->body.bytesPerLine = framebuffer->base.pitch;
  580. cmd->body.ptr.gmrId = framebuffer->user_handle;
  581. cmd->body.ptr.offset = 0;
  582. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  583. fifo_size, 0, NULL);
  584. kfree(cmd);
  585. return ret;
  586. }
  587. static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
  588. struct vmw_private *dev_priv,
  589. struct vmw_framebuffer *framebuffer,
  590. struct vmw_dma_buffer *buffer,
  591. unsigned flags, unsigned color,
  592. struct drm_clip_rect *clips,
  593. unsigned num_clips, int increment)
  594. {
  595. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  596. struct drm_clip_rect *clips_ptr;
  597. int i, k, num_units, ret;
  598. struct drm_crtc *crtc;
  599. size_t fifo_size;
  600. struct {
  601. uint32_t header;
  602. SVGAFifoCmdBlitGMRFBToScreen body;
  603. } *blits;
  604. ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
  605. if (unlikely(ret != 0))
  606. return ret; /* define_gmrfb prints warnings */
  607. fifo_size = sizeof(*blits) * num_clips;
  608. blits = kmalloc(fifo_size, GFP_KERNEL);
  609. if (unlikely(blits == NULL)) {
  610. DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
  611. return -ENOMEM;
  612. }
  613. num_units = 0;
  614. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  615. if (crtc->fb != &framebuffer->base)
  616. continue;
  617. units[num_units++] = vmw_crtc_to_du(crtc);
  618. }
  619. for (k = 0; k < num_units; k++) {
  620. struct vmw_display_unit *unit = units[k];
  621. int hit_num = 0;
  622. clips_ptr = clips;
  623. for (i = 0; i < num_clips; i++, clips_ptr += increment) {
  624. int clip_x1 = clips_ptr->x1 - unit->crtc.x;
  625. int clip_y1 = clips_ptr->y1 - unit->crtc.y;
  626. int clip_x2 = clips_ptr->x2 - unit->crtc.x;
  627. int clip_y2 = clips_ptr->y2 - unit->crtc.y;
  628. /* skip any crtcs that misses the clip region */
  629. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  630. clip_y1 >= unit->crtc.mode.vdisplay ||
  631. clip_x2 <= 0 || clip_y2 <= 0)
  632. continue;
  633. blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
  634. blits[hit_num].body.destScreenId = unit->unit;
  635. blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
  636. blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
  637. blits[hit_num].body.destRect.left = clip_x1;
  638. blits[hit_num].body.destRect.top = clip_y1;
  639. blits[hit_num].body.destRect.right = clip_x2;
  640. blits[hit_num].body.destRect.bottom = clip_y2;
  641. hit_num++;
  642. }
  643. /* no clips hit the crtc */
  644. if (hit_num == 0)
  645. continue;
  646. fifo_size = sizeof(*blits) * hit_num;
  647. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
  648. fifo_size, 0, NULL);
  649. if (unlikely(ret != 0))
  650. break;
  651. }
  652. kfree(blits);
  653. return ret;
  654. }
  655. int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
  656. struct drm_file *file_priv,
  657. unsigned flags, unsigned color,
  658. struct drm_clip_rect *clips,
  659. unsigned num_clips)
  660. {
  661. struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
  662. struct vmw_master *vmaster = vmw_master(file_priv->master);
  663. struct vmw_framebuffer_dmabuf *vfbd =
  664. vmw_framebuffer_to_vfbd(framebuffer);
  665. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  666. struct drm_clip_rect norect;
  667. int ret, increment = 1;
  668. ret = ttm_read_lock(&vmaster->lock, true);
  669. if (unlikely(ret != 0))
  670. return ret;
  671. if (!num_clips) {
  672. num_clips = 1;
  673. clips = &norect;
  674. norect.x1 = norect.y1 = 0;
  675. norect.x2 = framebuffer->width;
  676. norect.y2 = framebuffer->height;
  677. } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
  678. num_clips /= 2;
  679. increment = 2;
  680. }
  681. if (dev_priv->ldu_priv) {
  682. ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base, dmabuf,
  683. flags, color,
  684. clips, num_clips, increment);
  685. } else {
  686. ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
  687. dmabuf, flags, color,
  688. clips, num_clips, increment);
  689. }
  690. ttm_read_unlock(&vmaster->lock);
  691. return ret;
  692. }
  693. static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
  694. .destroy = vmw_framebuffer_dmabuf_destroy,
  695. .dirty = vmw_framebuffer_dmabuf_dirty,
  696. .create_handle = vmw_framebuffer_create_handle,
  697. };
  698. /**
  699. * Pin the dmabuffer to the start of vram.
  700. */
  701. static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
  702. {
  703. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  704. struct vmw_framebuffer_dmabuf *vfbd =
  705. vmw_framebuffer_to_vfbd(&vfb->base);
  706. int ret;
  707. /* This code should not be used with screen objects */
  708. BUG_ON(dev_priv->sou_priv);
  709. vmw_overlay_pause_all(dev_priv);
  710. ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
  711. vmw_overlay_resume_all(dev_priv);
  712. WARN_ON(ret != 0);
  713. return 0;
  714. }
  715. static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
  716. {
  717. struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
  718. struct vmw_framebuffer_dmabuf *vfbd =
  719. vmw_framebuffer_to_vfbd(&vfb->base);
  720. if (!vfbd->buffer) {
  721. WARN_ON(!vfbd->buffer);
  722. return 0;
  723. }
  724. return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
  725. }
  726. static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
  727. struct vmw_dma_buffer *dmabuf,
  728. struct vmw_framebuffer **out,
  729. const struct drm_mode_fb_cmd
  730. *mode_cmd)
  731. {
  732. struct drm_device *dev = dev_priv->dev;
  733. struct vmw_framebuffer_dmabuf *vfbd;
  734. unsigned int requested_size;
  735. int ret;
  736. requested_size = mode_cmd->height * mode_cmd->pitch;
  737. if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
  738. DRM_ERROR("Screen buffer object size is too small "
  739. "for requested mode.\n");
  740. return -EINVAL;
  741. }
  742. /* Limited framebuffer color depth support for screen objects */
  743. if (dev_priv->sou_priv) {
  744. switch (mode_cmd->depth) {
  745. case 32:
  746. case 24:
  747. /* Only support 32 bpp for 32 and 24 depth fbs */
  748. if (mode_cmd->bpp == 32)
  749. break;
  750. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  751. mode_cmd->depth, mode_cmd->bpp);
  752. return -EINVAL;
  753. case 16:
  754. case 15:
  755. /* Only support 16 bpp for 16 and 15 depth fbs */
  756. if (mode_cmd->bpp == 16)
  757. break;
  758. DRM_ERROR("Invalid color depth/bbp: %d %d\n",
  759. mode_cmd->depth, mode_cmd->bpp);
  760. return -EINVAL;
  761. default:
  762. DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
  763. return -EINVAL;
  764. }
  765. }
  766. vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
  767. if (!vfbd) {
  768. ret = -ENOMEM;
  769. goto out_err1;
  770. }
  771. ret = drm_framebuffer_init(dev, &vfbd->base.base,
  772. &vmw_framebuffer_dmabuf_funcs);
  773. if (ret)
  774. goto out_err2;
  775. if (!vmw_dmabuf_reference(dmabuf)) {
  776. DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
  777. goto out_err3;
  778. }
  779. vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
  780. vfbd->base.base.pitch = mode_cmd->pitch;
  781. vfbd->base.base.depth = mode_cmd->depth;
  782. vfbd->base.base.width = mode_cmd->width;
  783. vfbd->base.base.height = mode_cmd->height;
  784. if (!dev_priv->sou_priv) {
  785. vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
  786. vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
  787. }
  788. vfbd->base.dmabuf = true;
  789. vfbd->buffer = dmabuf;
  790. vfbd->base.user_handle = mode_cmd->handle;
  791. *out = &vfbd->base;
  792. return 0;
  793. out_err3:
  794. drm_framebuffer_cleanup(&vfbd->base.base);
  795. out_err2:
  796. kfree(vfbd);
  797. out_err1:
  798. return ret;
  799. }
  800. /*
  801. * Generic Kernel modesetting functions
  802. */
  803. static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
  804. struct drm_file *file_priv,
  805. struct drm_mode_fb_cmd *mode_cmd)
  806. {
  807. struct vmw_private *dev_priv = vmw_priv(dev);
  808. struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
  809. struct vmw_framebuffer *vfb = NULL;
  810. struct vmw_surface *surface = NULL;
  811. struct vmw_dma_buffer *bo = NULL;
  812. struct ttm_base_object *user_obj;
  813. u64 required_size;
  814. int ret;
  815. /**
  816. * This code should be conditioned on Screen Objects not being used.
  817. * If screen objects are used, we can allocate a GMR to hold the
  818. * requested framebuffer.
  819. */
  820. required_size = mode_cmd->pitch * mode_cmd->height;
  821. if (unlikely(required_size > (u64) dev_priv->vram_size)) {
  822. DRM_ERROR("VRAM size is too small for requested mode.\n");
  823. return NULL;
  824. }
  825. /*
  826. * Take a reference on the user object of the resource
  827. * backing the kms fb. This ensures that user-space handle
  828. * lookups on that resource will always work as long as
  829. * it's registered with a kms framebuffer. This is important,
  830. * since vmw_execbuf_process identifies resources in the
  831. * command stream using user-space handles.
  832. */
  833. user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
  834. if (unlikely(user_obj == NULL)) {
  835. DRM_ERROR("Could not locate requested kms frame buffer.\n");
  836. return ERR_PTR(-ENOENT);
  837. }
  838. /**
  839. * End conditioned code.
  840. */
  841. ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
  842. mode_cmd->handle, &surface);
  843. if (ret)
  844. goto try_dmabuf;
  845. if (!surface->scanout)
  846. goto err_not_scanout;
  847. ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
  848. &vfb, mode_cmd);
  849. /* vmw_user_surface_lookup takes one ref so does new_fb */
  850. vmw_surface_unreference(&surface);
  851. if (ret) {
  852. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  853. ttm_base_object_unref(&user_obj);
  854. return ERR_PTR(ret);
  855. } else
  856. vfb->user_obj = user_obj;
  857. return &vfb->base;
  858. try_dmabuf:
  859. DRM_INFO("%s: trying buffer\n", __func__);
  860. ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
  861. if (ret) {
  862. DRM_ERROR("failed to find buffer: %i\n", ret);
  863. return ERR_PTR(-ENOENT);
  864. }
  865. ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
  866. mode_cmd);
  867. /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
  868. vmw_dmabuf_unreference(&bo);
  869. if (ret) {
  870. DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
  871. ttm_base_object_unref(&user_obj);
  872. return ERR_PTR(ret);
  873. } else
  874. vfb->user_obj = user_obj;
  875. return &vfb->base;
  876. err_not_scanout:
  877. DRM_ERROR("surface not marked as scanout\n");
  878. /* vmw_user_surface_lookup takes one ref */
  879. vmw_surface_unreference(&surface);
  880. ttm_base_object_unref(&user_obj);
  881. return ERR_PTR(-EINVAL);
  882. }
  883. static struct drm_mode_config_funcs vmw_kms_funcs = {
  884. .fb_create = vmw_kms_fb_create,
  885. };
  886. int vmw_kms_present(struct vmw_private *dev_priv,
  887. struct drm_file *file_priv,
  888. struct vmw_framebuffer *vfb,
  889. struct vmw_surface *surface,
  890. uint32_t sid,
  891. int32_t destX, int32_t destY,
  892. struct drm_vmw_rect *clips,
  893. uint32_t num_clips)
  894. {
  895. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  896. struct drm_crtc *crtc;
  897. size_t fifo_size;
  898. int i, k, num_units;
  899. int ret = 0; /* silence warning */
  900. struct {
  901. SVGA3dCmdHeader header;
  902. SVGA3dCmdBlitSurfaceToScreen body;
  903. } *cmd;
  904. SVGASignedRect *blits;
  905. num_units = 0;
  906. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  907. if (crtc->fb != &vfb->base)
  908. continue;
  909. units[num_units++] = vmw_crtc_to_du(crtc);
  910. }
  911. BUG_ON(surface == NULL);
  912. BUG_ON(!clips || !num_clips);
  913. fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
  914. cmd = kmalloc(fifo_size, GFP_KERNEL);
  915. if (unlikely(cmd == NULL)) {
  916. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  917. return -ENOMEM;
  918. }
  919. /* only need to do this once */
  920. memset(cmd, 0, fifo_size);
  921. cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
  922. cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
  923. cmd->body.srcRect.left = 0;
  924. cmd->body.srcRect.right = surface->sizes[0].width;
  925. cmd->body.srcRect.top = 0;
  926. cmd->body.srcRect.bottom = surface->sizes[0].height;
  927. blits = (SVGASignedRect *)&cmd[1];
  928. for (i = 0; i < num_clips; i++) {
  929. blits[i].left = clips[i].x;
  930. blits[i].right = clips[i].x + clips[i].w;
  931. blits[i].top = clips[i].y;
  932. blits[i].bottom = clips[i].y + clips[i].h;
  933. }
  934. for (k = 0; k < num_units; k++) {
  935. struct vmw_display_unit *unit = units[k];
  936. int clip_x1 = destX - unit->crtc.x;
  937. int clip_y1 = destY - unit->crtc.y;
  938. int clip_x2 = clip_x1 + surface->sizes[0].width;
  939. int clip_y2 = clip_y1 + surface->sizes[0].height;
  940. /* skip any crtcs that misses the clip region */
  941. if (clip_x1 >= unit->crtc.mode.hdisplay ||
  942. clip_y1 >= unit->crtc.mode.vdisplay ||
  943. clip_x2 <= 0 || clip_y2 <= 0)
  944. continue;
  945. /* need to reset sid as it is changed by execbuf */
  946. cmd->body.srcImage.sid = sid;
  947. cmd->body.destScreenId = unit->unit;
  948. /*
  949. * The blit command is a lot more resilient then the
  950. * readback command when it comes to clip rects. So its
  951. * okay to go out of bounds.
  952. */
  953. cmd->body.destRect.left = clip_x1;
  954. cmd->body.destRect.right = clip_x2;
  955. cmd->body.destRect.top = clip_y1;
  956. cmd->body.destRect.bottom = clip_y2;
  957. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
  958. fifo_size, 0, NULL);
  959. if (unlikely(ret != 0))
  960. break;
  961. }
  962. kfree(cmd);
  963. return ret;
  964. }
  965. int vmw_kms_readback(struct vmw_private *dev_priv,
  966. struct drm_file *file_priv,
  967. struct vmw_framebuffer *vfb,
  968. struct drm_vmw_fence_rep __user *user_fence_rep,
  969. struct drm_vmw_rect *clips,
  970. uint32_t num_clips)
  971. {
  972. struct vmw_framebuffer_dmabuf *vfbd =
  973. vmw_framebuffer_to_vfbd(&vfb->base);
  974. struct vmw_dma_buffer *dmabuf = vfbd->buffer;
  975. struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
  976. struct drm_crtc *crtc;
  977. size_t fifo_size;
  978. int i, k, ret, num_units, blits_pos;
  979. struct {
  980. uint32_t header;
  981. SVGAFifoCmdDefineGMRFB body;
  982. } *cmd;
  983. struct {
  984. uint32_t header;
  985. SVGAFifoCmdBlitScreenToGMRFB body;
  986. } *blits;
  987. num_units = 0;
  988. list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
  989. if (crtc->fb != &vfb->base)
  990. continue;
  991. units[num_units++] = vmw_crtc_to_du(crtc);
  992. }
  993. BUG_ON(dmabuf == NULL);
  994. BUG_ON(!clips || !num_clips);
  995. /* take a safe guess at fifo size */
  996. fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
  997. cmd = kmalloc(fifo_size, GFP_KERNEL);
  998. if (unlikely(cmd == NULL)) {
  999. DRM_ERROR("Failed to allocate temporary fifo memory.\n");
  1000. return -ENOMEM;
  1001. }
  1002. memset(cmd, 0, fifo_size);
  1003. cmd->header = SVGA_CMD_DEFINE_GMRFB;
  1004. cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
  1005. cmd->body.format.colorDepth = vfb->base.depth;
  1006. cmd->body.format.reserved = 0;
  1007. cmd->body.bytesPerLine = vfb->base.pitch;
  1008. cmd->body.ptr.gmrId = vfb->user_handle;
  1009. cmd->body.ptr.offset = 0;
  1010. blits = (void *)&cmd[1];
  1011. blits_pos = 0;
  1012. for (i = 0; i < num_units; i++) {
  1013. struct drm_vmw_rect *c = clips;
  1014. for (k = 0; k < num_clips; k++, c++) {
  1015. /* transform clip coords to crtc origin based coords */
  1016. int clip_x1 = c->x - units[i]->crtc.x;
  1017. int clip_x2 = c->x - units[i]->crtc.x + c->w;
  1018. int clip_y1 = c->y - units[i]->crtc.y;
  1019. int clip_y2 = c->y - units[i]->crtc.y + c->h;
  1020. int dest_x = c->x;
  1021. int dest_y = c->y;
  1022. /* compensate for clipping, we negate
  1023. * a negative number and add that.
  1024. */
  1025. if (clip_x1 < 0)
  1026. dest_x += -clip_x1;
  1027. if (clip_y1 < 0)
  1028. dest_y += -clip_y1;
  1029. /* clip */
  1030. clip_x1 = max(clip_x1, 0);
  1031. clip_y1 = max(clip_y1, 0);
  1032. clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
  1033. clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
  1034. /* and cull any rects that misses the crtc */
  1035. if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
  1036. clip_y1 >= units[i]->crtc.mode.vdisplay ||
  1037. clip_x2 <= 0 || clip_y2 <= 0)
  1038. continue;
  1039. blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
  1040. blits[blits_pos].body.srcScreenId = units[i]->unit;
  1041. blits[blits_pos].body.destOrigin.x = dest_x;
  1042. blits[blits_pos].body.destOrigin.y = dest_y;
  1043. blits[blits_pos].body.srcRect.left = clip_x1;
  1044. blits[blits_pos].body.srcRect.top = clip_y1;
  1045. blits[blits_pos].body.srcRect.right = clip_x2;
  1046. blits[blits_pos].body.srcRect.bottom = clip_y2;
  1047. blits_pos++;
  1048. }
  1049. }
  1050. /* reset size here and use calculated exact size from loops */
  1051. fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
  1052. ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
  1053. 0, user_fence_rep);
  1054. kfree(cmd);
  1055. return ret;
  1056. }
  1057. int vmw_kms_init(struct vmw_private *dev_priv)
  1058. {
  1059. struct drm_device *dev = dev_priv->dev;
  1060. int ret;
  1061. drm_mode_config_init(dev);
  1062. dev->mode_config.funcs = &vmw_kms_funcs;
  1063. dev->mode_config.min_width = 1;
  1064. dev->mode_config.min_height = 1;
  1065. /* assumed largest fb size */
  1066. dev->mode_config.max_width = 8192;
  1067. dev->mode_config.max_height = 8192;
  1068. ret = vmw_kms_init_screen_object_display(dev_priv);
  1069. if (ret) /* Fallback */
  1070. (void)vmw_kms_init_legacy_display_system(dev_priv);
  1071. return 0;
  1072. }
  1073. int vmw_kms_close(struct vmw_private *dev_priv)
  1074. {
  1075. /*
  1076. * Docs says we should take the lock before calling this function
  1077. * but since it destroys encoders and our destructor calls
  1078. * drm_encoder_cleanup which takes the lock we deadlock.
  1079. */
  1080. drm_mode_config_cleanup(dev_priv->dev);
  1081. vmw_kms_close_legacy_display_system(dev_priv);
  1082. return 0;
  1083. }
  1084. int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
  1085. struct drm_file *file_priv)
  1086. {
  1087. struct drm_vmw_cursor_bypass_arg *arg = data;
  1088. struct vmw_display_unit *du;
  1089. struct drm_mode_object *obj;
  1090. struct drm_crtc *crtc;
  1091. int ret = 0;
  1092. mutex_lock(&dev->mode_config.mutex);
  1093. if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
  1094. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  1095. du = vmw_crtc_to_du(crtc);
  1096. du->hotspot_x = arg->xhot;
  1097. du->hotspot_y = arg->yhot;
  1098. }
  1099. mutex_unlock(&dev->mode_config.mutex);
  1100. return 0;
  1101. }
  1102. obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
  1103. if (!obj) {
  1104. ret = -EINVAL;
  1105. goto out;
  1106. }
  1107. crtc = obj_to_crtc(obj);
  1108. du = vmw_crtc_to_du(crtc);
  1109. du->hotspot_x = arg->xhot;
  1110. du->hotspot_y = arg->yhot;
  1111. out:
  1112. mutex_unlock(&dev->mode_config.mutex);
  1113. return ret;
  1114. }
  1115. int vmw_kms_write_svga(struct vmw_private *vmw_priv,
  1116. unsigned width, unsigned height, unsigned pitch,
  1117. unsigned bpp, unsigned depth)
  1118. {
  1119. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1120. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
  1121. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1122. iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1123. vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
  1124. vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
  1125. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
  1126. if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
  1127. DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
  1128. depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
  1129. return -EINVAL;
  1130. }
  1131. return 0;
  1132. }
  1133. int vmw_kms_save_vga(struct vmw_private *vmw_priv)
  1134. {
  1135. struct vmw_vga_topology_state *save;
  1136. uint32_t i;
  1137. vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
  1138. vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
  1139. vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
  1140. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1141. vmw_priv->vga_pitchlock =
  1142. vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
  1143. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1144. vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
  1145. SVGA_FIFO_PITCHLOCK);
  1146. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1147. return 0;
  1148. vmw_priv->num_displays = vmw_read(vmw_priv,
  1149. SVGA_REG_NUM_GUEST_DISPLAYS);
  1150. if (vmw_priv->num_displays == 0)
  1151. vmw_priv->num_displays = 1;
  1152. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1153. save = &vmw_priv->vga_save[i];
  1154. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1155. save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
  1156. save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
  1157. save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
  1158. save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
  1159. save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
  1160. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1161. if (i == 0 && vmw_priv->num_displays == 1 &&
  1162. save->width == 0 && save->height == 0) {
  1163. /*
  1164. * It should be fairly safe to assume that these
  1165. * values are uninitialized.
  1166. */
  1167. save->width = vmw_priv->vga_width - save->pos_x;
  1168. save->height = vmw_priv->vga_height - save->pos_y;
  1169. }
  1170. }
  1171. return 0;
  1172. }
  1173. int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
  1174. {
  1175. struct vmw_vga_topology_state *save;
  1176. uint32_t i;
  1177. vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
  1178. vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
  1179. vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
  1180. if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
  1181. vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
  1182. vmw_priv->vga_pitchlock);
  1183. else if (vmw_fifo_have_pitchlock(vmw_priv))
  1184. iowrite32(vmw_priv->vga_pitchlock,
  1185. vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
  1186. if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
  1187. return 0;
  1188. for (i = 0; i < vmw_priv->num_displays; ++i) {
  1189. save = &vmw_priv->vga_save[i];
  1190. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
  1191. vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
  1192. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
  1193. vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
  1194. vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
  1195. vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
  1196. vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
  1197. }
  1198. return 0;
  1199. }
  1200. bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
  1201. uint32_t pitch,
  1202. uint32_t height)
  1203. {
  1204. return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
  1205. }
  1206. /**
  1207. * Function called by DRM code called with vbl_lock held.
  1208. */
  1209. u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
  1210. {
  1211. return 0;
  1212. }
  1213. /**
  1214. * Function called by DRM code called with vbl_lock held.
  1215. */
  1216. int vmw_enable_vblank(struct drm_device *dev, int crtc)
  1217. {
  1218. return -ENOSYS;
  1219. }
  1220. /**
  1221. * Function called by DRM code called with vbl_lock held.
  1222. */
  1223. void vmw_disable_vblank(struct drm_device *dev, int crtc)
  1224. {
  1225. }
  1226. /*
  1227. * Small shared kms functions.
  1228. */
  1229. int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
  1230. struct drm_vmw_rect *rects)
  1231. {
  1232. struct drm_device *dev = dev_priv->dev;
  1233. struct vmw_display_unit *du;
  1234. struct drm_connector *con;
  1235. mutex_lock(&dev->mode_config.mutex);
  1236. #if 0
  1237. {
  1238. unsigned int i;
  1239. DRM_INFO("%s: new layout ", __func__);
  1240. for (i = 0; i < num; i++)
  1241. DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
  1242. rects[i].w, rects[i].h);
  1243. DRM_INFO("\n");
  1244. }
  1245. #endif
  1246. list_for_each_entry(con, &dev->mode_config.connector_list, head) {
  1247. du = vmw_connector_to_du(con);
  1248. if (num > du->unit) {
  1249. du->pref_width = rects[du->unit].w;
  1250. du->pref_height = rects[du->unit].h;
  1251. du->pref_active = true;
  1252. } else {
  1253. du->pref_width = 800;
  1254. du->pref_height = 600;
  1255. du->pref_active = false;
  1256. }
  1257. con->status = vmw_du_connector_detect(con, true);
  1258. }
  1259. mutex_unlock(&dev->mode_config.mutex);
  1260. return 0;
  1261. }
  1262. void vmw_du_crtc_save(struct drm_crtc *crtc)
  1263. {
  1264. }
  1265. void vmw_du_crtc_restore(struct drm_crtc *crtc)
  1266. {
  1267. }
  1268. void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
  1269. u16 *r, u16 *g, u16 *b,
  1270. uint32_t start, uint32_t size)
  1271. {
  1272. struct vmw_private *dev_priv = vmw_priv(crtc->dev);
  1273. int i;
  1274. for (i = 0; i < size; i++) {
  1275. DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
  1276. r[i], g[i], b[i]);
  1277. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
  1278. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
  1279. vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
  1280. }
  1281. }
  1282. void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
  1283. {
  1284. }
  1285. void vmw_du_connector_save(struct drm_connector *connector)
  1286. {
  1287. }
  1288. void vmw_du_connector_restore(struct drm_connector *connector)
  1289. {
  1290. }
  1291. enum drm_connector_status
  1292. vmw_du_connector_detect(struct drm_connector *connector, bool force)
  1293. {
  1294. uint32_t num_displays;
  1295. struct drm_device *dev = connector->dev;
  1296. struct vmw_private *dev_priv = vmw_priv(dev);
  1297. mutex_lock(&dev_priv->hw_mutex);
  1298. num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
  1299. mutex_unlock(&dev_priv->hw_mutex);
  1300. return ((vmw_connector_to_du(connector)->unit < num_displays) ?
  1301. connector_status_connected : connector_status_disconnected);
  1302. }
  1303. static struct drm_display_mode vmw_kms_connector_builtin[] = {
  1304. /* 640x480@60Hz */
  1305. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
  1306. 752, 800, 0, 480, 489, 492, 525, 0,
  1307. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1308. /* 800x600@60Hz */
  1309. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
  1310. 968, 1056, 0, 600, 601, 605, 628, 0,
  1311. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1312. /* 1024x768@60Hz */
  1313. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
  1314. 1184, 1344, 0, 768, 771, 777, 806, 0,
  1315. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1316. /* 1152x864@75Hz */
  1317. { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
  1318. 1344, 1600, 0, 864, 865, 868, 900, 0,
  1319. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1320. /* 1280x768@60Hz */
  1321. { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
  1322. 1472, 1664, 0, 768, 771, 778, 798, 0,
  1323. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1324. /* 1280x800@60Hz */
  1325. { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
  1326. 1480, 1680, 0, 800, 803, 809, 831, 0,
  1327. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
  1328. /* 1280x960@60Hz */
  1329. { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
  1330. 1488, 1800, 0, 960, 961, 964, 1000, 0,
  1331. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1332. /* 1280x1024@60Hz */
  1333. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
  1334. 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
  1335. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1336. /* 1360x768@60Hz */
  1337. { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
  1338. 1536, 1792, 0, 768, 771, 777, 795, 0,
  1339. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1340. /* 1440x1050@60Hz */
  1341. { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
  1342. 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
  1343. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1344. /* 1440x900@60Hz */
  1345. { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
  1346. 1672, 1904, 0, 900, 903, 909, 934, 0,
  1347. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1348. /* 1600x1200@60Hz */
  1349. { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
  1350. 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
  1351. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1352. /* 1680x1050@60Hz */
  1353. { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
  1354. 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
  1355. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1356. /* 1792x1344@60Hz */
  1357. { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
  1358. 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
  1359. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1360. /* 1853x1392@60Hz */
  1361. { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
  1362. 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
  1363. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1364. /* 1920x1200@60Hz */
  1365. { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
  1366. 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
  1367. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1368. /* 1920x1440@60Hz */
  1369. { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
  1370. 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
  1371. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1372. /* 2560x1600@60Hz */
  1373. { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
  1374. 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
  1375. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1376. /* Terminate */
  1377. { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
  1378. };
  1379. int vmw_du_connector_fill_modes(struct drm_connector *connector,
  1380. uint32_t max_width, uint32_t max_height)
  1381. {
  1382. struct vmw_display_unit *du = vmw_connector_to_du(connector);
  1383. struct drm_device *dev = connector->dev;
  1384. struct vmw_private *dev_priv = vmw_priv(dev);
  1385. struct drm_display_mode *mode = NULL;
  1386. struct drm_display_mode *bmode;
  1387. struct drm_display_mode prefmode = { DRM_MODE("preferred",
  1388. DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
  1389. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  1390. DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
  1391. };
  1392. int i;
  1393. /* Add preferred mode */
  1394. {
  1395. mode = drm_mode_duplicate(dev, &prefmode);
  1396. if (!mode)
  1397. return 0;
  1398. mode->hdisplay = du->pref_width;
  1399. mode->vdisplay = du->pref_height;
  1400. mode->vrefresh = drm_mode_vrefresh(mode);
  1401. if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
  1402. mode->vdisplay)) {
  1403. drm_mode_probed_add(connector, mode);
  1404. if (du->pref_mode) {
  1405. list_del_init(&du->pref_mode->head);
  1406. drm_mode_destroy(dev, du->pref_mode);
  1407. }
  1408. du->pref_mode = mode;
  1409. }
  1410. }
  1411. for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
  1412. bmode = &vmw_kms_connector_builtin[i];
  1413. if (bmode->hdisplay > max_width ||
  1414. bmode->vdisplay > max_height)
  1415. continue;
  1416. if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
  1417. bmode->vdisplay))
  1418. continue;
  1419. mode = drm_mode_duplicate(dev, bmode);
  1420. if (!mode)
  1421. return 0;
  1422. mode->vrefresh = drm_mode_vrefresh(mode);
  1423. drm_mode_probed_add(connector, mode);
  1424. }
  1425. drm_mode_connector_list_update(connector);
  1426. return 1;
  1427. }
  1428. int vmw_du_connector_set_property(struct drm_connector *connector,
  1429. struct drm_property *property,
  1430. uint64_t val)
  1431. {
  1432. return 0;
  1433. }