tegra-kbc.c 23 KB

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  1. /*
  2. * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
  3. * keyboard controller
  4. *
  5. * Copyright (c) 2009-2011, NVIDIA Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  20. */
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/input.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/delay.h>
  26. #include <linux/io.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/of.h>
  29. #include <linux/clk.h>
  30. #include <linux/slab.h>
  31. #include <linux/input/tegra_kbc.h>
  32. #include <mach/clk.h>
  33. #define KBC_MAX_DEBOUNCE_CNT 0x3ffu
  34. /* KBC row scan time and delay for beginning the row scan. */
  35. #define KBC_ROW_SCAN_TIME 16
  36. #define KBC_ROW_SCAN_DLY 5
  37. /* KBC uses a 32KHz clock so a cycle = 1/32Khz */
  38. #define KBC_CYCLE_MS 32
  39. /* KBC Registers */
  40. /* KBC Control Register */
  41. #define KBC_CONTROL_0 0x0
  42. #define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14)
  43. #define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4)
  44. #define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3)
  45. #define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1)
  46. #define KBC_CONTROL_KBC_EN (1 << 0)
  47. /* KBC Interrupt Register */
  48. #define KBC_INT_0 0x4
  49. #define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2)
  50. #define KBC_INT_KEYPRESS_INT_STATUS (1 << 0)
  51. #define KBC_ROW_CFG0_0 0x8
  52. #define KBC_COL_CFG0_0 0x18
  53. #define KBC_TO_CNT_0 0x24
  54. #define KBC_INIT_DLY_0 0x28
  55. #define KBC_RPT_DLY_0 0x2c
  56. #define KBC_KP_ENT0_0 0x30
  57. #define KBC_KP_ENT1_0 0x34
  58. #define KBC_ROW0_MASK_0 0x38
  59. #define KBC_ROW_SHIFT 3
  60. struct tegra_kbc {
  61. void __iomem *mmio;
  62. struct input_dev *idev;
  63. unsigned int irq;
  64. spinlock_t lock;
  65. unsigned int repoll_dly;
  66. unsigned long cp_dly_jiffies;
  67. unsigned int cp_to_wkup_dly;
  68. bool use_fn_map;
  69. bool use_ghost_filter;
  70. bool keypress_caused_wake;
  71. const struct tegra_kbc_platform_data *pdata;
  72. unsigned short keycode[KBC_MAX_KEY * 2];
  73. unsigned short current_keys[KBC_MAX_KPENT];
  74. unsigned int num_pressed_keys;
  75. u32 wakeup_key;
  76. struct timer_list timer;
  77. struct clk *clk;
  78. };
  79. static const u32 tegra_kbc_default_keymap[] = {
  80. KEY(0, 2, KEY_W),
  81. KEY(0, 3, KEY_S),
  82. KEY(0, 4, KEY_A),
  83. KEY(0, 5, KEY_Z),
  84. KEY(0, 7, KEY_FN),
  85. KEY(1, 7, KEY_LEFTMETA),
  86. KEY(2, 6, KEY_RIGHTALT),
  87. KEY(2, 7, KEY_LEFTALT),
  88. KEY(3, 0, KEY_5),
  89. KEY(3, 1, KEY_4),
  90. KEY(3, 2, KEY_R),
  91. KEY(3, 3, KEY_E),
  92. KEY(3, 4, KEY_F),
  93. KEY(3, 5, KEY_D),
  94. KEY(3, 6, KEY_X),
  95. KEY(4, 0, KEY_7),
  96. KEY(4, 1, KEY_6),
  97. KEY(4, 2, KEY_T),
  98. KEY(4, 3, KEY_H),
  99. KEY(4, 4, KEY_G),
  100. KEY(4, 5, KEY_V),
  101. KEY(4, 6, KEY_C),
  102. KEY(4, 7, KEY_SPACE),
  103. KEY(5, 0, KEY_9),
  104. KEY(5, 1, KEY_8),
  105. KEY(5, 2, KEY_U),
  106. KEY(5, 3, KEY_Y),
  107. KEY(5, 4, KEY_J),
  108. KEY(5, 5, KEY_N),
  109. KEY(5, 6, KEY_B),
  110. KEY(5, 7, KEY_BACKSLASH),
  111. KEY(6, 0, KEY_MINUS),
  112. KEY(6, 1, KEY_0),
  113. KEY(6, 2, KEY_O),
  114. KEY(6, 3, KEY_I),
  115. KEY(6, 4, KEY_L),
  116. KEY(6, 5, KEY_K),
  117. KEY(6, 6, KEY_COMMA),
  118. KEY(6, 7, KEY_M),
  119. KEY(7, 1, KEY_EQUAL),
  120. KEY(7, 2, KEY_RIGHTBRACE),
  121. KEY(7, 3, KEY_ENTER),
  122. KEY(7, 7, KEY_MENU),
  123. KEY(8, 4, KEY_RIGHTSHIFT),
  124. KEY(8, 5, KEY_LEFTSHIFT),
  125. KEY(9, 5, KEY_RIGHTCTRL),
  126. KEY(9, 7, KEY_LEFTCTRL),
  127. KEY(11, 0, KEY_LEFTBRACE),
  128. KEY(11, 1, KEY_P),
  129. KEY(11, 2, KEY_APOSTROPHE),
  130. KEY(11, 3, KEY_SEMICOLON),
  131. KEY(11, 4, KEY_SLASH),
  132. KEY(11, 5, KEY_DOT),
  133. KEY(12, 0, KEY_F10),
  134. KEY(12, 1, KEY_F9),
  135. KEY(12, 2, KEY_BACKSPACE),
  136. KEY(12, 3, KEY_3),
  137. KEY(12, 4, KEY_2),
  138. KEY(12, 5, KEY_UP),
  139. KEY(12, 6, KEY_PRINT),
  140. KEY(12, 7, KEY_PAUSE),
  141. KEY(13, 0, KEY_INSERT),
  142. KEY(13, 1, KEY_DELETE),
  143. KEY(13, 3, KEY_PAGEUP),
  144. KEY(13, 4, KEY_PAGEDOWN),
  145. KEY(13, 5, KEY_RIGHT),
  146. KEY(13, 6, KEY_DOWN),
  147. KEY(13, 7, KEY_LEFT),
  148. KEY(14, 0, KEY_F11),
  149. KEY(14, 1, KEY_F12),
  150. KEY(14, 2, KEY_F8),
  151. KEY(14, 3, KEY_Q),
  152. KEY(14, 4, KEY_F4),
  153. KEY(14, 5, KEY_F3),
  154. KEY(14, 6, KEY_1),
  155. KEY(14, 7, KEY_F7),
  156. KEY(15, 0, KEY_ESC),
  157. KEY(15, 1, KEY_GRAVE),
  158. KEY(15, 2, KEY_F5),
  159. KEY(15, 3, KEY_TAB),
  160. KEY(15, 4, KEY_F1),
  161. KEY(15, 5, KEY_F2),
  162. KEY(15, 6, KEY_CAPSLOCK),
  163. KEY(15, 7, KEY_F6),
  164. /* Software Handled Function Keys */
  165. KEY(20, 0, KEY_KP7),
  166. KEY(21, 0, KEY_KP9),
  167. KEY(21, 1, KEY_KP8),
  168. KEY(21, 2, KEY_KP4),
  169. KEY(21, 4, KEY_KP1),
  170. KEY(22, 1, KEY_KPSLASH),
  171. KEY(22, 2, KEY_KP6),
  172. KEY(22, 3, KEY_KP5),
  173. KEY(22, 4, KEY_KP3),
  174. KEY(22, 5, KEY_KP2),
  175. KEY(22, 7, KEY_KP0),
  176. KEY(27, 1, KEY_KPASTERISK),
  177. KEY(27, 3, KEY_KPMINUS),
  178. KEY(27, 4, KEY_KPPLUS),
  179. KEY(27, 5, KEY_KPDOT),
  180. KEY(28, 5, KEY_VOLUMEUP),
  181. KEY(29, 3, KEY_HOME),
  182. KEY(29, 4, KEY_END),
  183. KEY(29, 5, KEY_BRIGHTNESSDOWN),
  184. KEY(29, 6, KEY_VOLUMEDOWN),
  185. KEY(29, 7, KEY_BRIGHTNESSUP),
  186. KEY(30, 0, KEY_NUMLOCK),
  187. KEY(30, 1, KEY_SCROLLLOCK),
  188. KEY(30, 2, KEY_MUTE),
  189. KEY(31, 4, KEY_HELP),
  190. };
  191. static const
  192. struct matrix_keymap_data tegra_kbc_default_keymap_data = {
  193. .keymap = tegra_kbc_default_keymap,
  194. .keymap_size = ARRAY_SIZE(tegra_kbc_default_keymap),
  195. };
  196. static void tegra_kbc_report_released_keys(struct input_dev *input,
  197. unsigned short old_keycodes[],
  198. unsigned int old_num_keys,
  199. unsigned short new_keycodes[],
  200. unsigned int new_num_keys)
  201. {
  202. unsigned int i, j;
  203. for (i = 0; i < old_num_keys; i++) {
  204. for (j = 0; j < new_num_keys; j++)
  205. if (old_keycodes[i] == new_keycodes[j])
  206. break;
  207. if (j == new_num_keys)
  208. input_report_key(input, old_keycodes[i], 0);
  209. }
  210. }
  211. static void tegra_kbc_report_pressed_keys(struct input_dev *input,
  212. unsigned char scancodes[],
  213. unsigned short keycodes[],
  214. unsigned int num_pressed_keys)
  215. {
  216. unsigned int i;
  217. for (i = 0; i < num_pressed_keys; i++) {
  218. input_event(input, EV_MSC, MSC_SCAN, scancodes[i]);
  219. input_report_key(input, keycodes[i], 1);
  220. }
  221. }
  222. static void tegra_kbc_report_keys(struct tegra_kbc *kbc)
  223. {
  224. unsigned char scancodes[KBC_MAX_KPENT];
  225. unsigned short keycodes[KBC_MAX_KPENT];
  226. u32 val = 0;
  227. unsigned int i;
  228. unsigned int num_down = 0;
  229. bool fn_keypress = false;
  230. bool key_in_same_row = false;
  231. bool key_in_same_col = false;
  232. for (i = 0; i < KBC_MAX_KPENT; i++) {
  233. if ((i % 4) == 0)
  234. val = readl(kbc->mmio + KBC_KP_ENT0_0 + i);
  235. if (val & 0x80) {
  236. unsigned int col = val & 0x07;
  237. unsigned int row = (val >> 3) & 0x0f;
  238. unsigned char scancode =
  239. MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT);
  240. scancodes[num_down] = scancode;
  241. keycodes[num_down] = kbc->keycode[scancode];
  242. /* If driver uses Fn map, do not report the Fn key. */
  243. if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map)
  244. fn_keypress = true;
  245. else
  246. num_down++;
  247. }
  248. val >>= 8;
  249. }
  250. /*
  251. * Matrix keyboard designs are prone to keyboard ghosting.
  252. * Ghosting occurs if there are 3 keys such that -
  253. * any 2 of the 3 keys share a row, and any 2 of them share a column.
  254. * If so ignore the key presses for this iteration.
  255. */
  256. if (kbc->use_ghost_filter && num_down >= 3) {
  257. for (i = 0; i < num_down; i++) {
  258. unsigned int j;
  259. u8 curr_col = scancodes[i] & 0x07;
  260. u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
  261. /*
  262. * Find 2 keys such that one key is in the same row
  263. * and the other is in the same column as the i-th key.
  264. */
  265. for (j = i + 1; j < num_down; j++) {
  266. u8 col = scancodes[j] & 0x07;
  267. u8 row = scancodes[j] >> KBC_ROW_SHIFT;
  268. if (col == curr_col)
  269. key_in_same_col = true;
  270. if (row == curr_row)
  271. key_in_same_row = true;
  272. }
  273. }
  274. }
  275. /*
  276. * If the platform uses Fn keymaps, translate keys on a Fn keypress.
  277. * Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
  278. */
  279. if (fn_keypress) {
  280. for (i = 0; i < num_down; i++) {
  281. scancodes[i] += KBC_MAX_KEY;
  282. keycodes[i] = kbc->keycode[scancodes[i]];
  283. }
  284. }
  285. /* Ignore the key presses for this iteration? */
  286. if (key_in_same_col && key_in_same_row)
  287. return;
  288. tegra_kbc_report_released_keys(kbc->idev,
  289. kbc->current_keys, kbc->num_pressed_keys,
  290. keycodes, num_down);
  291. tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down);
  292. input_sync(kbc->idev);
  293. memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys));
  294. kbc->num_pressed_keys = num_down;
  295. }
  296. static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable)
  297. {
  298. u32 val;
  299. val = readl(kbc->mmio + KBC_CONTROL_0);
  300. if (enable)
  301. val |= KBC_CONTROL_FIFO_CNT_INT_EN;
  302. else
  303. val &= ~KBC_CONTROL_FIFO_CNT_INT_EN;
  304. writel(val, kbc->mmio + KBC_CONTROL_0);
  305. }
  306. static void tegra_kbc_keypress_timer(unsigned long data)
  307. {
  308. struct tegra_kbc *kbc = (struct tegra_kbc *)data;
  309. unsigned long flags;
  310. u32 val;
  311. unsigned int i;
  312. spin_lock_irqsave(&kbc->lock, flags);
  313. val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
  314. if (val) {
  315. unsigned long dly;
  316. tegra_kbc_report_keys(kbc);
  317. /*
  318. * If more than one keys are pressed we need not wait
  319. * for the repoll delay.
  320. */
  321. dly = (val == 1) ? kbc->repoll_dly : 1;
  322. mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly));
  323. } else {
  324. /* Release any pressed keys and exit the polling loop */
  325. for (i = 0; i < kbc->num_pressed_keys; i++)
  326. input_report_key(kbc->idev, kbc->current_keys[i], 0);
  327. input_sync(kbc->idev);
  328. kbc->num_pressed_keys = 0;
  329. /* All keys are released so enable the keypress interrupt */
  330. tegra_kbc_set_fifo_interrupt(kbc, true);
  331. }
  332. spin_unlock_irqrestore(&kbc->lock, flags);
  333. }
  334. static irqreturn_t tegra_kbc_isr(int irq, void *args)
  335. {
  336. struct tegra_kbc *kbc = args;
  337. unsigned long flags;
  338. u32 val;
  339. spin_lock_irqsave(&kbc->lock, flags);
  340. /*
  341. * Quickly bail out & reenable interrupts if the fifo threshold
  342. * count interrupt wasn't the interrupt source
  343. */
  344. val = readl(kbc->mmio + KBC_INT_0);
  345. writel(val, kbc->mmio + KBC_INT_0);
  346. if (val & KBC_INT_FIFO_CNT_INT_STATUS) {
  347. /*
  348. * Until all keys are released, defer further processing to
  349. * the polling loop in tegra_kbc_keypress_timer.
  350. */
  351. tegra_kbc_set_fifo_interrupt(kbc, false);
  352. mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies);
  353. } else if (val & KBC_INT_KEYPRESS_INT_STATUS) {
  354. /* We can be here only through system resume path */
  355. kbc->keypress_caused_wake = true;
  356. }
  357. spin_unlock_irqrestore(&kbc->lock, flags);
  358. return IRQ_HANDLED;
  359. }
  360. static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
  361. {
  362. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  363. int i;
  364. unsigned int rst_val;
  365. /* Either mask all keys or none. */
  366. rst_val = (filter && !pdata->wakeup) ? ~0 : 0;
  367. for (i = 0; i < KBC_MAX_ROW; i++)
  368. writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
  369. }
  370. static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
  371. {
  372. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  373. int i;
  374. for (i = 0; i < KBC_MAX_GPIO; i++) {
  375. u32 r_shft = 5 * (i % 6);
  376. u32 c_shft = 4 * (i % 8);
  377. u32 r_mask = 0x1f << r_shft;
  378. u32 c_mask = 0x0f << c_shft;
  379. u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0;
  380. u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0;
  381. u32 row_cfg = readl(kbc->mmio + r_offs);
  382. u32 col_cfg = readl(kbc->mmio + c_offs);
  383. row_cfg &= ~r_mask;
  384. col_cfg &= ~c_mask;
  385. switch (pdata->pin_cfg[i].type) {
  386. case PIN_CFG_ROW:
  387. row_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << r_shft;
  388. break;
  389. case PIN_CFG_COL:
  390. col_cfg |= ((pdata->pin_cfg[i].num << 1) | 1) << c_shft;
  391. break;
  392. case PIN_CFG_IGNORE:
  393. break;
  394. }
  395. writel(row_cfg, kbc->mmio + r_offs);
  396. writel(col_cfg, kbc->mmio + c_offs);
  397. }
  398. }
  399. static int tegra_kbc_start(struct tegra_kbc *kbc)
  400. {
  401. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  402. unsigned int debounce_cnt;
  403. u32 val = 0;
  404. clk_prepare_enable(kbc->clk);
  405. /* Reset the KBC controller to clear all previous status.*/
  406. tegra_periph_reset_assert(kbc->clk);
  407. udelay(100);
  408. tegra_periph_reset_deassert(kbc->clk);
  409. udelay(100);
  410. tegra_kbc_config_pins(kbc);
  411. tegra_kbc_setup_wakekeys(kbc, false);
  412. writel(pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
  413. /* Keyboard debounce count is maximum of 12 bits. */
  414. debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
  415. val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt);
  416. val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */
  417. val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */
  418. val |= KBC_CONTROL_KBC_EN; /* enable */
  419. writel(val, kbc->mmio + KBC_CONTROL_0);
  420. /*
  421. * Compute the delay(ns) from interrupt mode to continuous polling
  422. * mode so the timer routine is scheduled appropriately.
  423. */
  424. val = readl(kbc->mmio + KBC_INIT_DLY_0);
  425. kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32);
  426. kbc->num_pressed_keys = 0;
  427. /*
  428. * Atomically clear out any remaining entries in the key FIFO
  429. * and enable keyboard interrupts.
  430. */
  431. while (1) {
  432. val = readl(kbc->mmio + KBC_INT_0);
  433. val >>= 4;
  434. if (!val)
  435. break;
  436. val = readl(kbc->mmio + KBC_KP_ENT0_0);
  437. val = readl(kbc->mmio + KBC_KP_ENT1_0);
  438. }
  439. writel(0x7, kbc->mmio + KBC_INT_0);
  440. enable_irq(kbc->irq);
  441. return 0;
  442. }
  443. static void tegra_kbc_stop(struct tegra_kbc *kbc)
  444. {
  445. unsigned long flags;
  446. u32 val;
  447. spin_lock_irqsave(&kbc->lock, flags);
  448. val = readl(kbc->mmio + KBC_CONTROL_0);
  449. val &= ~1;
  450. writel(val, kbc->mmio + KBC_CONTROL_0);
  451. spin_unlock_irqrestore(&kbc->lock, flags);
  452. disable_irq(kbc->irq);
  453. del_timer_sync(&kbc->timer);
  454. clk_disable_unprepare(kbc->clk);
  455. }
  456. static int tegra_kbc_open(struct input_dev *dev)
  457. {
  458. struct tegra_kbc *kbc = input_get_drvdata(dev);
  459. return tegra_kbc_start(kbc);
  460. }
  461. static void tegra_kbc_close(struct input_dev *dev)
  462. {
  463. struct tegra_kbc *kbc = input_get_drvdata(dev);
  464. return tegra_kbc_stop(kbc);
  465. }
  466. static bool
  467. tegra_kbc_check_pin_cfg(const struct tegra_kbc_platform_data *pdata,
  468. struct device *dev, unsigned int *num_rows)
  469. {
  470. int i;
  471. *num_rows = 0;
  472. for (i = 0; i < KBC_MAX_GPIO; i++) {
  473. const struct tegra_kbc_pin_cfg *pin_cfg = &pdata->pin_cfg[i];
  474. switch (pin_cfg->type) {
  475. case PIN_CFG_ROW:
  476. if (pin_cfg->num >= KBC_MAX_ROW) {
  477. dev_err(dev,
  478. "pin_cfg[%d]: invalid row number %d\n",
  479. i, pin_cfg->num);
  480. return false;
  481. }
  482. (*num_rows)++;
  483. break;
  484. case PIN_CFG_COL:
  485. if (pin_cfg->num >= KBC_MAX_COL) {
  486. dev_err(dev,
  487. "pin_cfg[%d]: invalid column number %d\n",
  488. i, pin_cfg->num);
  489. return false;
  490. }
  491. break;
  492. case PIN_CFG_IGNORE:
  493. break;
  494. default:
  495. dev_err(dev,
  496. "pin_cfg[%d]: invalid entry type %d\n",
  497. pin_cfg->type, pin_cfg->num);
  498. return false;
  499. }
  500. }
  501. return true;
  502. }
  503. #ifdef CONFIG_OF
  504. static struct tegra_kbc_platform_data *tegra_kbc_dt_parse_pdata(
  505. struct platform_device *pdev)
  506. {
  507. struct tegra_kbc_platform_data *pdata;
  508. struct device_node *np = pdev->dev.of_node;
  509. u32 prop;
  510. int i;
  511. if (!np)
  512. return NULL;
  513. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  514. if (!pdata)
  515. return NULL;
  516. if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop))
  517. pdata->debounce_cnt = prop;
  518. if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop))
  519. pdata->repeat_cnt = prop;
  520. if (of_find_property(np, "nvidia,needs-ghost-filter", NULL))
  521. pdata->use_ghost_filter = true;
  522. if (of_find_property(np, "nvidia,wakeup-source", NULL))
  523. pdata->wakeup = true;
  524. /*
  525. * All currently known keymaps with device tree support use the same
  526. * pin_cfg, so set it up here.
  527. */
  528. for (i = 0; i < KBC_MAX_ROW; i++) {
  529. pdata->pin_cfg[i].num = i;
  530. pdata->pin_cfg[i].type = PIN_CFG_ROW;
  531. }
  532. for (i = 0; i < KBC_MAX_COL; i++) {
  533. pdata->pin_cfg[KBC_MAX_ROW + i].num = i;
  534. pdata->pin_cfg[KBC_MAX_ROW + i].type = PIN_CFG_COL;
  535. }
  536. return pdata;
  537. }
  538. #else
  539. static inline struct tegra_kbc_platform_data *tegra_kbc_dt_parse_pdata(
  540. struct platform_device *pdev)
  541. {
  542. return NULL;
  543. }
  544. #endif
  545. static int tegra_kbd_setup_keymap(struct tegra_kbc *kbc)
  546. {
  547. const struct tegra_kbc_platform_data *pdata = kbc->pdata;
  548. const struct matrix_keymap_data *keymap_data = pdata->keymap_data;
  549. unsigned int keymap_rows = KBC_MAX_KEY;
  550. int retval;
  551. if (keymap_data && pdata->use_fn_map)
  552. keymap_rows *= 2;
  553. retval = matrix_keypad_build_keymap(keymap_data, NULL,
  554. keymap_rows, KBC_MAX_COL,
  555. kbc->keycode, kbc->idev);
  556. if (retval == -ENOSYS || retval == -ENOENT) {
  557. /*
  558. * If there is no OF support in kernel or keymap
  559. * property is missing, use default keymap.
  560. */
  561. retval = matrix_keypad_build_keymap(
  562. &tegra_kbc_default_keymap_data, NULL,
  563. keymap_rows, KBC_MAX_COL,
  564. kbc->keycode, kbc->idev);
  565. }
  566. return retval;
  567. }
  568. static int tegra_kbc_probe(struct platform_device *pdev)
  569. {
  570. const struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
  571. struct tegra_kbc *kbc;
  572. struct input_dev *input_dev;
  573. struct resource *res;
  574. int irq;
  575. int err;
  576. int num_rows = 0;
  577. unsigned int debounce_cnt;
  578. unsigned int scan_time_rows;
  579. if (!pdata)
  580. pdata = tegra_kbc_dt_parse_pdata(pdev);
  581. if (!pdata)
  582. return -EINVAL;
  583. if (!tegra_kbc_check_pin_cfg(pdata, &pdev->dev, &num_rows)) {
  584. err = -EINVAL;
  585. goto err_free_pdata;
  586. }
  587. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  588. if (!res) {
  589. dev_err(&pdev->dev, "failed to get I/O memory\n");
  590. err = -ENXIO;
  591. goto err_free_pdata;
  592. }
  593. irq = platform_get_irq(pdev, 0);
  594. if (irq < 0) {
  595. dev_err(&pdev->dev, "failed to get keyboard IRQ\n");
  596. err = -ENXIO;
  597. goto err_free_pdata;
  598. }
  599. kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
  600. input_dev = input_allocate_device();
  601. if (!kbc || !input_dev) {
  602. err = -ENOMEM;
  603. goto err_free_mem;
  604. }
  605. kbc->pdata = pdata;
  606. kbc->idev = input_dev;
  607. kbc->irq = irq;
  608. spin_lock_init(&kbc->lock);
  609. setup_timer(&kbc->timer, tegra_kbc_keypress_timer, (unsigned long)kbc);
  610. res = request_mem_region(res->start, resource_size(res), pdev->name);
  611. if (!res) {
  612. dev_err(&pdev->dev, "failed to request I/O memory\n");
  613. err = -EBUSY;
  614. goto err_free_mem;
  615. }
  616. kbc->mmio = ioremap(res->start, resource_size(res));
  617. if (!kbc->mmio) {
  618. dev_err(&pdev->dev, "failed to remap I/O memory\n");
  619. err = -ENXIO;
  620. goto err_free_mem_region;
  621. }
  622. kbc->clk = clk_get(&pdev->dev, NULL);
  623. if (IS_ERR(kbc->clk)) {
  624. dev_err(&pdev->dev, "failed to get keyboard clock\n");
  625. err = PTR_ERR(kbc->clk);
  626. goto err_iounmap;
  627. }
  628. /*
  629. * The time delay between two consecutive reads of the FIFO is
  630. * the sum of the repeat time and the time taken for scanning
  631. * the rows. There is an additional delay before the row scanning
  632. * starts. The repoll delay is computed in milliseconds.
  633. */
  634. debounce_cnt = min(pdata->debounce_cnt, KBC_MAX_DEBOUNCE_CNT);
  635. scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows;
  636. kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + pdata->repeat_cnt;
  637. kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS);
  638. kbc->wakeup_key = pdata->wakeup_key;
  639. kbc->use_fn_map = pdata->use_fn_map;
  640. kbc->use_ghost_filter = pdata->use_ghost_filter;
  641. input_dev->name = pdev->name;
  642. input_dev->id.bustype = BUS_HOST;
  643. input_dev->dev.parent = &pdev->dev;
  644. input_dev->open = tegra_kbc_open;
  645. input_dev->close = tegra_kbc_close;
  646. err = tegra_kbd_setup_keymap(kbc);
  647. if (err) {
  648. dev_err(&pdev->dev, "failed to setup keymap\n");
  649. goto err_put_clk;
  650. }
  651. __set_bit(EV_REP, input_dev->evbit);
  652. input_set_capability(input_dev, EV_MSC, MSC_SCAN);
  653. input_set_drvdata(input_dev, kbc);
  654. err = request_irq(kbc->irq, tegra_kbc_isr,
  655. IRQF_NO_SUSPEND | IRQF_TRIGGER_HIGH, pdev->name, kbc);
  656. if (err) {
  657. dev_err(&pdev->dev, "failed to request keyboard IRQ\n");
  658. goto err_put_clk;
  659. }
  660. disable_irq(kbc->irq);
  661. err = input_register_device(kbc->idev);
  662. if (err) {
  663. dev_err(&pdev->dev, "failed to register input device\n");
  664. goto err_free_irq;
  665. }
  666. platform_set_drvdata(pdev, kbc);
  667. device_init_wakeup(&pdev->dev, pdata->wakeup);
  668. return 0;
  669. err_free_irq:
  670. free_irq(kbc->irq, pdev);
  671. err_put_clk:
  672. clk_put(kbc->clk);
  673. err_iounmap:
  674. iounmap(kbc->mmio);
  675. err_free_mem_region:
  676. release_mem_region(res->start, resource_size(res));
  677. err_free_mem:
  678. input_free_device(input_dev);
  679. kfree(kbc);
  680. err_free_pdata:
  681. if (!pdev->dev.platform_data)
  682. kfree(pdata);
  683. return err;
  684. }
  685. static int tegra_kbc_remove(struct platform_device *pdev)
  686. {
  687. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  688. struct resource *res;
  689. platform_set_drvdata(pdev, NULL);
  690. free_irq(kbc->irq, pdev);
  691. clk_put(kbc->clk);
  692. input_unregister_device(kbc->idev);
  693. iounmap(kbc->mmio);
  694. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  695. release_mem_region(res->start, resource_size(res));
  696. /*
  697. * If we do not have platform data attached to the device we
  698. * allocated it ourselves and thus need to free it.
  699. */
  700. if (!pdev->dev.platform_data)
  701. kfree(kbc->pdata);
  702. kfree(kbc);
  703. return 0;
  704. }
  705. #ifdef CONFIG_PM_SLEEP
  706. static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable)
  707. {
  708. u32 val;
  709. val = readl(kbc->mmio + KBC_CONTROL_0);
  710. if (enable)
  711. val |= KBC_CONTROL_KEYPRESS_INT_EN;
  712. else
  713. val &= ~KBC_CONTROL_KEYPRESS_INT_EN;
  714. writel(val, kbc->mmio + KBC_CONTROL_0);
  715. }
  716. static int tegra_kbc_suspend(struct device *dev)
  717. {
  718. struct platform_device *pdev = to_platform_device(dev);
  719. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  720. mutex_lock(&kbc->idev->mutex);
  721. if (device_may_wakeup(&pdev->dev)) {
  722. disable_irq(kbc->irq);
  723. del_timer_sync(&kbc->timer);
  724. tegra_kbc_set_fifo_interrupt(kbc, false);
  725. /* Forcefully clear the interrupt status */
  726. writel(0x7, kbc->mmio + KBC_INT_0);
  727. /*
  728. * Store the previous resident time of continuous polling mode.
  729. * Force the keyboard into interrupt mode.
  730. */
  731. kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0);
  732. writel(0, kbc->mmio + KBC_TO_CNT_0);
  733. tegra_kbc_setup_wakekeys(kbc, true);
  734. msleep(30);
  735. kbc->keypress_caused_wake = false;
  736. /* Enable keypress interrupt before going into suspend. */
  737. tegra_kbc_set_keypress_interrupt(kbc, true);
  738. enable_irq(kbc->irq);
  739. enable_irq_wake(kbc->irq);
  740. } else {
  741. if (kbc->idev->users)
  742. tegra_kbc_stop(kbc);
  743. }
  744. mutex_unlock(&kbc->idev->mutex);
  745. return 0;
  746. }
  747. static int tegra_kbc_resume(struct device *dev)
  748. {
  749. struct platform_device *pdev = to_platform_device(dev);
  750. struct tegra_kbc *kbc = platform_get_drvdata(pdev);
  751. int err = 0;
  752. mutex_lock(&kbc->idev->mutex);
  753. if (device_may_wakeup(&pdev->dev)) {
  754. disable_irq_wake(kbc->irq);
  755. tegra_kbc_setup_wakekeys(kbc, false);
  756. /* We will use fifo interrupts for key detection. */
  757. tegra_kbc_set_keypress_interrupt(kbc, false);
  758. /* Restore the resident time of continuous polling mode. */
  759. writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0);
  760. tegra_kbc_set_fifo_interrupt(kbc, true);
  761. if (kbc->keypress_caused_wake && kbc->wakeup_key) {
  762. /*
  763. * We can't report events directly from the ISR
  764. * because timekeeping is stopped when processing
  765. * wakeup request and we get a nasty warning when
  766. * we try to call do_gettimeofday() in evdev
  767. * handler.
  768. */
  769. input_report_key(kbc->idev, kbc->wakeup_key, 1);
  770. input_sync(kbc->idev);
  771. input_report_key(kbc->idev, kbc->wakeup_key, 0);
  772. input_sync(kbc->idev);
  773. }
  774. } else {
  775. if (kbc->idev->users)
  776. err = tegra_kbc_start(kbc);
  777. }
  778. mutex_unlock(&kbc->idev->mutex);
  779. return err;
  780. }
  781. #endif
  782. static SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, tegra_kbc_suspend, tegra_kbc_resume);
  783. static const struct of_device_id tegra_kbc_of_match[] = {
  784. { .compatible = "nvidia,tegra20-kbc", },
  785. { },
  786. };
  787. MODULE_DEVICE_TABLE(of, tegra_kbc_of_match);
  788. static struct platform_driver tegra_kbc_driver = {
  789. .probe = tegra_kbc_probe,
  790. .remove = tegra_kbc_remove,
  791. .driver = {
  792. .name = "tegra-kbc",
  793. .owner = THIS_MODULE,
  794. .pm = &tegra_kbc_pm_ops,
  795. .of_match_table = tegra_kbc_of_match,
  796. },
  797. };
  798. module_platform_driver(tegra_kbc_driver);
  799. MODULE_LICENSE("GPL");
  800. MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>");
  801. MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
  802. MODULE_ALIAS("platform:tegra-kbc");