lpfc_sli.c 82 KB

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  1. /*******************************************************************
  2. * This file is part of the Emulex Linux Device Driver for *
  3. * Fibre Channel Host Bus Adapters. *
  4. * Copyright (C) 2004-2006 Emulex. All rights reserved. *
  5. * EMULEX and SLI are trademarks of Emulex. *
  6. * www.emulex.com *
  7. * Portions Copyright (C) 2004-2005 Christoph Hellwig *
  8. * *
  9. * This program is free software; you can redistribute it and/or *
  10. * modify it under the terms of version 2 of the GNU General *
  11. * Public License as published by the Free Software Foundation. *
  12. * This program is distributed in the hope that it will be useful. *
  13. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  14. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  15. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  16. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  17. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  18. * more details, a copy of which can be found in the file COPYING *
  19. * included with this package. *
  20. *******************************************************************/
  21. #include <linux/blkdev.h>
  22. #include <linux/pci.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <scsi/scsi.h>
  26. #include <scsi/scsi_cmnd.h>
  27. #include <scsi/scsi_device.h>
  28. #include <scsi/scsi_host.h>
  29. #include <scsi/scsi_transport_fc.h>
  30. #include "lpfc_hw.h"
  31. #include "lpfc_sli.h"
  32. #include "lpfc_disc.h"
  33. #include "lpfc_scsi.h"
  34. #include "lpfc.h"
  35. #include "lpfc_crtn.h"
  36. #include "lpfc_logmsg.h"
  37. #include "lpfc_compat.h"
  38. /*
  39. * Define macro to log: Mailbox command x%x cannot issue Data
  40. * This allows multiple uses of lpfc_msgBlk0311
  41. * w/o perturbing log msg utility.
  42. */
  43. #define LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag) \
  44. lpfc_printf_log(phba, \
  45. KERN_INFO, \
  46. LOG_MBOX | LOG_SLI, \
  47. "%d:0311 Mailbox command x%x cannot issue " \
  48. "Data: x%x x%x x%x\n", \
  49. phba->brd_no, \
  50. mb->mbxCommand, \
  51. phba->hba_state, \
  52. psli->sli_flag, \
  53. flag);
  54. /* There are only four IOCB completion types. */
  55. typedef enum _lpfc_iocb_type {
  56. LPFC_UNKNOWN_IOCB,
  57. LPFC_UNSOL_IOCB,
  58. LPFC_SOL_IOCB,
  59. LPFC_ABORT_IOCB
  60. } lpfc_iocb_type;
  61. struct lpfc_iocbq *
  62. lpfc_sli_get_iocbq(struct lpfc_hba * phba)
  63. {
  64. struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
  65. struct lpfc_iocbq * iocbq = NULL;
  66. list_remove_head(lpfc_iocb_list, iocbq, struct lpfc_iocbq, list);
  67. return iocbq;
  68. }
  69. void
  70. lpfc_sli_release_iocbq(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
  71. {
  72. size_t start_clean = (size_t)(&((struct lpfc_iocbq *)NULL)->iocb);
  73. /*
  74. * Clean all volatile data fields, preserve iotag and node struct.
  75. */
  76. memset((char*)iocbq + start_clean, 0, sizeof(*iocbq) - start_clean);
  77. list_add_tail(&iocbq->list, &phba->lpfc_iocb_list);
  78. }
  79. /*
  80. * Translate the iocb command to an iocb command type used to decide the final
  81. * disposition of each completed IOCB.
  82. */
  83. static lpfc_iocb_type
  84. lpfc_sli_iocb_cmd_type(uint8_t iocb_cmnd)
  85. {
  86. lpfc_iocb_type type = LPFC_UNKNOWN_IOCB;
  87. if (iocb_cmnd > CMD_MAX_IOCB_CMD)
  88. return 0;
  89. switch (iocb_cmnd) {
  90. case CMD_XMIT_SEQUENCE_CR:
  91. case CMD_XMIT_SEQUENCE_CX:
  92. case CMD_XMIT_BCAST_CN:
  93. case CMD_XMIT_BCAST_CX:
  94. case CMD_ELS_REQUEST_CR:
  95. case CMD_ELS_REQUEST_CX:
  96. case CMD_CREATE_XRI_CR:
  97. case CMD_CREATE_XRI_CX:
  98. case CMD_GET_RPI_CN:
  99. case CMD_XMIT_ELS_RSP_CX:
  100. case CMD_GET_RPI_CR:
  101. case CMD_FCP_IWRITE_CR:
  102. case CMD_FCP_IWRITE_CX:
  103. case CMD_FCP_IREAD_CR:
  104. case CMD_FCP_IREAD_CX:
  105. case CMD_FCP_ICMND_CR:
  106. case CMD_FCP_ICMND_CX:
  107. case CMD_ADAPTER_MSG:
  108. case CMD_ADAPTER_DUMP:
  109. case CMD_XMIT_SEQUENCE64_CR:
  110. case CMD_XMIT_SEQUENCE64_CX:
  111. case CMD_XMIT_BCAST64_CN:
  112. case CMD_XMIT_BCAST64_CX:
  113. case CMD_ELS_REQUEST64_CR:
  114. case CMD_ELS_REQUEST64_CX:
  115. case CMD_FCP_IWRITE64_CR:
  116. case CMD_FCP_IWRITE64_CX:
  117. case CMD_FCP_IREAD64_CR:
  118. case CMD_FCP_IREAD64_CX:
  119. case CMD_FCP_ICMND64_CR:
  120. case CMD_FCP_ICMND64_CX:
  121. case CMD_GEN_REQUEST64_CR:
  122. case CMD_GEN_REQUEST64_CX:
  123. case CMD_XMIT_ELS_RSP64_CX:
  124. type = LPFC_SOL_IOCB;
  125. break;
  126. case CMD_ABORT_XRI_CN:
  127. case CMD_ABORT_XRI_CX:
  128. case CMD_CLOSE_XRI_CN:
  129. case CMD_CLOSE_XRI_CX:
  130. case CMD_XRI_ABORTED_CX:
  131. case CMD_ABORT_MXRI64_CN:
  132. type = LPFC_ABORT_IOCB;
  133. break;
  134. case CMD_RCV_SEQUENCE_CX:
  135. case CMD_RCV_ELS_REQ_CX:
  136. case CMD_RCV_SEQUENCE64_CX:
  137. case CMD_RCV_ELS_REQ64_CX:
  138. type = LPFC_UNSOL_IOCB;
  139. break;
  140. default:
  141. type = LPFC_UNKNOWN_IOCB;
  142. break;
  143. }
  144. return type;
  145. }
  146. static int
  147. lpfc_sli_ring_map(struct lpfc_hba * phba, LPFC_MBOXQ_t *pmb)
  148. {
  149. struct lpfc_sli *psli = &phba->sli;
  150. MAILBOX_t *pmbox = &pmb->mb;
  151. int i, rc;
  152. for (i = 0; i < psli->num_rings; i++) {
  153. phba->hba_state = LPFC_INIT_MBX_CMDS;
  154. lpfc_config_ring(phba, i, pmb);
  155. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
  156. if (rc != MBX_SUCCESS) {
  157. lpfc_printf_log(phba,
  158. KERN_ERR,
  159. LOG_INIT,
  160. "%d:0446 Adapter failed to init, "
  161. "mbxCmd x%x CFG_RING, mbxStatus x%x, "
  162. "ring %d\n",
  163. phba->brd_no,
  164. pmbox->mbxCommand,
  165. pmbox->mbxStatus,
  166. i);
  167. phba->hba_state = LPFC_HBA_ERROR;
  168. return -ENXIO;
  169. }
  170. }
  171. return 0;
  172. }
  173. static int
  174. lpfc_sli_ringtxcmpl_put(struct lpfc_hba * phba,
  175. struct lpfc_sli_ring * pring, struct lpfc_iocbq * piocb)
  176. {
  177. list_add_tail(&piocb->list, &pring->txcmplq);
  178. pring->txcmplq_cnt++;
  179. if (unlikely(pring->ringno == LPFC_ELS_RING))
  180. mod_timer(&phba->els_tmofunc,
  181. jiffies + HZ * (phba->fc_ratov << 1));
  182. return (0);
  183. }
  184. static struct lpfc_iocbq *
  185. lpfc_sli_ringtx_get(struct lpfc_hba * phba, struct lpfc_sli_ring * pring)
  186. {
  187. struct list_head *dlp;
  188. struct lpfc_iocbq *cmd_iocb;
  189. dlp = &pring->txq;
  190. cmd_iocb = NULL;
  191. list_remove_head((&pring->txq), cmd_iocb,
  192. struct lpfc_iocbq,
  193. list);
  194. if (cmd_iocb) {
  195. /* If the first ptr is not equal to the list header,
  196. * deque the IOCBQ_t and return it.
  197. */
  198. pring->txq_cnt--;
  199. }
  200. return (cmd_iocb);
  201. }
  202. static IOCB_t *
  203. lpfc_sli_next_iocb_slot (struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
  204. {
  205. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  206. uint32_t max_cmd_idx = pring->numCiocb;
  207. IOCB_t *iocb = NULL;
  208. if ((pring->next_cmdidx == pring->cmdidx) &&
  209. (++pring->next_cmdidx >= max_cmd_idx))
  210. pring->next_cmdidx = 0;
  211. if (unlikely(pring->local_getidx == pring->next_cmdidx)) {
  212. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  213. if (unlikely(pring->local_getidx >= max_cmd_idx)) {
  214. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  215. "%d:0315 Ring %d issue: portCmdGet %d "
  216. "is bigger then cmd ring %d\n",
  217. phba->brd_no, pring->ringno,
  218. pring->local_getidx, max_cmd_idx);
  219. phba->hba_state = LPFC_HBA_ERROR;
  220. /*
  221. * All error attention handlers are posted to
  222. * worker thread
  223. */
  224. phba->work_ha |= HA_ERATT;
  225. phba->work_hs = HS_FFER3;
  226. if (phba->work_wait)
  227. wake_up(phba->work_wait);
  228. return NULL;
  229. }
  230. if (pring->local_getidx == pring->next_cmdidx)
  231. return NULL;
  232. }
  233. iocb = IOCB_ENTRY(pring->cmdringaddr, pring->cmdidx);
  234. return iocb;
  235. }
  236. uint16_t
  237. lpfc_sli_next_iotag(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
  238. {
  239. struct lpfc_iocbq ** new_arr;
  240. struct lpfc_iocbq ** old_arr;
  241. size_t new_len;
  242. struct lpfc_sli *psli = &phba->sli;
  243. uint16_t iotag;
  244. spin_lock_irq(phba->host->host_lock);
  245. iotag = psli->last_iotag;
  246. if(++iotag < psli->iocbq_lookup_len) {
  247. psli->last_iotag = iotag;
  248. psli->iocbq_lookup[iotag] = iocbq;
  249. spin_unlock_irq(phba->host->host_lock);
  250. iocbq->iotag = iotag;
  251. return iotag;
  252. }
  253. else if (psli->iocbq_lookup_len < (0xffff
  254. - LPFC_IOCBQ_LOOKUP_INCREMENT)) {
  255. new_len = psli->iocbq_lookup_len + LPFC_IOCBQ_LOOKUP_INCREMENT;
  256. spin_unlock_irq(phba->host->host_lock);
  257. new_arr = kmalloc(new_len * sizeof (struct lpfc_iocbq *),
  258. GFP_KERNEL);
  259. if (new_arr) {
  260. memset((char *)new_arr, 0,
  261. new_len * sizeof (struct lpfc_iocbq *));
  262. spin_lock_irq(phba->host->host_lock);
  263. old_arr = psli->iocbq_lookup;
  264. if (new_len <= psli->iocbq_lookup_len) {
  265. /* highly unprobable case */
  266. kfree(new_arr);
  267. iotag = psli->last_iotag;
  268. if(++iotag < psli->iocbq_lookup_len) {
  269. psli->last_iotag = iotag;
  270. psli->iocbq_lookup[iotag] = iocbq;
  271. spin_unlock_irq(phba->host->host_lock);
  272. iocbq->iotag = iotag;
  273. return iotag;
  274. }
  275. spin_unlock_irq(phba->host->host_lock);
  276. return 0;
  277. }
  278. if (psli->iocbq_lookup)
  279. memcpy(new_arr, old_arr,
  280. ((psli->last_iotag + 1) *
  281. sizeof (struct lpfc_iocbq *)));
  282. psli->iocbq_lookup = new_arr;
  283. psli->iocbq_lookup_len = new_len;
  284. psli->last_iotag = iotag;
  285. psli->iocbq_lookup[iotag] = iocbq;
  286. spin_unlock_irq(phba->host->host_lock);
  287. iocbq->iotag = iotag;
  288. kfree(old_arr);
  289. return iotag;
  290. }
  291. }
  292. lpfc_printf_log(phba, KERN_ERR,LOG_SLI,
  293. "%d:0318 Failed to allocate IOTAG.last IOTAG is %d\n",
  294. phba->brd_no, psli->last_iotag);
  295. return 0;
  296. }
  297. static void
  298. lpfc_sli_submit_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  299. IOCB_t *iocb, struct lpfc_iocbq *nextiocb)
  300. {
  301. /*
  302. * Set up an iotag
  303. */
  304. nextiocb->iocb.ulpIoTag = (nextiocb->iocb_cmpl) ? nextiocb->iotag : 0;
  305. /*
  306. * Issue iocb command to adapter
  307. */
  308. lpfc_sli_pcimem_bcopy(&nextiocb->iocb, iocb, sizeof (IOCB_t));
  309. wmb();
  310. pring->stats.iocb_cmd++;
  311. /*
  312. * If there is no completion routine to call, we can release the
  313. * IOCB buffer back right now. For IOCBs, like QUE_RING_BUF,
  314. * that have no rsp ring completion, iocb_cmpl MUST be NULL.
  315. */
  316. if (nextiocb->iocb_cmpl)
  317. lpfc_sli_ringtxcmpl_put(phba, pring, nextiocb);
  318. else
  319. lpfc_sli_release_iocbq(phba, nextiocb);
  320. /*
  321. * Let the HBA know what IOCB slot will be the next one the
  322. * driver will put a command into.
  323. */
  324. pring->cmdidx = pring->next_cmdidx;
  325. writel(pring->cmdidx, phba->MBslimaddr
  326. + (SLIMOFF + (pring->ringno * 2)) * 4);
  327. }
  328. static void
  329. lpfc_sli_update_full_ring(struct lpfc_hba * phba,
  330. struct lpfc_sli_ring *pring)
  331. {
  332. int ringno = pring->ringno;
  333. pring->flag |= LPFC_CALL_RING_AVAILABLE;
  334. wmb();
  335. /*
  336. * Set ring 'ringno' to SET R0CE_REQ in Chip Att register.
  337. * The HBA will tell us when an IOCB entry is available.
  338. */
  339. writel((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr);
  340. readl(phba->CAregaddr); /* flush */
  341. pring->stats.iocb_cmd_full++;
  342. }
  343. static void
  344. lpfc_sli_update_ring(struct lpfc_hba * phba,
  345. struct lpfc_sli_ring *pring)
  346. {
  347. int ringno = pring->ringno;
  348. /*
  349. * Tell the HBA that there is work to do in this ring.
  350. */
  351. wmb();
  352. writel(CA_R0ATT << (ringno * 4), phba->CAregaddr);
  353. readl(phba->CAregaddr); /* flush */
  354. }
  355. static void
  356. lpfc_sli_resume_iocb(struct lpfc_hba * phba, struct lpfc_sli_ring * pring)
  357. {
  358. IOCB_t *iocb;
  359. struct lpfc_iocbq *nextiocb;
  360. /*
  361. * Check to see if:
  362. * (a) there is anything on the txq to send
  363. * (b) link is up
  364. * (c) link attention events can be processed (fcp ring only)
  365. * (d) IOCB processing is not blocked by the outstanding mbox command.
  366. */
  367. if (pring->txq_cnt &&
  368. (phba->hba_state > LPFC_LINK_DOWN) &&
  369. (pring->ringno != phba->sli.fcp_ring ||
  370. phba->sli.sli_flag & LPFC_PROCESS_LA) &&
  371. !(pring->flag & LPFC_STOP_IOCB_MBX)) {
  372. while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
  373. (nextiocb = lpfc_sli_ringtx_get(phba, pring)))
  374. lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
  375. if (iocb)
  376. lpfc_sli_update_ring(phba, pring);
  377. else
  378. lpfc_sli_update_full_ring(phba, pring);
  379. }
  380. return;
  381. }
  382. /* lpfc_sli_turn_on_ring is only called by lpfc_sli_handle_mb_event below */
  383. static void
  384. lpfc_sli_turn_on_ring(struct lpfc_hba * phba, int ringno)
  385. {
  386. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[ringno];
  387. /* If the ring is active, flag it */
  388. if (phba->sli.ring[ringno].cmdringaddr) {
  389. if (phba->sli.ring[ringno].flag & LPFC_STOP_IOCB_MBX) {
  390. phba->sli.ring[ringno].flag &= ~LPFC_STOP_IOCB_MBX;
  391. /*
  392. * Force update of the local copy of cmdGetInx
  393. */
  394. phba->sli.ring[ringno].local_getidx
  395. = le32_to_cpu(pgp->cmdGetInx);
  396. spin_lock_irq(phba->host->host_lock);
  397. lpfc_sli_resume_iocb(phba, &phba->sli.ring[ringno]);
  398. spin_unlock_irq(phba->host->host_lock);
  399. }
  400. }
  401. }
  402. static int
  403. lpfc_sli_chk_mbx_command(uint8_t mbxCommand)
  404. {
  405. uint8_t ret;
  406. switch (mbxCommand) {
  407. case MBX_LOAD_SM:
  408. case MBX_READ_NV:
  409. case MBX_WRITE_NV:
  410. case MBX_RUN_BIU_DIAG:
  411. case MBX_INIT_LINK:
  412. case MBX_DOWN_LINK:
  413. case MBX_CONFIG_LINK:
  414. case MBX_CONFIG_RING:
  415. case MBX_RESET_RING:
  416. case MBX_READ_CONFIG:
  417. case MBX_READ_RCONFIG:
  418. case MBX_READ_SPARM:
  419. case MBX_READ_STATUS:
  420. case MBX_READ_RPI:
  421. case MBX_READ_XRI:
  422. case MBX_READ_REV:
  423. case MBX_READ_LNK_STAT:
  424. case MBX_REG_LOGIN:
  425. case MBX_UNREG_LOGIN:
  426. case MBX_READ_LA:
  427. case MBX_CLEAR_LA:
  428. case MBX_DUMP_MEMORY:
  429. case MBX_DUMP_CONTEXT:
  430. case MBX_RUN_DIAGS:
  431. case MBX_RESTART:
  432. case MBX_UPDATE_CFG:
  433. case MBX_DOWN_LOAD:
  434. case MBX_DEL_LD_ENTRY:
  435. case MBX_RUN_PROGRAM:
  436. case MBX_SET_MASK:
  437. case MBX_SET_SLIM:
  438. case MBX_UNREG_D_ID:
  439. case MBX_KILL_BOARD:
  440. case MBX_CONFIG_FARP:
  441. case MBX_BEACON:
  442. case MBX_LOAD_AREA:
  443. case MBX_RUN_BIU_DIAG64:
  444. case MBX_CONFIG_PORT:
  445. case MBX_READ_SPARM64:
  446. case MBX_READ_RPI64:
  447. case MBX_REG_LOGIN64:
  448. case MBX_READ_LA64:
  449. case MBX_FLASH_WR_ULA:
  450. case MBX_SET_DEBUG:
  451. case MBX_LOAD_EXP_ROM:
  452. ret = mbxCommand;
  453. break;
  454. default:
  455. ret = MBX_SHUTDOWN;
  456. break;
  457. }
  458. return (ret);
  459. }
  460. static void
  461. lpfc_sli_wake_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
  462. {
  463. wait_queue_head_t *pdone_q;
  464. /*
  465. * If pdone_q is empty, the driver thread gave up waiting and
  466. * continued running.
  467. */
  468. pdone_q = (wait_queue_head_t *) pmboxq->context1;
  469. if (pdone_q)
  470. wake_up_interruptible(pdone_q);
  471. return;
  472. }
  473. void
  474. lpfc_sli_def_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  475. {
  476. struct lpfc_dmabuf *mp;
  477. mp = (struct lpfc_dmabuf *) (pmb->context1);
  478. if (mp) {
  479. lpfc_mbuf_free(phba, mp->virt, mp->phys);
  480. kfree(mp);
  481. }
  482. mempool_free( pmb, phba->mbox_mem_pool);
  483. return;
  484. }
  485. int
  486. lpfc_sli_handle_mb_event(struct lpfc_hba * phba)
  487. {
  488. MAILBOX_t *mbox;
  489. MAILBOX_t *pmbox;
  490. LPFC_MBOXQ_t *pmb;
  491. struct lpfc_sli *psli;
  492. int i, rc;
  493. uint32_t process_next;
  494. psli = &phba->sli;
  495. /* We should only get here if we are in SLI2 mode */
  496. if (!(phba->sli.sli_flag & LPFC_SLI2_ACTIVE)) {
  497. return (1);
  498. }
  499. phba->sli.slistat.mbox_event++;
  500. /* Get a Mailbox buffer to setup mailbox commands for callback */
  501. if ((pmb = phba->sli.mbox_active)) {
  502. pmbox = &pmb->mb;
  503. mbox = &phba->slim2p->mbx;
  504. /* First check out the status word */
  505. lpfc_sli_pcimem_bcopy(mbox, pmbox, sizeof (uint32_t));
  506. /* Sanity check to ensure the host owns the mailbox */
  507. if (pmbox->mbxOwner != OWN_HOST) {
  508. /* Lets try for a while */
  509. for (i = 0; i < 10240; i++) {
  510. /* First copy command data */
  511. lpfc_sli_pcimem_bcopy(mbox, pmbox,
  512. sizeof (uint32_t));
  513. if (pmbox->mbxOwner == OWN_HOST)
  514. goto mbout;
  515. }
  516. /* Stray Mailbox Interrupt, mbxCommand <cmd> mbxStatus
  517. <status> */
  518. lpfc_printf_log(phba,
  519. KERN_WARNING,
  520. LOG_MBOX | LOG_SLI,
  521. "%d:0304 Stray Mailbox Interrupt "
  522. "mbxCommand x%x mbxStatus x%x\n",
  523. phba->brd_no,
  524. pmbox->mbxCommand,
  525. pmbox->mbxStatus);
  526. spin_lock_irq(phba->host->host_lock);
  527. phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
  528. spin_unlock_irq(phba->host->host_lock);
  529. return (1);
  530. }
  531. mbout:
  532. del_timer_sync(&phba->sli.mbox_tmo);
  533. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  534. /*
  535. * It is a fatal error if unknown mbox command completion.
  536. */
  537. if (lpfc_sli_chk_mbx_command(pmbox->mbxCommand) ==
  538. MBX_SHUTDOWN) {
  539. /* Unknow mailbox command compl */
  540. lpfc_printf_log(phba,
  541. KERN_ERR,
  542. LOG_MBOX | LOG_SLI,
  543. "%d:0323 Unknown Mailbox command %x Cmpl\n",
  544. phba->brd_no,
  545. pmbox->mbxCommand);
  546. phba->hba_state = LPFC_HBA_ERROR;
  547. phba->work_hs = HS_FFER3;
  548. lpfc_handle_eratt(phba);
  549. return (0);
  550. }
  551. phba->sli.mbox_active = NULL;
  552. if (pmbox->mbxStatus) {
  553. phba->sli.slistat.mbox_stat_err++;
  554. if (pmbox->mbxStatus == MBXERR_NO_RESOURCES) {
  555. /* Mbox cmd cmpl error - RETRYing */
  556. lpfc_printf_log(phba,
  557. KERN_INFO,
  558. LOG_MBOX | LOG_SLI,
  559. "%d:0305 Mbox cmd cmpl error - "
  560. "RETRYing Data: x%x x%x x%x x%x\n",
  561. phba->brd_no,
  562. pmbox->mbxCommand,
  563. pmbox->mbxStatus,
  564. pmbox->un.varWords[0],
  565. phba->hba_state);
  566. pmbox->mbxStatus = 0;
  567. pmbox->mbxOwner = OWN_HOST;
  568. spin_lock_irq(phba->host->host_lock);
  569. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  570. spin_unlock_irq(phba->host->host_lock);
  571. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
  572. if (rc == MBX_SUCCESS)
  573. return (0);
  574. }
  575. }
  576. /* Mailbox cmd <cmd> Cmpl <cmpl> */
  577. lpfc_printf_log(phba,
  578. KERN_INFO,
  579. LOG_MBOX | LOG_SLI,
  580. "%d:0307 Mailbox cmd x%x Cmpl x%p "
  581. "Data: x%x x%x x%x x%x x%x x%x x%x x%x x%x\n",
  582. phba->brd_no,
  583. pmbox->mbxCommand,
  584. pmb->mbox_cmpl,
  585. *((uint32_t *) pmbox),
  586. pmbox->un.varWords[0],
  587. pmbox->un.varWords[1],
  588. pmbox->un.varWords[2],
  589. pmbox->un.varWords[3],
  590. pmbox->un.varWords[4],
  591. pmbox->un.varWords[5],
  592. pmbox->un.varWords[6],
  593. pmbox->un.varWords[7]);
  594. if (pmb->mbox_cmpl) {
  595. lpfc_sli_pcimem_bcopy(mbox, pmbox, MAILBOX_CMD_SIZE);
  596. pmb->mbox_cmpl(phba,pmb);
  597. }
  598. }
  599. do {
  600. process_next = 0; /* by default don't loop */
  601. spin_lock_irq(phba->host->host_lock);
  602. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  603. /* Process next mailbox command if there is one */
  604. if ((pmb = lpfc_mbox_get(phba))) {
  605. spin_unlock_irq(phba->host->host_lock);
  606. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
  607. if (rc == MBX_NOT_FINISHED) {
  608. pmb->mb.mbxStatus = MBX_NOT_FINISHED;
  609. pmb->mbox_cmpl(phba,pmb);
  610. process_next = 1;
  611. continue; /* loop back */
  612. }
  613. } else {
  614. spin_unlock_irq(phba->host->host_lock);
  615. /* Turn on IOCB processing */
  616. for (i = 0; i < phba->sli.num_rings; i++) {
  617. lpfc_sli_turn_on_ring(phba, i);
  618. }
  619. /* Free any lpfc_dmabuf's waiting for mbox cmd cmpls */
  620. while (!list_empty(&phba->freebufList)) {
  621. struct lpfc_dmabuf *mp;
  622. mp = NULL;
  623. list_remove_head((&phba->freebufList),
  624. mp,
  625. struct lpfc_dmabuf,
  626. list);
  627. if (mp) {
  628. lpfc_mbuf_free(phba, mp->virt,
  629. mp->phys);
  630. kfree(mp);
  631. }
  632. }
  633. }
  634. } while (process_next);
  635. return (0);
  636. }
  637. static int
  638. lpfc_sli_process_unsol_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  639. struct lpfc_iocbq *saveq)
  640. {
  641. IOCB_t * irsp;
  642. WORD5 * w5p;
  643. uint32_t Rctl, Type;
  644. uint32_t match, i;
  645. match = 0;
  646. irsp = &(saveq->iocb);
  647. if ((irsp->ulpCommand == CMD_RCV_ELS_REQ64_CX)
  648. || (irsp->ulpCommand == CMD_RCV_ELS_REQ_CX)) {
  649. Rctl = FC_ELS_REQ;
  650. Type = FC_ELS_DATA;
  651. } else {
  652. w5p =
  653. (WORD5 *) & (saveq->iocb.un.
  654. ulpWord[5]);
  655. Rctl = w5p->hcsw.Rctl;
  656. Type = w5p->hcsw.Type;
  657. /* Firmware Workaround */
  658. if ((Rctl == 0) && (pring->ringno == LPFC_ELS_RING) &&
  659. (irsp->ulpCommand == CMD_RCV_SEQUENCE64_CX)) {
  660. Rctl = FC_ELS_REQ;
  661. Type = FC_ELS_DATA;
  662. w5p->hcsw.Rctl = Rctl;
  663. w5p->hcsw.Type = Type;
  664. }
  665. }
  666. /* unSolicited Responses */
  667. if (pring->prt[0].profile) {
  668. if (pring->prt[0].lpfc_sli_rcv_unsol_event)
  669. (pring->prt[0].lpfc_sli_rcv_unsol_event) (phba, pring,
  670. saveq);
  671. match = 1;
  672. } else {
  673. /* We must search, based on rctl / type
  674. for the right routine */
  675. for (i = 0; i < pring->num_mask;
  676. i++) {
  677. if ((pring->prt[i].rctl ==
  678. Rctl)
  679. && (pring->prt[i].
  680. type == Type)) {
  681. if (pring->prt[i].lpfc_sli_rcv_unsol_event)
  682. (pring->prt[i].lpfc_sli_rcv_unsol_event)
  683. (phba, pring, saveq);
  684. match = 1;
  685. break;
  686. }
  687. }
  688. }
  689. if (match == 0) {
  690. /* Unexpected Rctl / Type received */
  691. /* Ring <ringno> handler: unexpected
  692. Rctl <Rctl> Type <Type> received */
  693. lpfc_printf_log(phba,
  694. KERN_WARNING,
  695. LOG_SLI,
  696. "%d:0313 Ring %d handler: unexpected Rctl x%x "
  697. "Type x%x received \n",
  698. phba->brd_no,
  699. pring->ringno,
  700. Rctl,
  701. Type);
  702. }
  703. return(1);
  704. }
  705. static struct lpfc_iocbq *
  706. lpfc_sli_iocbq_lookup(struct lpfc_hba * phba,
  707. struct lpfc_sli_ring * pring,
  708. struct lpfc_iocbq * prspiocb)
  709. {
  710. struct lpfc_iocbq *cmd_iocb = NULL;
  711. uint16_t iotag;
  712. iotag = prspiocb->iocb.ulpIoTag;
  713. if (iotag != 0 && iotag <= phba->sli.last_iotag) {
  714. cmd_iocb = phba->sli.iocbq_lookup[iotag];
  715. list_del(&cmd_iocb->list);
  716. pring->txcmplq_cnt--;
  717. return cmd_iocb;
  718. }
  719. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  720. "%d:0317 iotag x%x is out off "
  721. "range: max iotag x%x wd0 x%x\n",
  722. phba->brd_no, iotag,
  723. phba->sli.last_iotag,
  724. *(((uint32_t *) &prspiocb->iocb) + 7));
  725. return NULL;
  726. }
  727. static int
  728. lpfc_sli_process_sol_iocb(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
  729. struct lpfc_iocbq *saveq)
  730. {
  731. struct lpfc_iocbq * cmdiocbp;
  732. int rc = 1;
  733. unsigned long iflag;
  734. /* Based on the iotag field, get the cmd IOCB from the txcmplq */
  735. spin_lock_irqsave(phba->host->host_lock, iflag);
  736. cmdiocbp = lpfc_sli_iocbq_lookup(phba, pring, saveq);
  737. if (cmdiocbp) {
  738. if (cmdiocbp->iocb_cmpl) {
  739. /*
  740. * Post all ELS completions to the worker thread.
  741. * All other are passed to the completion callback.
  742. */
  743. if (pring->ringno == LPFC_ELS_RING) {
  744. spin_unlock_irqrestore(phba->host->host_lock,
  745. iflag);
  746. (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
  747. spin_lock_irqsave(phba->host->host_lock, iflag);
  748. }
  749. else {
  750. spin_unlock_irqrestore(phba->host->host_lock,
  751. iflag);
  752. (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
  753. spin_lock_irqsave(phba->host->host_lock, iflag);
  754. }
  755. } else
  756. lpfc_sli_release_iocbq(phba, cmdiocbp);
  757. } else {
  758. /*
  759. * Unknown initiating command based on the response iotag.
  760. * This could be the case on the ELS ring because of
  761. * lpfc_els_abort().
  762. */
  763. if (pring->ringno != LPFC_ELS_RING) {
  764. /*
  765. * Ring <ringno> handler: unexpected completion IoTag
  766. * <IoTag>
  767. */
  768. lpfc_printf_log(phba,
  769. KERN_WARNING,
  770. LOG_SLI,
  771. "%d:0322 Ring %d handler: unexpected "
  772. "completion IoTag x%x Data: x%x x%x x%x x%x\n",
  773. phba->brd_no,
  774. pring->ringno,
  775. saveq->iocb.ulpIoTag,
  776. saveq->iocb.ulpStatus,
  777. saveq->iocb.un.ulpWord[4],
  778. saveq->iocb.ulpCommand,
  779. saveq->iocb.ulpContext);
  780. }
  781. }
  782. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  783. return rc;
  784. }
  785. static void lpfc_sli_rsp_pointers_error(struct lpfc_hba * phba,
  786. struct lpfc_sli_ring * pring)
  787. {
  788. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  789. /*
  790. * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
  791. * rsp ring <portRspMax>
  792. */
  793. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  794. "%d:0312 Ring %d handler: portRspPut %d "
  795. "is bigger then rsp ring %d\n",
  796. phba->brd_no, pring->ringno,
  797. le32_to_cpu(pgp->rspPutInx),
  798. pring->numRiocb);
  799. phba->hba_state = LPFC_HBA_ERROR;
  800. /*
  801. * All error attention handlers are posted to
  802. * worker thread
  803. */
  804. phba->work_ha |= HA_ERATT;
  805. phba->work_hs = HS_FFER3;
  806. if (phba->work_wait)
  807. wake_up(phba->work_wait);
  808. return;
  809. }
  810. void lpfc_sli_poll_fcp_ring(struct lpfc_hba * phba)
  811. {
  812. struct lpfc_sli * psli = &phba->sli;
  813. struct lpfc_sli_ring * pring = &psli->ring[LPFC_FCP_RING];
  814. IOCB_t *irsp = NULL;
  815. IOCB_t *entry = NULL;
  816. struct lpfc_iocbq *cmdiocbq = NULL;
  817. struct lpfc_iocbq rspiocbq;
  818. struct lpfc_pgp *pgp;
  819. uint32_t status;
  820. uint32_t portRspPut, portRspMax;
  821. int type;
  822. uint32_t rsp_cmpl = 0;
  823. void __iomem *to_slim;
  824. uint32_t ha_copy;
  825. pring->stats.iocb_event++;
  826. /* The driver assumes SLI-2 mode */
  827. pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  828. /*
  829. * The next available response entry should never exceed the maximum
  830. * entries. If it does, treat it as an adapter hardware error.
  831. */
  832. portRspMax = pring->numRiocb;
  833. portRspPut = le32_to_cpu(pgp->rspPutInx);
  834. if (unlikely(portRspPut >= portRspMax)) {
  835. lpfc_sli_rsp_pointers_error(phba, pring);
  836. return;
  837. }
  838. rmb();
  839. while (pring->rspidx != portRspPut) {
  840. entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
  841. if (++pring->rspidx >= portRspMax)
  842. pring->rspidx = 0;
  843. lpfc_sli_pcimem_bcopy((uint32_t *) entry,
  844. (uint32_t *) &rspiocbq.iocb,
  845. sizeof (IOCB_t));
  846. irsp = &rspiocbq.iocb;
  847. type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
  848. pring->stats.iocb_rsp++;
  849. rsp_cmpl++;
  850. if (unlikely(irsp->ulpStatus)) {
  851. /* Rsp ring <ringno> error: IOCB */
  852. lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
  853. "%d:0326 Rsp Ring %d error: IOCB Data: "
  854. "x%x x%x x%x x%x x%x x%x x%x x%x\n",
  855. phba->brd_no, pring->ringno,
  856. irsp->un.ulpWord[0],
  857. irsp->un.ulpWord[1],
  858. irsp->un.ulpWord[2],
  859. irsp->un.ulpWord[3],
  860. irsp->un.ulpWord[4],
  861. irsp->un.ulpWord[5],
  862. *(((uint32_t *) irsp) + 6),
  863. *(((uint32_t *) irsp) + 7));
  864. }
  865. switch (type) {
  866. case LPFC_ABORT_IOCB:
  867. case LPFC_SOL_IOCB:
  868. /*
  869. * Idle exchange closed via ABTS from port. No iocb
  870. * resources need to be recovered.
  871. */
  872. if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
  873. printk(KERN_INFO "%s: IOCB cmd 0x%x processed."
  874. " Skipping completion\n", __FUNCTION__,
  875. irsp->ulpCommand);
  876. break;
  877. }
  878. cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
  879. &rspiocbq);
  880. if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
  881. (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
  882. &rspiocbq);
  883. }
  884. break;
  885. default:
  886. if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
  887. char adaptermsg[LPFC_MAX_ADPTMSG];
  888. memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
  889. memcpy(&adaptermsg[0], (uint8_t *) irsp,
  890. MAX_MSG_DATA);
  891. dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
  892. phba->brd_no, adaptermsg);
  893. } else {
  894. /* Unknown IOCB command */
  895. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  896. "%d:0321 Unknown IOCB command "
  897. "Data: x%x, x%x x%x x%x x%x\n",
  898. phba->brd_no, type,
  899. irsp->ulpCommand,
  900. irsp->ulpStatus,
  901. irsp->ulpIoTag,
  902. irsp->ulpContext);
  903. }
  904. break;
  905. }
  906. /*
  907. * The response IOCB has been processed. Update the ring
  908. * pointer in SLIM. If the port response put pointer has not
  909. * been updated, sync the pgp->rspPutInx and fetch the new port
  910. * response put pointer.
  911. */
  912. to_slim = phba->MBslimaddr +
  913. (SLIMOFF + (pring->ringno * 2) + 1) * 4;
  914. writeb(pring->rspidx, to_slim);
  915. if (pring->rspidx == portRspPut)
  916. portRspPut = le32_to_cpu(pgp->rspPutInx);
  917. }
  918. ha_copy = readl(phba->HAregaddr);
  919. ha_copy >>= (LPFC_FCP_RING * 4);
  920. if ((rsp_cmpl > 0) && (ha_copy & HA_R0RE_REQ)) {
  921. pring->stats.iocb_rsp_full++;
  922. status = ((CA_R0ATT | CA_R0RE_RSP) << (LPFC_FCP_RING * 4));
  923. writel(status, phba->CAregaddr);
  924. readl(phba->CAregaddr);
  925. }
  926. if ((ha_copy & HA_R0CE_RSP) &&
  927. (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
  928. pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
  929. pring->stats.iocb_cmd_empty++;
  930. /* Force update of the local copy of cmdGetInx */
  931. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  932. lpfc_sli_resume_iocb(phba, pring);
  933. if ((pring->lpfc_sli_cmd_available))
  934. (pring->lpfc_sli_cmd_available) (phba, pring);
  935. }
  936. return;
  937. }
  938. /*
  939. * This routine presumes LPFC_FCP_RING handling and doesn't bother
  940. * to check it explicitly.
  941. */
  942. static int
  943. lpfc_sli_handle_fast_ring_event(struct lpfc_hba * phba,
  944. struct lpfc_sli_ring * pring, uint32_t mask)
  945. {
  946. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  947. IOCB_t *irsp = NULL;
  948. IOCB_t *entry = NULL;
  949. struct lpfc_iocbq *cmdiocbq = NULL;
  950. struct lpfc_iocbq rspiocbq;
  951. uint32_t status;
  952. uint32_t portRspPut, portRspMax;
  953. int rc = 1;
  954. lpfc_iocb_type type;
  955. unsigned long iflag;
  956. uint32_t rsp_cmpl = 0;
  957. void __iomem *to_slim;
  958. spin_lock_irqsave(phba->host->host_lock, iflag);
  959. pring->stats.iocb_event++;
  960. /*
  961. * The next available response entry should never exceed the maximum
  962. * entries. If it does, treat it as an adapter hardware error.
  963. */
  964. portRspMax = pring->numRiocb;
  965. portRspPut = le32_to_cpu(pgp->rspPutInx);
  966. if (unlikely(portRspPut >= portRspMax)) {
  967. lpfc_sli_rsp_pointers_error(phba, pring);
  968. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  969. return 1;
  970. }
  971. rmb();
  972. while (pring->rspidx != portRspPut) {
  973. /*
  974. * Fetch an entry off the ring and copy it into a local data
  975. * structure. The copy involves a byte-swap since the
  976. * network byte order and pci byte orders are different.
  977. */
  978. entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
  979. if (++pring->rspidx >= portRspMax)
  980. pring->rspidx = 0;
  981. lpfc_sli_pcimem_bcopy((uint32_t *) entry,
  982. (uint32_t *) &rspiocbq.iocb,
  983. sizeof (IOCB_t));
  984. irsp = &rspiocbq.iocb;
  985. type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
  986. pring->stats.iocb_rsp++;
  987. rsp_cmpl++;
  988. if (unlikely(irsp->ulpStatus)) {
  989. /* Rsp ring <ringno> error: IOCB */
  990. lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
  991. "%d:0326 Rsp Ring %d error: IOCB Data: "
  992. "x%x x%x x%x x%x x%x x%x x%x x%x\n",
  993. phba->brd_no, pring->ringno,
  994. irsp->un.ulpWord[0], irsp->un.ulpWord[1],
  995. irsp->un.ulpWord[2], irsp->un.ulpWord[3],
  996. irsp->un.ulpWord[4], irsp->un.ulpWord[5],
  997. *(((uint32_t *) irsp) + 6),
  998. *(((uint32_t *) irsp) + 7));
  999. }
  1000. switch (type) {
  1001. case LPFC_ABORT_IOCB:
  1002. case LPFC_SOL_IOCB:
  1003. /*
  1004. * Idle exchange closed via ABTS from port. No iocb
  1005. * resources need to be recovered.
  1006. */
  1007. if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
  1008. printk(KERN_INFO "%s: IOCB cmd 0x%x processed. "
  1009. "Skipping completion\n", __FUNCTION__,
  1010. irsp->ulpCommand);
  1011. break;
  1012. }
  1013. cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
  1014. &rspiocbq);
  1015. if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
  1016. if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
  1017. (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
  1018. &rspiocbq);
  1019. } else {
  1020. spin_unlock_irqrestore(
  1021. phba->host->host_lock, iflag);
  1022. (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
  1023. &rspiocbq);
  1024. spin_lock_irqsave(phba->host->host_lock,
  1025. iflag);
  1026. }
  1027. }
  1028. break;
  1029. default:
  1030. if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
  1031. char adaptermsg[LPFC_MAX_ADPTMSG];
  1032. memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
  1033. memcpy(&adaptermsg[0], (uint8_t *) irsp,
  1034. MAX_MSG_DATA);
  1035. dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
  1036. phba->brd_no, adaptermsg);
  1037. } else {
  1038. /* Unknown IOCB command */
  1039. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  1040. "%d:0321 Unknown IOCB command "
  1041. "Data: x%x, x%x x%x x%x x%x\n",
  1042. phba->brd_no, type, irsp->ulpCommand,
  1043. irsp->ulpStatus, irsp->ulpIoTag,
  1044. irsp->ulpContext);
  1045. }
  1046. break;
  1047. }
  1048. /*
  1049. * The response IOCB has been processed. Update the ring
  1050. * pointer in SLIM. If the port response put pointer has not
  1051. * been updated, sync the pgp->rspPutInx and fetch the new port
  1052. * response put pointer.
  1053. */
  1054. to_slim = phba->MBslimaddr +
  1055. (SLIMOFF + (pring->ringno * 2) + 1) * 4;
  1056. writel(pring->rspidx, to_slim);
  1057. if (pring->rspidx == portRspPut)
  1058. portRspPut = le32_to_cpu(pgp->rspPutInx);
  1059. }
  1060. if ((rsp_cmpl > 0) && (mask & HA_R0RE_REQ)) {
  1061. pring->stats.iocb_rsp_full++;
  1062. status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
  1063. writel(status, phba->CAregaddr);
  1064. readl(phba->CAregaddr);
  1065. }
  1066. if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
  1067. pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
  1068. pring->stats.iocb_cmd_empty++;
  1069. /* Force update of the local copy of cmdGetInx */
  1070. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  1071. lpfc_sli_resume_iocb(phba, pring);
  1072. if ((pring->lpfc_sli_cmd_available))
  1073. (pring->lpfc_sli_cmd_available) (phba, pring);
  1074. }
  1075. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1076. return rc;
  1077. }
  1078. int
  1079. lpfc_sli_handle_slow_ring_event(struct lpfc_hba * phba,
  1080. struct lpfc_sli_ring * pring, uint32_t mask)
  1081. {
  1082. IOCB_t *entry;
  1083. IOCB_t *irsp = NULL;
  1084. struct lpfc_iocbq *rspiocbp = NULL;
  1085. struct lpfc_iocbq *next_iocb;
  1086. struct lpfc_iocbq *cmdiocbp;
  1087. struct lpfc_iocbq *saveq;
  1088. struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
  1089. uint8_t iocb_cmd_type;
  1090. lpfc_iocb_type type;
  1091. uint32_t status, free_saveq;
  1092. uint32_t portRspPut, portRspMax;
  1093. int rc = 1;
  1094. unsigned long iflag;
  1095. void __iomem *to_slim;
  1096. spin_lock_irqsave(phba->host->host_lock, iflag);
  1097. pring->stats.iocb_event++;
  1098. /*
  1099. * The next available response entry should never exceed the maximum
  1100. * entries. If it does, treat it as an adapter hardware error.
  1101. */
  1102. portRspMax = pring->numRiocb;
  1103. portRspPut = le32_to_cpu(pgp->rspPutInx);
  1104. if (portRspPut >= portRspMax) {
  1105. /*
  1106. * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
  1107. * rsp ring <portRspMax>
  1108. */
  1109. lpfc_printf_log(phba,
  1110. KERN_ERR,
  1111. LOG_SLI,
  1112. "%d:0312 Ring %d handler: portRspPut %d "
  1113. "is bigger then rsp ring %d\n",
  1114. phba->brd_no,
  1115. pring->ringno, portRspPut, portRspMax);
  1116. phba->hba_state = LPFC_HBA_ERROR;
  1117. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1118. phba->work_hs = HS_FFER3;
  1119. lpfc_handle_eratt(phba);
  1120. return 1;
  1121. }
  1122. rmb();
  1123. while (pring->rspidx != portRspPut) {
  1124. /*
  1125. * Build a completion list and call the appropriate handler.
  1126. * The process is to get the next available response iocb, get
  1127. * a free iocb from the list, copy the response data into the
  1128. * free iocb, insert to the continuation list, and update the
  1129. * next response index to slim. This process makes response
  1130. * iocb's in the ring available to DMA as fast as possible but
  1131. * pays a penalty for a copy operation. Since the iocb is
  1132. * only 32 bytes, this penalty is considered small relative to
  1133. * the PCI reads for register values and a slim write. When
  1134. * the ulpLe field is set, the entire Command has been
  1135. * received.
  1136. */
  1137. entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
  1138. rspiocbp = lpfc_sli_get_iocbq(phba);
  1139. if (rspiocbp == NULL) {
  1140. printk(KERN_ERR "%s: out of buffers! Failing "
  1141. "completion.\n", __FUNCTION__);
  1142. break;
  1143. }
  1144. lpfc_sli_pcimem_bcopy(entry, &rspiocbp->iocb, sizeof (IOCB_t));
  1145. irsp = &rspiocbp->iocb;
  1146. if (++pring->rspidx >= portRspMax)
  1147. pring->rspidx = 0;
  1148. to_slim = phba->MBslimaddr + (SLIMOFF + (pring->ringno * 2)
  1149. + 1) * 4;
  1150. writel(pring->rspidx, to_slim);
  1151. if (list_empty(&(pring->iocb_continueq))) {
  1152. list_add(&rspiocbp->list, &(pring->iocb_continueq));
  1153. } else {
  1154. list_add_tail(&rspiocbp->list,
  1155. &(pring->iocb_continueq));
  1156. }
  1157. pring->iocb_continueq_cnt++;
  1158. if (irsp->ulpLe) {
  1159. /*
  1160. * By default, the driver expects to free all resources
  1161. * associated with this iocb completion.
  1162. */
  1163. free_saveq = 1;
  1164. saveq = list_get_first(&pring->iocb_continueq,
  1165. struct lpfc_iocbq, list);
  1166. irsp = &(saveq->iocb);
  1167. list_del_init(&pring->iocb_continueq);
  1168. pring->iocb_continueq_cnt = 0;
  1169. pring->stats.iocb_rsp++;
  1170. if (irsp->ulpStatus) {
  1171. /* Rsp ring <ringno> error: IOCB */
  1172. lpfc_printf_log(phba,
  1173. KERN_WARNING,
  1174. LOG_SLI,
  1175. "%d:0328 Rsp Ring %d error: IOCB Data: "
  1176. "x%x x%x x%x x%x x%x x%x x%x x%x\n",
  1177. phba->brd_no,
  1178. pring->ringno,
  1179. irsp->un.ulpWord[0],
  1180. irsp->un.ulpWord[1],
  1181. irsp->un.ulpWord[2],
  1182. irsp->un.ulpWord[3],
  1183. irsp->un.ulpWord[4],
  1184. irsp->un.ulpWord[5],
  1185. *(((uint32_t *) irsp) + 6),
  1186. *(((uint32_t *) irsp) + 7));
  1187. }
  1188. /*
  1189. * Fetch the IOCB command type and call the correct
  1190. * completion routine. Solicited and Unsolicited
  1191. * IOCBs on the ELS ring get freed back to the
  1192. * lpfc_iocb_list by the discovery kernel thread.
  1193. */
  1194. iocb_cmd_type = irsp->ulpCommand & CMD_IOCB_MASK;
  1195. type = lpfc_sli_iocb_cmd_type(iocb_cmd_type);
  1196. if (type == LPFC_SOL_IOCB) {
  1197. spin_unlock_irqrestore(phba->host->host_lock,
  1198. iflag);
  1199. rc = lpfc_sli_process_sol_iocb(phba, pring,
  1200. saveq);
  1201. spin_lock_irqsave(phba->host->host_lock, iflag);
  1202. } else if (type == LPFC_UNSOL_IOCB) {
  1203. spin_unlock_irqrestore(phba->host->host_lock,
  1204. iflag);
  1205. rc = lpfc_sli_process_unsol_iocb(phba, pring,
  1206. saveq);
  1207. spin_lock_irqsave(phba->host->host_lock, iflag);
  1208. } else if (type == LPFC_ABORT_IOCB) {
  1209. if ((irsp->ulpCommand != CMD_XRI_ABORTED_CX) &&
  1210. ((cmdiocbp =
  1211. lpfc_sli_iocbq_lookup(phba, pring,
  1212. saveq)))) {
  1213. /* Call the specified completion
  1214. routine */
  1215. if (cmdiocbp->iocb_cmpl) {
  1216. spin_unlock_irqrestore(
  1217. phba->host->host_lock,
  1218. iflag);
  1219. (cmdiocbp->iocb_cmpl) (phba,
  1220. cmdiocbp, saveq);
  1221. spin_lock_irqsave(
  1222. phba->host->host_lock,
  1223. iflag);
  1224. } else
  1225. lpfc_sli_release_iocbq(phba,
  1226. cmdiocbp);
  1227. }
  1228. } else if (type == LPFC_UNKNOWN_IOCB) {
  1229. if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
  1230. char adaptermsg[LPFC_MAX_ADPTMSG];
  1231. memset(adaptermsg, 0,
  1232. LPFC_MAX_ADPTMSG);
  1233. memcpy(&adaptermsg[0], (uint8_t *) irsp,
  1234. MAX_MSG_DATA);
  1235. dev_warn(&((phba->pcidev)->dev),
  1236. "lpfc%d: %s",
  1237. phba->brd_no, adaptermsg);
  1238. } else {
  1239. /* Unknown IOCB command */
  1240. lpfc_printf_log(phba,
  1241. KERN_ERR,
  1242. LOG_SLI,
  1243. "%d:0321 Unknown IOCB command "
  1244. "Data: x%x x%x x%x x%x\n",
  1245. phba->brd_no,
  1246. irsp->ulpCommand,
  1247. irsp->ulpStatus,
  1248. irsp->ulpIoTag,
  1249. irsp->ulpContext);
  1250. }
  1251. }
  1252. if (free_saveq) {
  1253. if (!list_empty(&saveq->list)) {
  1254. list_for_each_entry_safe(rspiocbp,
  1255. next_iocb,
  1256. &saveq->list,
  1257. list) {
  1258. lpfc_sli_release_iocbq(phba,
  1259. rspiocbp);
  1260. }
  1261. }
  1262. lpfc_sli_release_iocbq(phba, saveq);
  1263. }
  1264. }
  1265. /*
  1266. * If the port response put pointer has not been updated, sync
  1267. * the pgp->rspPutInx in the MAILBOX_tand fetch the new port
  1268. * response put pointer.
  1269. */
  1270. if (pring->rspidx == portRspPut) {
  1271. portRspPut = le32_to_cpu(pgp->rspPutInx);
  1272. }
  1273. } /* while (pring->rspidx != portRspPut) */
  1274. if ((rspiocbp != 0) && (mask & HA_R0RE_REQ)) {
  1275. /* At least one response entry has been freed */
  1276. pring->stats.iocb_rsp_full++;
  1277. /* SET RxRE_RSP in Chip Att register */
  1278. status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
  1279. writel(status, phba->CAregaddr);
  1280. readl(phba->CAregaddr); /* flush */
  1281. }
  1282. if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
  1283. pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
  1284. pring->stats.iocb_cmd_empty++;
  1285. /* Force update of the local copy of cmdGetInx */
  1286. pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
  1287. lpfc_sli_resume_iocb(phba, pring);
  1288. if ((pring->lpfc_sli_cmd_available))
  1289. (pring->lpfc_sli_cmd_available) (phba, pring);
  1290. }
  1291. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1292. return rc;
  1293. }
  1294. int
  1295. lpfc_sli_abort_iocb_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
  1296. {
  1297. struct lpfc_iocbq *iocb, *next_iocb;
  1298. IOCB_t *icmd = NULL, *cmd = NULL;
  1299. int errcnt;
  1300. errcnt = 0;
  1301. /* Error everything on txq and txcmplq
  1302. * First do the txq.
  1303. */
  1304. spin_lock_irq(phba->host->host_lock);
  1305. list_for_each_entry_safe(iocb, next_iocb, &pring->txq, list) {
  1306. list_del_init(&iocb->list);
  1307. if (iocb->iocb_cmpl) {
  1308. icmd = &iocb->iocb;
  1309. icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
  1310. icmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
  1311. spin_unlock_irq(phba->host->host_lock);
  1312. (iocb->iocb_cmpl) (phba, iocb, iocb);
  1313. spin_lock_irq(phba->host->host_lock);
  1314. } else
  1315. lpfc_sli_release_iocbq(phba, iocb);
  1316. }
  1317. pring->txq_cnt = 0;
  1318. INIT_LIST_HEAD(&(pring->txq));
  1319. /* Next issue ABTS for everything on the txcmplq */
  1320. list_for_each_entry_safe(iocb, next_iocb, &pring->txcmplq, list) {
  1321. cmd = &iocb->iocb;
  1322. /*
  1323. * Imediate abort of IOCB, deque and call compl
  1324. */
  1325. list_del_init(&iocb->list);
  1326. pring->txcmplq_cnt--;
  1327. if (iocb->iocb_cmpl) {
  1328. cmd->ulpStatus = IOSTAT_LOCAL_REJECT;
  1329. cmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
  1330. spin_unlock_irq(phba->host->host_lock);
  1331. (iocb->iocb_cmpl) (phba, iocb, iocb);
  1332. spin_lock_irq(phba->host->host_lock);
  1333. } else
  1334. lpfc_sli_release_iocbq(phba, iocb);
  1335. }
  1336. INIT_LIST_HEAD(&pring->txcmplq);
  1337. pring->txcmplq_cnt = 0;
  1338. spin_unlock_irq(phba->host->host_lock);
  1339. return errcnt;
  1340. }
  1341. int
  1342. lpfc_sli_brdready(struct lpfc_hba * phba, uint32_t mask)
  1343. {
  1344. uint32_t status;
  1345. int i = 0;
  1346. int retval = 0;
  1347. /* Read the HBA Host Status Register */
  1348. status = readl(phba->HSregaddr);
  1349. /*
  1350. * Check status register every 100ms for 5 retries, then every
  1351. * 500ms for 5, then every 2.5 sec for 5, then reset board and
  1352. * every 2.5 sec for 4.
  1353. * Break our of the loop if errors occurred during init.
  1354. */
  1355. while (((status & mask) != mask) &&
  1356. !(status & HS_FFERM) &&
  1357. i++ < 20) {
  1358. if (i <= 5)
  1359. msleep(10);
  1360. else if (i <= 10)
  1361. msleep(500);
  1362. else
  1363. msleep(2500);
  1364. if (i == 15) {
  1365. phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
  1366. lpfc_sli_brdrestart(phba);
  1367. }
  1368. /* Read the HBA Host Status Register */
  1369. status = readl(phba->HSregaddr);
  1370. }
  1371. /* Check to see if any errors occurred during init */
  1372. if ((status & HS_FFERM) || (i >= 20)) {
  1373. phba->hba_state = LPFC_HBA_ERROR;
  1374. retval = 1;
  1375. }
  1376. return retval;
  1377. }
  1378. #define BARRIER_TEST_PATTERN (0xdeadbeef)
  1379. void lpfc_reset_barrier(struct lpfc_hba * phba)
  1380. {
  1381. uint32_t __iomem *resp_buf;
  1382. uint32_t __iomem *mbox_buf;
  1383. volatile uint32_t mbox;
  1384. uint32_t hc_copy;
  1385. int i;
  1386. uint8_t hdrtype;
  1387. pci_read_config_byte(phba->pcidev, PCI_HEADER_TYPE, &hdrtype);
  1388. if (hdrtype != 0x80 ||
  1389. (FC_JEDEC_ID(phba->vpd.rev.biuRev) != HELIOS_JEDEC_ID &&
  1390. FC_JEDEC_ID(phba->vpd.rev.biuRev) != THOR_JEDEC_ID))
  1391. return;
  1392. /*
  1393. * Tell the other part of the chip to suspend temporarily all
  1394. * its DMA activity.
  1395. */
  1396. resp_buf = phba->MBslimaddr;
  1397. /* Disable the error attention */
  1398. hc_copy = readl(phba->HCregaddr);
  1399. writel((hc_copy & ~HC_ERINT_ENA), phba->HCregaddr);
  1400. readl(phba->HCregaddr); /* flush */
  1401. if (readl(phba->HAregaddr) & HA_ERATT) {
  1402. /* Clear Chip error bit */
  1403. writel(HA_ERATT, phba->HAregaddr);
  1404. phba->stopped = 1;
  1405. }
  1406. mbox = 0;
  1407. ((MAILBOX_t *)&mbox)->mbxCommand = MBX_KILL_BOARD;
  1408. ((MAILBOX_t *)&mbox)->mbxOwner = OWN_CHIP;
  1409. writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
  1410. mbox_buf = phba->MBslimaddr;
  1411. writel(mbox, mbox_buf);
  1412. for (i = 0;
  1413. readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN) && i < 50; i++)
  1414. mdelay(1);
  1415. if (readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN)) {
  1416. if (phba->sli.sli_flag & LPFC_SLI2_ACTIVE ||
  1417. phba->stopped)
  1418. goto restore_hc;
  1419. else
  1420. goto clear_errat;
  1421. }
  1422. ((MAILBOX_t *)&mbox)->mbxOwner = OWN_HOST;
  1423. for (i = 0; readl(resp_buf) != mbox && i < 500; i++)
  1424. mdelay(1);
  1425. clear_errat:
  1426. while (!(readl(phba->HAregaddr) & HA_ERATT) && ++i < 500)
  1427. mdelay(1);
  1428. if (readl(phba->HAregaddr) & HA_ERATT) {
  1429. writel(HA_ERATT, phba->HAregaddr);
  1430. phba->stopped = 1;
  1431. }
  1432. restore_hc:
  1433. writel(hc_copy, phba->HCregaddr);
  1434. readl(phba->HCregaddr); /* flush */
  1435. }
  1436. int
  1437. lpfc_sli_brdkill(struct lpfc_hba * phba)
  1438. {
  1439. struct lpfc_sli *psli;
  1440. LPFC_MBOXQ_t *pmb;
  1441. uint32_t status;
  1442. uint32_t ha_copy;
  1443. int retval;
  1444. int i = 0;
  1445. psli = &phba->sli;
  1446. /* Kill HBA */
  1447. lpfc_printf_log(phba,
  1448. KERN_INFO,
  1449. LOG_SLI,
  1450. "%d:0329 Kill HBA Data: x%x x%x\n",
  1451. phba->brd_no,
  1452. phba->hba_state,
  1453. psli->sli_flag);
  1454. if ((pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
  1455. GFP_KERNEL)) == 0)
  1456. return 1;
  1457. /* Disable the error attention */
  1458. spin_lock_irq(phba->host->host_lock);
  1459. status = readl(phba->HCregaddr);
  1460. status &= ~HC_ERINT_ENA;
  1461. writel(status, phba->HCregaddr);
  1462. readl(phba->HCregaddr); /* flush */
  1463. spin_unlock_irq(phba->host->host_lock);
  1464. lpfc_kill_board(phba, pmb);
  1465. pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
  1466. retval = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
  1467. if (retval != MBX_SUCCESS) {
  1468. if (retval != MBX_BUSY)
  1469. mempool_free(pmb, phba->mbox_mem_pool);
  1470. return 1;
  1471. }
  1472. psli->sli_flag &= ~LPFC_SLI2_ACTIVE;
  1473. mempool_free(pmb, phba->mbox_mem_pool);
  1474. /* There is no completion for a KILL_BOARD mbox cmd. Check for an error
  1475. * attention every 100ms for 3 seconds. If we don't get ERATT after
  1476. * 3 seconds we still set HBA_ERROR state because the status of the
  1477. * board is now undefined.
  1478. */
  1479. ha_copy = readl(phba->HAregaddr);
  1480. while ((i++ < 30) && !(ha_copy & HA_ERATT)) {
  1481. mdelay(100);
  1482. ha_copy = readl(phba->HAregaddr);
  1483. }
  1484. del_timer_sync(&psli->mbox_tmo);
  1485. if (ha_copy & HA_ERATT) {
  1486. writel(HA_ERATT, phba->HAregaddr);
  1487. phba->stopped = 1;
  1488. }
  1489. spin_lock_irq(phba->host->host_lock);
  1490. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1491. spin_unlock_irq(phba->host->host_lock);
  1492. psli->mbox_active = NULL;
  1493. lpfc_hba_down_post(phba);
  1494. phba->hba_state = LPFC_HBA_ERROR;
  1495. return (ha_copy & HA_ERATT ? 0 : 1);
  1496. }
  1497. int
  1498. lpfc_sli_brdreset(struct lpfc_hba * phba)
  1499. {
  1500. struct lpfc_sli *psli;
  1501. struct lpfc_sli_ring *pring;
  1502. uint16_t cfg_value;
  1503. int i;
  1504. psli = &phba->sli;
  1505. /* Reset HBA */
  1506. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  1507. "%d:0325 Reset HBA Data: x%x x%x\n", phba->brd_no,
  1508. phba->hba_state, psli->sli_flag);
  1509. /* perform board reset */
  1510. phba->fc_eventTag = 0;
  1511. phba->fc_myDID = 0;
  1512. phba->fc_prevDID = 0;
  1513. /* Turn off parity checking and serr during the physical reset */
  1514. pci_read_config_word(phba->pcidev, PCI_COMMAND, &cfg_value);
  1515. pci_write_config_word(phba->pcidev, PCI_COMMAND,
  1516. (cfg_value &
  1517. ~(PCI_COMMAND_PARITY | PCI_COMMAND_SERR)));
  1518. psli->sli_flag &= ~(LPFC_SLI2_ACTIVE | LPFC_PROCESS_LA);
  1519. /* Now toggle INITFF bit in the Host Control Register */
  1520. writel(HC_INITFF, phba->HCregaddr);
  1521. mdelay(1);
  1522. readl(phba->HCregaddr); /* flush */
  1523. writel(0, phba->HCregaddr);
  1524. readl(phba->HCregaddr); /* flush */
  1525. /* Restore PCI cmd register */
  1526. pci_write_config_word(phba->pcidev, PCI_COMMAND, cfg_value);
  1527. /* Initialize relevant SLI info */
  1528. for (i = 0; i < psli->num_rings; i++) {
  1529. pring = &psli->ring[i];
  1530. pring->flag = 0;
  1531. pring->rspidx = 0;
  1532. pring->next_cmdidx = 0;
  1533. pring->local_getidx = 0;
  1534. pring->cmdidx = 0;
  1535. pring->missbufcnt = 0;
  1536. }
  1537. phba->hba_state = LPFC_WARM_START;
  1538. return 0;
  1539. }
  1540. int
  1541. lpfc_sli_brdrestart(struct lpfc_hba * phba)
  1542. {
  1543. MAILBOX_t *mb;
  1544. struct lpfc_sli *psli;
  1545. uint16_t skip_post;
  1546. volatile uint32_t word0;
  1547. void __iomem *to_slim;
  1548. spin_lock_irq(phba->host->host_lock);
  1549. psli = &phba->sli;
  1550. /* Restart HBA */
  1551. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  1552. "%d:0328 Restart HBA Data: x%x x%x\n", phba->brd_no,
  1553. phba->hba_state, psli->sli_flag);
  1554. word0 = 0;
  1555. mb = (MAILBOX_t *) &word0;
  1556. mb->mbxCommand = MBX_RESTART;
  1557. mb->mbxHc = 1;
  1558. lpfc_reset_barrier(phba);
  1559. to_slim = phba->MBslimaddr;
  1560. writel(*(uint32_t *) mb, to_slim);
  1561. readl(to_slim); /* flush */
  1562. /* Only skip post after fc_ffinit is completed */
  1563. if (phba->hba_state) {
  1564. skip_post = 1;
  1565. word0 = 1; /* This is really setting up word1 */
  1566. } else {
  1567. skip_post = 0;
  1568. word0 = 0; /* This is really setting up word1 */
  1569. }
  1570. to_slim = phba->MBslimaddr + sizeof (uint32_t);
  1571. writel(*(uint32_t *) mb, to_slim);
  1572. readl(to_slim); /* flush */
  1573. lpfc_sli_brdreset(phba);
  1574. phba->stopped = 0;
  1575. phba->hba_state = LPFC_INIT_START;
  1576. spin_unlock_irq(phba->host->host_lock);
  1577. memset(&psli->lnk_stat_offsets, 0, sizeof(psli->lnk_stat_offsets));
  1578. psli->stats_start = get_seconds();
  1579. if (skip_post)
  1580. mdelay(100);
  1581. else
  1582. mdelay(2000);
  1583. lpfc_hba_down_post(phba);
  1584. return 0;
  1585. }
  1586. static int
  1587. lpfc_sli_chipset_init(struct lpfc_hba *phba)
  1588. {
  1589. uint32_t status, i = 0;
  1590. /* Read the HBA Host Status Register */
  1591. status = readl(phba->HSregaddr);
  1592. /* Check status register to see what current state is */
  1593. i = 0;
  1594. while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) {
  1595. /* Check every 100ms for 5 retries, then every 500ms for 5, then
  1596. * every 2.5 sec for 5, then reset board and every 2.5 sec for
  1597. * 4.
  1598. */
  1599. if (i++ >= 20) {
  1600. /* Adapter failed to init, timeout, status reg
  1601. <status> */
  1602. lpfc_printf_log(phba,
  1603. KERN_ERR,
  1604. LOG_INIT,
  1605. "%d:0436 Adapter failed to init, "
  1606. "timeout, status reg x%x\n",
  1607. phba->brd_no,
  1608. status);
  1609. phba->hba_state = LPFC_HBA_ERROR;
  1610. return -ETIMEDOUT;
  1611. }
  1612. /* Check to see if any errors occurred during init */
  1613. if (status & HS_FFERM) {
  1614. /* ERROR: During chipset initialization */
  1615. /* Adapter failed to init, chipset, status reg
  1616. <status> */
  1617. lpfc_printf_log(phba,
  1618. KERN_ERR,
  1619. LOG_INIT,
  1620. "%d:0437 Adapter failed to init, "
  1621. "chipset, status reg x%x\n",
  1622. phba->brd_no,
  1623. status);
  1624. phba->hba_state = LPFC_HBA_ERROR;
  1625. return -EIO;
  1626. }
  1627. if (i <= 5) {
  1628. msleep(10);
  1629. } else if (i <= 10) {
  1630. msleep(500);
  1631. } else {
  1632. msleep(2500);
  1633. }
  1634. if (i == 15) {
  1635. phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
  1636. lpfc_sli_brdrestart(phba);
  1637. }
  1638. /* Read the HBA Host Status Register */
  1639. status = readl(phba->HSregaddr);
  1640. }
  1641. /* Check to see if any errors occurred during init */
  1642. if (status & HS_FFERM) {
  1643. /* ERROR: During chipset initialization */
  1644. /* Adapter failed to init, chipset, status reg <status> */
  1645. lpfc_printf_log(phba,
  1646. KERN_ERR,
  1647. LOG_INIT,
  1648. "%d:0438 Adapter failed to init, chipset, "
  1649. "status reg x%x\n",
  1650. phba->brd_no,
  1651. status);
  1652. phba->hba_state = LPFC_HBA_ERROR;
  1653. return -EIO;
  1654. }
  1655. /* Clear all interrupt enable conditions */
  1656. writel(0, phba->HCregaddr);
  1657. readl(phba->HCregaddr); /* flush */
  1658. /* setup host attn register */
  1659. writel(0xffffffff, phba->HAregaddr);
  1660. readl(phba->HAregaddr); /* flush */
  1661. return 0;
  1662. }
  1663. int
  1664. lpfc_sli_hba_setup(struct lpfc_hba * phba)
  1665. {
  1666. LPFC_MBOXQ_t *pmb;
  1667. uint32_t resetcount = 0, rc = 0, done = 0;
  1668. pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
  1669. if (!pmb) {
  1670. phba->hba_state = LPFC_HBA_ERROR;
  1671. return -ENOMEM;
  1672. }
  1673. while (resetcount < 2 && !done) {
  1674. spin_lock_irq(phba->host->host_lock);
  1675. phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
  1676. spin_unlock_irq(phba->host->host_lock);
  1677. phba->hba_state = LPFC_STATE_UNKNOWN;
  1678. lpfc_sli_brdrestart(phba);
  1679. msleep(2500);
  1680. rc = lpfc_sli_chipset_init(phba);
  1681. if (rc)
  1682. break;
  1683. spin_lock_irq(phba->host->host_lock);
  1684. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1685. spin_unlock_irq(phba->host->host_lock);
  1686. resetcount++;
  1687. /* Call pre CONFIG_PORT mailbox command initialization. A value of 0
  1688. * means the call was successful. Any other nonzero value is a failure,
  1689. * but if ERESTART is returned, the driver may reset the HBA and try
  1690. * again.
  1691. */
  1692. rc = lpfc_config_port_prep(phba);
  1693. if (rc == -ERESTART) {
  1694. phba->hba_state = 0;
  1695. continue;
  1696. } else if (rc) {
  1697. break;
  1698. }
  1699. phba->hba_state = LPFC_INIT_MBX_CMDS;
  1700. lpfc_config_port(phba, pmb);
  1701. rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
  1702. if (rc == MBX_SUCCESS)
  1703. done = 1;
  1704. else {
  1705. lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
  1706. "%d:0442 Adapter failed to init, mbxCmd x%x "
  1707. "CONFIG_PORT, mbxStatus x%x Data: x%x\n",
  1708. phba->brd_no, pmb->mb.mbxCommand,
  1709. pmb->mb.mbxStatus, 0);
  1710. phba->sli.sli_flag &= ~LPFC_SLI2_ACTIVE;
  1711. }
  1712. }
  1713. if (!done)
  1714. goto lpfc_sli_hba_setup_error;
  1715. rc = lpfc_sli_ring_map(phba, pmb);
  1716. if (rc)
  1717. goto lpfc_sli_hba_setup_error;
  1718. phba->sli.sli_flag |= LPFC_PROCESS_LA;
  1719. rc = lpfc_config_port_post(phba);
  1720. if (rc)
  1721. goto lpfc_sli_hba_setup_error;
  1722. goto lpfc_sli_hba_setup_exit;
  1723. lpfc_sli_hba_setup_error:
  1724. phba->hba_state = LPFC_HBA_ERROR;
  1725. lpfc_sli_hba_setup_exit:
  1726. mempool_free(pmb, phba->mbox_mem_pool);
  1727. return rc;
  1728. }
  1729. static void
  1730. lpfc_mbox_abort(struct lpfc_hba * phba)
  1731. {
  1732. LPFC_MBOXQ_t *pmbox;
  1733. MAILBOX_t *mb;
  1734. if (phba->sli.mbox_active) {
  1735. del_timer_sync(&phba->sli.mbox_tmo);
  1736. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  1737. pmbox = phba->sli.mbox_active;
  1738. mb = &pmbox->mb;
  1739. phba->sli.mbox_active = NULL;
  1740. if (pmbox->mbox_cmpl) {
  1741. mb->mbxStatus = MBX_NOT_FINISHED;
  1742. (pmbox->mbox_cmpl) (phba, pmbox);
  1743. }
  1744. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1745. }
  1746. /* Abort all the non active mailbox commands. */
  1747. spin_lock_irq(phba->host->host_lock);
  1748. pmbox = lpfc_mbox_get(phba);
  1749. while (pmbox) {
  1750. mb = &pmbox->mb;
  1751. if (pmbox->mbox_cmpl) {
  1752. mb->mbxStatus = MBX_NOT_FINISHED;
  1753. spin_unlock_irq(phba->host->host_lock);
  1754. (pmbox->mbox_cmpl) (phba, pmbox);
  1755. spin_lock_irq(phba->host->host_lock);
  1756. }
  1757. pmbox = lpfc_mbox_get(phba);
  1758. }
  1759. spin_unlock_irq(phba->host->host_lock);
  1760. return;
  1761. }
  1762. /*! lpfc_mbox_timeout
  1763. *
  1764. * \pre
  1765. * \post
  1766. * \param hba Pointer to per struct lpfc_hba structure
  1767. * \param l1 Pointer to the driver's mailbox queue.
  1768. * \return
  1769. * void
  1770. *
  1771. * \b Description:
  1772. *
  1773. * This routine handles mailbox timeout events at timer interrupt context.
  1774. */
  1775. void
  1776. lpfc_mbox_timeout(unsigned long ptr)
  1777. {
  1778. struct lpfc_hba *phba;
  1779. unsigned long iflag;
  1780. phba = (struct lpfc_hba *)ptr;
  1781. spin_lock_irqsave(phba->host->host_lock, iflag);
  1782. if (!(phba->work_hba_events & WORKER_MBOX_TMO)) {
  1783. phba->work_hba_events |= WORKER_MBOX_TMO;
  1784. if (phba->work_wait)
  1785. wake_up(phba->work_wait);
  1786. }
  1787. spin_unlock_irqrestore(phba->host->host_lock, iflag);
  1788. }
  1789. void
  1790. lpfc_mbox_timeout_handler(struct lpfc_hba *phba)
  1791. {
  1792. LPFC_MBOXQ_t *pmbox;
  1793. MAILBOX_t *mb;
  1794. spin_lock_irq(phba->host->host_lock);
  1795. if (!(phba->work_hba_events & WORKER_MBOX_TMO)) {
  1796. spin_unlock_irq(phba->host->host_lock);
  1797. return;
  1798. }
  1799. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  1800. pmbox = phba->sli.mbox_active;
  1801. mb = &pmbox->mb;
  1802. /* Mbox cmd <mbxCommand> timeout */
  1803. lpfc_printf_log(phba,
  1804. KERN_ERR,
  1805. LOG_MBOX | LOG_SLI,
  1806. "%d:0310 Mailbox command x%x timeout Data: x%x x%x x%p\n",
  1807. phba->brd_no,
  1808. mb->mbxCommand,
  1809. phba->hba_state,
  1810. phba->sli.sli_flag,
  1811. phba->sli.mbox_active);
  1812. phba->sli.mbox_active = NULL;
  1813. if (pmbox->mbox_cmpl) {
  1814. mb->mbxStatus = MBX_NOT_FINISHED;
  1815. spin_unlock_irq(phba->host->host_lock);
  1816. (pmbox->mbox_cmpl) (phba, pmbox);
  1817. spin_lock_irq(phba->host->host_lock);
  1818. }
  1819. phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1820. spin_unlock_irq(phba->host->host_lock);
  1821. lpfc_mbox_abort(phba);
  1822. return;
  1823. }
  1824. int
  1825. lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
  1826. {
  1827. MAILBOX_t *mb;
  1828. struct lpfc_sli *psli;
  1829. uint32_t status, evtctr;
  1830. uint32_t ha_copy;
  1831. int i;
  1832. unsigned long drvr_flag = 0;
  1833. volatile uint32_t word0, ldata;
  1834. void __iomem *to_slim;
  1835. psli = &phba->sli;
  1836. spin_lock_irqsave(phba->host->host_lock, drvr_flag);
  1837. mb = &pmbox->mb;
  1838. status = MBX_SUCCESS;
  1839. if (phba->hba_state == LPFC_HBA_ERROR) {
  1840. spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
  1841. /* Mbox command <mbxCommand> cannot issue */
  1842. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1843. return (MBX_NOT_FINISHED);
  1844. }
  1845. if (mb->mbxCommand != MBX_KILL_BOARD && flag & MBX_NOWAIT &&
  1846. !(readl(phba->HCregaddr) & HC_MBINT_ENA)) {
  1847. spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
  1848. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1849. return (MBX_NOT_FINISHED);
  1850. }
  1851. if (psli->sli_flag & LPFC_SLI_MBOX_ACTIVE) {
  1852. /* Polling for a mbox command when another one is already active
  1853. * is not allowed in SLI. Also, the driver must have established
  1854. * SLI2 mode to queue and process multiple mbox commands.
  1855. */
  1856. if (flag & MBX_POLL) {
  1857. spin_unlock_irqrestore(phba->host->host_lock,
  1858. drvr_flag);
  1859. /* Mbox command <mbxCommand> cannot issue */
  1860. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1861. return (MBX_NOT_FINISHED);
  1862. }
  1863. if (!(psli->sli_flag & LPFC_SLI2_ACTIVE)) {
  1864. spin_unlock_irqrestore(phba->host->host_lock,
  1865. drvr_flag);
  1866. /* Mbox command <mbxCommand> cannot issue */
  1867. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
  1868. return (MBX_NOT_FINISHED);
  1869. }
  1870. /* Handle STOP IOCB processing flag. This is only meaningful
  1871. * if we are not polling for mbox completion.
  1872. */
  1873. if (flag & MBX_STOP_IOCB) {
  1874. flag &= ~MBX_STOP_IOCB;
  1875. /* Now flag each ring */
  1876. for (i = 0; i < psli->num_rings; i++) {
  1877. /* If the ring is active, flag it */
  1878. if (psli->ring[i].cmdringaddr) {
  1879. psli->ring[i].flag |=
  1880. LPFC_STOP_IOCB_MBX;
  1881. }
  1882. }
  1883. }
  1884. /* Another mailbox command is still being processed, queue this
  1885. * command to be processed later.
  1886. */
  1887. lpfc_mbox_put(phba, pmbox);
  1888. /* Mbox cmd issue - BUSY */
  1889. lpfc_printf_log(phba,
  1890. KERN_INFO,
  1891. LOG_MBOX | LOG_SLI,
  1892. "%d:0308 Mbox cmd issue - BUSY Data: x%x x%x x%x x%x\n",
  1893. phba->brd_no,
  1894. mb->mbxCommand,
  1895. phba->hba_state,
  1896. psli->sli_flag,
  1897. flag);
  1898. psli->slistat.mbox_busy++;
  1899. spin_unlock_irqrestore(phba->host->host_lock,
  1900. drvr_flag);
  1901. return (MBX_BUSY);
  1902. }
  1903. /* Handle STOP IOCB processing flag. This is only meaningful
  1904. * if we are not polling for mbox completion.
  1905. */
  1906. if (flag & MBX_STOP_IOCB) {
  1907. flag &= ~MBX_STOP_IOCB;
  1908. if (flag == MBX_NOWAIT) {
  1909. /* Now flag each ring */
  1910. for (i = 0; i < psli->num_rings; i++) {
  1911. /* If the ring is active, flag it */
  1912. if (psli->ring[i].cmdringaddr) {
  1913. psli->ring[i].flag |=
  1914. LPFC_STOP_IOCB_MBX;
  1915. }
  1916. }
  1917. }
  1918. }
  1919. psli->sli_flag |= LPFC_SLI_MBOX_ACTIVE;
  1920. /* If we are not polling, we MUST be in SLI2 mode */
  1921. if (flag != MBX_POLL) {
  1922. if (!(psli->sli_flag & LPFC_SLI2_ACTIVE) &&
  1923. (mb->mbxCommand != MBX_KILL_BOARD)) {
  1924. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  1925. spin_unlock_irqrestore(phba->host->host_lock,
  1926. drvr_flag);
  1927. /* Mbox command <mbxCommand> cannot issue */
  1928. LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag);
  1929. return (MBX_NOT_FINISHED);
  1930. }
  1931. /* timeout active mbox command */
  1932. mod_timer(&psli->mbox_tmo, (jiffies +
  1933. (HZ * lpfc_mbox_tmo_val(phba, mb->mbxCommand))));
  1934. }
  1935. /* Mailbox cmd <cmd> issue */
  1936. lpfc_printf_log(phba,
  1937. KERN_INFO,
  1938. LOG_MBOX | LOG_SLI,
  1939. "%d:0309 Mailbox cmd x%x issue Data: x%x x%x x%x\n",
  1940. phba->brd_no,
  1941. mb->mbxCommand,
  1942. phba->hba_state,
  1943. psli->sli_flag,
  1944. flag);
  1945. psli->slistat.mbox_cmd++;
  1946. evtctr = psli->slistat.mbox_event;
  1947. /* next set own bit for the adapter and copy over command word */
  1948. mb->mbxOwner = OWN_CHIP;
  1949. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  1950. /* First copy command data to host SLIM area */
  1951. lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx, MAILBOX_CMD_SIZE);
  1952. } else {
  1953. if (mb->mbxCommand == MBX_CONFIG_PORT) {
  1954. /* copy command data into host mbox for cmpl */
  1955. lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx,
  1956. MAILBOX_CMD_SIZE);
  1957. }
  1958. /* First copy mbox command data to HBA SLIM, skip past first
  1959. word */
  1960. to_slim = phba->MBslimaddr + sizeof (uint32_t);
  1961. lpfc_memcpy_to_slim(to_slim, &mb->un.varWords[0],
  1962. MAILBOX_CMD_SIZE - sizeof (uint32_t));
  1963. /* Next copy over first word, with mbxOwner set */
  1964. ldata = *((volatile uint32_t *)mb);
  1965. to_slim = phba->MBslimaddr;
  1966. writel(ldata, to_slim);
  1967. readl(to_slim); /* flush */
  1968. if (mb->mbxCommand == MBX_CONFIG_PORT) {
  1969. /* switch over to host mailbox */
  1970. psli->sli_flag |= LPFC_SLI2_ACTIVE;
  1971. }
  1972. }
  1973. wmb();
  1974. /* interrupt board to doit right away */
  1975. writel(CA_MBATT, phba->CAregaddr);
  1976. readl(phba->CAregaddr); /* flush */
  1977. switch (flag) {
  1978. case MBX_NOWAIT:
  1979. /* Don't wait for it to finish, just return */
  1980. psli->mbox_active = pmbox;
  1981. break;
  1982. case MBX_POLL:
  1983. psli->mbox_active = NULL;
  1984. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  1985. /* First read mbox status word */
  1986. word0 = *((volatile uint32_t *)&phba->slim2p->mbx);
  1987. word0 = le32_to_cpu(word0);
  1988. } else {
  1989. /* First read mbox status word */
  1990. word0 = readl(phba->MBslimaddr);
  1991. }
  1992. /* Read the HBA Host Attention Register */
  1993. ha_copy = readl(phba->HAregaddr);
  1994. i = lpfc_mbox_tmo_val(phba, mb->mbxCommand);
  1995. i *= 1000; /* Convert to ms */
  1996. /* Wait for command to complete */
  1997. while (((word0 & OWN_CHIP) == OWN_CHIP) ||
  1998. (!(ha_copy & HA_MBATT) &&
  1999. (phba->hba_state > LPFC_WARM_START))) {
  2000. if (i-- <= 0) {
  2001. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  2002. spin_unlock_irqrestore(phba->host->host_lock,
  2003. drvr_flag);
  2004. return (MBX_NOT_FINISHED);
  2005. }
  2006. /* Check if we took a mbox interrupt while we were
  2007. polling */
  2008. if (((word0 & OWN_CHIP) != OWN_CHIP)
  2009. && (evtctr != psli->slistat.mbox_event))
  2010. break;
  2011. spin_unlock_irqrestore(phba->host->host_lock,
  2012. drvr_flag);
  2013. /* Can be in interrupt context, do not sleep */
  2014. /* (or might be called with interrupts disabled) */
  2015. mdelay(1);
  2016. spin_lock_irqsave(phba->host->host_lock, drvr_flag);
  2017. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  2018. /* First copy command data */
  2019. word0 = *((volatile uint32_t *)
  2020. &phba->slim2p->mbx);
  2021. word0 = le32_to_cpu(word0);
  2022. if (mb->mbxCommand == MBX_CONFIG_PORT) {
  2023. MAILBOX_t *slimmb;
  2024. volatile uint32_t slimword0;
  2025. /* Check real SLIM for any errors */
  2026. slimword0 = readl(phba->MBslimaddr);
  2027. slimmb = (MAILBOX_t *) & slimword0;
  2028. if (((slimword0 & OWN_CHIP) != OWN_CHIP)
  2029. && slimmb->mbxStatus) {
  2030. psli->sli_flag &=
  2031. ~LPFC_SLI2_ACTIVE;
  2032. word0 = slimword0;
  2033. }
  2034. }
  2035. } else {
  2036. /* First copy command data */
  2037. word0 = readl(phba->MBslimaddr);
  2038. }
  2039. /* Read the HBA Host Attention Register */
  2040. ha_copy = readl(phba->HAregaddr);
  2041. }
  2042. if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
  2043. /* copy results back to user */
  2044. lpfc_sli_pcimem_bcopy(&phba->slim2p->mbx, mb,
  2045. MAILBOX_CMD_SIZE);
  2046. } else {
  2047. /* First copy command data */
  2048. lpfc_memcpy_from_slim(mb, phba->MBslimaddr,
  2049. MAILBOX_CMD_SIZE);
  2050. if ((mb->mbxCommand == MBX_DUMP_MEMORY) &&
  2051. pmbox->context2) {
  2052. lpfc_memcpy_from_slim((void *)pmbox->context2,
  2053. phba->MBslimaddr + DMP_RSP_OFFSET,
  2054. mb->un.varDmp.word_cnt);
  2055. }
  2056. }
  2057. writel(HA_MBATT, phba->HAregaddr);
  2058. readl(phba->HAregaddr); /* flush */
  2059. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  2060. status = mb->mbxStatus;
  2061. }
  2062. spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
  2063. return (status);
  2064. }
  2065. static int
  2066. lpfc_sli_ringtx_put(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
  2067. struct lpfc_iocbq * piocb)
  2068. {
  2069. /* Insert the caller's iocb in the txq tail for later processing. */
  2070. list_add_tail(&piocb->list, &pring->txq);
  2071. pring->txq_cnt++;
  2072. return (0);
  2073. }
  2074. static struct lpfc_iocbq *
  2075. lpfc_sli_next_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2076. struct lpfc_iocbq ** piocb)
  2077. {
  2078. struct lpfc_iocbq * nextiocb;
  2079. nextiocb = lpfc_sli_ringtx_get(phba, pring);
  2080. if (!nextiocb) {
  2081. nextiocb = *piocb;
  2082. *piocb = NULL;
  2083. }
  2084. return nextiocb;
  2085. }
  2086. int
  2087. lpfc_sli_issue_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2088. struct lpfc_iocbq *piocb, uint32_t flag)
  2089. {
  2090. struct lpfc_iocbq *nextiocb;
  2091. IOCB_t *iocb;
  2092. /*
  2093. * We should never get an IOCB if we are in a < LINK_DOWN state
  2094. */
  2095. if (unlikely(phba->hba_state < LPFC_LINK_DOWN))
  2096. return IOCB_ERROR;
  2097. /*
  2098. * Check to see if we are blocking IOCB processing because of a
  2099. * outstanding mbox command.
  2100. */
  2101. if (unlikely(pring->flag & LPFC_STOP_IOCB_MBX))
  2102. goto iocb_busy;
  2103. if (unlikely(phba->hba_state == LPFC_LINK_DOWN)) {
  2104. /*
  2105. * Only CREATE_XRI, CLOSE_XRI, ABORT_XRI, and QUE_RING_BUF
  2106. * can be issued if the link is not up.
  2107. */
  2108. switch (piocb->iocb.ulpCommand) {
  2109. case CMD_QUE_RING_BUF_CN:
  2110. case CMD_QUE_RING_BUF64_CN:
  2111. /*
  2112. * For IOCBs, like QUE_RING_BUF, that have no rsp ring
  2113. * completion, iocb_cmpl MUST be 0.
  2114. */
  2115. if (piocb->iocb_cmpl)
  2116. piocb->iocb_cmpl = NULL;
  2117. /*FALLTHROUGH*/
  2118. case CMD_CREATE_XRI_CR:
  2119. break;
  2120. default:
  2121. goto iocb_busy;
  2122. }
  2123. /*
  2124. * For FCP commands, we must be in a state where we can process link
  2125. * attention events.
  2126. */
  2127. } else if (unlikely(pring->ringno == phba->sli.fcp_ring &&
  2128. !(phba->sli.sli_flag & LPFC_PROCESS_LA)))
  2129. goto iocb_busy;
  2130. while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
  2131. (nextiocb = lpfc_sli_next_iocb(phba, pring, &piocb)))
  2132. lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
  2133. if (iocb)
  2134. lpfc_sli_update_ring(phba, pring);
  2135. else
  2136. lpfc_sli_update_full_ring(phba, pring);
  2137. if (!piocb)
  2138. return IOCB_SUCCESS;
  2139. goto out_busy;
  2140. iocb_busy:
  2141. pring->stats.iocb_cmd_delay++;
  2142. out_busy:
  2143. if (!(flag & SLI_IOCB_RET_IOCB)) {
  2144. lpfc_sli_ringtx_put(phba, pring, piocb);
  2145. return IOCB_SUCCESS;
  2146. }
  2147. return IOCB_BUSY;
  2148. }
  2149. static int
  2150. lpfc_extra_ring_setup( struct lpfc_hba *phba)
  2151. {
  2152. struct lpfc_sli *psli;
  2153. struct lpfc_sli_ring *pring;
  2154. psli = &phba->sli;
  2155. /* Adjust cmd/rsp ring iocb entries more evenly */
  2156. pring = &psli->ring[psli->fcp_ring];
  2157. pring->numCiocb -= SLI2_IOCB_CMD_R1XTRA_ENTRIES;
  2158. pring->numRiocb -= SLI2_IOCB_RSP_R1XTRA_ENTRIES;
  2159. pring->numCiocb -= SLI2_IOCB_CMD_R3XTRA_ENTRIES;
  2160. pring->numRiocb -= SLI2_IOCB_RSP_R3XTRA_ENTRIES;
  2161. pring = &psli->ring[1];
  2162. pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
  2163. pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
  2164. pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
  2165. pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
  2166. /* Setup default profile for this ring */
  2167. pring->iotag_max = 4096;
  2168. pring->num_mask = 1;
  2169. pring->prt[0].profile = 0; /* Mask 0 */
  2170. pring->prt[0].rctl = FC_UNSOL_DATA;
  2171. pring->prt[0].type = 5;
  2172. pring->prt[0].lpfc_sli_rcv_unsol_event = NULL;
  2173. return 0;
  2174. }
  2175. int
  2176. lpfc_sli_setup(struct lpfc_hba *phba)
  2177. {
  2178. int i, totiocb = 0;
  2179. struct lpfc_sli *psli = &phba->sli;
  2180. struct lpfc_sli_ring *pring;
  2181. psli->num_rings = MAX_CONFIGURED_RINGS;
  2182. psli->sli_flag = 0;
  2183. psli->fcp_ring = LPFC_FCP_RING;
  2184. psli->next_ring = LPFC_FCP_NEXT_RING;
  2185. psli->ip_ring = LPFC_IP_RING;
  2186. psli->iocbq_lookup = NULL;
  2187. psli->iocbq_lookup_len = 0;
  2188. psli->last_iotag = 0;
  2189. for (i = 0; i < psli->num_rings; i++) {
  2190. pring = &psli->ring[i];
  2191. switch (i) {
  2192. case LPFC_FCP_RING: /* ring 0 - FCP */
  2193. /* numCiocb and numRiocb are used in config_port */
  2194. pring->numCiocb = SLI2_IOCB_CMD_R0_ENTRIES;
  2195. pring->numRiocb = SLI2_IOCB_RSP_R0_ENTRIES;
  2196. pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
  2197. pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
  2198. pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
  2199. pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
  2200. pring->iotag_ctr = 0;
  2201. pring->iotag_max =
  2202. (phba->cfg_hba_queue_depth * 2);
  2203. pring->fast_iotag = pring->iotag_max;
  2204. pring->num_mask = 0;
  2205. break;
  2206. case LPFC_IP_RING: /* ring 1 - IP */
  2207. /* numCiocb and numRiocb are used in config_port */
  2208. pring->numCiocb = SLI2_IOCB_CMD_R1_ENTRIES;
  2209. pring->numRiocb = SLI2_IOCB_RSP_R1_ENTRIES;
  2210. pring->num_mask = 0;
  2211. break;
  2212. case LPFC_ELS_RING: /* ring 2 - ELS / CT */
  2213. /* numCiocb and numRiocb are used in config_port */
  2214. pring->numCiocb = SLI2_IOCB_CMD_R2_ENTRIES;
  2215. pring->numRiocb = SLI2_IOCB_RSP_R2_ENTRIES;
  2216. pring->fast_iotag = 0;
  2217. pring->iotag_ctr = 0;
  2218. pring->iotag_max = 4096;
  2219. pring->num_mask = 4;
  2220. pring->prt[0].profile = 0; /* Mask 0 */
  2221. pring->prt[0].rctl = FC_ELS_REQ;
  2222. pring->prt[0].type = FC_ELS_DATA;
  2223. pring->prt[0].lpfc_sli_rcv_unsol_event =
  2224. lpfc_els_unsol_event;
  2225. pring->prt[1].profile = 0; /* Mask 1 */
  2226. pring->prt[1].rctl = FC_ELS_RSP;
  2227. pring->prt[1].type = FC_ELS_DATA;
  2228. pring->prt[1].lpfc_sli_rcv_unsol_event =
  2229. lpfc_els_unsol_event;
  2230. pring->prt[2].profile = 0; /* Mask 2 */
  2231. /* NameServer Inquiry */
  2232. pring->prt[2].rctl = FC_UNSOL_CTL;
  2233. /* NameServer */
  2234. pring->prt[2].type = FC_COMMON_TRANSPORT_ULP;
  2235. pring->prt[2].lpfc_sli_rcv_unsol_event =
  2236. lpfc_ct_unsol_event;
  2237. pring->prt[3].profile = 0; /* Mask 3 */
  2238. /* NameServer response */
  2239. pring->prt[3].rctl = FC_SOL_CTL;
  2240. /* NameServer */
  2241. pring->prt[3].type = FC_COMMON_TRANSPORT_ULP;
  2242. pring->prt[3].lpfc_sli_rcv_unsol_event =
  2243. lpfc_ct_unsol_event;
  2244. break;
  2245. }
  2246. totiocb += (pring->numCiocb + pring->numRiocb);
  2247. }
  2248. if (totiocb > MAX_SLI2_IOCB) {
  2249. /* Too many cmd / rsp ring entries in SLI2 SLIM */
  2250. lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
  2251. "%d:0462 Too many cmd / rsp ring entries in "
  2252. "SLI2 SLIM Data: x%x x%x\n",
  2253. phba->brd_no, totiocb, MAX_SLI2_IOCB);
  2254. }
  2255. if (phba->cfg_multi_ring_support == 2)
  2256. lpfc_extra_ring_setup(phba);
  2257. return 0;
  2258. }
  2259. int
  2260. lpfc_sli_queue_setup(struct lpfc_hba * phba)
  2261. {
  2262. struct lpfc_sli *psli;
  2263. struct lpfc_sli_ring *pring;
  2264. int i;
  2265. psli = &phba->sli;
  2266. spin_lock_irq(phba->host->host_lock);
  2267. INIT_LIST_HEAD(&psli->mboxq);
  2268. /* Initialize list headers for txq and txcmplq as double linked lists */
  2269. for (i = 0; i < psli->num_rings; i++) {
  2270. pring = &psli->ring[i];
  2271. pring->ringno = i;
  2272. pring->next_cmdidx = 0;
  2273. pring->local_getidx = 0;
  2274. pring->cmdidx = 0;
  2275. INIT_LIST_HEAD(&pring->txq);
  2276. INIT_LIST_HEAD(&pring->txcmplq);
  2277. INIT_LIST_HEAD(&pring->iocb_continueq);
  2278. INIT_LIST_HEAD(&pring->postbufq);
  2279. }
  2280. spin_unlock_irq(phba->host->host_lock);
  2281. return (1);
  2282. }
  2283. int
  2284. lpfc_sli_hba_down(struct lpfc_hba * phba)
  2285. {
  2286. struct lpfc_sli *psli;
  2287. struct lpfc_sli_ring *pring;
  2288. LPFC_MBOXQ_t *pmb;
  2289. struct lpfc_iocbq *iocb, *next_iocb;
  2290. IOCB_t *icmd = NULL;
  2291. int i;
  2292. unsigned long flags = 0;
  2293. psli = &phba->sli;
  2294. lpfc_hba_down_prep(phba);
  2295. spin_lock_irqsave(phba->host->host_lock, flags);
  2296. for (i = 0; i < psli->num_rings; i++) {
  2297. pring = &psli->ring[i];
  2298. pring->flag |= LPFC_DEFERRED_RING_EVENT;
  2299. /*
  2300. * Error everything on the txq since these iocbs have not been
  2301. * given to the FW yet.
  2302. */
  2303. pring->txq_cnt = 0;
  2304. list_for_each_entry_safe(iocb, next_iocb, &pring->txq, list) {
  2305. list_del_init(&iocb->list);
  2306. if (iocb->iocb_cmpl) {
  2307. icmd = &iocb->iocb;
  2308. icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
  2309. icmd->un.ulpWord[4] = IOERR_SLI_DOWN;
  2310. spin_unlock_irqrestore(phba->host->host_lock,
  2311. flags);
  2312. (iocb->iocb_cmpl) (phba, iocb, iocb);
  2313. spin_lock_irqsave(phba->host->host_lock, flags);
  2314. } else
  2315. lpfc_sli_release_iocbq(phba, iocb);
  2316. }
  2317. INIT_LIST_HEAD(&(pring->txq));
  2318. }
  2319. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2320. /* Return any active mbox cmds */
  2321. del_timer_sync(&psli->mbox_tmo);
  2322. spin_lock_irqsave(phba->host->host_lock, flags);
  2323. phba->work_hba_events &= ~WORKER_MBOX_TMO;
  2324. if (psli->mbox_active) {
  2325. pmb = psli->mbox_active;
  2326. pmb->mb.mbxStatus = MBX_NOT_FINISHED;
  2327. if (pmb->mbox_cmpl) {
  2328. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2329. pmb->mbox_cmpl(phba,pmb);
  2330. spin_lock_irqsave(phba->host->host_lock, flags);
  2331. }
  2332. }
  2333. psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
  2334. psli->mbox_active = NULL;
  2335. /* Return any pending mbox cmds */
  2336. while ((pmb = lpfc_mbox_get(phba)) != NULL) {
  2337. pmb->mb.mbxStatus = MBX_NOT_FINISHED;
  2338. if (pmb->mbox_cmpl) {
  2339. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2340. pmb->mbox_cmpl(phba,pmb);
  2341. spin_lock_irqsave(phba->host->host_lock, flags);
  2342. }
  2343. }
  2344. INIT_LIST_HEAD(&psli->mboxq);
  2345. spin_unlock_irqrestore(phba->host->host_lock, flags);
  2346. return 1;
  2347. }
  2348. void
  2349. lpfc_sli_pcimem_bcopy(void *srcp, void *destp, uint32_t cnt)
  2350. {
  2351. uint32_t *src = srcp;
  2352. uint32_t *dest = destp;
  2353. uint32_t ldata;
  2354. int i;
  2355. for (i = 0; i < (int)cnt; i += sizeof (uint32_t)) {
  2356. ldata = *src;
  2357. ldata = le32_to_cpu(ldata);
  2358. *dest = ldata;
  2359. src++;
  2360. dest++;
  2361. }
  2362. }
  2363. int
  2364. lpfc_sli_ringpostbuf_put(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
  2365. struct lpfc_dmabuf * mp)
  2366. {
  2367. /* Stick struct lpfc_dmabuf at end of postbufq so driver can look it up
  2368. later */
  2369. list_add_tail(&mp->list, &pring->postbufq);
  2370. pring->postbufq_cnt++;
  2371. return 0;
  2372. }
  2373. struct lpfc_dmabuf *
  2374. lpfc_sli_ringpostbuf_get(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2375. dma_addr_t phys)
  2376. {
  2377. struct lpfc_dmabuf *mp, *next_mp;
  2378. struct list_head *slp = &pring->postbufq;
  2379. /* Search postbufq, from the begining, looking for a match on phys */
  2380. list_for_each_entry_safe(mp, next_mp, &pring->postbufq, list) {
  2381. if (mp->phys == phys) {
  2382. list_del_init(&mp->list);
  2383. pring->postbufq_cnt--;
  2384. return mp;
  2385. }
  2386. }
  2387. lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
  2388. "%d:0410 Cannot find virtual addr for mapped buf on "
  2389. "ring %d Data x%llx x%p x%p x%x\n",
  2390. phba->brd_no, pring->ringno, (unsigned long long)phys,
  2391. slp->next, slp->prev, pring->postbufq_cnt);
  2392. return NULL;
  2393. }
  2394. static void
  2395. lpfc_sli_abort_elsreq_cmpl(struct lpfc_hba * phba, struct lpfc_iocbq * cmdiocb,
  2396. struct lpfc_iocbq * rspiocb)
  2397. {
  2398. struct lpfc_dmabuf *buf_ptr, *buf_ptr1;
  2399. /* Free the resources associated with the ELS_REQUEST64 IOCB the driver
  2400. * just aborted.
  2401. * In this case, context2 = cmd, context2->next = rsp, context3 = bpl
  2402. */
  2403. if (cmdiocb->context2) {
  2404. buf_ptr1 = (struct lpfc_dmabuf *) cmdiocb->context2;
  2405. /* Free the response IOCB before completing the abort
  2406. command. */
  2407. buf_ptr = NULL;
  2408. list_remove_head((&buf_ptr1->list), buf_ptr,
  2409. struct lpfc_dmabuf, list);
  2410. if (buf_ptr) {
  2411. lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
  2412. kfree(buf_ptr);
  2413. }
  2414. lpfc_mbuf_free(phba, buf_ptr1->virt, buf_ptr1->phys);
  2415. kfree(buf_ptr1);
  2416. }
  2417. if (cmdiocb->context3) {
  2418. buf_ptr = (struct lpfc_dmabuf *) cmdiocb->context3;
  2419. lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
  2420. kfree(buf_ptr);
  2421. }
  2422. lpfc_sli_release_iocbq(phba, cmdiocb);
  2423. return;
  2424. }
  2425. int
  2426. lpfc_sli_issue_abort_iotag32(struct lpfc_hba * phba,
  2427. struct lpfc_sli_ring * pring,
  2428. struct lpfc_iocbq * cmdiocb)
  2429. {
  2430. struct lpfc_iocbq *abtsiocbp;
  2431. IOCB_t *icmd = NULL;
  2432. IOCB_t *iabt = NULL;
  2433. /* issue ABTS for this IOCB based on iotag */
  2434. abtsiocbp = lpfc_sli_get_iocbq(phba);
  2435. if (abtsiocbp == NULL)
  2436. return 0;
  2437. iabt = &abtsiocbp->iocb;
  2438. icmd = &cmdiocb->iocb;
  2439. switch (icmd->ulpCommand) {
  2440. case CMD_ELS_REQUEST64_CR:
  2441. /* Even though we abort the ELS command, the firmware may access
  2442. * the BPL or other resources before it processes our
  2443. * ABORT_MXRI64. Thus we must delay reusing the cmdiocb
  2444. * resources till the actual abort request completes.
  2445. */
  2446. abtsiocbp->context1 = (void *)((unsigned long)icmd->ulpCommand);
  2447. abtsiocbp->context2 = cmdiocb->context2;
  2448. abtsiocbp->context3 = cmdiocb->context3;
  2449. cmdiocb->context2 = NULL;
  2450. cmdiocb->context3 = NULL;
  2451. abtsiocbp->iocb_cmpl = lpfc_sli_abort_elsreq_cmpl;
  2452. break;
  2453. default:
  2454. lpfc_sli_release_iocbq(phba, abtsiocbp);
  2455. return 0;
  2456. }
  2457. iabt->un.amxri.abortType = ABORT_TYPE_ABTS;
  2458. iabt->un.amxri.iotag32 = icmd->un.elsreq64.bdl.ulpIoTag32;
  2459. iabt->ulpLe = 1;
  2460. iabt->ulpClass = CLASS3;
  2461. iabt->ulpCommand = CMD_ABORT_MXRI64_CN;
  2462. if (lpfc_sli_issue_iocb(phba, pring, abtsiocbp, 0) == IOCB_ERROR) {
  2463. lpfc_sli_release_iocbq(phba, abtsiocbp);
  2464. return 0;
  2465. }
  2466. return 1;
  2467. }
  2468. static int
  2469. lpfc_sli_validate_fcp_iocb(struct lpfc_iocbq *iocbq, uint16_t tgt_id,
  2470. uint64_t lun_id, uint32_t ctx,
  2471. lpfc_ctx_cmd ctx_cmd)
  2472. {
  2473. struct lpfc_scsi_buf *lpfc_cmd;
  2474. struct scsi_cmnd *cmnd;
  2475. int rc = 1;
  2476. if (!(iocbq->iocb_flag & LPFC_IO_FCP))
  2477. return rc;
  2478. lpfc_cmd = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq);
  2479. cmnd = lpfc_cmd->pCmd;
  2480. if (cmnd == NULL)
  2481. return rc;
  2482. switch (ctx_cmd) {
  2483. case LPFC_CTX_LUN:
  2484. if ((cmnd->device->id == tgt_id) &&
  2485. (cmnd->device->lun == lun_id))
  2486. rc = 0;
  2487. break;
  2488. case LPFC_CTX_TGT:
  2489. if (cmnd->device->id == tgt_id)
  2490. rc = 0;
  2491. break;
  2492. case LPFC_CTX_CTX:
  2493. if (iocbq->iocb.ulpContext == ctx)
  2494. rc = 0;
  2495. break;
  2496. case LPFC_CTX_HOST:
  2497. rc = 0;
  2498. break;
  2499. default:
  2500. printk(KERN_ERR "%s: Unknown context cmd type, value %d\n",
  2501. __FUNCTION__, ctx_cmd);
  2502. break;
  2503. }
  2504. return rc;
  2505. }
  2506. int
  2507. lpfc_sli_sum_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2508. uint16_t tgt_id, uint64_t lun_id, lpfc_ctx_cmd ctx_cmd)
  2509. {
  2510. struct lpfc_iocbq *iocbq;
  2511. int sum, i;
  2512. for (i = 1, sum = 0; i <= phba->sli.last_iotag; i++) {
  2513. iocbq = phba->sli.iocbq_lookup[i];
  2514. if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
  2515. 0, ctx_cmd) == 0)
  2516. sum++;
  2517. }
  2518. return sum;
  2519. }
  2520. void
  2521. lpfc_sli_abort_fcp_cmpl(struct lpfc_hba * phba, struct lpfc_iocbq * cmdiocb,
  2522. struct lpfc_iocbq * rspiocb)
  2523. {
  2524. spin_lock_irq(phba->host->host_lock);
  2525. lpfc_sli_release_iocbq(phba, cmdiocb);
  2526. spin_unlock_irq(phba->host->host_lock);
  2527. return;
  2528. }
  2529. int
  2530. lpfc_sli_abort_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
  2531. uint16_t tgt_id, uint64_t lun_id, uint32_t ctx,
  2532. lpfc_ctx_cmd abort_cmd)
  2533. {
  2534. struct lpfc_iocbq *iocbq;
  2535. struct lpfc_iocbq *abtsiocb;
  2536. IOCB_t *cmd = NULL;
  2537. int errcnt = 0, ret_val = 0;
  2538. int i;
  2539. for (i = 1; i <= phba->sli.last_iotag; i++) {
  2540. iocbq = phba->sli.iocbq_lookup[i];
  2541. if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
  2542. 0, abort_cmd) != 0)
  2543. continue;
  2544. /* issue ABTS for this IOCB based on iotag */
  2545. abtsiocb = lpfc_sli_get_iocbq(phba);
  2546. if (abtsiocb == NULL) {
  2547. errcnt++;
  2548. continue;
  2549. }
  2550. cmd = &iocbq->iocb;
  2551. abtsiocb->iocb.un.acxri.abortType = ABORT_TYPE_ABTS;
  2552. abtsiocb->iocb.un.acxri.abortContextTag = cmd->ulpContext;
  2553. abtsiocb->iocb.un.acxri.abortIoTag = cmd->ulpIoTag;
  2554. abtsiocb->iocb.ulpLe = 1;
  2555. abtsiocb->iocb.ulpClass = cmd->ulpClass;
  2556. if (phba->hba_state >= LPFC_LINK_UP)
  2557. abtsiocb->iocb.ulpCommand = CMD_ABORT_XRI_CN;
  2558. else
  2559. abtsiocb->iocb.ulpCommand = CMD_CLOSE_XRI_CN;
  2560. /* Setup callback routine and issue the command. */
  2561. abtsiocb->iocb_cmpl = lpfc_sli_abort_fcp_cmpl;
  2562. ret_val = lpfc_sli_issue_iocb(phba, pring, abtsiocb, 0);
  2563. if (ret_val == IOCB_ERROR) {
  2564. lpfc_sli_release_iocbq(phba, abtsiocb);
  2565. errcnt++;
  2566. continue;
  2567. }
  2568. }
  2569. return errcnt;
  2570. }
  2571. static void
  2572. lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba,
  2573. struct lpfc_iocbq *cmdiocbq,
  2574. struct lpfc_iocbq *rspiocbq)
  2575. {
  2576. wait_queue_head_t *pdone_q;
  2577. unsigned long iflags;
  2578. spin_lock_irqsave(phba->host->host_lock, iflags);
  2579. cmdiocbq->iocb_flag |= LPFC_IO_WAKE;
  2580. if (cmdiocbq->context2 && rspiocbq)
  2581. memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb,
  2582. &rspiocbq->iocb, sizeof(IOCB_t));
  2583. pdone_q = cmdiocbq->context_un.wait_queue;
  2584. spin_unlock_irqrestore(phba->host->host_lock, iflags);
  2585. if (pdone_q)
  2586. wake_up(pdone_q);
  2587. return;
  2588. }
  2589. /*
  2590. * Issue the caller's iocb and wait for its completion, but no longer than the
  2591. * caller's timeout. Note that iocb_flags is cleared before the
  2592. * lpfc_sli_issue_call since the wake routine sets a unique value and by
  2593. * definition this is a wait function.
  2594. */
  2595. int
  2596. lpfc_sli_issue_iocb_wait(struct lpfc_hba * phba,
  2597. struct lpfc_sli_ring * pring,
  2598. struct lpfc_iocbq * piocb,
  2599. struct lpfc_iocbq * prspiocbq,
  2600. uint32_t timeout)
  2601. {
  2602. DECLARE_WAIT_QUEUE_HEAD(done_q);
  2603. long timeleft, timeout_req = 0;
  2604. int retval = IOCB_SUCCESS;
  2605. uint32_t creg_val;
  2606. /*
  2607. * If the caller has provided a response iocbq buffer, then context2
  2608. * is NULL or its an error.
  2609. */
  2610. if (prspiocbq) {
  2611. if (piocb->context2)
  2612. return IOCB_ERROR;
  2613. piocb->context2 = prspiocbq;
  2614. }
  2615. piocb->iocb_cmpl = lpfc_sli_wake_iocb_wait;
  2616. piocb->context_un.wait_queue = &done_q;
  2617. piocb->iocb_flag &= ~LPFC_IO_WAKE;
  2618. if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
  2619. creg_val = readl(phba->HCregaddr);
  2620. creg_val |= (HC_R0INT_ENA << LPFC_FCP_RING);
  2621. writel(creg_val, phba->HCregaddr);
  2622. readl(phba->HCregaddr); /* flush */
  2623. }
  2624. retval = lpfc_sli_issue_iocb(phba, pring, piocb, 0);
  2625. if (retval == IOCB_SUCCESS) {
  2626. timeout_req = timeout * HZ;
  2627. spin_unlock_irq(phba->host->host_lock);
  2628. timeleft = wait_event_timeout(done_q,
  2629. piocb->iocb_flag & LPFC_IO_WAKE,
  2630. timeout_req);
  2631. spin_lock_irq(phba->host->host_lock);
  2632. if (timeleft == 0) {
  2633. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  2634. "%d:0329 IOCB wait timeout error - no "
  2635. "wake response Data x%x\n",
  2636. phba->brd_no, timeout);
  2637. retval = IOCB_TIMEDOUT;
  2638. } else if (!(piocb->iocb_flag & LPFC_IO_WAKE)) {
  2639. lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
  2640. "%d:0330 IOCB wake NOT set, "
  2641. "Data x%x x%lx\n", phba->brd_no,
  2642. timeout, (timeleft / jiffies));
  2643. retval = IOCB_TIMEDOUT;
  2644. } else {
  2645. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  2646. "%d:0331 IOCB wake signaled\n",
  2647. phba->brd_no);
  2648. }
  2649. } else {
  2650. lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
  2651. "%d:0332 IOCB wait issue failed, Data x%x\n",
  2652. phba->brd_no, retval);
  2653. retval = IOCB_ERROR;
  2654. }
  2655. if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
  2656. creg_val = readl(phba->HCregaddr);
  2657. creg_val &= ~(HC_R0INT_ENA << LPFC_FCP_RING);
  2658. writel(creg_val, phba->HCregaddr);
  2659. readl(phba->HCregaddr); /* flush */
  2660. }
  2661. if (prspiocbq)
  2662. piocb->context2 = NULL;
  2663. piocb->context_un.wait_queue = NULL;
  2664. piocb->iocb_cmpl = NULL;
  2665. return retval;
  2666. }
  2667. int
  2668. lpfc_sli_issue_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq,
  2669. uint32_t timeout)
  2670. {
  2671. DECLARE_WAIT_QUEUE_HEAD(done_q);
  2672. DECLARE_WAITQUEUE(wq_entry, current);
  2673. uint32_t timeleft = 0;
  2674. int retval;
  2675. /* The caller must leave context1 empty. */
  2676. if (pmboxq->context1 != 0) {
  2677. return (MBX_NOT_FINISHED);
  2678. }
  2679. /* setup wake call as IOCB callback */
  2680. pmboxq->mbox_cmpl = lpfc_sli_wake_mbox_wait;
  2681. /* setup context field to pass wait_queue pointer to wake function */
  2682. pmboxq->context1 = &done_q;
  2683. /* start to sleep before we wait, to avoid races */
  2684. set_current_state(TASK_INTERRUPTIBLE);
  2685. add_wait_queue(&done_q, &wq_entry);
  2686. /* now issue the command */
  2687. retval = lpfc_sli_issue_mbox(phba, pmboxq, MBX_NOWAIT);
  2688. if (retval == MBX_BUSY || retval == MBX_SUCCESS) {
  2689. timeleft = schedule_timeout(timeout * HZ);
  2690. pmboxq->context1 = NULL;
  2691. /* if schedule_timeout returns 0, we timed out and were not
  2692. woken up */
  2693. if ((timeleft == 0) || signal_pending(current))
  2694. retval = MBX_TIMEOUT;
  2695. else
  2696. retval = MBX_SUCCESS;
  2697. }
  2698. set_current_state(TASK_RUNNING);
  2699. remove_wait_queue(&done_q, &wq_entry);
  2700. return retval;
  2701. }
  2702. int
  2703. lpfc_sli_flush_mbox_queue(struct lpfc_hba * phba)
  2704. {
  2705. int i = 0;
  2706. while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE && !phba->stopped) {
  2707. if (i++ > LPFC_MBOX_TMO * 1000)
  2708. return 1;
  2709. if (lpfc_sli_handle_mb_event(phba) == 0)
  2710. i = 0;
  2711. msleep(1);
  2712. }
  2713. return (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) ? 1 : 0;
  2714. }
  2715. irqreturn_t
  2716. lpfc_intr_handler(int irq, void *dev_id, struct pt_regs * regs)
  2717. {
  2718. struct lpfc_hba *phba;
  2719. uint32_t ha_copy;
  2720. uint32_t work_ha_copy;
  2721. unsigned long status;
  2722. int i;
  2723. uint32_t control;
  2724. /*
  2725. * Get the driver's phba structure from the dev_id and
  2726. * assume the HBA is not interrupting.
  2727. */
  2728. phba = (struct lpfc_hba *) dev_id;
  2729. if (unlikely(!phba))
  2730. return IRQ_NONE;
  2731. phba->sli.slistat.sli_intr++;
  2732. /*
  2733. * Call the HBA to see if it is interrupting. If not, don't claim
  2734. * the interrupt
  2735. */
  2736. /* Ignore all interrupts during initialization. */
  2737. if (unlikely(phba->hba_state < LPFC_LINK_DOWN))
  2738. return IRQ_NONE;
  2739. /*
  2740. * Read host attention register to determine interrupt source
  2741. * Clear Attention Sources, except Error Attention (to
  2742. * preserve status) and Link Attention
  2743. */
  2744. spin_lock(phba->host->host_lock);
  2745. ha_copy = readl(phba->HAregaddr);
  2746. writel((ha_copy & ~(HA_LATT | HA_ERATT)), phba->HAregaddr);
  2747. readl(phba->HAregaddr); /* flush */
  2748. spin_unlock(phba->host->host_lock);
  2749. if (unlikely(!ha_copy))
  2750. return IRQ_NONE;
  2751. work_ha_copy = ha_copy & phba->work_ha_mask;
  2752. if (unlikely(work_ha_copy)) {
  2753. if (work_ha_copy & HA_LATT) {
  2754. if (phba->sli.sli_flag & LPFC_PROCESS_LA) {
  2755. /*
  2756. * Turn off Link Attention interrupts
  2757. * until CLEAR_LA done
  2758. */
  2759. spin_lock(phba->host->host_lock);
  2760. phba->sli.sli_flag &= ~LPFC_PROCESS_LA;
  2761. control = readl(phba->HCregaddr);
  2762. control &= ~HC_LAINT_ENA;
  2763. writel(control, phba->HCregaddr);
  2764. readl(phba->HCregaddr); /* flush */
  2765. spin_unlock(phba->host->host_lock);
  2766. }
  2767. else
  2768. work_ha_copy &= ~HA_LATT;
  2769. }
  2770. if (work_ha_copy & ~(HA_ERATT|HA_MBATT|HA_LATT)) {
  2771. for (i = 0; i < phba->sli.num_rings; i++) {
  2772. if (work_ha_copy & (HA_RXATT << (4*i))) {
  2773. /*
  2774. * Turn off Slow Rings interrupts
  2775. */
  2776. spin_lock(phba->host->host_lock);
  2777. control = readl(phba->HCregaddr);
  2778. control &= ~(HC_R0INT_ENA << i);
  2779. writel(control, phba->HCregaddr);
  2780. readl(phba->HCregaddr); /* flush */
  2781. spin_unlock(phba->host->host_lock);
  2782. }
  2783. }
  2784. }
  2785. if (work_ha_copy & HA_ERATT) {
  2786. phba->hba_state = LPFC_HBA_ERROR;
  2787. /*
  2788. * There was a link/board error. Read the
  2789. * status register to retrieve the error event
  2790. * and process it.
  2791. */
  2792. phba->sli.slistat.err_attn_event++;
  2793. /* Save status info */
  2794. phba->work_hs = readl(phba->HSregaddr);
  2795. phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
  2796. phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
  2797. /* Clear Chip error bit */
  2798. writel(HA_ERATT, phba->HAregaddr);
  2799. readl(phba->HAregaddr); /* flush */
  2800. phba->stopped = 1;
  2801. }
  2802. spin_lock(phba->host->host_lock);
  2803. phba->work_ha |= work_ha_copy;
  2804. if (phba->work_wait)
  2805. wake_up(phba->work_wait);
  2806. spin_unlock(phba->host->host_lock);
  2807. }
  2808. ha_copy &= ~(phba->work_ha_mask);
  2809. /*
  2810. * Process all events on FCP ring. Take the optimized path for
  2811. * FCP IO. Any other IO is slow path and is handled by
  2812. * the worker thread.
  2813. */
  2814. status = (ha_copy & (HA_RXMASK << (4*LPFC_FCP_RING)));
  2815. status >>= (4*LPFC_FCP_RING);
  2816. if (status & HA_RXATT)
  2817. lpfc_sli_handle_fast_ring_event(phba,
  2818. &phba->sli.ring[LPFC_FCP_RING],
  2819. status);
  2820. return IRQ_HANDLED;
  2821. } /* lpfc_intr_handler */