cputable.c 36 KB

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  1. /*
  2. * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
  3. *
  4. * Modifications for ppc64:
  5. * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/string.h>
  13. #include <linux/sched.h>
  14. #include <linux/threads.h>
  15. #include <linux/init.h>
  16. #include <linux/module.h>
  17. #include <asm/oprofile_impl.h>
  18. #include <asm/cputable.h>
  19. #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */
  20. struct cpu_spec* cur_cpu_spec = NULL;
  21. EXPORT_SYMBOL(cur_cpu_spec);
  22. /* NOTE:
  23. * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
  24. * the responsibility of the appropriate CPU save/restore functions to
  25. * eventually copy these settings over. Those save/restore aren't yet
  26. * part of the cputable though. That has to be fixed for both ppc32
  27. * and ppc64
  28. */
  29. #ifdef CONFIG_PPC32
  30. extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
  31. extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
  32. extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
  33. extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
  34. extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
  35. extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
  36. extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
  37. extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
  38. #endif /* CONFIG_PPC32 */
  39. #ifdef CONFIG_PPC64
  40. extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
  41. extern void __setup_cpu_ppc970MP(unsigned long offset, struct cpu_spec* spec);
  42. extern void __restore_cpu_ppc970(void);
  43. #endif /* CONFIG_PPC64 */
  44. /* This table only contains "desktop" CPUs, it need to be filled with embedded
  45. * ones as well...
  46. */
  47. #define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
  48. PPC_FEATURE_HAS_MMU)
  49. #define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
  50. #define COMMON_USER_POWER4 (COMMON_USER_PPC64 | PPC_FEATURE_POWER4)
  51. #define COMMON_USER_POWER5 (COMMON_USER_PPC64 | PPC_FEATURE_POWER5 |\
  52. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  53. #define COMMON_USER_POWER5_PLUS (COMMON_USER_PPC64 | PPC_FEATURE_POWER5_PLUS|\
  54. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP)
  55. #define COMMON_USER_POWER6 (COMMON_USER_PPC64 | PPC_FEATURE_ARCH_2_05 |\
  56. PPC_FEATURE_SMT | PPC_FEATURE_ICACHE_SNOOP | \
  57. PPC_FEATURE_TRUE_LE)
  58. #define COMMON_USER_PA6T (COMMON_USER_PPC64 | PPC_FEATURE_PA6T |\
  59. PPC_FEATURE_TRUE_LE | \
  60. PPC_FEATURE_HAS_ALTIVEC_COMP)
  61. #define COMMON_USER_BOOKE (PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | \
  62. PPC_FEATURE_BOOKE)
  63. /* We only set the spe features if the kernel was compiled with
  64. * spe support
  65. */
  66. #ifdef CONFIG_SPE
  67. #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
  68. #else
  69. #define PPC_FEATURE_SPE_COMP 0
  70. #endif
  71. static struct cpu_spec cpu_specs[] = {
  72. #ifdef CONFIG_PPC64
  73. { /* Power3 */
  74. .pvr_mask = 0xffff0000,
  75. .pvr_value = 0x00400000,
  76. .cpu_name = "POWER3 (630)",
  77. .cpu_features = CPU_FTRS_POWER3,
  78. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  79. .icache_bsize = 128,
  80. .dcache_bsize = 128,
  81. .num_pmcs = 8,
  82. .pmc_type = PPC_PMC_IBM,
  83. .oprofile_cpu_type = "ppc64/power3",
  84. .oprofile_type = PPC_OPROFILE_RS64,
  85. .platform = "power3",
  86. },
  87. { /* Power3+ */
  88. .pvr_mask = 0xffff0000,
  89. .pvr_value = 0x00410000,
  90. .cpu_name = "POWER3 (630+)",
  91. .cpu_features = CPU_FTRS_POWER3,
  92. .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE,
  93. .icache_bsize = 128,
  94. .dcache_bsize = 128,
  95. .num_pmcs = 8,
  96. .pmc_type = PPC_PMC_IBM,
  97. .oprofile_cpu_type = "ppc64/power3",
  98. .oprofile_type = PPC_OPROFILE_RS64,
  99. .platform = "power3",
  100. },
  101. { /* Northstar */
  102. .pvr_mask = 0xffff0000,
  103. .pvr_value = 0x00330000,
  104. .cpu_name = "RS64-II (northstar)",
  105. .cpu_features = CPU_FTRS_RS64,
  106. .cpu_user_features = COMMON_USER_PPC64,
  107. .icache_bsize = 128,
  108. .dcache_bsize = 128,
  109. .num_pmcs = 8,
  110. .pmc_type = PPC_PMC_IBM,
  111. .oprofile_cpu_type = "ppc64/rs64",
  112. .oprofile_type = PPC_OPROFILE_RS64,
  113. .platform = "rs64",
  114. },
  115. { /* Pulsar */
  116. .pvr_mask = 0xffff0000,
  117. .pvr_value = 0x00340000,
  118. .cpu_name = "RS64-III (pulsar)",
  119. .cpu_features = CPU_FTRS_RS64,
  120. .cpu_user_features = COMMON_USER_PPC64,
  121. .icache_bsize = 128,
  122. .dcache_bsize = 128,
  123. .num_pmcs = 8,
  124. .pmc_type = PPC_PMC_IBM,
  125. .oprofile_cpu_type = "ppc64/rs64",
  126. .oprofile_type = PPC_OPROFILE_RS64,
  127. .platform = "rs64",
  128. },
  129. { /* I-star */
  130. .pvr_mask = 0xffff0000,
  131. .pvr_value = 0x00360000,
  132. .cpu_name = "RS64-III (icestar)",
  133. .cpu_features = CPU_FTRS_RS64,
  134. .cpu_user_features = COMMON_USER_PPC64,
  135. .icache_bsize = 128,
  136. .dcache_bsize = 128,
  137. .num_pmcs = 8,
  138. .pmc_type = PPC_PMC_IBM,
  139. .oprofile_cpu_type = "ppc64/rs64",
  140. .oprofile_type = PPC_OPROFILE_RS64,
  141. .platform = "rs64",
  142. },
  143. { /* S-star */
  144. .pvr_mask = 0xffff0000,
  145. .pvr_value = 0x00370000,
  146. .cpu_name = "RS64-IV (sstar)",
  147. .cpu_features = CPU_FTRS_RS64,
  148. .cpu_user_features = COMMON_USER_PPC64,
  149. .icache_bsize = 128,
  150. .dcache_bsize = 128,
  151. .num_pmcs = 8,
  152. .pmc_type = PPC_PMC_IBM,
  153. .oprofile_cpu_type = "ppc64/rs64",
  154. .oprofile_type = PPC_OPROFILE_RS64,
  155. .platform = "rs64",
  156. },
  157. { /* Power4 */
  158. .pvr_mask = 0xffff0000,
  159. .pvr_value = 0x00350000,
  160. .cpu_name = "POWER4 (gp)",
  161. .cpu_features = CPU_FTRS_POWER4,
  162. .cpu_user_features = COMMON_USER_POWER4,
  163. .icache_bsize = 128,
  164. .dcache_bsize = 128,
  165. .num_pmcs = 8,
  166. .pmc_type = PPC_PMC_IBM,
  167. .oprofile_cpu_type = "ppc64/power4",
  168. .oprofile_type = PPC_OPROFILE_POWER4,
  169. .platform = "power4",
  170. },
  171. { /* Power4+ */
  172. .pvr_mask = 0xffff0000,
  173. .pvr_value = 0x00380000,
  174. .cpu_name = "POWER4+ (gq)",
  175. .cpu_features = CPU_FTRS_POWER4,
  176. .cpu_user_features = COMMON_USER_POWER4,
  177. .icache_bsize = 128,
  178. .dcache_bsize = 128,
  179. .num_pmcs = 8,
  180. .pmc_type = PPC_PMC_IBM,
  181. .oprofile_cpu_type = "ppc64/power4",
  182. .oprofile_type = PPC_OPROFILE_POWER4,
  183. .platform = "power4",
  184. },
  185. { /* PPC970 */
  186. .pvr_mask = 0xffff0000,
  187. .pvr_value = 0x00390000,
  188. .cpu_name = "PPC970",
  189. .cpu_features = CPU_FTRS_PPC970,
  190. .cpu_user_features = COMMON_USER_POWER4 |
  191. PPC_FEATURE_HAS_ALTIVEC_COMP,
  192. .icache_bsize = 128,
  193. .dcache_bsize = 128,
  194. .num_pmcs = 8,
  195. .pmc_type = PPC_PMC_IBM,
  196. .cpu_setup = __setup_cpu_ppc970,
  197. .cpu_restore = __restore_cpu_ppc970,
  198. .oprofile_cpu_type = "ppc64/970",
  199. .oprofile_type = PPC_OPROFILE_POWER4,
  200. .platform = "ppc970",
  201. },
  202. { /* PPC970FX */
  203. .pvr_mask = 0xffff0000,
  204. .pvr_value = 0x003c0000,
  205. .cpu_name = "PPC970FX",
  206. .cpu_features = CPU_FTRS_PPC970,
  207. .cpu_user_features = COMMON_USER_POWER4 |
  208. PPC_FEATURE_HAS_ALTIVEC_COMP,
  209. .icache_bsize = 128,
  210. .dcache_bsize = 128,
  211. .num_pmcs = 8,
  212. .pmc_type = PPC_PMC_IBM,
  213. .cpu_setup = __setup_cpu_ppc970,
  214. .cpu_restore = __restore_cpu_ppc970,
  215. .oprofile_cpu_type = "ppc64/970",
  216. .oprofile_type = PPC_OPROFILE_POWER4,
  217. .platform = "ppc970",
  218. },
  219. { /* PPC970MP */
  220. .pvr_mask = 0xffff0000,
  221. .pvr_value = 0x00440000,
  222. .cpu_name = "PPC970MP",
  223. .cpu_features = CPU_FTRS_PPC970,
  224. .cpu_user_features = COMMON_USER_POWER4 |
  225. PPC_FEATURE_HAS_ALTIVEC_COMP,
  226. .icache_bsize = 128,
  227. .dcache_bsize = 128,
  228. .num_pmcs = 8,
  229. .cpu_setup = __setup_cpu_ppc970MP,
  230. .cpu_restore = __restore_cpu_ppc970,
  231. .oprofile_cpu_type = "ppc64/970MP",
  232. .oprofile_type = PPC_OPROFILE_POWER4,
  233. .platform = "ppc970",
  234. },
  235. { /* PPC970GX */
  236. .pvr_mask = 0xffff0000,
  237. .pvr_value = 0x00450000,
  238. .cpu_name = "PPC970GX",
  239. .cpu_features = CPU_FTRS_PPC970,
  240. .cpu_user_features = COMMON_USER_POWER4 |
  241. PPC_FEATURE_HAS_ALTIVEC_COMP,
  242. .icache_bsize = 128,
  243. .dcache_bsize = 128,
  244. .num_pmcs = 8,
  245. .pmc_type = PPC_PMC_IBM,
  246. .cpu_setup = __setup_cpu_ppc970,
  247. .oprofile_cpu_type = "ppc64/970",
  248. .oprofile_type = PPC_OPROFILE_POWER4,
  249. .platform = "ppc970",
  250. },
  251. { /* Power5 GR */
  252. .pvr_mask = 0xffff0000,
  253. .pvr_value = 0x003a0000,
  254. .cpu_name = "POWER5 (gr)",
  255. .cpu_features = CPU_FTRS_POWER5,
  256. .cpu_user_features = COMMON_USER_POWER5,
  257. .icache_bsize = 128,
  258. .dcache_bsize = 128,
  259. .num_pmcs = 6,
  260. .pmc_type = PPC_PMC_IBM,
  261. .oprofile_cpu_type = "ppc64/power5",
  262. .oprofile_type = PPC_OPROFILE_POWER4,
  263. /* SIHV / SIPR bits are implemented on POWER4+ (GQ)
  264. * and above but only works on POWER5 and above
  265. */
  266. .oprofile_mmcra_sihv = MMCRA_SIHV,
  267. .oprofile_mmcra_sipr = MMCRA_SIPR,
  268. .platform = "power5",
  269. },
  270. { /* Power5 GS */
  271. .pvr_mask = 0xffff0000,
  272. .pvr_value = 0x003b0000,
  273. .cpu_name = "POWER5+ (gs)",
  274. .cpu_features = CPU_FTRS_POWER5,
  275. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  276. .icache_bsize = 128,
  277. .dcache_bsize = 128,
  278. .num_pmcs = 6,
  279. .pmc_type = PPC_PMC_IBM,
  280. .oprofile_cpu_type = "ppc64/power5+",
  281. .oprofile_type = PPC_OPROFILE_POWER4,
  282. .oprofile_mmcra_sihv = MMCRA_SIHV,
  283. .oprofile_mmcra_sipr = MMCRA_SIPR,
  284. .platform = "power5+",
  285. },
  286. { /* POWER6 in P5+ mode; 2.04-compliant processor */
  287. .pvr_mask = 0xffffffff,
  288. .pvr_value = 0x0f000001,
  289. .cpu_name = "POWER5+",
  290. .cpu_features = CPU_FTRS_POWER5,
  291. .cpu_user_features = COMMON_USER_POWER5_PLUS,
  292. .icache_bsize = 128,
  293. .dcache_bsize = 128,
  294. .num_pmcs = 6,
  295. .oprofile_cpu_type = "ppc64/power6",
  296. .oprofile_type = PPC_OPROFILE_POWER4,
  297. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  298. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  299. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  300. POWER6_MMCRA_OTHER,
  301. .platform = "power5+",
  302. },
  303. { /* Power6 */
  304. .pvr_mask = 0xffff0000,
  305. .pvr_value = 0x003e0000,
  306. .cpu_name = "POWER6 (raw)",
  307. .cpu_features = CPU_FTRS_POWER6,
  308. .cpu_user_features = COMMON_USER_POWER6 |
  309. PPC_FEATURE_POWER6_EXT,
  310. .icache_bsize = 128,
  311. .dcache_bsize = 128,
  312. .num_pmcs = 6,
  313. .oprofile_cpu_type = "ppc64/power6",
  314. .oprofile_type = PPC_OPROFILE_POWER4,
  315. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  316. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  317. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  318. POWER6_MMCRA_OTHER,
  319. .platform = "power6x",
  320. },
  321. { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
  322. .pvr_mask = 0xffffffff,
  323. .pvr_value = 0x0f000002,
  324. .cpu_name = "POWER6 (architected)",
  325. .cpu_features = CPU_FTRS_POWER6,
  326. .cpu_user_features = COMMON_USER_POWER6,
  327. .icache_bsize = 128,
  328. .dcache_bsize = 128,
  329. .num_pmcs = 6,
  330. .pmc_type = PPC_PMC_IBM,
  331. .oprofile_cpu_type = "ppc64/power6",
  332. .oprofile_type = PPC_OPROFILE_POWER4,
  333. .oprofile_mmcra_sihv = POWER6_MMCRA_SIHV,
  334. .oprofile_mmcra_sipr = POWER6_MMCRA_SIPR,
  335. .oprofile_mmcra_clear = POWER6_MMCRA_THRM |
  336. POWER6_MMCRA_OTHER,
  337. .platform = "power6",
  338. },
  339. { /* Cell Broadband Engine */
  340. .pvr_mask = 0xffff0000,
  341. .pvr_value = 0x00700000,
  342. .cpu_name = "Cell Broadband Engine",
  343. .cpu_features = CPU_FTRS_CELL,
  344. .cpu_user_features = COMMON_USER_PPC64 |
  345. PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
  346. PPC_FEATURE_SMT,
  347. .icache_bsize = 128,
  348. .dcache_bsize = 128,
  349. .num_pmcs = 4,
  350. .pmc_type = PPC_PMC_IBM,
  351. .oprofile_cpu_type = "ppc64/cell-be",
  352. .oprofile_type = PPC_OPROFILE_CELL,
  353. .platform = "ppc-cell-be",
  354. },
  355. { /* PA Semi PA6T */
  356. .pvr_mask = 0x7fff0000,
  357. .pvr_value = 0x00900000,
  358. .cpu_name = "PA6T",
  359. .cpu_features = CPU_FTRS_PA6T,
  360. .cpu_user_features = COMMON_USER_PA6T,
  361. .icache_bsize = 64,
  362. .dcache_bsize = 64,
  363. .num_pmcs = 6,
  364. .pmc_type = PPC_PMC_PA6T,
  365. .platform = "pa6t",
  366. },
  367. { /* default match */
  368. .pvr_mask = 0x00000000,
  369. .pvr_value = 0x00000000,
  370. .cpu_name = "POWER4 (compatible)",
  371. .cpu_features = CPU_FTRS_COMPATIBLE,
  372. .cpu_user_features = COMMON_USER_PPC64,
  373. .icache_bsize = 128,
  374. .dcache_bsize = 128,
  375. .num_pmcs = 6,
  376. .pmc_type = PPC_PMC_IBM,
  377. .platform = "power4",
  378. }
  379. #endif /* CONFIG_PPC64 */
  380. #ifdef CONFIG_PPC32
  381. #if CLASSIC_PPC
  382. { /* 601 */
  383. .pvr_mask = 0xffff0000,
  384. .pvr_value = 0x00010000,
  385. .cpu_name = "601",
  386. .cpu_features = CPU_FTRS_PPC601,
  387. .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
  388. PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB,
  389. .icache_bsize = 32,
  390. .dcache_bsize = 32,
  391. .platform = "ppc601",
  392. },
  393. { /* 603 */
  394. .pvr_mask = 0xffff0000,
  395. .pvr_value = 0x00030000,
  396. .cpu_name = "603",
  397. .cpu_features = CPU_FTRS_603,
  398. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  399. .icache_bsize = 32,
  400. .dcache_bsize = 32,
  401. .cpu_setup = __setup_cpu_603,
  402. .platform = "ppc603",
  403. },
  404. { /* 603e */
  405. .pvr_mask = 0xffff0000,
  406. .pvr_value = 0x00060000,
  407. .cpu_name = "603e",
  408. .cpu_features = CPU_FTRS_603,
  409. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  410. .icache_bsize = 32,
  411. .dcache_bsize = 32,
  412. .cpu_setup = __setup_cpu_603,
  413. .platform = "ppc603",
  414. },
  415. { /* 603ev */
  416. .pvr_mask = 0xffff0000,
  417. .pvr_value = 0x00070000,
  418. .cpu_name = "603ev",
  419. .cpu_features = CPU_FTRS_603,
  420. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  421. .icache_bsize = 32,
  422. .dcache_bsize = 32,
  423. .cpu_setup = __setup_cpu_603,
  424. .platform = "ppc603",
  425. },
  426. { /* 604 */
  427. .pvr_mask = 0xffff0000,
  428. .pvr_value = 0x00040000,
  429. .cpu_name = "604",
  430. .cpu_features = CPU_FTRS_604,
  431. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  432. .icache_bsize = 32,
  433. .dcache_bsize = 32,
  434. .num_pmcs = 2,
  435. .cpu_setup = __setup_cpu_604,
  436. .platform = "ppc604",
  437. },
  438. { /* 604e */
  439. .pvr_mask = 0xfffff000,
  440. .pvr_value = 0x00090000,
  441. .cpu_name = "604e",
  442. .cpu_features = CPU_FTRS_604,
  443. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  444. .icache_bsize = 32,
  445. .dcache_bsize = 32,
  446. .num_pmcs = 4,
  447. .cpu_setup = __setup_cpu_604,
  448. .platform = "ppc604",
  449. },
  450. { /* 604r */
  451. .pvr_mask = 0xffff0000,
  452. .pvr_value = 0x00090000,
  453. .cpu_name = "604r",
  454. .cpu_features = CPU_FTRS_604,
  455. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  456. .icache_bsize = 32,
  457. .dcache_bsize = 32,
  458. .num_pmcs = 4,
  459. .cpu_setup = __setup_cpu_604,
  460. .platform = "ppc604",
  461. },
  462. { /* 604ev */
  463. .pvr_mask = 0xffff0000,
  464. .pvr_value = 0x000a0000,
  465. .cpu_name = "604ev",
  466. .cpu_features = CPU_FTRS_604,
  467. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  468. .icache_bsize = 32,
  469. .dcache_bsize = 32,
  470. .num_pmcs = 4,
  471. .cpu_setup = __setup_cpu_604,
  472. .platform = "ppc604",
  473. },
  474. { /* 740/750 (0x4202, don't support TAU ?) */
  475. .pvr_mask = 0xffffffff,
  476. .pvr_value = 0x00084202,
  477. .cpu_name = "740/750",
  478. .cpu_features = CPU_FTRS_740_NOTAU,
  479. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  480. .icache_bsize = 32,
  481. .dcache_bsize = 32,
  482. .num_pmcs = 4,
  483. .cpu_setup = __setup_cpu_750,
  484. .platform = "ppc750",
  485. },
  486. { /* 750CX (80100 and 8010x?) */
  487. .pvr_mask = 0xfffffff0,
  488. .pvr_value = 0x00080100,
  489. .cpu_name = "750CX",
  490. .cpu_features = CPU_FTRS_750,
  491. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  492. .icache_bsize = 32,
  493. .dcache_bsize = 32,
  494. .num_pmcs = 4,
  495. .cpu_setup = __setup_cpu_750cx,
  496. .platform = "ppc750",
  497. },
  498. { /* 750CX (82201 and 82202) */
  499. .pvr_mask = 0xfffffff0,
  500. .pvr_value = 0x00082200,
  501. .cpu_name = "750CX",
  502. .cpu_features = CPU_FTRS_750,
  503. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  504. .icache_bsize = 32,
  505. .dcache_bsize = 32,
  506. .num_pmcs = 4,
  507. .cpu_setup = __setup_cpu_750cx,
  508. .platform = "ppc750",
  509. },
  510. { /* 750CXe (82214) */
  511. .pvr_mask = 0xfffffff0,
  512. .pvr_value = 0x00082210,
  513. .cpu_name = "750CXe",
  514. .cpu_features = CPU_FTRS_750,
  515. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  516. .icache_bsize = 32,
  517. .dcache_bsize = 32,
  518. .num_pmcs = 4,
  519. .cpu_setup = __setup_cpu_750cx,
  520. .platform = "ppc750",
  521. },
  522. { /* 750CXe "Gekko" (83214) */
  523. .pvr_mask = 0xffffffff,
  524. .pvr_value = 0x00083214,
  525. .cpu_name = "750CXe",
  526. .cpu_features = CPU_FTRS_750,
  527. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  528. .icache_bsize = 32,
  529. .dcache_bsize = 32,
  530. .num_pmcs = 4,
  531. .cpu_setup = __setup_cpu_750cx,
  532. .platform = "ppc750",
  533. },
  534. { /* 745/755 */
  535. .pvr_mask = 0xfffff000,
  536. .pvr_value = 0x00083000,
  537. .cpu_name = "745/755",
  538. .cpu_features = CPU_FTRS_750,
  539. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  540. .icache_bsize = 32,
  541. .dcache_bsize = 32,
  542. .num_pmcs = 4,
  543. .cpu_setup = __setup_cpu_750,
  544. .platform = "ppc750",
  545. },
  546. { /* 750FX rev 1.x */
  547. .pvr_mask = 0xffffff00,
  548. .pvr_value = 0x70000100,
  549. .cpu_name = "750FX",
  550. .cpu_features = CPU_FTRS_750FX1,
  551. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  552. .icache_bsize = 32,
  553. .dcache_bsize = 32,
  554. .num_pmcs = 4,
  555. .cpu_setup = __setup_cpu_750,
  556. .platform = "ppc750",
  557. },
  558. { /* 750FX rev 2.0 must disable HID0[DPM] */
  559. .pvr_mask = 0xffffffff,
  560. .pvr_value = 0x70000200,
  561. .cpu_name = "750FX",
  562. .cpu_features = CPU_FTRS_750FX2,
  563. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  564. .icache_bsize = 32,
  565. .dcache_bsize = 32,
  566. .num_pmcs = 4,
  567. .cpu_setup = __setup_cpu_750,
  568. .platform = "ppc750",
  569. },
  570. { /* 750FX (All revs except 2.0) */
  571. .pvr_mask = 0xffff0000,
  572. .pvr_value = 0x70000000,
  573. .cpu_name = "750FX",
  574. .cpu_features = CPU_FTRS_750FX,
  575. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  576. .icache_bsize = 32,
  577. .dcache_bsize = 32,
  578. .num_pmcs = 4,
  579. .cpu_setup = __setup_cpu_750fx,
  580. .platform = "ppc750",
  581. },
  582. { /* 750GX */
  583. .pvr_mask = 0xffff0000,
  584. .pvr_value = 0x70020000,
  585. .cpu_name = "750GX",
  586. .cpu_features = CPU_FTRS_750GX,
  587. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  588. .icache_bsize = 32,
  589. .dcache_bsize = 32,
  590. .num_pmcs = 4,
  591. .cpu_setup = __setup_cpu_750fx,
  592. .platform = "ppc750",
  593. },
  594. { /* 740/750 (L2CR bit need fixup for 740) */
  595. .pvr_mask = 0xffff0000,
  596. .pvr_value = 0x00080000,
  597. .cpu_name = "740/750",
  598. .cpu_features = CPU_FTRS_740,
  599. .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE,
  600. .icache_bsize = 32,
  601. .dcache_bsize = 32,
  602. .num_pmcs = 4,
  603. .cpu_setup = __setup_cpu_750,
  604. .platform = "ppc750",
  605. },
  606. { /* 7400 rev 1.1 ? (no TAU) */
  607. .pvr_mask = 0xffffffff,
  608. .pvr_value = 0x000c1101,
  609. .cpu_name = "7400 (1.1)",
  610. .cpu_features = CPU_FTRS_7400_NOTAU,
  611. .cpu_user_features = COMMON_USER |
  612. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  613. .icache_bsize = 32,
  614. .dcache_bsize = 32,
  615. .num_pmcs = 4,
  616. .cpu_setup = __setup_cpu_7400,
  617. .platform = "ppc7400",
  618. },
  619. { /* 7400 */
  620. .pvr_mask = 0xffff0000,
  621. .pvr_value = 0x000c0000,
  622. .cpu_name = "7400",
  623. .cpu_features = CPU_FTRS_7400,
  624. .cpu_user_features = COMMON_USER |
  625. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  626. .icache_bsize = 32,
  627. .dcache_bsize = 32,
  628. .num_pmcs = 4,
  629. .cpu_setup = __setup_cpu_7400,
  630. .platform = "ppc7400",
  631. },
  632. { /* 7410 */
  633. .pvr_mask = 0xffff0000,
  634. .pvr_value = 0x800c0000,
  635. .cpu_name = "7410",
  636. .cpu_features = CPU_FTRS_7400,
  637. .cpu_user_features = COMMON_USER |
  638. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  639. .icache_bsize = 32,
  640. .dcache_bsize = 32,
  641. .num_pmcs = 4,
  642. .cpu_setup = __setup_cpu_7410,
  643. .platform = "ppc7400",
  644. },
  645. { /* 7450 2.0 - no doze/nap */
  646. .pvr_mask = 0xffffffff,
  647. .pvr_value = 0x80000200,
  648. .cpu_name = "7450",
  649. .cpu_features = CPU_FTRS_7450_20,
  650. .cpu_user_features = COMMON_USER |
  651. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  652. .icache_bsize = 32,
  653. .dcache_bsize = 32,
  654. .num_pmcs = 6,
  655. .cpu_setup = __setup_cpu_745x,
  656. .oprofile_cpu_type = "ppc/7450",
  657. .oprofile_type = PPC_OPROFILE_G4,
  658. .platform = "ppc7450",
  659. },
  660. { /* 7450 2.1 */
  661. .pvr_mask = 0xffffffff,
  662. .pvr_value = 0x80000201,
  663. .cpu_name = "7450",
  664. .cpu_features = CPU_FTRS_7450_21,
  665. .cpu_user_features = COMMON_USER |
  666. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  667. .icache_bsize = 32,
  668. .dcache_bsize = 32,
  669. .num_pmcs = 6,
  670. .cpu_setup = __setup_cpu_745x,
  671. .oprofile_cpu_type = "ppc/7450",
  672. .oprofile_type = PPC_OPROFILE_G4,
  673. .platform = "ppc7450",
  674. },
  675. { /* 7450 2.3 and newer */
  676. .pvr_mask = 0xffff0000,
  677. .pvr_value = 0x80000000,
  678. .cpu_name = "7450",
  679. .cpu_features = CPU_FTRS_7450_23,
  680. .cpu_user_features = COMMON_USER |
  681. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  682. .icache_bsize = 32,
  683. .dcache_bsize = 32,
  684. .num_pmcs = 6,
  685. .cpu_setup = __setup_cpu_745x,
  686. .oprofile_cpu_type = "ppc/7450",
  687. .oprofile_type = PPC_OPROFILE_G4,
  688. .platform = "ppc7450",
  689. },
  690. { /* 7455 rev 1.x */
  691. .pvr_mask = 0xffffff00,
  692. .pvr_value = 0x80010100,
  693. .cpu_name = "7455",
  694. .cpu_features = CPU_FTRS_7455_1,
  695. .cpu_user_features = COMMON_USER |
  696. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  697. .icache_bsize = 32,
  698. .dcache_bsize = 32,
  699. .num_pmcs = 6,
  700. .cpu_setup = __setup_cpu_745x,
  701. .oprofile_cpu_type = "ppc/7450",
  702. .oprofile_type = PPC_OPROFILE_G4,
  703. .platform = "ppc7450",
  704. },
  705. { /* 7455 rev 2.0 */
  706. .pvr_mask = 0xffffffff,
  707. .pvr_value = 0x80010200,
  708. .cpu_name = "7455",
  709. .cpu_features = CPU_FTRS_7455_20,
  710. .cpu_user_features = COMMON_USER |
  711. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  712. .icache_bsize = 32,
  713. .dcache_bsize = 32,
  714. .num_pmcs = 6,
  715. .cpu_setup = __setup_cpu_745x,
  716. .oprofile_cpu_type = "ppc/7450",
  717. .oprofile_type = PPC_OPROFILE_G4,
  718. .platform = "ppc7450",
  719. },
  720. { /* 7455 others */
  721. .pvr_mask = 0xffff0000,
  722. .pvr_value = 0x80010000,
  723. .cpu_name = "7455",
  724. .cpu_features = CPU_FTRS_7455,
  725. .cpu_user_features = COMMON_USER |
  726. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  727. .icache_bsize = 32,
  728. .dcache_bsize = 32,
  729. .num_pmcs = 6,
  730. .cpu_setup = __setup_cpu_745x,
  731. .oprofile_cpu_type = "ppc/7450",
  732. .oprofile_type = PPC_OPROFILE_G4,
  733. .platform = "ppc7450",
  734. },
  735. { /* 7447/7457 Rev 1.0 */
  736. .pvr_mask = 0xffffffff,
  737. .pvr_value = 0x80020100,
  738. .cpu_name = "7447/7457",
  739. .cpu_features = CPU_FTRS_7447_10,
  740. .cpu_user_features = COMMON_USER |
  741. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  742. .icache_bsize = 32,
  743. .dcache_bsize = 32,
  744. .num_pmcs = 6,
  745. .cpu_setup = __setup_cpu_745x,
  746. .oprofile_cpu_type = "ppc/7450",
  747. .oprofile_type = PPC_OPROFILE_G4,
  748. .platform = "ppc7450",
  749. },
  750. { /* 7447/7457 Rev 1.1 */
  751. .pvr_mask = 0xffffffff,
  752. .pvr_value = 0x80020101,
  753. .cpu_name = "7447/7457",
  754. .cpu_features = CPU_FTRS_7447_10,
  755. .cpu_user_features = COMMON_USER |
  756. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  757. .icache_bsize = 32,
  758. .dcache_bsize = 32,
  759. .num_pmcs = 6,
  760. .cpu_setup = __setup_cpu_745x,
  761. .oprofile_cpu_type = "ppc/7450",
  762. .oprofile_type = PPC_OPROFILE_G4,
  763. .platform = "ppc7450",
  764. },
  765. { /* 7447/7457 Rev 1.2 and later */
  766. .pvr_mask = 0xffff0000,
  767. .pvr_value = 0x80020000,
  768. .cpu_name = "7447/7457",
  769. .cpu_features = CPU_FTRS_7447,
  770. .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  771. .icache_bsize = 32,
  772. .dcache_bsize = 32,
  773. .num_pmcs = 6,
  774. .cpu_setup = __setup_cpu_745x,
  775. .oprofile_cpu_type = "ppc/7450",
  776. .oprofile_type = PPC_OPROFILE_G4,
  777. .platform = "ppc7450",
  778. },
  779. { /* 7447A */
  780. .pvr_mask = 0xffff0000,
  781. .pvr_value = 0x80030000,
  782. .cpu_name = "7447A",
  783. .cpu_features = CPU_FTRS_7447A,
  784. .cpu_user_features = COMMON_USER |
  785. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  786. .icache_bsize = 32,
  787. .dcache_bsize = 32,
  788. .num_pmcs = 6,
  789. .cpu_setup = __setup_cpu_745x,
  790. .oprofile_cpu_type = "ppc/7450",
  791. .oprofile_type = PPC_OPROFILE_G4,
  792. .platform = "ppc7450",
  793. },
  794. { /* 7448 */
  795. .pvr_mask = 0xffff0000,
  796. .pvr_value = 0x80040000,
  797. .cpu_name = "7448",
  798. .cpu_features = CPU_FTRS_7447A,
  799. .cpu_user_features = COMMON_USER |
  800. PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,
  801. .icache_bsize = 32,
  802. .dcache_bsize = 32,
  803. .num_pmcs = 6,
  804. .cpu_setup = __setup_cpu_745x,
  805. .oprofile_cpu_type = "ppc/7450",
  806. .oprofile_type = PPC_OPROFILE_G4,
  807. .platform = "ppc7450",
  808. },
  809. { /* 82xx (8240, 8245, 8260 are all 603e cores) */
  810. .pvr_mask = 0x7fff0000,
  811. .pvr_value = 0x00810000,
  812. .cpu_name = "82xx",
  813. .cpu_features = CPU_FTRS_82XX,
  814. .cpu_user_features = COMMON_USER,
  815. .icache_bsize = 32,
  816. .dcache_bsize = 32,
  817. .cpu_setup = __setup_cpu_603,
  818. .platform = "ppc603",
  819. },
  820. { /* All G2_LE (603e core, plus some) have the same pvr */
  821. .pvr_mask = 0x7fff0000,
  822. .pvr_value = 0x00820000,
  823. .cpu_name = "G2_LE",
  824. .cpu_features = CPU_FTRS_G2_LE,
  825. .cpu_user_features = COMMON_USER,
  826. .icache_bsize = 32,
  827. .dcache_bsize = 32,
  828. .cpu_setup = __setup_cpu_603,
  829. .platform = "ppc603",
  830. },
  831. { /* e300c1 (a 603e core, plus some) on 83xx */
  832. .pvr_mask = 0x7fff0000,
  833. .pvr_value = 0x00830000,
  834. .cpu_name = "e300c1",
  835. .cpu_features = CPU_FTRS_E300,
  836. .cpu_user_features = COMMON_USER,
  837. .icache_bsize = 32,
  838. .dcache_bsize = 32,
  839. .cpu_setup = __setup_cpu_603,
  840. .platform = "ppc603",
  841. },
  842. { /* e300c2 (an e300c1 core, plus some, minus FPU) on 83xx */
  843. .pvr_mask = 0x7fff0000,
  844. .pvr_value = 0x00840000,
  845. .cpu_name = "e300c2",
  846. .cpu_features = CPU_FTRS_E300C2,
  847. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  848. .icache_bsize = 32,
  849. .dcache_bsize = 32,
  850. .cpu_setup = __setup_cpu_603,
  851. .platform = "ppc603",
  852. },
  853. { /* e300c3 on 83xx */
  854. .pvr_mask = 0x7fff0000,
  855. .pvr_value = 0x00850000,
  856. .cpu_name = "e300c3",
  857. .cpu_features = CPU_FTRS_E300,
  858. .cpu_user_features = COMMON_USER,
  859. .icache_bsize = 32,
  860. .dcache_bsize = 32,
  861. .cpu_setup = __setup_cpu_603,
  862. .platform = "ppc603",
  863. },
  864. { /* default match, we assume split I/D cache & TB (non-601)... */
  865. .pvr_mask = 0x00000000,
  866. .pvr_value = 0x00000000,
  867. .cpu_name = "(generic PPC)",
  868. .cpu_features = CPU_FTRS_CLASSIC32,
  869. .cpu_user_features = COMMON_USER,
  870. .icache_bsize = 32,
  871. .dcache_bsize = 32,
  872. .platform = "ppc603",
  873. },
  874. #endif /* CLASSIC_PPC */
  875. #ifdef CONFIG_8xx
  876. { /* 8xx */
  877. .pvr_mask = 0xffff0000,
  878. .pvr_value = 0x00500000,
  879. .cpu_name = "8xx",
  880. /* CPU_FTR_MAYBE_CAN_DOZE is possible,
  881. * if the 8xx code is there.... */
  882. .cpu_features = CPU_FTRS_8XX,
  883. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  884. .icache_bsize = 16,
  885. .dcache_bsize = 16,
  886. .platform = "ppc823",
  887. },
  888. #endif /* CONFIG_8xx */
  889. #ifdef CONFIG_40x
  890. { /* 403GC */
  891. .pvr_mask = 0xffffff00,
  892. .pvr_value = 0x00200200,
  893. .cpu_name = "403GC",
  894. .cpu_features = CPU_FTRS_40X,
  895. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  896. .icache_bsize = 16,
  897. .dcache_bsize = 16,
  898. .platform = "ppc403",
  899. },
  900. { /* 403GCX */
  901. .pvr_mask = 0xffffff00,
  902. .pvr_value = 0x00201400,
  903. .cpu_name = "403GCX",
  904. .cpu_features = CPU_FTRS_40X,
  905. .cpu_user_features = PPC_FEATURE_32 |
  906. PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB,
  907. .icache_bsize = 16,
  908. .dcache_bsize = 16,
  909. .platform = "ppc403",
  910. },
  911. { /* 403G ?? */
  912. .pvr_mask = 0xffff0000,
  913. .pvr_value = 0x00200000,
  914. .cpu_name = "403G ??",
  915. .cpu_features = CPU_FTRS_40X,
  916. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  917. .icache_bsize = 16,
  918. .dcache_bsize = 16,
  919. .platform = "ppc403",
  920. },
  921. { /* 405GP */
  922. .pvr_mask = 0xffff0000,
  923. .pvr_value = 0x40110000,
  924. .cpu_name = "405GP",
  925. .cpu_features = CPU_FTRS_40X,
  926. .cpu_user_features = PPC_FEATURE_32 |
  927. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  928. .icache_bsize = 32,
  929. .dcache_bsize = 32,
  930. .platform = "ppc405",
  931. },
  932. { /* STB 03xxx */
  933. .pvr_mask = 0xffff0000,
  934. .pvr_value = 0x40130000,
  935. .cpu_name = "STB03xxx",
  936. .cpu_features = CPU_FTRS_40X,
  937. .cpu_user_features = PPC_FEATURE_32 |
  938. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  939. .icache_bsize = 32,
  940. .dcache_bsize = 32,
  941. .platform = "ppc405",
  942. },
  943. { /* STB 04xxx */
  944. .pvr_mask = 0xffff0000,
  945. .pvr_value = 0x41810000,
  946. .cpu_name = "STB04xxx",
  947. .cpu_features = CPU_FTRS_40X,
  948. .cpu_user_features = PPC_FEATURE_32 |
  949. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  950. .icache_bsize = 32,
  951. .dcache_bsize = 32,
  952. .platform = "ppc405",
  953. },
  954. { /* NP405L */
  955. .pvr_mask = 0xffff0000,
  956. .pvr_value = 0x41610000,
  957. .cpu_name = "NP405L",
  958. .cpu_features = CPU_FTRS_40X,
  959. .cpu_user_features = PPC_FEATURE_32 |
  960. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  961. .icache_bsize = 32,
  962. .dcache_bsize = 32,
  963. .platform = "ppc405",
  964. },
  965. { /* NP4GS3 */
  966. .pvr_mask = 0xffff0000,
  967. .pvr_value = 0x40B10000,
  968. .cpu_name = "NP4GS3",
  969. .cpu_features = CPU_FTRS_40X,
  970. .cpu_user_features = PPC_FEATURE_32 |
  971. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  972. .icache_bsize = 32,
  973. .dcache_bsize = 32,
  974. .platform = "ppc405",
  975. },
  976. { /* NP405H */
  977. .pvr_mask = 0xffff0000,
  978. .pvr_value = 0x41410000,
  979. .cpu_name = "NP405H",
  980. .cpu_features = CPU_FTRS_40X,
  981. .cpu_user_features = PPC_FEATURE_32 |
  982. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  983. .icache_bsize = 32,
  984. .dcache_bsize = 32,
  985. .platform = "ppc405",
  986. },
  987. { /* 405GPr */
  988. .pvr_mask = 0xffff0000,
  989. .pvr_value = 0x50910000,
  990. .cpu_name = "405GPr",
  991. .cpu_features = CPU_FTRS_40X,
  992. .cpu_user_features = PPC_FEATURE_32 |
  993. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  994. .icache_bsize = 32,
  995. .dcache_bsize = 32,
  996. .platform = "ppc405",
  997. },
  998. { /* STBx25xx */
  999. .pvr_mask = 0xffff0000,
  1000. .pvr_value = 0x51510000,
  1001. .cpu_name = "STBx25xx",
  1002. .cpu_features = CPU_FTRS_40X,
  1003. .cpu_user_features = PPC_FEATURE_32 |
  1004. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1005. .icache_bsize = 32,
  1006. .dcache_bsize = 32,
  1007. .platform = "ppc405",
  1008. },
  1009. { /* 405LP */
  1010. .pvr_mask = 0xffff0000,
  1011. .pvr_value = 0x41F10000,
  1012. .cpu_name = "405LP",
  1013. .cpu_features = CPU_FTRS_40X,
  1014. .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
  1015. .icache_bsize = 32,
  1016. .dcache_bsize = 32,
  1017. .platform = "ppc405",
  1018. },
  1019. { /* Xilinx Virtex-II Pro */
  1020. .pvr_mask = 0xfffff000,
  1021. .pvr_value = 0x20010000,
  1022. .cpu_name = "Virtex-II Pro",
  1023. .cpu_features = CPU_FTRS_40X,
  1024. .cpu_user_features = PPC_FEATURE_32 |
  1025. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1026. .icache_bsize = 32,
  1027. .dcache_bsize = 32,
  1028. .platform = "ppc405",
  1029. },
  1030. { /* Xilinx Virtex-4 FX */
  1031. .pvr_mask = 0xfffff000,
  1032. .pvr_value = 0x20011000,
  1033. .cpu_name = "Virtex-4 FX",
  1034. .cpu_features = CPU_FTRS_40X,
  1035. .cpu_user_features = PPC_FEATURE_32 |
  1036. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1037. .icache_bsize = 32,
  1038. .dcache_bsize = 32,
  1039. .platform = "ppc405",
  1040. },
  1041. { /* 405EP */
  1042. .pvr_mask = 0xffff0000,
  1043. .pvr_value = 0x51210000,
  1044. .cpu_name = "405EP",
  1045. .cpu_features = CPU_FTRS_40X,
  1046. .cpu_user_features = PPC_FEATURE_32 |
  1047. PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
  1048. .icache_bsize = 32,
  1049. .dcache_bsize = 32,
  1050. .platform = "ppc405",
  1051. },
  1052. #endif /* CONFIG_40x */
  1053. #ifdef CONFIG_44x
  1054. {
  1055. .pvr_mask = 0xf0000fff,
  1056. .pvr_value = 0x40000850,
  1057. .cpu_name = "440EP Rev. A",
  1058. .cpu_features = CPU_FTRS_44X,
  1059. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1060. .icache_bsize = 32,
  1061. .dcache_bsize = 32,
  1062. .platform = "ppc440",
  1063. },
  1064. {
  1065. .pvr_mask = 0xf0000fff,
  1066. .pvr_value = 0x400008d3,
  1067. .cpu_name = "440EP Rev. B",
  1068. .cpu_features = CPU_FTRS_44X,
  1069. .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
  1070. .icache_bsize = 32,
  1071. .dcache_bsize = 32,
  1072. .platform = "ppc440",
  1073. },
  1074. { /* 440GP Rev. B */
  1075. .pvr_mask = 0xf0000fff,
  1076. .pvr_value = 0x40000440,
  1077. .cpu_name = "440GP Rev. B",
  1078. .cpu_features = CPU_FTRS_44X,
  1079. .cpu_user_features = COMMON_USER_BOOKE,
  1080. .icache_bsize = 32,
  1081. .dcache_bsize = 32,
  1082. .platform = "ppc440gp",
  1083. },
  1084. { /* 440GP Rev. C */
  1085. .pvr_mask = 0xf0000fff,
  1086. .pvr_value = 0x40000481,
  1087. .cpu_name = "440GP Rev. C",
  1088. .cpu_features = CPU_FTRS_44X,
  1089. .cpu_user_features = COMMON_USER_BOOKE,
  1090. .icache_bsize = 32,
  1091. .dcache_bsize = 32,
  1092. .platform = "ppc440gp",
  1093. },
  1094. { /* 440GX Rev. A */
  1095. .pvr_mask = 0xf0000fff,
  1096. .pvr_value = 0x50000850,
  1097. .cpu_name = "440GX Rev. A",
  1098. .cpu_features = CPU_FTRS_44X,
  1099. .cpu_user_features = COMMON_USER_BOOKE,
  1100. .icache_bsize = 32,
  1101. .dcache_bsize = 32,
  1102. .platform = "ppc440",
  1103. },
  1104. { /* 440GX Rev. B */
  1105. .pvr_mask = 0xf0000fff,
  1106. .pvr_value = 0x50000851,
  1107. .cpu_name = "440GX Rev. B",
  1108. .cpu_features = CPU_FTRS_44X,
  1109. .cpu_user_features = COMMON_USER_BOOKE,
  1110. .icache_bsize = 32,
  1111. .dcache_bsize = 32,
  1112. .platform = "ppc440",
  1113. },
  1114. { /* 440GX Rev. C */
  1115. .pvr_mask = 0xf0000fff,
  1116. .pvr_value = 0x50000892,
  1117. .cpu_name = "440GX Rev. C",
  1118. .cpu_features = CPU_FTRS_44X,
  1119. .cpu_user_features = COMMON_USER_BOOKE,
  1120. .icache_bsize = 32,
  1121. .dcache_bsize = 32,
  1122. .platform = "ppc440",
  1123. },
  1124. { /* 440GX Rev. F */
  1125. .pvr_mask = 0xf0000fff,
  1126. .pvr_value = 0x50000894,
  1127. .cpu_name = "440GX Rev. F",
  1128. .cpu_features = CPU_FTRS_44X,
  1129. .cpu_user_features = COMMON_USER_BOOKE,
  1130. .icache_bsize = 32,
  1131. .dcache_bsize = 32,
  1132. .platform = "ppc440",
  1133. },
  1134. { /* 440SP Rev. A */
  1135. .pvr_mask = 0xff000fff,
  1136. .pvr_value = 0x53000891,
  1137. .cpu_name = "440SP Rev. A",
  1138. .cpu_features = CPU_FTRS_44X,
  1139. .cpu_user_features = COMMON_USER_BOOKE,
  1140. .icache_bsize = 32,
  1141. .dcache_bsize = 32,
  1142. .platform = "ppc440",
  1143. },
  1144. { /* 440SPe Rev. A */
  1145. .pvr_mask = 0xff000fff,
  1146. .pvr_value = 0x53000890,
  1147. .cpu_name = "440SPe Rev. A",
  1148. .cpu_features = CPU_FTRS_44X,
  1149. .cpu_user_features = COMMON_USER_BOOKE,
  1150. .icache_bsize = 32,
  1151. .dcache_bsize = 32,
  1152. .platform = "ppc440",
  1153. },
  1154. #endif /* CONFIG_44x */
  1155. #ifdef CONFIG_FSL_BOOKE
  1156. { /* e200z5 */
  1157. .pvr_mask = 0xfff00000,
  1158. .pvr_value = 0x81000000,
  1159. .cpu_name = "e200z5",
  1160. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1161. .cpu_features = CPU_FTRS_E200,
  1162. .cpu_user_features = COMMON_USER_BOOKE |
  1163. PPC_FEATURE_HAS_EFP_SINGLE |
  1164. PPC_FEATURE_UNIFIED_CACHE,
  1165. .dcache_bsize = 32,
  1166. .platform = "ppc5554",
  1167. },
  1168. { /* e200z6 */
  1169. .pvr_mask = 0xfff00000,
  1170. .pvr_value = 0x81100000,
  1171. .cpu_name = "e200z6",
  1172. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1173. .cpu_features = CPU_FTRS_E200,
  1174. .cpu_user_features = COMMON_USER_BOOKE |
  1175. PPC_FEATURE_SPE_COMP |
  1176. PPC_FEATURE_HAS_EFP_SINGLE |
  1177. PPC_FEATURE_UNIFIED_CACHE,
  1178. .dcache_bsize = 32,
  1179. .platform = "ppc5554",
  1180. },
  1181. { /* e500 */
  1182. .pvr_mask = 0xffff0000,
  1183. .pvr_value = 0x80200000,
  1184. .cpu_name = "e500",
  1185. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1186. .cpu_features = CPU_FTRS_E500,
  1187. .cpu_user_features = COMMON_USER_BOOKE |
  1188. PPC_FEATURE_SPE_COMP |
  1189. PPC_FEATURE_HAS_EFP_SINGLE,
  1190. .icache_bsize = 32,
  1191. .dcache_bsize = 32,
  1192. .num_pmcs = 4,
  1193. .oprofile_cpu_type = "ppc/e500",
  1194. .oprofile_type = PPC_OPROFILE_BOOKE,
  1195. .platform = "ppc8540",
  1196. },
  1197. { /* e500v2 */
  1198. .pvr_mask = 0xffff0000,
  1199. .pvr_value = 0x80210000,
  1200. .cpu_name = "e500v2",
  1201. /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
  1202. .cpu_features = CPU_FTRS_E500_2,
  1203. .cpu_user_features = COMMON_USER_BOOKE |
  1204. PPC_FEATURE_SPE_COMP |
  1205. PPC_FEATURE_HAS_EFP_SINGLE |
  1206. PPC_FEATURE_HAS_EFP_DOUBLE,
  1207. .icache_bsize = 32,
  1208. .dcache_bsize = 32,
  1209. .num_pmcs = 4,
  1210. .oprofile_cpu_type = "ppc/e500",
  1211. .oprofile_type = PPC_OPROFILE_BOOKE,
  1212. .platform = "ppc8548",
  1213. },
  1214. #endif
  1215. #if !CLASSIC_PPC
  1216. { /* default match */
  1217. .pvr_mask = 0x00000000,
  1218. .pvr_value = 0x00000000,
  1219. .cpu_name = "(generic PPC)",
  1220. .cpu_features = CPU_FTRS_GENERIC_32,
  1221. .cpu_user_features = PPC_FEATURE_32,
  1222. .icache_bsize = 32,
  1223. .dcache_bsize = 32,
  1224. .platform = "powerpc",
  1225. }
  1226. #endif /* !CLASSIC_PPC */
  1227. #endif /* CONFIG_PPC32 */
  1228. };
  1229. struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr)
  1230. {
  1231. struct cpu_spec *s = cpu_specs;
  1232. struct cpu_spec **cur = &cur_cpu_spec;
  1233. int i;
  1234. s = PTRRELOC(s);
  1235. cur = PTRRELOC(cur);
  1236. for (i = 0; i < ARRAY_SIZE(cpu_specs); i++,s++)
  1237. if ((pvr & s->pvr_mask) == s->pvr_value) {
  1238. *cur = cpu_specs + i;
  1239. #ifdef CONFIG_PPC64
  1240. /* ppc64 expects identify_cpu to also call setup_cpu
  1241. * for that processor. I will consolidate that at a
  1242. * later time, for now, just use our friend #ifdef.
  1243. * we also don't need to PTRRELOC the function pointer
  1244. * on ppc64 as we are running at 0 in real mode.
  1245. */
  1246. if (s->cpu_setup) {
  1247. s->cpu_setup(offset, s);
  1248. }
  1249. #endif /* CONFIG_PPC64 */
  1250. return s;
  1251. }
  1252. BUG();
  1253. return NULL;
  1254. }
  1255. void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
  1256. {
  1257. struct fixup_entry {
  1258. unsigned long mask;
  1259. unsigned long value;
  1260. long start_off;
  1261. long end_off;
  1262. } *fcur, *fend;
  1263. fcur = fixup_start;
  1264. fend = fixup_end;
  1265. for (; fcur < fend; fcur++) {
  1266. unsigned int *pstart, *pend, *p;
  1267. if ((value & fcur->mask) == fcur->value)
  1268. continue;
  1269. /* These PTRRELOCs will disappear once the new scheme for
  1270. * modules and vdso is implemented
  1271. */
  1272. pstart = ((unsigned int *)fcur) + (fcur->start_off / 4);
  1273. pend = ((unsigned int *)fcur) + (fcur->end_off / 4);
  1274. for (p = pstart; p < pend; p++) {
  1275. *p = 0x60000000u;
  1276. asm volatile ("dcbst 0, %0" : : "r" (p));
  1277. }
  1278. asm volatile ("sync" : : : "memory");
  1279. for (p = pstart; p < pend; p++)
  1280. asm volatile ("icbi 0,%0" : : "r" (p));
  1281. asm volatile ("sync; isync" : : : "memory");
  1282. }
  1283. }