netxen_nic_init.c 40 KB

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  1. /*
  2. * Copyright (C) 2003 - 2009 NetXen, Inc.
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18. * MA 02111-1307, USA.
  19. *
  20. * The full GNU General Public License is included in this distribution
  21. * in the file called LICENSE.
  22. *
  23. * Contact Information:
  24. * info@netxen.com
  25. * NetXen Inc,
  26. * 18922 Forge Drive
  27. * Cupertino, CA 95014-0701
  28. *
  29. */
  30. #include <linux/netdevice.h>
  31. #include <linux/delay.h>
  32. #include "netxen_nic.h"
  33. #include "netxen_nic_hw.h"
  34. #include "netxen_nic_phan_reg.h"
  35. struct crb_addr_pair {
  36. u32 addr;
  37. u32 data;
  38. };
  39. #define NETXEN_MAX_CRB_XFORM 60
  40. static unsigned int crb_addr_xform[NETXEN_MAX_CRB_XFORM];
  41. #define NETXEN_ADDR_ERROR (0xffffffff)
  42. #define crb_addr_transform(name) \
  43. crb_addr_xform[NETXEN_HW_PX_MAP_CRB_##name] = \
  44. NETXEN_HW_CRB_HUB_AGT_ADR_##name << 20
  45. #define NETXEN_NIC_XDMA_RESET 0x8000ff
  46. static void
  47. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  48. struct nx_host_rds_ring *rds_ring);
  49. static void crb_addr_transform_setup(void)
  50. {
  51. crb_addr_transform(XDMA);
  52. crb_addr_transform(TIMR);
  53. crb_addr_transform(SRE);
  54. crb_addr_transform(SQN3);
  55. crb_addr_transform(SQN2);
  56. crb_addr_transform(SQN1);
  57. crb_addr_transform(SQN0);
  58. crb_addr_transform(SQS3);
  59. crb_addr_transform(SQS2);
  60. crb_addr_transform(SQS1);
  61. crb_addr_transform(SQS0);
  62. crb_addr_transform(RPMX7);
  63. crb_addr_transform(RPMX6);
  64. crb_addr_transform(RPMX5);
  65. crb_addr_transform(RPMX4);
  66. crb_addr_transform(RPMX3);
  67. crb_addr_transform(RPMX2);
  68. crb_addr_transform(RPMX1);
  69. crb_addr_transform(RPMX0);
  70. crb_addr_transform(ROMUSB);
  71. crb_addr_transform(SN);
  72. crb_addr_transform(QMN);
  73. crb_addr_transform(QMS);
  74. crb_addr_transform(PGNI);
  75. crb_addr_transform(PGND);
  76. crb_addr_transform(PGN3);
  77. crb_addr_transform(PGN2);
  78. crb_addr_transform(PGN1);
  79. crb_addr_transform(PGN0);
  80. crb_addr_transform(PGSI);
  81. crb_addr_transform(PGSD);
  82. crb_addr_transform(PGS3);
  83. crb_addr_transform(PGS2);
  84. crb_addr_transform(PGS1);
  85. crb_addr_transform(PGS0);
  86. crb_addr_transform(PS);
  87. crb_addr_transform(PH);
  88. crb_addr_transform(NIU);
  89. crb_addr_transform(I2Q);
  90. crb_addr_transform(EG);
  91. crb_addr_transform(MN);
  92. crb_addr_transform(MS);
  93. crb_addr_transform(CAS2);
  94. crb_addr_transform(CAS1);
  95. crb_addr_transform(CAS0);
  96. crb_addr_transform(CAM);
  97. crb_addr_transform(C2C1);
  98. crb_addr_transform(C2C0);
  99. crb_addr_transform(SMB);
  100. crb_addr_transform(OCM0);
  101. crb_addr_transform(I2C0);
  102. }
  103. void netxen_release_rx_buffers(struct netxen_adapter *adapter)
  104. {
  105. struct netxen_recv_context *recv_ctx;
  106. struct nx_host_rds_ring *rds_ring;
  107. struct netxen_rx_buffer *rx_buf;
  108. int i, ring;
  109. recv_ctx = &adapter->recv_ctx;
  110. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  111. rds_ring = &recv_ctx->rds_rings[ring];
  112. for (i = 0; i < rds_ring->num_desc; ++i) {
  113. rx_buf = &(rds_ring->rx_buf_arr[i]);
  114. if (rx_buf->state == NETXEN_BUFFER_FREE)
  115. continue;
  116. pci_unmap_single(adapter->pdev,
  117. rx_buf->dma,
  118. rds_ring->dma_size,
  119. PCI_DMA_FROMDEVICE);
  120. if (rx_buf->skb != NULL)
  121. dev_kfree_skb_any(rx_buf->skb);
  122. }
  123. }
  124. }
  125. void netxen_release_tx_buffers(struct netxen_adapter *adapter)
  126. {
  127. struct netxen_cmd_buffer *cmd_buf;
  128. struct netxen_skb_frag *buffrag;
  129. int i, j;
  130. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  131. cmd_buf = tx_ring->cmd_buf_arr;
  132. for (i = 0; i < tx_ring->num_desc; i++) {
  133. buffrag = cmd_buf->frag_array;
  134. if (buffrag->dma) {
  135. pci_unmap_single(adapter->pdev, buffrag->dma,
  136. buffrag->length, PCI_DMA_TODEVICE);
  137. buffrag->dma = 0ULL;
  138. }
  139. for (j = 0; j < cmd_buf->frag_count; j++) {
  140. buffrag++;
  141. if (buffrag->dma) {
  142. pci_unmap_page(adapter->pdev, buffrag->dma,
  143. buffrag->length,
  144. PCI_DMA_TODEVICE);
  145. buffrag->dma = 0ULL;
  146. }
  147. }
  148. if (cmd_buf->skb) {
  149. dev_kfree_skb_any(cmd_buf->skb);
  150. cmd_buf->skb = NULL;
  151. }
  152. cmd_buf++;
  153. }
  154. }
  155. void netxen_free_sw_resources(struct netxen_adapter *adapter)
  156. {
  157. struct netxen_recv_context *recv_ctx;
  158. struct nx_host_rds_ring *rds_ring;
  159. struct nx_host_tx_ring *tx_ring;
  160. int ring;
  161. recv_ctx = &adapter->recv_ctx;
  162. if (recv_ctx->rds_rings == NULL)
  163. goto skip_rds;
  164. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  165. rds_ring = &recv_ctx->rds_rings[ring];
  166. vfree(rds_ring->rx_buf_arr);
  167. rds_ring->rx_buf_arr = NULL;
  168. }
  169. kfree(recv_ctx->rds_rings);
  170. skip_rds:
  171. if (adapter->tx_ring == NULL)
  172. return;
  173. tx_ring = adapter->tx_ring;
  174. vfree(tx_ring->cmd_buf_arr);
  175. }
  176. int netxen_alloc_sw_resources(struct netxen_adapter *adapter)
  177. {
  178. struct netxen_recv_context *recv_ctx;
  179. struct nx_host_rds_ring *rds_ring;
  180. struct nx_host_sds_ring *sds_ring;
  181. struct nx_host_tx_ring *tx_ring;
  182. struct netxen_rx_buffer *rx_buf;
  183. int ring, i, size;
  184. struct netxen_cmd_buffer *cmd_buf_arr;
  185. struct net_device *netdev = adapter->netdev;
  186. struct pci_dev *pdev = adapter->pdev;
  187. size = sizeof(struct nx_host_tx_ring);
  188. tx_ring = kzalloc(size, GFP_KERNEL);
  189. if (tx_ring == NULL) {
  190. dev_err(&pdev->dev, "%s: failed to allocate tx ring struct\n",
  191. netdev->name);
  192. return -ENOMEM;
  193. }
  194. adapter->tx_ring = tx_ring;
  195. tx_ring->num_desc = adapter->num_txd;
  196. tx_ring->txq = netdev_get_tx_queue(netdev, 0);
  197. cmd_buf_arr = vmalloc(TX_BUFF_RINGSIZE(tx_ring));
  198. if (cmd_buf_arr == NULL) {
  199. dev_err(&pdev->dev, "%s: failed to allocate cmd buffer ring\n",
  200. netdev->name);
  201. return -ENOMEM;
  202. }
  203. memset(cmd_buf_arr, 0, TX_BUFF_RINGSIZE(tx_ring));
  204. tx_ring->cmd_buf_arr = cmd_buf_arr;
  205. recv_ctx = &adapter->recv_ctx;
  206. size = adapter->max_rds_rings * sizeof (struct nx_host_rds_ring);
  207. rds_ring = kzalloc(size, GFP_KERNEL);
  208. if (rds_ring == NULL) {
  209. dev_err(&pdev->dev, "%s: failed to allocate rds ring struct\n",
  210. netdev->name);
  211. return -ENOMEM;
  212. }
  213. recv_ctx->rds_rings = rds_ring;
  214. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  215. rds_ring = &recv_ctx->rds_rings[ring];
  216. switch (ring) {
  217. case RCV_RING_NORMAL:
  218. rds_ring->num_desc = adapter->num_rxd;
  219. if (adapter->ahw.cut_through) {
  220. rds_ring->dma_size =
  221. NX_CT_DEFAULT_RX_BUF_LEN;
  222. rds_ring->skb_size =
  223. NX_CT_DEFAULT_RX_BUF_LEN;
  224. } else {
  225. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  226. rds_ring->dma_size =
  227. NX_P3_RX_BUF_MAX_LEN;
  228. else
  229. rds_ring->dma_size =
  230. NX_P2_RX_BUF_MAX_LEN;
  231. rds_ring->skb_size =
  232. rds_ring->dma_size + NET_IP_ALIGN;
  233. }
  234. break;
  235. case RCV_RING_JUMBO:
  236. rds_ring->num_desc = adapter->num_jumbo_rxd;
  237. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  238. rds_ring->dma_size =
  239. NX_P3_RX_JUMBO_BUF_MAX_LEN;
  240. else
  241. rds_ring->dma_size =
  242. NX_P2_RX_JUMBO_BUF_MAX_LEN;
  243. rds_ring->skb_size =
  244. rds_ring->dma_size + NET_IP_ALIGN;
  245. break;
  246. case RCV_RING_LRO:
  247. rds_ring->num_desc = adapter->num_lro_rxd;
  248. rds_ring->dma_size = NX_RX_LRO_BUFFER_LENGTH;
  249. rds_ring->skb_size = rds_ring->dma_size + NET_IP_ALIGN;
  250. break;
  251. }
  252. rds_ring->rx_buf_arr = (struct netxen_rx_buffer *)
  253. vmalloc(RCV_BUFF_RINGSIZE(rds_ring));
  254. if (rds_ring->rx_buf_arr == NULL) {
  255. printk(KERN_ERR "%s: Failed to allocate "
  256. "rx buffer ring %d\n",
  257. netdev->name, ring);
  258. /* free whatever was already allocated */
  259. goto err_out;
  260. }
  261. memset(rds_ring->rx_buf_arr, 0, RCV_BUFF_RINGSIZE(rds_ring));
  262. INIT_LIST_HEAD(&rds_ring->free_list);
  263. /*
  264. * Now go through all of them, set reference handles
  265. * and put them in the queues.
  266. */
  267. rx_buf = rds_ring->rx_buf_arr;
  268. for (i = 0; i < rds_ring->num_desc; i++) {
  269. list_add_tail(&rx_buf->list,
  270. &rds_ring->free_list);
  271. rx_buf->ref_handle = i;
  272. rx_buf->state = NETXEN_BUFFER_FREE;
  273. rx_buf++;
  274. }
  275. spin_lock_init(&rds_ring->lock);
  276. }
  277. for (ring = 0; ring < adapter->max_sds_rings; ring++) {
  278. sds_ring = &recv_ctx->sds_rings[ring];
  279. sds_ring->irq = adapter->msix_entries[ring].vector;
  280. sds_ring->adapter = adapter;
  281. sds_ring->num_desc = adapter->num_rxd;
  282. for (i = 0; i < NUM_RCV_DESC_RINGS; i++)
  283. INIT_LIST_HEAD(&sds_ring->free_list[i]);
  284. }
  285. return 0;
  286. err_out:
  287. netxen_free_sw_resources(adapter);
  288. return -ENOMEM;
  289. }
  290. void netxen_initialize_adapter_ops(struct netxen_adapter *adapter)
  291. {
  292. adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
  293. adapter->set_multi = netxen_p2_nic_set_multi;
  294. switch (adapter->ahw.port_type) {
  295. case NETXEN_NIC_GBE:
  296. adapter->enable_phy_interrupts =
  297. netxen_niu_gbe_enable_phy_interrupts;
  298. adapter->disable_phy_interrupts =
  299. netxen_niu_gbe_disable_phy_interrupts;
  300. adapter->set_mtu = netxen_nic_set_mtu_gb;
  301. adapter->set_promisc = netxen_niu_set_promiscuous_mode;
  302. adapter->phy_read = netxen_niu_gbe_phy_read;
  303. adapter->phy_write = netxen_niu_gbe_phy_write;
  304. adapter->init_port = netxen_niu_gbe_init_port;
  305. adapter->stop_port = netxen_niu_disable_gbe_port;
  306. break;
  307. case NETXEN_NIC_XGBE:
  308. adapter->enable_phy_interrupts =
  309. netxen_niu_xgbe_enable_phy_interrupts;
  310. adapter->disable_phy_interrupts =
  311. netxen_niu_xgbe_disable_phy_interrupts;
  312. adapter->set_mtu = netxen_nic_set_mtu_xgb;
  313. adapter->init_port = netxen_niu_xg_init_port;
  314. adapter->set_promisc = netxen_niu_xg_set_promiscuous_mode;
  315. adapter->stop_port = netxen_niu_disable_xg_port;
  316. break;
  317. default:
  318. break;
  319. }
  320. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  321. adapter->set_mtu = nx_fw_cmd_set_mtu;
  322. adapter->set_promisc = netxen_p3_nic_set_promisc;
  323. adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
  324. adapter->set_multi = netxen_p3_nic_set_multi;
  325. }
  326. }
  327. /*
  328. * netxen_decode_crb_addr(0 - utility to translate from internal Phantom CRB
  329. * address to external PCI CRB address.
  330. */
  331. static u32 netxen_decode_crb_addr(u32 addr)
  332. {
  333. int i;
  334. u32 base_addr, offset, pci_base;
  335. crb_addr_transform_setup();
  336. pci_base = NETXEN_ADDR_ERROR;
  337. base_addr = addr & 0xfff00000;
  338. offset = addr & 0x000fffff;
  339. for (i = 0; i < NETXEN_MAX_CRB_XFORM; i++) {
  340. if (crb_addr_xform[i] == base_addr) {
  341. pci_base = i << 20;
  342. break;
  343. }
  344. }
  345. if (pci_base == NETXEN_ADDR_ERROR)
  346. return pci_base;
  347. else
  348. return (pci_base + offset);
  349. }
  350. static long rom_max_timeout = 100;
  351. static long rom_lock_timeout = 10000;
  352. static int rom_lock(struct netxen_adapter *adapter)
  353. {
  354. int iter;
  355. u32 done = 0;
  356. int timeout = 0;
  357. while (!done) {
  358. /* acquire semaphore2 from PCI HW block */
  359. done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_LOCK));
  360. if (done == 1)
  361. break;
  362. if (timeout >= rom_lock_timeout)
  363. return -EIO;
  364. timeout++;
  365. /*
  366. * Yield CPU
  367. */
  368. if (!in_atomic())
  369. schedule();
  370. else {
  371. for (iter = 0; iter < 20; iter++)
  372. cpu_relax(); /*This a nop instr on i386 */
  373. }
  374. }
  375. NXWR32(adapter, NETXEN_ROM_LOCK_ID, ROM_LOCK_DRIVER);
  376. return 0;
  377. }
  378. static int netxen_wait_rom_done(struct netxen_adapter *adapter)
  379. {
  380. long timeout = 0;
  381. long done = 0;
  382. cond_resched();
  383. while (done == 0) {
  384. done = NXRD32(adapter, NETXEN_ROMUSB_GLB_STATUS);
  385. done &= 2;
  386. timeout++;
  387. if (timeout >= rom_max_timeout) {
  388. printk("Timeout reached waiting for rom done");
  389. return -EIO;
  390. }
  391. }
  392. return 0;
  393. }
  394. static void netxen_rom_unlock(struct netxen_adapter *adapter)
  395. {
  396. /* release semaphore2 */
  397. NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM2_UNLOCK));
  398. }
  399. static int do_rom_fast_read(struct netxen_adapter *adapter,
  400. int addr, int *valp)
  401. {
  402. NXWR32(adapter, NETXEN_ROMUSB_ROM_ADDRESS, addr);
  403. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  404. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 3);
  405. NXWR32(adapter, NETXEN_ROMUSB_ROM_INSTR_OPCODE, 0xb);
  406. if (netxen_wait_rom_done(adapter)) {
  407. printk("Error waiting for rom done\n");
  408. return -EIO;
  409. }
  410. /* reset abyte_cnt and dummy_byte_cnt */
  411. NXWR32(adapter, NETXEN_ROMUSB_ROM_ABYTE_CNT, 0);
  412. udelay(10);
  413. NXWR32(adapter, NETXEN_ROMUSB_ROM_DUMMY_BYTE_CNT, 0);
  414. *valp = NXRD32(adapter, NETXEN_ROMUSB_ROM_RDATA);
  415. return 0;
  416. }
  417. static int do_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  418. u8 *bytes, size_t size)
  419. {
  420. int addridx;
  421. int ret = 0;
  422. for (addridx = addr; addridx < (addr + size); addridx += 4) {
  423. int v;
  424. ret = do_rom_fast_read(adapter, addridx, &v);
  425. if (ret != 0)
  426. break;
  427. *(__le32 *)bytes = cpu_to_le32(v);
  428. bytes += 4;
  429. }
  430. return ret;
  431. }
  432. int
  433. netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
  434. u8 *bytes, size_t size)
  435. {
  436. int ret;
  437. ret = rom_lock(adapter);
  438. if (ret < 0)
  439. return ret;
  440. ret = do_rom_fast_read_words(adapter, addr, bytes, size);
  441. netxen_rom_unlock(adapter);
  442. return ret;
  443. }
  444. int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp)
  445. {
  446. int ret;
  447. if (rom_lock(adapter) != 0)
  448. return -EIO;
  449. ret = do_rom_fast_read(adapter, addr, valp);
  450. netxen_rom_unlock(adapter);
  451. return ret;
  452. }
  453. #define NETXEN_BOARDTYPE 0x4008
  454. #define NETXEN_BOARDNUM 0x400c
  455. #define NETXEN_CHIPNUM 0x4010
  456. int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose)
  457. {
  458. int addr, val;
  459. int i, n, init_delay = 0;
  460. struct crb_addr_pair *buf;
  461. unsigned offset;
  462. u32 off;
  463. /* resetall */
  464. rom_lock(adapter);
  465. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0xffffffff);
  466. netxen_rom_unlock(adapter);
  467. if (verbose) {
  468. if (netxen_rom_fast_read(adapter, NETXEN_BOARDTYPE, &val) == 0)
  469. printk("P2 ROM board type: 0x%08x\n", val);
  470. else
  471. printk("Could not read board type\n");
  472. if (netxen_rom_fast_read(adapter, NETXEN_BOARDNUM, &val) == 0)
  473. printk("P2 ROM board num: 0x%08x\n", val);
  474. else
  475. printk("Could not read board number\n");
  476. if (netxen_rom_fast_read(adapter, NETXEN_CHIPNUM, &val) == 0)
  477. printk("P2 ROM chip num: 0x%08x\n", val);
  478. else
  479. printk("Could not read chip number\n");
  480. }
  481. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  482. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  483. (n != 0xcafecafe) ||
  484. netxen_rom_fast_read(adapter, 4, &n) != 0) {
  485. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  486. "n: %08x\n", netxen_nic_driver_name, n);
  487. return -EIO;
  488. }
  489. offset = n & 0xffffU;
  490. n = (n >> 16) & 0xffffU;
  491. } else {
  492. if (netxen_rom_fast_read(adapter, 0, &n) != 0 ||
  493. !(n & 0x80000000)) {
  494. printk(KERN_ERR "%s: ERROR Reading crb_init area: "
  495. "n: %08x\n", netxen_nic_driver_name, n);
  496. return -EIO;
  497. }
  498. offset = 1;
  499. n &= ~0x80000000;
  500. }
  501. if (n < 1024) {
  502. if (verbose)
  503. printk(KERN_DEBUG "%s: %d CRB init values found"
  504. " in ROM.\n", netxen_nic_driver_name, n);
  505. } else {
  506. printk(KERN_ERR "%s:n=0x%x Error! NetXen card flash not"
  507. " initialized.\n", __func__, n);
  508. return -EIO;
  509. }
  510. buf = kcalloc(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
  511. if (buf == NULL) {
  512. printk("%s: netxen_pinit_from_rom: Unable to calloc memory.\n",
  513. netxen_nic_driver_name);
  514. return -ENOMEM;
  515. }
  516. for (i = 0; i < n; i++) {
  517. if (netxen_rom_fast_read(adapter, 8*i + 4*offset, &val) != 0 ||
  518. netxen_rom_fast_read(adapter, 8*i + 4*offset + 4, &addr) != 0) {
  519. kfree(buf);
  520. return -EIO;
  521. }
  522. buf[i].addr = addr;
  523. buf[i].data = val;
  524. if (verbose)
  525. printk(KERN_DEBUG "%s: PCI: 0x%08x == 0x%08x\n",
  526. netxen_nic_driver_name,
  527. (u32)netxen_decode_crb_addr(addr), val);
  528. }
  529. for (i = 0; i < n; i++) {
  530. off = netxen_decode_crb_addr(buf[i].addr);
  531. if (off == NETXEN_ADDR_ERROR) {
  532. printk(KERN_ERR"CRB init value out of range %x\n",
  533. buf[i].addr);
  534. continue;
  535. }
  536. off += NETXEN_PCI_CRBSPACE;
  537. /* skipping cold reboot MAGIC */
  538. if (off == NETXEN_CAM_RAM(0x1fc))
  539. continue;
  540. if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
  541. /* do not reset PCI */
  542. if (off == (ROMUSB_GLB + 0xbc))
  543. continue;
  544. if (off == (ROMUSB_GLB + 0xa8))
  545. continue;
  546. if (off == (ROMUSB_GLB + 0xc8)) /* core clock */
  547. continue;
  548. if (off == (ROMUSB_GLB + 0x24)) /* MN clock */
  549. continue;
  550. if (off == (ROMUSB_GLB + 0x1c)) /* MS clock */
  551. continue;
  552. if (off == (NETXEN_CRB_PEG_NET_1 + 0x18))
  553. buf[i].data = 0x1020;
  554. /* skip the function enable register */
  555. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION))
  556. continue;
  557. if (off == NETXEN_PCIE_REG(PCIE_SETUP_FUNCTION2))
  558. continue;
  559. if ((off & 0x0ff00000) == NETXEN_CRB_SMB)
  560. continue;
  561. }
  562. if (off == NETXEN_ADDR_ERROR) {
  563. printk(KERN_ERR "%s: Err: Unknown addr: 0x%08x\n",
  564. netxen_nic_driver_name, buf[i].addr);
  565. continue;
  566. }
  567. init_delay = 1;
  568. /* After writing this register, HW needs time for CRB */
  569. /* to quiet down (else crb_window returns 0xffffffff) */
  570. if (off == NETXEN_ROMUSB_GLB_SW_RESET) {
  571. init_delay = 1000;
  572. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  573. /* hold xdma in reset also */
  574. buf[i].data = NETXEN_NIC_XDMA_RESET;
  575. buf[i].data = 0x8000ff;
  576. }
  577. }
  578. NXWR32(adapter, off, buf[i].data);
  579. msleep(init_delay);
  580. }
  581. kfree(buf);
  582. /* disable_peg_cache_all */
  583. /* unreset_net_cache */
  584. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  585. val = NXRD32(adapter, NETXEN_ROMUSB_GLB_SW_RESET);
  586. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, (val & 0xffffff0f));
  587. }
  588. /* p2dn replyCount */
  589. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0xec, 0x1e);
  590. /* disable_peg_cache 0 */
  591. NXWR32(adapter, NETXEN_CRB_PEG_NET_D + 0x4c, 8);
  592. /* disable_peg_cache 1 */
  593. NXWR32(adapter, NETXEN_CRB_PEG_NET_I + 0x4c, 8);
  594. /* peg_clr_all */
  595. /* peg_clr 0 */
  596. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0x8, 0);
  597. NXWR32(adapter, NETXEN_CRB_PEG_NET_0 + 0xc, 0);
  598. /* peg_clr 1 */
  599. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0x8, 0);
  600. NXWR32(adapter, NETXEN_CRB_PEG_NET_1 + 0xc, 0);
  601. /* peg_clr 2 */
  602. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0x8, 0);
  603. NXWR32(adapter, NETXEN_CRB_PEG_NET_2 + 0xc, 0);
  604. /* peg_clr 3 */
  605. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0x8, 0);
  606. NXWR32(adapter, NETXEN_CRB_PEG_NET_3 + 0xc, 0);
  607. return 0;
  608. }
  609. int
  610. netxen_need_fw_reset(struct netxen_adapter *adapter)
  611. {
  612. u32 count, old_count;
  613. u32 val, version, major, minor, build;
  614. int i, timeout;
  615. u8 fw_type;
  616. /* NX2031 firmware doesn't support heartbit */
  617. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  618. return 1;
  619. /* last attempt had failed */
  620. if (NXRD32(adapter, CRB_CMDPEG_STATE) == PHAN_INITIALIZE_FAILED)
  621. return 1;
  622. old_count = count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  623. for (i = 0; i < 10; i++) {
  624. timeout = msleep_interruptible(200);
  625. if (timeout) {
  626. NXWR32(adapter, CRB_CMDPEG_STATE,
  627. PHAN_INITIALIZE_FAILED);
  628. return -EINTR;
  629. }
  630. count = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);
  631. if (count != old_count)
  632. break;
  633. }
  634. /* firmware is dead */
  635. if (count == old_count)
  636. return 1;
  637. /* check if we have got newer or different file firmware */
  638. if (adapter->fw) {
  639. const struct firmware *fw = adapter->fw;
  640. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  641. version = NETXEN_DECODE_VERSION(val);
  642. major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
  643. minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
  644. build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
  645. if (version > NETXEN_VERSION_CODE(major, minor, build))
  646. return 1;
  647. if (version == NETXEN_VERSION_CODE(major, minor, build)) {
  648. val = NXRD32(adapter, NETXEN_MIU_MN_CONTROL);
  649. fw_type = (val & 0x4) ?
  650. NX_P3_CT_ROMIMAGE : NX_P3_MN_ROMIMAGE;
  651. if (adapter->fw_type != fw_type)
  652. return 1;
  653. }
  654. }
  655. return 0;
  656. }
  657. static char *fw_name[] = {
  658. "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin", "flash",
  659. };
  660. int
  661. netxen_load_firmware(struct netxen_adapter *adapter)
  662. {
  663. u64 *ptr64;
  664. u32 i, flashaddr, size;
  665. const struct firmware *fw = adapter->fw;
  666. struct pci_dev *pdev = adapter->pdev;
  667. dev_info(&pdev->dev, "loading firmware from %s\n",
  668. fw_name[adapter->fw_type]);
  669. if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
  670. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 1);
  671. if (fw) {
  672. __le64 data;
  673. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
  674. ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
  675. flashaddr = NETXEN_BOOTLD_START;
  676. for (i = 0; i < size; i++) {
  677. data = cpu_to_le64(ptr64[i]);
  678. adapter->pci_mem_write(adapter, flashaddr, &data, 8);
  679. flashaddr += 8;
  680. }
  681. size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
  682. size = (__force u32)cpu_to_le32(size) / 8;
  683. ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
  684. flashaddr = NETXEN_IMAGE_START;
  685. for (i = 0; i < size; i++) {
  686. data = cpu_to_le64(ptr64[i]);
  687. if (adapter->pci_mem_write(adapter,
  688. flashaddr, &data, 8))
  689. return -EIO;
  690. flashaddr += 8;
  691. }
  692. } else {
  693. u32 data;
  694. size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
  695. flashaddr = NETXEN_BOOTLD_START;
  696. for (i = 0; i < size; i++) {
  697. if (netxen_rom_fast_read(adapter,
  698. flashaddr, (int *)&data) != 0)
  699. return -EIO;
  700. if (adapter->pci_mem_write(adapter,
  701. flashaddr, &data, 4))
  702. return -EIO;
  703. flashaddr += 4;
  704. }
  705. }
  706. msleep(1);
  707. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  708. NXWR32(adapter, NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
  709. else {
  710. NXWR32(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
  711. NXWR32(adapter, NETXEN_ROMUSB_GLB_CAS_RST, 0);
  712. }
  713. return 0;
  714. }
  715. static int
  716. netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname)
  717. {
  718. __le32 val;
  719. u32 ver, min_ver, bios;
  720. struct pci_dev *pdev = adapter->pdev;
  721. const struct firmware *fw = adapter->fw;
  722. if (fw->size < NX_FW_MIN_SIZE)
  723. return -EINVAL;
  724. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
  725. if ((__force u32)val != NETXEN_BDINFO_MAGIC)
  726. return -EINVAL;
  727. val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
  728. if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
  729. min_ver = NETXEN_VERSION_CODE(4, 0, 216);
  730. else
  731. min_ver = NETXEN_VERSION_CODE(3, 4, 216);
  732. ver = NETXEN_DECODE_VERSION(val);
  733. if ((_major(ver) > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
  734. dev_err(&pdev->dev,
  735. "%s: firmware version %d.%d.%d unsupported\n",
  736. fwname, _major(ver), _minor(ver), _build(ver));
  737. return -EINVAL;
  738. }
  739. val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
  740. netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
  741. if ((__force u32)val != bios) {
  742. dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
  743. fwname);
  744. return -EINVAL;
  745. }
  746. /* check if flashed firmware is newer */
  747. if (netxen_rom_fast_read(adapter,
  748. NX_FW_VERSION_OFFSET, (int *)&val))
  749. return -EIO;
  750. val = NETXEN_DECODE_VERSION(val);
  751. if (val > ver) {
  752. dev_info(&pdev->dev, "%s: firmware is older than flash\n",
  753. fwname);
  754. return -EINVAL;
  755. }
  756. NXWR32(adapter, NETXEN_CAM_RAM(0x1fc), NETXEN_BDINFO_MAGIC);
  757. return 0;
  758. }
  759. static int
  760. netxen_p3_has_mn(struct netxen_adapter *adapter)
  761. {
  762. u32 capability, flashed_ver;
  763. capability = 0;
  764. netxen_rom_fast_read(adapter,
  765. NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
  766. flashed_ver = NETXEN_DECODE_VERSION(flashed_ver);
  767. if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
  768. capability = NXRD32(adapter, NX_PEG_TUNE_CAPABILITY);
  769. if (capability & NX_PEG_TUNE_MN_PRESENT)
  770. return 1;
  771. }
  772. return 0;
  773. }
  774. void netxen_request_firmware(struct netxen_adapter *adapter)
  775. {
  776. u8 fw_type;
  777. struct pci_dev *pdev = adapter->pdev;
  778. int rc = 0;
  779. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  780. fw_type = NX_P2_MN_ROMIMAGE;
  781. goto request_fw;
  782. }
  783. fw_type = netxen_p3_has_mn(adapter) ?
  784. NX_P3_MN_ROMIMAGE : NX_P3_CT_ROMIMAGE;
  785. request_fw:
  786. rc = request_firmware(&adapter->fw, fw_name[fw_type], &pdev->dev);
  787. if (rc != 0) {
  788. if (fw_type == NX_P3_MN_ROMIMAGE) {
  789. msleep(1);
  790. fw_type = NX_P3_CT_ROMIMAGE;
  791. goto request_fw;
  792. }
  793. fw_type = NX_FLASH_ROMIMAGE;
  794. adapter->fw = NULL;
  795. goto done;
  796. }
  797. rc = netxen_validate_firmware(adapter, fw_name[fw_type]);
  798. if (rc != 0) {
  799. release_firmware(adapter->fw);
  800. if (fw_type == NX_P3_MN_ROMIMAGE) {
  801. msleep(1);
  802. fw_type = NX_P3_CT_ROMIMAGE;
  803. goto request_fw;
  804. }
  805. fw_type = NX_FLASH_ROMIMAGE;
  806. adapter->fw = NULL;
  807. goto done;
  808. }
  809. done:
  810. adapter->fw_type = fw_type;
  811. }
  812. void
  813. netxen_release_firmware(struct netxen_adapter *adapter)
  814. {
  815. if (adapter->fw)
  816. release_firmware(adapter->fw);
  817. }
  818. int netxen_init_dummy_dma(struct netxen_adapter *adapter)
  819. {
  820. u64 addr;
  821. u32 hi, lo;
  822. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  823. return 0;
  824. adapter->dummy_dma.addr = pci_alloc_consistent(adapter->pdev,
  825. NETXEN_HOST_DUMMY_DMA_SIZE,
  826. &adapter->dummy_dma.phys_addr);
  827. if (adapter->dummy_dma.addr == NULL) {
  828. dev_err(&adapter->pdev->dev,
  829. "ERROR: Could not allocate dummy DMA memory\n");
  830. return -ENOMEM;
  831. }
  832. addr = (uint64_t) adapter->dummy_dma.phys_addr;
  833. hi = (addr >> 32) & 0xffffffff;
  834. lo = addr & 0xffffffff;
  835. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_HI, hi);
  836. NXWR32(adapter, CRB_HOST_DUMMY_BUF_ADDR_LO, lo);
  837. return 0;
  838. }
  839. /*
  840. * NetXen DMA watchdog control:
  841. *
  842. * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
  843. * Bit 1 : disable_request => 1 req disable dma watchdog
  844. * Bit 2 : enable_request => 1 req enable dma watchdog
  845. * Bit 3-31 : unused
  846. */
  847. void netxen_free_dummy_dma(struct netxen_adapter *adapter)
  848. {
  849. int i = 100;
  850. u32 ctrl;
  851. if (!NX_IS_REVISION_P2(adapter->ahw.revision_id))
  852. return;
  853. if (!adapter->dummy_dma.addr)
  854. return;
  855. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  856. if ((ctrl & 0x1) != 0) {
  857. NXWR32(adapter, NETXEN_DMA_WATCHDOG_CTRL, (ctrl | 0x2));
  858. while ((ctrl & 0x1) != 0) {
  859. msleep(50);
  860. ctrl = NXRD32(adapter, NETXEN_DMA_WATCHDOG_CTRL);
  861. if (--i == 0)
  862. break;
  863. };
  864. }
  865. if (i) {
  866. pci_free_consistent(adapter->pdev,
  867. NETXEN_HOST_DUMMY_DMA_SIZE,
  868. adapter->dummy_dma.addr,
  869. adapter->dummy_dma.phys_addr);
  870. adapter->dummy_dma.addr = NULL;
  871. } else
  872. dev_err(&adapter->pdev->dev, "dma_watchdog_shutdown failed\n");
  873. }
  874. int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val)
  875. {
  876. u32 val = 0;
  877. int retries = 60;
  878. if (pegtune_val)
  879. return 0;
  880. do {
  881. val = NXRD32(adapter, CRB_CMDPEG_STATE);
  882. switch (val) {
  883. case PHAN_INITIALIZE_COMPLETE:
  884. case PHAN_INITIALIZE_ACK:
  885. return 0;
  886. case PHAN_INITIALIZE_FAILED:
  887. goto out_err;
  888. default:
  889. break;
  890. }
  891. msleep(500);
  892. } while (--retries);
  893. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
  894. out_err:
  895. dev_warn(&adapter->pdev->dev, "firmware init failed\n");
  896. return -EIO;
  897. }
  898. static int
  899. netxen_receive_peg_ready(struct netxen_adapter *adapter)
  900. {
  901. u32 val = 0;
  902. int retries = 2000;
  903. do {
  904. val = NXRD32(adapter, CRB_RCVPEG_STATE);
  905. if (val == PHAN_PEG_RCV_INITIALIZED)
  906. return 0;
  907. msleep(10);
  908. } while (--retries);
  909. if (!retries) {
  910. printk(KERN_ERR "Receive Peg initialization not "
  911. "complete, state: 0x%x.\n", val);
  912. return -EIO;
  913. }
  914. return 0;
  915. }
  916. int netxen_init_firmware(struct netxen_adapter *adapter)
  917. {
  918. int err;
  919. err = netxen_receive_peg_ready(adapter);
  920. if (err)
  921. return err;
  922. NXWR32(adapter, CRB_NIC_CAPABILITIES_HOST, INTR_SCHEME_PERPORT);
  923. NXWR32(adapter, CRB_NIC_MSI_MODE_HOST, MSI_MODE_MULTIFUNC);
  924. NXWR32(adapter, CRB_MPORT_MODE, MPORT_MULTI_FUNCTION_MODE);
  925. NXWR32(adapter, CRB_CMDPEG_STATE, PHAN_INITIALIZE_ACK);
  926. return err;
  927. }
  928. static void
  929. netxen_handle_linkevent(struct netxen_adapter *adapter, nx_fw_msg_t *msg)
  930. {
  931. u32 cable_OUI;
  932. u16 cable_len;
  933. u16 link_speed;
  934. u8 link_status, module, duplex, autoneg;
  935. struct net_device *netdev = adapter->netdev;
  936. adapter->has_link_events = 1;
  937. cable_OUI = msg->body[1] & 0xffffffff;
  938. cable_len = (msg->body[1] >> 32) & 0xffff;
  939. link_speed = (msg->body[1] >> 48) & 0xffff;
  940. link_status = msg->body[2] & 0xff;
  941. duplex = (msg->body[2] >> 16) & 0xff;
  942. autoneg = (msg->body[2] >> 24) & 0xff;
  943. module = (msg->body[2] >> 8) & 0xff;
  944. if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE) {
  945. printk(KERN_INFO "%s: unsupported cable: OUI 0x%x, length %d\n",
  946. netdev->name, cable_OUI, cable_len);
  947. } else if (module == LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN) {
  948. printk(KERN_INFO "%s: unsupported cable length %d\n",
  949. netdev->name, cable_len);
  950. }
  951. netxen_advert_link_change(adapter, link_status);
  952. /* update link parameters */
  953. if (duplex == LINKEVENT_FULL_DUPLEX)
  954. adapter->link_duplex = DUPLEX_FULL;
  955. else
  956. adapter->link_duplex = DUPLEX_HALF;
  957. adapter->module_type = module;
  958. adapter->link_autoneg = autoneg;
  959. adapter->link_speed = link_speed;
  960. }
  961. static void
  962. netxen_handle_fw_message(int desc_cnt, int index,
  963. struct nx_host_sds_ring *sds_ring)
  964. {
  965. nx_fw_msg_t msg;
  966. struct status_desc *desc;
  967. int i = 0, opcode;
  968. while (desc_cnt > 0 && i < 8) {
  969. desc = &sds_ring->desc_head[index];
  970. msg.words[i++] = le64_to_cpu(desc->status_desc_data[0]);
  971. msg.words[i++] = le64_to_cpu(desc->status_desc_data[1]);
  972. index = get_next_index(index, sds_ring->num_desc);
  973. desc_cnt--;
  974. }
  975. opcode = netxen_get_nic_msg_opcode(msg.body[0]);
  976. switch (opcode) {
  977. case NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE:
  978. netxen_handle_linkevent(sds_ring->adapter, &msg);
  979. break;
  980. default:
  981. break;
  982. }
  983. }
  984. static int
  985. netxen_alloc_rx_skb(struct netxen_adapter *adapter,
  986. struct nx_host_rds_ring *rds_ring,
  987. struct netxen_rx_buffer *buffer)
  988. {
  989. struct sk_buff *skb;
  990. dma_addr_t dma;
  991. struct pci_dev *pdev = adapter->pdev;
  992. buffer->skb = dev_alloc_skb(rds_ring->skb_size);
  993. if (!buffer->skb)
  994. return 1;
  995. skb = buffer->skb;
  996. if (!adapter->ahw.cut_through)
  997. skb_reserve(skb, 2);
  998. dma = pci_map_single(pdev, skb->data,
  999. rds_ring->dma_size, PCI_DMA_FROMDEVICE);
  1000. if (pci_dma_mapping_error(pdev, dma)) {
  1001. dev_kfree_skb_any(skb);
  1002. buffer->skb = NULL;
  1003. return 1;
  1004. }
  1005. buffer->skb = skb;
  1006. buffer->dma = dma;
  1007. buffer->state = NETXEN_BUFFER_BUSY;
  1008. return 0;
  1009. }
  1010. static struct sk_buff *netxen_process_rxbuf(struct netxen_adapter *adapter,
  1011. struct nx_host_rds_ring *rds_ring, u16 index, u16 cksum)
  1012. {
  1013. struct netxen_rx_buffer *buffer;
  1014. struct sk_buff *skb;
  1015. buffer = &rds_ring->rx_buf_arr[index];
  1016. pci_unmap_single(adapter->pdev, buffer->dma, rds_ring->dma_size,
  1017. PCI_DMA_FROMDEVICE);
  1018. skb = buffer->skb;
  1019. if (!skb)
  1020. goto no_skb;
  1021. if (likely(adapter->rx_csum && cksum == STATUS_CKSUM_OK)) {
  1022. adapter->stats.csummed++;
  1023. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1024. } else
  1025. skb->ip_summed = CHECKSUM_NONE;
  1026. skb->dev = adapter->netdev;
  1027. buffer->skb = NULL;
  1028. no_skb:
  1029. buffer->state = NETXEN_BUFFER_FREE;
  1030. return skb;
  1031. }
  1032. static struct netxen_rx_buffer *
  1033. netxen_process_rcv(struct netxen_adapter *adapter,
  1034. struct nx_host_sds_ring *sds_ring,
  1035. int ring, u64 sts_data0)
  1036. {
  1037. struct net_device *netdev = adapter->netdev;
  1038. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1039. struct netxen_rx_buffer *buffer;
  1040. struct sk_buff *skb;
  1041. struct nx_host_rds_ring *rds_ring;
  1042. int index, length, cksum, pkt_offset;
  1043. if (unlikely(ring >= adapter->max_rds_rings))
  1044. return NULL;
  1045. rds_ring = &recv_ctx->rds_rings[ring];
  1046. index = netxen_get_sts_refhandle(sts_data0);
  1047. if (unlikely(index >= rds_ring->num_desc))
  1048. return NULL;
  1049. buffer = &rds_ring->rx_buf_arr[index];
  1050. length = netxen_get_sts_totallength(sts_data0);
  1051. cksum = netxen_get_sts_status(sts_data0);
  1052. pkt_offset = netxen_get_sts_pkt_offset(sts_data0);
  1053. skb = netxen_process_rxbuf(adapter, rds_ring, index, cksum);
  1054. if (!skb)
  1055. return buffer;
  1056. if (length > rds_ring->skb_size)
  1057. skb_put(skb, rds_ring->skb_size);
  1058. else
  1059. skb_put(skb, length);
  1060. if (pkt_offset)
  1061. skb_pull(skb, pkt_offset);
  1062. skb->protocol = eth_type_trans(skb, netdev);
  1063. napi_gro_receive(&sds_ring->napi, skb);
  1064. adapter->stats.rx_pkts++;
  1065. adapter->stats.rxbytes += length;
  1066. return buffer;
  1067. }
  1068. #define TCP_HDR_SIZE 20
  1069. #define TCP_TS_OPTION_SIZE 12
  1070. #define TCP_TS_HDR_SIZE (TCP_HDR_SIZE + TCP_TS_OPTION_SIZE)
  1071. static struct netxen_rx_buffer *
  1072. netxen_process_lro(struct netxen_adapter *adapter,
  1073. struct nx_host_sds_ring *sds_ring,
  1074. int ring, u64 sts_data0, u64 sts_data1)
  1075. {
  1076. struct net_device *netdev = adapter->netdev;
  1077. struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;
  1078. struct netxen_rx_buffer *buffer;
  1079. struct sk_buff *skb;
  1080. struct nx_host_rds_ring *rds_ring;
  1081. struct iphdr *iph;
  1082. struct tcphdr *th;
  1083. bool push, timestamp;
  1084. int l2_hdr_offset, l4_hdr_offset;
  1085. int index;
  1086. u16 lro_length, length, data_offset;
  1087. u32 seq_number;
  1088. if (unlikely(ring > adapter->max_rds_rings))
  1089. return NULL;
  1090. rds_ring = &recv_ctx->rds_rings[ring];
  1091. index = netxen_get_lro_sts_refhandle(sts_data0);
  1092. if (unlikely(index > rds_ring->num_desc))
  1093. return NULL;
  1094. buffer = &rds_ring->rx_buf_arr[index];
  1095. timestamp = netxen_get_lro_sts_timestamp(sts_data0);
  1096. lro_length = netxen_get_lro_sts_length(sts_data0);
  1097. l2_hdr_offset = netxen_get_lro_sts_l2_hdr_offset(sts_data0);
  1098. l4_hdr_offset = netxen_get_lro_sts_l4_hdr_offset(sts_data0);
  1099. push = netxen_get_lro_sts_push_flag(sts_data0);
  1100. seq_number = netxen_get_lro_sts_seq_number(sts_data1);
  1101. skb = netxen_process_rxbuf(adapter, rds_ring, index, STATUS_CKSUM_OK);
  1102. if (!skb)
  1103. return buffer;
  1104. if (timestamp)
  1105. data_offset = l4_hdr_offset + TCP_TS_HDR_SIZE;
  1106. else
  1107. data_offset = l4_hdr_offset + TCP_HDR_SIZE;
  1108. skb_put(skb, lro_length + data_offset);
  1109. skb->truesize = (skb->len + sizeof(struct sk_buff) +
  1110. ((unsigned long)skb->data - (unsigned long)skb->head));
  1111. skb_pull(skb, l2_hdr_offset);
  1112. skb->protocol = eth_type_trans(skb, netdev);
  1113. iph = (struct iphdr *)skb->data;
  1114. th = (struct tcphdr *)(skb->data + (iph->ihl << 2));
  1115. length = (iph->ihl << 2) + (th->doff << 2) + lro_length;
  1116. iph->tot_len = htons(length);
  1117. iph->check = 0;
  1118. iph->check = ip_fast_csum((unsigned char *)iph, iph->ihl);
  1119. th->psh = push;
  1120. th->seq = htonl(seq_number);
  1121. length = skb->len;
  1122. netif_receive_skb(skb);
  1123. adapter->stats.lro_pkts++;
  1124. adapter->stats.rxbytes += length;
  1125. return buffer;
  1126. }
  1127. #define netxen_merge_rx_buffers(list, head) \
  1128. do { list_splice_tail_init(list, head); } while (0);
  1129. int
  1130. netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max)
  1131. {
  1132. struct netxen_adapter *adapter = sds_ring->adapter;
  1133. struct list_head *cur;
  1134. struct status_desc *desc;
  1135. struct netxen_rx_buffer *rxbuf;
  1136. u32 consumer = sds_ring->consumer;
  1137. int count = 0;
  1138. u64 sts_data0, sts_data1;
  1139. int opcode, ring = 0, desc_cnt;
  1140. while (count < max) {
  1141. desc = &sds_ring->desc_head[consumer];
  1142. sts_data0 = le64_to_cpu(desc->status_desc_data[0]);
  1143. if (!(sts_data0 & STATUS_OWNER_HOST))
  1144. break;
  1145. desc_cnt = netxen_get_sts_desc_cnt(sts_data0);
  1146. opcode = netxen_get_sts_opcode(sts_data0);
  1147. switch (opcode) {
  1148. case NETXEN_NIC_RXPKT_DESC:
  1149. case NETXEN_OLD_RXPKT_DESC:
  1150. case NETXEN_NIC_SYN_OFFLOAD:
  1151. ring = netxen_get_sts_type(sts_data0);
  1152. rxbuf = netxen_process_rcv(adapter, sds_ring,
  1153. ring, sts_data0);
  1154. break;
  1155. case NETXEN_NIC_LRO_DESC:
  1156. ring = netxen_get_lro_sts_type(sts_data0);
  1157. sts_data1 = le64_to_cpu(desc->status_desc_data[1]);
  1158. rxbuf = netxen_process_lro(adapter, sds_ring,
  1159. ring, sts_data0, sts_data1);
  1160. break;
  1161. case NETXEN_NIC_RESPONSE_DESC:
  1162. netxen_handle_fw_message(desc_cnt, consumer, sds_ring);
  1163. default:
  1164. goto skip;
  1165. }
  1166. WARN_ON(desc_cnt > 1);
  1167. if (rxbuf)
  1168. list_add_tail(&rxbuf->list, &sds_ring->free_list[ring]);
  1169. skip:
  1170. for (; desc_cnt > 0; desc_cnt--) {
  1171. desc = &sds_ring->desc_head[consumer];
  1172. desc->status_desc_data[0] =
  1173. cpu_to_le64(STATUS_OWNER_PHANTOM);
  1174. consumer = get_next_index(consumer, sds_ring->num_desc);
  1175. }
  1176. count++;
  1177. }
  1178. for (ring = 0; ring < adapter->max_rds_rings; ring++) {
  1179. struct nx_host_rds_ring *rds_ring =
  1180. &adapter->recv_ctx.rds_rings[ring];
  1181. if (!list_empty(&sds_ring->free_list[ring])) {
  1182. list_for_each(cur, &sds_ring->free_list[ring]) {
  1183. rxbuf = list_entry(cur,
  1184. struct netxen_rx_buffer, list);
  1185. netxen_alloc_rx_skb(adapter, rds_ring, rxbuf);
  1186. }
  1187. spin_lock(&rds_ring->lock);
  1188. netxen_merge_rx_buffers(&sds_ring->free_list[ring],
  1189. &rds_ring->free_list);
  1190. spin_unlock(&rds_ring->lock);
  1191. }
  1192. netxen_post_rx_buffers_nodb(adapter, rds_ring);
  1193. }
  1194. if (count) {
  1195. sds_ring->consumer = consumer;
  1196. NXWR32(adapter, sds_ring->crb_sts_consumer, consumer);
  1197. }
  1198. return count;
  1199. }
  1200. /* Process Command status ring */
  1201. int netxen_process_cmd_ring(struct netxen_adapter *adapter)
  1202. {
  1203. u32 sw_consumer, hw_consumer;
  1204. int count = 0, i;
  1205. struct netxen_cmd_buffer *buffer;
  1206. struct pci_dev *pdev = adapter->pdev;
  1207. struct net_device *netdev = adapter->netdev;
  1208. struct netxen_skb_frag *frag;
  1209. int done = 0;
  1210. struct nx_host_tx_ring *tx_ring = adapter->tx_ring;
  1211. if (!spin_trylock(&adapter->tx_clean_lock))
  1212. return 1;
  1213. sw_consumer = tx_ring->sw_consumer;
  1214. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1215. while (sw_consumer != hw_consumer) {
  1216. buffer = &tx_ring->cmd_buf_arr[sw_consumer];
  1217. if (buffer->skb) {
  1218. frag = &buffer->frag_array[0];
  1219. pci_unmap_single(pdev, frag->dma, frag->length,
  1220. PCI_DMA_TODEVICE);
  1221. frag->dma = 0ULL;
  1222. for (i = 1; i < buffer->frag_count; i++) {
  1223. frag++; /* Get the next frag */
  1224. pci_unmap_page(pdev, frag->dma, frag->length,
  1225. PCI_DMA_TODEVICE);
  1226. frag->dma = 0ULL;
  1227. }
  1228. adapter->stats.xmitfinished++;
  1229. dev_kfree_skb_any(buffer->skb);
  1230. buffer->skb = NULL;
  1231. }
  1232. sw_consumer = get_next_index(sw_consumer, tx_ring->num_desc);
  1233. if (++count >= MAX_STATUS_HANDLE)
  1234. break;
  1235. }
  1236. if (count && netif_running(netdev)) {
  1237. tx_ring->sw_consumer = sw_consumer;
  1238. smp_mb();
  1239. if (netif_queue_stopped(netdev) && netif_carrier_ok(netdev)) {
  1240. __netif_tx_lock(tx_ring->txq, smp_processor_id());
  1241. if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
  1242. netif_wake_queue(netdev);
  1243. __netif_tx_unlock(tx_ring->txq);
  1244. }
  1245. }
  1246. /*
  1247. * If everything is freed up to consumer then check if the ring is full
  1248. * If the ring is full then check if more needs to be freed and
  1249. * schedule the call back again.
  1250. *
  1251. * This happens when there are 2 CPUs. One could be freeing and the
  1252. * other filling it. If the ring is full when we get out of here and
  1253. * the card has already interrupted the host then the host can miss the
  1254. * interrupt.
  1255. *
  1256. * There is still a possible race condition and the host could miss an
  1257. * interrupt. The card has to take care of this.
  1258. */
  1259. hw_consumer = le32_to_cpu(*(tx_ring->hw_consumer));
  1260. done = (sw_consumer == hw_consumer);
  1261. spin_unlock(&adapter->tx_clean_lock);
  1262. return (done);
  1263. }
  1264. void
  1265. netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
  1266. struct nx_host_rds_ring *rds_ring)
  1267. {
  1268. struct rcv_desc *pdesc;
  1269. struct netxen_rx_buffer *buffer;
  1270. int producer, count = 0;
  1271. netxen_ctx_msg msg = 0;
  1272. struct list_head *head;
  1273. producer = rds_ring->producer;
  1274. spin_lock(&rds_ring->lock);
  1275. head = &rds_ring->free_list;
  1276. while (!list_empty(head)) {
  1277. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1278. if (!buffer->skb) {
  1279. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1280. break;
  1281. }
  1282. count++;
  1283. list_del(&buffer->list);
  1284. /* make a rcv descriptor */
  1285. pdesc = &rds_ring->desc_head[producer];
  1286. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1287. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1288. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1289. producer = get_next_index(producer, rds_ring->num_desc);
  1290. }
  1291. spin_unlock(&rds_ring->lock);
  1292. if (count) {
  1293. rds_ring->producer = producer;
  1294. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1295. (producer-1) & (rds_ring->num_desc-1));
  1296. if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
  1297. /*
  1298. * Write a doorbell msg to tell phanmon of change in
  1299. * receive ring producer
  1300. * Only for firmware version < 4.0.0
  1301. */
  1302. netxen_set_msg_peg_id(msg, NETXEN_RCV_PEG_DB_ID);
  1303. netxen_set_msg_privid(msg);
  1304. netxen_set_msg_count(msg,
  1305. ((producer - 1) &
  1306. (rds_ring->num_desc - 1)));
  1307. netxen_set_msg_ctxid(msg, adapter->portnum);
  1308. netxen_set_msg_opcode(msg, NETXEN_RCV_PRODUCER(ringid));
  1309. writel(msg,
  1310. DB_NORMALIZE(adapter,
  1311. NETXEN_RCV_PRODUCER_OFFSET));
  1312. }
  1313. }
  1314. }
  1315. static void
  1316. netxen_post_rx_buffers_nodb(struct netxen_adapter *adapter,
  1317. struct nx_host_rds_ring *rds_ring)
  1318. {
  1319. struct rcv_desc *pdesc;
  1320. struct netxen_rx_buffer *buffer;
  1321. int producer, count = 0;
  1322. struct list_head *head;
  1323. producer = rds_ring->producer;
  1324. if (!spin_trylock(&rds_ring->lock))
  1325. return;
  1326. head = &rds_ring->free_list;
  1327. while (!list_empty(head)) {
  1328. buffer = list_entry(head->next, struct netxen_rx_buffer, list);
  1329. if (!buffer->skb) {
  1330. if (netxen_alloc_rx_skb(adapter, rds_ring, buffer))
  1331. break;
  1332. }
  1333. count++;
  1334. list_del(&buffer->list);
  1335. /* make a rcv descriptor */
  1336. pdesc = &rds_ring->desc_head[producer];
  1337. pdesc->reference_handle = cpu_to_le16(buffer->ref_handle);
  1338. pdesc->buffer_length = cpu_to_le32(rds_ring->dma_size);
  1339. pdesc->addr_buffer = cpu_to_le64(buffer->dma);
  1340. producer = get_next_index(producer, rds_ring->num_desc);
  1341. }
  1342. if (count) {
  1343. rds_ring->producer = producer;
  1344. NXWR32(adapter, rds_ring->crb_rcv_producer,
  1345. (producer - 1) & (rds_ring->num_desc - 1));
  1346. }
  1347. spin_unlock(&rds_ring->lock);
  1348. }
  1349. void netxen_nic_clear_stats(struct netxen_adapter *adapter)
  1350. {
  1351. memset(&adapter->stats, 0, sizeof(adapter->stats));
  1352. return;
  1353. }