e1000_osdep.h 3.1 KB

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  1. /*******************************************************************************
  2. Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. The full GNU General Public License is included in this distribution in the
  15. file called LICENSE.
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. *******************************************************************************/
  20. /* glue for the OS independent part of e1000
  21. * includes register access macros
  22. */
  23. #ifndef _E1000_OSDEP_H_
  24. #define _E1000_OSDEP_H_
  25. #include <linux/types.h>
  26. #include <linux/pci.h>
  27. #include <linux/delay.h>
  28. #include <asm/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/sched.h>
  31. #ifndef msec_delay
  32. #define msec_delay(x) msleep(x)
  33. /* Some workarounds require millisecond delays and are run during interrupt
  34. * context. Most notably, when establishing link, the phy may need tweaking
  35. * but cannot process phy register reads/writes faster than millisecond
  36. * intervals...and we establish link due to a "link status change" interrupt.
  37. */
  38. #define msec_delay_irq(x) mdelay(x)
  39. #endif
  40. #define PCI_COMMAND_REGISTER PCI_COMMAND
  41. #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
  42. typedef enum {
  43. #undef FALSE
  44. FALSE = 0,
  45. #undef TRUE
  46. TRUE = 1
  47. } boolean_t;
  48. #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
  49. #ifdef DBG
  50. #define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
  51. #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
  52. #else
  53. #define DEBUGOUT(S)
  54. #define DEBUGOUT1(S, A...)
  55. #endif
  56. #define DEBUGFUNC(F) DEBUGOUT(F)
  57. #define DEBUGOUT2 DEBUGOUT1
  58. #define DEBUGOUT3 DEBUGOUT2
  59. #define DEBUGOUT7 DEBUGOUT3
  60. #define E1000_WRITE_REG(a, reg, value) ( \
  61. writel((value), ((a)->hw_addr + \
  62. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))
  63. #define E1000_READ_REG(a, reg) ( \
  64. readl((a)->hw_addr + \
  65. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
  66. #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
  67. writel((value), ((a)->hw_addr + \
  68. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  69. ((offset) << 2))))
  70. #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
  71. readl((a)->hw_addr + \
  72. (((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
  73. ((offset) << 2)))
  74. #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
  75. #endif /* _E1000_OSDEP_H_ */