iwl3945-base.c 234 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/version.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/delay.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/ieee80211_radiotap.h>
  43. #include <net/mac80211.h>
  44. #include <asm/div64.h>
  45. #include "iwl-3945-core.h"
  46. #include "iwl-3945.h"
  47. #include "iwl-helpers.h"
  48. #ifdef CONFIG_IWL3945_DEBUG
  49. u32 iwl3945_debug_level;
  50. #endif
  51. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  52. struct iwl3945_tx_queue *txq);
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /* module parameters */
  59. static int iwl3945_param_disable_hw_scan; /* def: 0 = use 3945's h/w scan */
  60. static int iwl3945_param_debug; /* def: 0 = minimal debug log messages */
  61. static int iwl3945_param_disable; /* def: 0 = enable radio */
  62. static int iwl3945_param_antenna; /* def: 0 = both antennas (use diversity) */
  63. int iwl3945_param_hwcrypto; /* def: 0 = use software encryption */
  64. static int iwl3945_param_qos_enable = 1; /* def: 1 = use quality of service */
  65. int iwl3945_param_queues_num = IWL39_MAX_NUM_QUEUES; /* def: 8 Tx queues */
  66. /*
  67. * module name, copyright, version, etc.
  68. * NOTE: DRV_NAME is defined in iwlwifi.h for use by iwl-debug.h and printk
  69. */
  70. #define DRV_DESCRIPTION \
  71. "Intel(R) PRO/Wireless 3945ABG/BG Network Connection driver for Linux"
  72. #ifdef CONFIG_IWL3945_DEBUG
  73. #define VD "d"
  74. #else
  75. #define VD
  76. #endif
  77. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  78. #define VS "s"
  79. #else
  80. #define VS
  81. #endif
  82. #define IWLWIFI_VERSION "1.2.26k" VD VS
  83. #define DRV_COPYRIGHT "Copyright(c) 2003-2008 Intel Corporation"
  84. #define DRV_VERSION IWLWIFI_VERSION
  85. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86. MODULE_VERSION(DRV_VERSION);
  87. MODULE_AUTHOR(DRV_COPYRIGHT);
  88. MODULE_LICENSE("GPL");
  89. static const struct ieee80211_supported_band *iwl3945_get_band(
  90. struct iwl3945_priv *priv, enum ieee80211_band band)
  91. {
  92. return priv->hw->wiphy->bands[band];
  93. }
  94. static int iwl3945_is_empty_essid(const char *essid, int essid_len)
  95. {
  96. /* Single white space is for Linksys APs */
  97. if (essid_len == 1 && essid[0] == ' ')
  98. return 1;
  99. /* Otherwise, if the entire essid is 0, we assume it is hidden */
  100. while (essid_len) {
  101. essid_len--;
  102. if (essid[essid_len] != '\0')
  103. return 0;
  104. }
  105. return 1;
  106. }
  107. static const char *iwl3945_escape_essid(const char *essid, u8 essid_len)
  108. {
  109. static char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
  110. const char *s = essid;
  111. char *d = escaped;
  112. if (iwl3945_is_empty_essid(essid, essid_len)) {
  113. memcpy(escaped, "<hidden>", sizeof("<hidden>"));
  114. return escaped;
  115. }
  116. essid_len = min(essid_len, (u8) IW_ESSID_MAX_SIZE);
  117. while (essid_len--) {
  118. if (*s == '\0') {
  119. *d++ = '\\';
  120. *d++ = '0';
  121. s++;
  122. } else
  123. *d++ = *s++;
  124. }
  125. *d = '\0';
  126. return escaped;
  127. }
  128. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  129. * DMA services
  130. *
  131. * Theory of operation
  132. *
  133. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  134. * of buffer descriptors, each of which points to one or more data buffers for
  135. * the device to read from or fill. Driver and device exchange status of each
  136. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  137. * entries in each circular buffer, to protect against confusing empty and full
  138. * queue states.
  139. *
  140. * The device reads or writes the data in the queues via the device's several
  141. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  142. *
  143. * For Tx queue, there are low mark and high mark limits. If, after queuing
  144. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  145. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  146. * Tx queue resumed.
  147. *
  148. * The 3945 operates with six queues: One receive queue, one transmit queue
  149. * (#4) for sending commands to the device firmware, and four transmit queues
  150. * (#0-3) for data tx via EDCA. An additional 2 HCCA queues are unused.
  151. ***************************************************/
  152. int iwl3945_queue_space(const struct iwl3945_queue *q)
  153. {
  154. int s = q->read_ptr - q->write_ptr;
  155. if (q->read_ptr > q->write_ptr)
  156. s -= q->n_bd;
  157. if (s <= 0)
  158. s += q->n_window;
  159. /* keep some reserve to not confuse empty and full situations */
  160. s -= 2;
  161. if (s < 0)
  162. s = 0;
  163. return s;
  164. }
  165. int iwl3945_x2_queue_used(const struct iwl3945_queue *q, int i)
  166. {
  167. return q->write_ptr > q->read_ptr ?
  168. (i >= q->read_ptr && i < q->write_ptr) :
  169. !(i < q->read_ptr && i >= q->write_ptr);
  170. }
  171. static inline u8 get_cmd_index(struct iwl3945_queue *q, u32 index, int is_huge)
  172. {
  173. /* This is for scan command, the big buffer at end of command array */
  174. if (is_huge)
  175. return q->n_window; /* must be power of 2 */
  176. /* Otherwise, use normal size buffers */
  177. return index & (q->n_window - 1);
  178. }
  179. /**
  180. * iwl3945_queue_init - Initialize queue's high/low-water and read/write indexes
  181. */
  182. static int iwl3945_queue_init(struct iwl3945_priv *priv, struct iwl3945_queue *q,
  183. int count, int slots_num, u32 id)
  184. {
  185. q->n_bd = count;
  186. q->n_window = slots_num;
  187. q->id = id;
  188. /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
  189. * and iwl_queue_dec_wrap are broken. */
  190. BUG_ON(!is_power_of_2(count));
  191. /* slots_num must be power-of-two size, otherwise
  192. * get_cmd_index is broken. */
  193. BUG_ON(!is_power_of_2(slots_num));
  194. q->low_mark = q->n_window / 4;
  195. if (q->low_mark < 4)
  196. q->low_mark = 4;
  197. q->high_mark = q->n_window / 8;
  198. if (q->high_mark < 2)
  199. q->high_mark = 2;
  200. q->write_ptr = q->read_ptr = 0;
  201. return 0;
  202. }
  203. /**
  204. * iwl3945_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  205. */
  206. static int iwl3945_tx_queue_alloc(struct iwl3945_priv *priv,
  207. struct iwl3945_tx_queue *txq, u32 id)
  208. {
  209. struct pci_dev *dev = priv->pci_dev;
  210. /* Driver private data, only for Tx (not command) queues,
  211. * not shared with device. */
  212. if (id != IWL_CMD_QUEUE_NUM) {
  213. txq->txb = kmalloc(sizeof(txq->txb[0]) *
  214. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  215. if (!txq->txb) {
  216. IWL_ERROR("kmalloc for auxiliary BD "
  217. "structures failed\n");
  218. goto error;
  219. }
  220. } else
  221. txq->txb = NULL;
  222. /* Circular buffer of transmit frame descriptors (TFDs),
  223. * shared with device */
  224. txq->bd = pci_alloc_consistent(dev,
  225. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX,
  226. &txq->q.dma_addr);
  227. if (!txq->bd) {
  228. IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
  229. sizeof(txq->bd[0]) * TFD_QUEUE_SIZE_MAX);
  230. goto error;
  231. }
  232. txq->q.id = id;
  233. return 0;
  234. error:
  235. if (txq->txb) {
  236. kfree(txq->txb);
  237. txq->txb = NULL;
  238. }
  239. return -ENOMEM;
  240. }
  241. /**
  242. * iwl3945_tx_queue_init - Allocate and initialize one tx/cmd queue
  243. */
  244. int iwl3945_tx_queue_init(struct iwl3945_priv *priv,
  245. struct iwl3945_tx_queue *txq, int slots_num, u32 txq_id)
  246. {
  247. struct pci_dev *dev = priv->pci_dev;
  248. int len;
  249. int rc = 0;
  250. /*
  251. * Alloc buffer array for commands (Tx or other types of commands).
  252. * For the command queue (#4), allocate command space + one big
  253. * command for scan, since scan command is very huge; the system will
  254. * not have two scans at the same time, so only one is needed.
  255. * For data Tx queues (all other queues), no super-size command
  256. * space is needed.
  257. */
  258. len = sizeof(struct iwl3945_cmd) * slots_num;
  259. if (txq_id == IWL_CMD_QUEUE_NUM)
  260. len += IWL_MAX_SCAN_SIZE;
  261. txq->cmd = pci_alloc_consistent(dev, len, &txq->dma_addr_cmd);
  262. if (!txq->cmd)
  263. return -ENOMEM;
  264. /* Alloc driver data array and TFD circular buffer */
  265. rc = iwl3945_tx_queue_alloc(priv, txq, txq_id);
  266. if (rc) {
  267. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  268. return -ENOMEM;
  269. }
  270. txq->need_update = 0;
  271. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  272. * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
  273. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  274. /* Initialize queue high/low-water, head/tail indexes */
  275. iwl3945_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  276. /* Tell device where to find queue, enable DMA channel. */
  277. iwl3945_hw_tx_queue_init(priv, txq);
  278. return 0;
  279. }
  280. /**
  281. * iwl3945_tx_queue_free - Deallocate DMA queue.
  282. * @txq: Transmit queue to deallocate.
  283. *
  284. * Empty queue by removing and destroying all BD's.
  285. * Free all buffers.
  286. * 0-fill, but do not free "txq" descriptor structure.
  287. */
  288. void iwl3945_tx_queue_free(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
  289. {
  290. struct iwl3945_queue *q = &txq->q;
  291. struct pci_dev *dev = priv->pci_dev;
  292. int len;
  293. if (q->n_bd == 0)
  294. return;
  295. /* first, empty all BD's */
  296. for (; q->write_ptr != q->read_ptr;
  297. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
  298. iwl3945_hw_txq_free_tfd(priv, txq);
  299. len = sizeof(struct iwl3945_cmd) * q->n_window;
  300. if (q->id == IWL_CMD_QUEUE_NUM)
  301. len += IWL_MAX_SCAN_SIZE;
  302. /* De-alloc array of command/tx buffers */
  303. pci_free_consistent(dev, len, txq->cmd, txq->dma_addr_cmd);
  304. /* De-alloc circular buffer of TFDs */
  305. if (txq->q.n_bd)
  306. pci_free_consistent(dev, sizeof(struct iwl3945_tfd_frame) *
  307. txq->q.n_bd, txq->bd, txq->q.dma_addr);
  308. /* De-alloc array of per-TFD driver data */
  309. if (txq->txb) {
  310. kfree(txq->txb);
  311. txq->txb = NULL;
  312. }
  313. /* 0-fill queue descriptor structure */
  314. memset(txq, 0, sizeof(*txq));
  315. }
  316. const u8 iwl3945_broadcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  317. /*************** STATION TABLE MANAGEMENT ****
  318. * mac80211 should be examined to determine if sta_info is duplicating
  319. * the functionality provided here
  320. */
  321. /**************************************************************/
  322. #if 0 /* temporary disable till we add real remove station */
  323. /**
  324. * iwl3945_remove_station - Remove driver's knowledge of station.
  325. *
  326. * NOTE: This does not remove station from device's station table.
  327. */
  328. static u8 iwl3945_remove_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap)
  329. {
  330. int index = IWL_INVALID_STATION;
  331. int i;
  332. unsigned long flags;
  333. spin_lock_irqsave(&priv->sta_lock, flags);
  334. if (is_ap)
  335. index = IWL_AP_ID;
  336. else if (is_broadcast_ether_addr(addr))
  337. index = priv->hw_setting.bcast_sta_id;
  338. else
  339. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
  340. if (priv->stations[i].used &&
  341. !compare_ether_addr(priv->stations[i].sta.sta.addr,
  342. addr)) {
  343. index = i;
  344. break;
  345. }
  346. if (unlikely(index == IWL_INVALID_STATION))
  347. goto out;
  348. if (priv->stations[index].used) {
  349. priv->stations[index].used = 0;
  350. priv->num_stations--;
  351. }
  352. BUG_ON(priv->num_stations < 0);
  353. out:
  354. spin_unlock_irqrestore(&priv->sta_lock, flags);
  355. return 0;
  356. }
  357. #endif
  358. /**
  359. * iwl3945_clear_stations_table - Clear the driver's station table
  360. *
  361. * NOTE: This does not clear or otherwise alter the device's station table.
  362. */
  363. static void iwl3945_clear_stations_table(struct iwl3945_priv *priv)
  364. {
  365. unsigned long flags;
  366. spin_lock_irqsave(&priv->sta_lock, flags);
  367. priv->num_stations = 0;
  368. memset(priv->stations, 0, sizeof(priv->stations));
  369. spin_unlock_irqrestore(&priv->sta_lock, flags);
  370. }
  371. /**
  372. * iwl3945_add_station - Add station to station tables in driver and device
  373. */
  374. u8 iwl3945_add_station(struct iwl3945_priv *priv, const u8 *addr, int is_ap, u8 flags)
  375. {
  376. int i;
  377. int index = IWL_INVALID_STATION;
  378. struct iwl3945_station_entry *station;
  379. unsigned long flags_spin;
  380. DECLARE_MAC_BUF(mac);
  381. u8 rate;
  382. spin_lock_irqsave(&priv->sta_lock, flags_spin);
  383. if (is_ap)
  384. index = IWL_AP_ID;
  385. else if (is_broadcast_ether_addr(addr))
  386. index = priv->hw_setting.bcast_sta_id;
  387. else
  388. for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++) {
  389. if (!compare_ether_addr(priv->stations[i].sta.sta.addr,
  390. addr)) {
  391. index = i;
  392. break;
  393. }
  394. if (!priv->stations[i].used &&
  395. index == IWL_INVALID_STATION)
  396. index = i;
  397. }
  398. /* These two conditions has the same outcome but keep them separate
  399. since they have different meaning */
  400. if (unlikely(index == IWL_INVALID_STATION)) {
  401. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  402. return index;
  403. }
  404. if (priv->stations[index].used &&
  405. !compare_ether_addr(priv->stations[index].sta.sta.addr, addr)) {
  406. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  407. return index;
  408. }
  409. IWL_DEBUG_ASSOC("Add STA ID %d: %s\n", index, print_mac(mac, addr));
  410. station = &priv->stations[index];
  411. station->used = 1;
  412. priv->num_stations++;
  413. /* Set up the REPLY_ADD_STA command to send to device */
  414. memset(&station->sta, 0, sizeof(struct iwl3945_addsta_cmd));
  415. memcpy(station->sta.sta.addr, addr, ETH_ALEN);
  416. station->sta.mode = 0;
  417. station->sta.sta.sta_id = index;
  418. station->sta.station_flags = 0;
  419. if (priv->band == IEEE80211_BAND_5GHZ)
  420. rate = IWL_RATE_6M_PLCP;
  421. else
  422. rate = IWL_RATE_1M_PLCP;
  423. /* Turn on both antennas for the station... */
  424. station->sta.rate_n_flags =
  425. iwl3945_hw_set_rate_n_flags(rate, RATE_MCS_ANT_AB_MSK);
  426. station->current_rate.rate_n_flags =
  427. le16_to_cpu(station->sta.rate_n_flags);
  428. spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
  429. /* Add station to device's station table */
  430. iwl3945_send_add_station(priv, &station->sta, flags);
  431. return index;
  432. }
  433. /*************** DRIVER STATUS FUNCTIONS *****/
  434. static inline int iwl3945_is_ready(struct iwl3945_priv *priv)
  435. {
  436. /* The adapter is 'ready' if READY and GEO_CONFIGURED bits are
  437. * set but EXIT_PENDING is not */
  438. return test_bit(STATUS_READY, &priv->status) &&
  439. test_bit(STATUS_GEO_CONFIGURED, &priv->status) &&
  440. !test_bit(STATUS_EXIT_PENDING, &priv->status);
  441. }
  442. static inline int iwl3945_is_alive(struct iwl3945_priv *priv)
  443. {
  444. return test_bit(STATUS_ALIVE, &priv->status);
  445. }
  446. static inline int iwl3945_is_init(struct iwl3945_priv *priv)
  447. {
  448. return test_bit(STATUS_INIT, &priv->status);
  449. }
  450. static inline int iwl3945_is_rfkill(struct iwl3945_priv *priv)
  451. {
  452. return test_bit(STATUS_RF_KILL_HW, &priv->status) ||
  453. test_bit(STATUS_RF_KILL_SW, &priv->status);
  454. }
  455. static inline int iwl3945_is_ready_rf(struct iwl3945_priv *priv)
  456. {
  457. if (iwl3945_is_rfkill(priv))
  458. return 0;
  459. return iwl3945_is_ready(priv);
  460. }
  461. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  462. #define IWL_CMD(x) case x : return #x
  463. static const char *get_cmd_string(u8 cmd)
  464. {
  465. switch (cmd) {
  466. IWL_CMD(REPLY_ALIVE);
  467. IWL_CMD(REPLY_ERROR);
  468. IWL_CMD(REPLY_RXON);
  469. IWL_CMD(REPLY_RXON_ASSOC);
  470. IWL_CMD(REPLY_QOS_PARAM);
  471. IWL_CMD(REPLY_RXON_TIMING);
  472. IWL_CMD(REPLY_ADD_STA);
  473. IWL_CMD(REPLY_REMOVE_STA);
  474. IWL_CMD(REPLY_REMOVE_ALL_STA);
  475. IWL_CMD(REPLY_3945_RX);
  476. IWL_CMD(REPLY_TX);
  477. IWL_CMD(REPLY_RATE_SCALE);
  478. IWL_CMD(REPLY_LEDS_CMD);
  479. IWL_CMD(REPLY_TX_LINK_QUALITY_CMD);
  480. IWL_CMD(RADAR_NOTIFICATION);
  481. IWL_CMD(REPLY_QUIET_CMD);
  482. IWL_CMD(REPLY_CHANNEL_SWITCH);
  483. IWL_CMD(CHANNEL_SWITCH_NOTIFICATION);
  484. IWL_CMD(REPLY_SPECTRUM_MEASUREMENT_CMD);
  485. IWL_CMD(SPECTRUM_MEASURE_NOTIFICATION);
  486. IWL_CMD(POWER_TABLE_CMD);
  487. IWL_CMD(PM_SLEEP_NOTIFICATION);
  488. IWL_CMD(PM_DEBUG_STATISTIC_NOTIFIC);
  489. IWL_CMD(REPLY_SCAN_CMD);
  490. IWL_CMD(REPLY_SCAN_ABORT_CMD);
  491. IWL_CMD(SCAN_START_NOTIFICATION);
  492. IWL_CMD(SCAN_RESULTS_NOTIFICATION);
  493. IWL_CMD(SCAN_COMPLETE_NOTIFICATION);
  494. IWL_CMD(BEACON_NOTIFICATION);
  495. IWL_CMD(REPLY_TX_BEACON);
  496. IWL_CMD(WHO_IS_AWAKE_NOTIFICATION);
  497. IWL_CMD(QUIET_NOTIFICATION);
  498. IWL_CMD(REPLY_TX_PWR_TABLE_CMD);
  499. IWL_CMD(MEASURE_ABORT_NOTIFICATION);
  500. IWL_CMD(REPLY_BT_CONFIG);
  501. IWL_CMD(REPLY_STATISTICS_CMD);
  502. IWL_CMD(STATISTICS_NOTIFICATION);
  503. IWL_CMD(REPLY_CARD_STATE_CMD);
  504. IWL_CMD(CARD_STATE_NOTIFICATION);
  505. IWL_CMD(MISSED_BEACONS_NOTIFICATION);
  506. default:
  507. return "UNKNOWN";
  508. }
  509. }
  510. #define HOST_COMPLETE_TIMEOUT (HZ / 2)
  511. /**
  512. * iwl3945_enqueue_hcmd - enqueue a uCode command
  513. * @priv: device private data point
  514. * @cmd: a point to the ucode command structure
  515. *
  516. * The function returns < 0 values to indicate the operation is
  517. * failed. On success, it turns the index (> 0) of command in the
  518. * command queue.
  519. */
  520. static int iwl3945_enqueue_hcmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  521. {
  522. struct iwl3945_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
  523. struct iwl3945_queue *q = &txq->q;
  524. struct iwl3945_tfd_frame *tfd;
  525. u32 *control_flags;
  526. struct iwl3945_cmd *out_cmd;
  527. u32 idx;
  528. u16 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  529. dma_addr_t phys_addr;
  530. int pad;
  531. u16 count;
  532. int ret;
  533. unsigned long flags;
  534. /* If any of the command structures end up being larger than
  535. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  536. * we will need to increase the size of the TFD entries */
  537. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  538. !(cmd->meta.flags & CMD_SIZE_HUGE));
  539. if (iwl3945_is_rfkill(priv)) {
  540. IWL_DEBUG_INFO("Not sending command - RF KILL");
  541. return -EIO;
  542. }
  543. if (iwl3945_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
  544. IWL_ERROR("No space for Tx\n");
  545. return -ENOSPC;
  546. }
  547. spin_lock_irqsave(&priv->hcmd_lock, flags);
  548. tfd = &txq->bd[q->write_ptr];
  549. memset(tfd, 0, sizeof(*tfd));
  550. control_flags = (u32 *) tfd;
  551. idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
  552. out_cmd = &txq->cmd[idx];
  553. out_cmd->hdr.cmd = cmd->id;
  554. memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
  555. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  556. /* At this point, the out_cmd now has all of the incoming cmd
  557. * information */
  558. out_cmd->hdr.flags = 0;
  559. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
  560. INDEX_TO_SEQ(q->write_ptr));
  561. if (out_cmd->meta.flags & CMD_SIZE_HUGE)
  562. out_cmd->hdr.sequence |= cpu_to_le16(SEQ_HUGE_FRAME);
  563. phys_addr = txq->dma_addr_cmd + sizeof(txq->cmd[0]) * idx +
  564. offsetof(struct iwl3945_cmd, hdr);
  565. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
  566. pad = U32_PAD(cmd->len);
  567. count = TFD_CTL_COUNT_GET(*control_flags);
  568. *control_flags = TFD_CTL_COUNT_SET(count) | TFD_CTL_PAD_SET(pad);
  569. IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
  570. "%d bytes at %d[%d]:%d\n",
  571. get_cmd_string(out_cmd->hdr.cmd),
  572. out_cmd->hdr.cmd, le16_to_cpu(out_cmd->hdr.sequence),
  573. fix_size, q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
  574. txq->need_update = 1;
  575. /* Increment and update queue's write index */
  576. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  577. ret = iwl3945_tx_queue_update_write_ptr(priv, txq);
  578. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  579. return ret ? ret : idx;
  580. }
  581. static int iwl3945_send_cmd_async(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  582. {
  583. int ret;
  584. BUG_ON(!(cmd->meta.flags & CMD_ASYNC));
  585. /* An asynchronous command can not expect an SKB to be set. */
  586. BUG_ON(cmd->meta.flags & CMD_WANT_SKB);
  587. /* An asynchronous command MUST have a callback. */
  588. BUG_ON(!cmd->meta.u.callback);
  589. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  590. return -EBUSY;
  591. ret = iwl3945_enqueue_hcmd(priv, cmd);
  592. if (ret < 0) {
  593. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  594. get_cmd_string(cmd->id), ret);
  595. return ret;
  596. }
  597. return 0;
  598. }
  599. static int iwl3945_send_cmd_sync(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  600. {
  601. int cmd_idx;
  602. int ret;
  603. BUG_ON(cmd->meta.flags & CMD_ASYNC);
  604. /* A synchronous command can not have a callback set. */
  605. BUG_ON(cmd->meta.u.callback != NULL);
  606. if (test_and_set_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status)) {
  607. IWL_ERROR("Error sending %s: Already sending a host command\n",
  608. get_cmd_string(cmd->id));
  609. ret = -EBUSY;
  610. goto out;
  611. }
  612. set_bit(STATUS_HCMD_ACTIVE, &priv->status);
  613. if (cmd->meta.flags & CMD_WANT_SKB)
  614. cmd->meta.source = &cmd->meta;
  615. cmd_idx = iwl3945_enqueue_hcmd(priv, cmd);
  616. if (cmd_idx < 0) {
  617. ret = cmd_idx;
  618. IWL_ERROR("Error sending %s: iwl3945_enqueue_hcmd failed: %d\n",
  619. get_cmd_string(cmd->id), ret);
  620. goto out;
  621. }
  622. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  623. !test_bit(STATUS_HCMD_ACTIVE, &priv->status),
  624. HOST_COMPLETE_TIMEOUT);
  625. if (!ret) {
  626. if (test_bit(STATUS_HCMD_ACTIVE, &priv->status)) {
  627. IWL_ERROR("Error sending %s: time out after %dms.\n",
  628. get_cmd_string(cmd->id),
  629. jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
  630. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  631. ret = -ETIMEDOUT;
  632. goto cancel;
  633. }
  634. }
  635. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  636. IWL_DEBUG_INFO("Command %s aborted: RF KILL Switch\n",
  637. get_cmd_string(cmd->id));
  638. ret = -ECANCELED;
  639. goto fail;
  640. }
  641. if (test_bit(STATUS_FW_ERROR, &priv->status)) {
  642. IWL_DEBUG_INFO("Command %s failed: FW Error\n",
  643. get_cmd_string(cmd->id));
  644. ret = -EIO;
  645. goto fail;
  646. }
  647. if ((cmd->meta.flags & CMD_WANT_SKB) && !cmd->meta.u.skb) {
  648. IWL_ERROR("Error: Response NULL in '%s'\n",
  649. get_cmd_string(cmd->id));
  650. ret = -EIO;
  651. goto out;
  652. }
  653. ret = 0;
  654. goto out;
  655. cancel:
  656. if (cmd->meta.flags & CMD_WANT_SKB) {
  657. struct iwl3945_cmd *qcmd;
  658. /* Cancel the CMD_WANT_SKB flag for the cmd in the
  659. * TX cmd queue. Otherwise in case the cmd comes
  660. * in later, it will possibly set an invalid
  661. * address (cmd->meta.source). */
  662. qcmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_idx];
  663. qcmd->meta.flags &= ~CMD_WANT_SKB;
  664. }
  665. fail:
  666. if (cmd->meta.u.skb) {
  667. dev_kfree_skb_any(cmd->meta.u.skb);
  668. cmd->meta.u.skb = NULL;
  669. }
  670. out:
  671. clear_bit(STATUS_HCMD_SYNC_ACTIVE, &priv->status);
  672. return ret;
  673. }
  674. int iwl3945_send_cmd(struct iwl3945_priv *priv, struct iwl3945_host_cmd *cmd)
  675. {
  676. if (cmd->meta.flags & CMD_ASYNC)
  677. return iwl3945_send_cmd_async(priv, cmd);
  678. return iwl3945_send_cmd_sync(priv, cmd);
  679. }
  680. int iwl3945_send_cmd_pdu(struct iwl3945_priv *priv, u8 id, u16 len, const void *data)
  681. {
  682. struct iwl3945_host_cmd cmd = {
  683. .id = id,
  684. .len = len,
  685. .data = data,
  686. };
  687. return iwl3945_send_cmd_sync(priv, &cmd);
  688. }
  689. static int __must_check iwl3945_send_cmd_u32(struct iwl3945_priv *priv, u8 id, u32 val)
  690. {
  691. struct iwl3945_host_cmd cmd = {
  692. .id = id,
  693. .len = sizeof(val),
  694. .data = &val,
  695. };
  696. return iwl3945_send_cmd_sync(priv, &cmd);
  697. }
  698. int iwl3945_send_statistics_request(struct iwl3945_priv *priv)
  699. {
  700. return iwl3945_send_cmd_u32(priv, REPLY_STATISTICS_CMD, 0);
  701. }
  702. /**
  703. * iwl3945_set_rxon_channel - Set the phymode and channel values in staging RXON
  704. * @band: 2.4 or 5 GHz band
  705. * @channel: Any channel valid for the requested band
  706. * In addition to setting the staging RXON, priv->band is also set.
  707. *
  708. * NOTE: Does not commit to the hardware; it sets appropriate bit fields
  709. * in the staging RXON flag structure based on the band
  710. */
  711. static int iwl3945_set_rxon_channel(struct iwl3945_priv *priv,
  712. enum ieee80211_band band,
  713. u16 channel)
  714. {
  715. if (!iwl3945_get_channel_info(priv, band, channel)) {
  716. IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
  717. channel, band);
  718. return -EINVAL;
  719. }
  720. if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
  721. (priv->band == band))
  722. return 0;
  723. priv->staging_rxon.channel = cpu_to_le16(channel);
  724. if (band == IEEE80211_BAND_5GHZ)
  725. priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
  726. else
  727. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  728. priv->band = band;
  729. IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
  730. return 0;
  731. }
  732. /**
  733. * iwl3945_check_rxon_cmd - validate RXON structure is valid
  734. *
  735. * NOTE: This is really only useful during development and can eventually
  736. * be #ifdef'd out once the driver is stable and folks aren't actively
  737. * making changes
  738. */
  739. static int iwl3945_check_rxon_cmd(struct iwl3945_rxon_cmd *rxon)
  740. {
  741. int error = 0;
  742. int counter = 1;
  743. if (rxon->flags & RXON_FLG_BAND_24G_MSK) {
  744. error |= le32_to_cpu(rxon->flags &
  745. (RXON_FLG_TGJ_NARROW_BAND_MSK |
  746. RXON_FLG_RADAR_DETECT_MSK));
  747. if (error)
  748. IWL_WARNING("check 24G fields %d | %d\n",
  749. counter++, error);
  750. } else {
  751. error |= (rxon->flags & RXON_FLG_SHORT_SLOT_MSK) ?
  752. 0 : le32_to_cpu(RXON_FLG_SHORT_SLOT_MSK);
  753. if (error)
  754. IWL_WARNING("check 52 fields %d | %d\n",
  755. counter++, error);
  756. error |= le32_to_cpu(rxon->flags & RXON_FLG_CCK_MSK);
  757. if (error)
  758. IWL_WARNING("check 52 CCK %d | %d\n",
  759. counter++, error);
  760. }
  761. error |= (rxon->node_addr[0] | rxon->bssid_addr[0]) & 0x1;
  762. if (error)
  763. IWL_WARNING("check mac addr %d | %d\n", counter++, error);
  764. /* make sure basic rates 6Mbps and 1Mbps are supported */
  765. error |= (((rxon->ofdm_basic_rates & IWL_RATE_6M_MASK) == 0) &&
  766. ((rxon->cck_basic_rates & IWL_RATE_1M_MASK) == 0));
  767. if (error)
  768. IWL_WARNING("check basic rate %d | %d\n", counter++, error);
  769. error |= (le16_to_cpu(rxon->assoc_id) > 2007);
  770. if (error)
  771. IWL_WARNING("check assoc id %d | %d\n", counter++, error);
  772. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK))
  773. == (RXON_FLG_CCK_MSK | RXON_FLG_SHORT_SLOT_MSK));
  774. if (error)
  775. IWL_WARNING("check CCK and short slot %d | %d\n",
  776. counter++, error);
  777. error |= ((rxon->flags & (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK))
  778. == (RXON_FLG_CCK_MSK | RXON_FLG_AUTO_DETECT_MSK));
  779. if (error)
  780. IWL_WARNING("check CCK & auto detect %d | %d\n",
  781. counter++, error);
  782. error |= ((rxon->flags & (RXON_FLG_AUTO_DETECT_MSK |
  783. RXON_FLG_TGG_PROTECT_MSK)) == RXON_FLG_TGG_PROTECT_MSK);
  784. if (error)
  785. IWL_WARNING("check TGG and auto detect %d | %d\n",
  786. counter++, error);
  787. if ((rxon->flags & RXON_FLG_DIS_DIV_MSK))
  788. error |= ((rxon->flags & (RXON_FLG_ANT_B_MSK |
  789. RXON_FLG_ANT_A_MSK)) == 0);
  790. if (error)
  791. IWL_WARNING("check antenna %d %d\n", counter++, error);
  792. if (error)
  793. IWL_WARNING("Tuning to channel %d\n",
  794. le16_to_cpu(rxon->channel));
  795. if (error) {
  796. IWL_ERROR("Not a valid iwl3945_rxon_assoc_cmd field values\n");
  797. return -1;
  798. }
  799. return 0;
  800. }
  801. /**
  802. * iwl3945_full_rxon_required - check if full RXON (vs RXON_ASSOC) cmd is needed
  803. * @priv: staging_rxon is compared to active_rxon
  804. *
  805. * If the RXON structure is changing enough to require a new tune,
  806. * or is clearing the RXON_FILTER_ASSOC_MSK, then return 1 to indicate that
  807. * a new tune (full RXON command, rather than RXON_ASSOC cmd) is required.
  808. */
  809. static int iwl3945_full_rxon_required(struct iwl3945_priv *priv)
  810. {
  811. /* These items are only settable from the full RXON command */
  812. if (!(priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) ||
  813. compare_ether_addr(priv->staging_rxon.bssid_addr,
  814. priv->active_rxon.bssid_addr) ||
  815. compare_ether_addr(priv->staging_rxon.node_addr,
  816. priv->active_rxon.node_addr) ||
  817. compare_ether_addr(priv->staging_rxon.wlap_bssid_addr,
  818. priv->active_rxon.wlap_bssid_addr) ||
  819. (priv->staging_rxon.dev_type != priv->active_rxon.dev_type) ||
  820. (priv->staging_rxon.channel != priv->active_rxon.channel) ||
  821. (priv->staging_rxon.air_propagation !=
  822. priv->active_rxon.air_propagation) ||
  823. (priv->staging_rxon.assoc_id != priv->active_rxon.assoc_id))
  824. return 1;
  825. /* flags, filter_flags, ofdm_basic_rates, and cck_basic_rates can
  826. * be updated with the RXON_ASSOC command -- however only some
  827. * flag transitions are allowed using RXON_ASSOC */
  828. /* Check if we are not switching bands */
  829. if ((priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) !=
  830. (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK))
  831. return 1;
  832. /* Check if we are switching association toggle */
  833. if ((priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) !=
  834. (priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK))
  835. return 1;
  836. return 0;
  837. }
  838. static int iwl3945_send_rxon_assoc(struct iwl3945_priv *priv)
  839. {
  840. int rc = 0;
  841. struct iwl3945_rx_packet *res = NULL;
  842. struct iwl3945_rxon_assoc_cmd rxon_assoc;
  843. struct iwl3945_host_cmd cmd = {
  844. .id = REPLY_RXON_ASSOC,
  845. .len = sizeof(rxon_assoc),
  846. .meta.flags = CMD_WANT_SKB,
  847. .data = &rxon_assoc,
  848. };
  849. const struct iwl3945_rxon_cmd *rxon1 = &priv->staging_rxon;
  850. const struct iwl3945_rxon_cmd *rxon2 = &priv->active_rxon;
  851. if ((rxon1->flags == rxon2->flags) &&
  852. (rxon1->filter_flags == rxon2->filter_flags) &&
  853. (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
  854. (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
  855. IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
  856. return 0;
  857. }
  858. rxon_assoc.flags = priv->staging_rxon.flags;
  859. rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
  860. rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
  861. rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
  862. rxon_assoc.reserved = 0;
  863. rc = iwl3945_send_cmd_sync(priv, &cmd);
  864. if (rc)
  865. return rc;
  866. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  867. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  868. IWL_ERROR("Bad return from REPLY_RXON_ASSOC command\n");
  869. rc = -EIO;
  870. }
  871. priv->alloc_rxb_skb--;
  872. dev_kfree_skb_any(cmd.meta.u.skb);
  873. return rc;
  874. }
  875. /**
  876. * iwl3945_commit_rxon - commit staging_rxon to hardware
  877. *
  878. * The RXON command in staging_rxon is committed to the hardware and
  879. * the active_rxon structure is updated with the new data. This
  880. * function correctly transitions out of the RXON_ASSOC_MSK state if
  881. * a HW tune is required based on the RXON structure changes.
  882. */
  883. static int iwl3945_commit_rxon(struct iwl3945_priv *priv)
  884. {
  885. /* cast away the const for active_rxon in this function */
  886. struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  887. int rc = 0;
  888. DECLARE_MAC_BUF(mac);
  889. if (!iwl3945_is_alive(priv))
  890. return -1;
  891. /* always get timestamp with Rx frame */
  892. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  893. /* select antenna */
  894. priv->staging_rxon.flags &=
  895. ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
  896. priv->staging_rxon.flags |= iwl3945_get_antenna_flags(priv);
  897. rc = iwl3945_check_rxon_cmd(&priv->staging_rxon);
  898. if (rc) {
  899. IWL_ERROR("Invalid RXON configuration. Not committing.\n");
  900. return -EINVAL;
  901. }
  902. /* If we don't need to send a full RXON, we can use
  903. * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
  904. * and other flags for the current radio configuration. */
  905. if (!iwl3945_full_rxon_required(priv)) {
  906. rc = iwl3945_send_rxon_assoc(priv);
  907. if (rc) {
  908. IWL_ERROR("Error setting RXON_ASSOC "
  909. "configuration (%d).\n", rc);
  910. return rc;
  911. }
  912. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  913. return 0;
  914. }
  915. /* If we are currently associated and the new config requires
  916. * an RXON_ASSOC and the new config wants the associated mask enabled,
  917. * we must clear the associated from the active configuration
  918. * before we apply the new config */
  919. if (iwl3945_is_associated(priv) &&
  920. (priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK)) {
  921. IWL_DEBUG_INFO("Toggling associated bit on current RXON\n");
  922. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  923. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  924. sizeof(struct iwl3945_rxon_cmd),
  925. &priv->active_rxon);
  926. /* If the mask clearing failed then we set
  927. * active_rxon back to what it was previously */
  928. if (rc) {
  929. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  930. IWL_ERROR("Error clearing ASSOC_MSK on current "
  931. "configuration (%d).\n", rc);
  932. return rc;
  933. }
  934. }
  935. IWL_DEBUG_INFO("Sending RXON\n"
  936. "* with%s RXON_FILTER_ASSOC_MSK\n"
  937. "* channel = %d\n"
  938. "* bssid = %s\n",
  939. ((priv->staging_rxon.filter_flags &
  940. RXON_FILTER_ASSOC_MSK) ? "" : "out"),
  941. le16_to_cpu(priv->staging_rxon.channel),
  942. print_mac(mac, priv->staging_rxon.bssid_addr));
  943. /* Apply the new configuration */
  944. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON,
  945. sizeof(struct iwl3945_rxon_cmd), &priv->staging_rxon);
  946. if (rc) {
  947. IWL_ERROR("Error setting new configuration (%d).\n", rc);
  948. return rc;
  949. }
  950. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  951. iwl3945_clear_stations_table(priv);
  952. /* If we issue a new RXON command which required a tune then we must
  953. * send a new TXPOWER command or we won't be able to Tx any frames */
  954. rc = iwl3945_hw_reg_send_txpower(priv);
  955. if (rc) {
  956. IWL_ERROR("Error setting Tx power (%d).\n", rc);
  957. return rc;
  958. }
  959. /* Add the broadcast address so we can send broadcast frames */
  960. if (iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0) ==
  961. IWL_INVALID_STATION) {
  962. IWL_ERROR("Error adding BROADCAST address for transmit.\n");
  963. return -EIO;
  964. }
  965. /* If we have set the ASSOC_MSK and we are in BSS mode then
  966. * add the IWL_AP_ID to the station rate table */
  967. if (iwl3945_is_associated(priv) &&
  968. (priv->iw_mode == IEEE80211_IF_TYPE_STA))
  969. if (iwl3945_add_station(priv, priv->active_rxon.bssid_addr, 1, 0)
  970. == IWL_INVALID_STATION) {
  971. IWL_ERROR("Error adding AP address for transmit.\n");
  972. return -EIO;
  973. }
  974. /* Init the hardware's rate fallback order based on the band */
  975. rc = iwl3945_init_hw_rate_table(priv);
  976. if (rc) {
  977. IWL_ERROR("Error setting HW rate table: %02X\n", rc);
  978. return -EIO;
  979. }
  980. return 0;
  981. }
  982. static int iwl3945_send_bt_config(struct iwl3945_priv *priv)
  983. {
  984. struct iwl3945_bt_cmd bt_cmd = {
  985. .flags = 3,
  986. .lead_time = 0xAA,
  987. .max_kill = 1,
  988. .kill_ack_mask = 0,
  989. .kill_cts_mask = 0,
  990. };
  991. return iwl3945_send_cmd_pdu(priv, REPLY_BT_CONFIG,
  992. sizeof(struct iwl3945_bt_cmd), &bt_cmd);
  993. }
  994. static int iwl3945_send_scan_abort(struct iwl3945_priv *priv)
  995. {
  996. int rc = 0;
  997. struct iwl3945_rx_packet *res;
  998. struct iwl3945_host_cmd cmd = {
  999. .id = REPLY_SCAN_ABORT_CMD,
  1000. .meta.flags = CMD_WANT_SKB,
  1001. };
  1002. /* If there isn't a scan actively going on in the hardware
  1003. * then we are in between scan bands and not actually
  1004. * actively scanning, so don't send the abort command */
  1005. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1006. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1007. return 0;
  1008. }
  1009. rc = iwl3945_send_cmd_sync(priv, &cmd);
  1010. if (rc) {
  1011. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1012. return rc;
  1013. }
  1014. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1015. if (res->u.status != CAN_ABORT_STATUS) {
  1016. /* The scan abort will return 1 for success or
  1017. * 2 for "failure". A failure condition can be
  1018. * due to simply not being in an active scan which
  1019. * can occur if we send the scan abort before we
  1020. * the microcode has notified us that a scan is
  1021. * completed. */
  1022. IWL_DEBUG_INFO("SCAN_ABORT returned %d.\n", res->u.status);
  1023. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  1024. clear_bit(STATUS_SCAN_HW, &priv->status);
  1025. }
  1026. dev_kfree_skb_any(cmd.meta.u.skb);
  1027. return rc;
  1028. }
  1029. static int iwl3945_card_state_sync_callback(struct iwl3945_priv *priv,
  1030. struct iwl3945_cmd *cmd,
  1031. struct sk_buff *skb)
  1032. {
  1033. return 1;
  1034. }
  1035. /*
  1036. * CARD_STATE_CMD
  1037. *
  1038. * Use: Sets the device's internal card state to enable, disable, or halt
  1039. *
  1040. * When in the 'enable' state the card operates as normal.
  1041. * When in the 'disable' state, the card enters into a low power mode.
  1042. * When in the 'halt' state, the card is shut down and must be fully
  1043. * restarted to come back on.
  1044. */
  1045. static int iwl3945_send_card_state(struct iwl3945_priv *priv, u32 flags, u8 meta_flag)
  1046. {
  1047. struct iwl3945_host_cmd cmd = {
  1048. .id = REPLY_CARD_STATE_CMD,
  1049. .len = sizeof(u32),
  1050. .data = &flags,
  1051. .meta.flags = meta_flag,
  1052. };
  1053. if (meta_flag & CMD_ASYNC)
  1054. cmd.meta.u.callback = iwl3945_card_state_sync_callback;
  1055. return iwl3945_send_cmd(priv, &cmd);
  1056. }
  1057. static int iwl3945_add_sta_sync_callback(struct iwl3945_priv *priv,
  1058. struct iwl3945_cmd *cmd, struct sk_buff *skb)
  1059. {
  1060. struct iwl3945_rx_packet *res = NULL;
  1061. if (!skb) {
  1062. IWL_ERROR("Error: Response NULL in REPLY_ADD_STA.\n");
  1063. return 1;
  1064. }
  1065. res = (struct iwl3945_rx_packet *)skb->data;
  1066. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1067. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1068. res->hdr.flags);
  1069. return 1;
  1070. }
  1071. switch (res->u.add_sta.status) {
  1072. case ADD_STA_SUCCESS_MSK:
  1073. break;
  1074. default:
  1075. break;
  1076. }
  1077. /* We didn't cache the SKB; let the caller free it */
  1078. return 1;
  1079. }
  1080. int iwl3945_send_add_station(struct iwl3945_priv *priv,
  1081. struct iwl3945_addsta_cmd *sta, u8 flags)
  1082. {
  1083. struct iwl3945_rx_packet *res = NULL;
  1084. int rc = 0;
  1085. struct iwl3945_host_cmd cmd = {
  1086. .id = REPLY_ADD_STA,
  1087. .len = sizeof(struct iwl3945_addsta_cmd),
  1088. .meta.flags = flags,
  1089. .data = sta,
  1090. };
  1091. if (flags & CMD_ASYNC)
  1092. cmd.meta.u.callback = iwl3945_add_sta_sync_callback;
  1093. else
  1094. cmd.meta.flags |= CMD_WANT_SKB;
  1095. rc = iwl3945_send_cmd(priv, &cmd);
  1096. if (rc || (flags & CMD_ASYNC))
  1097. return rc;
  1098. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  1099. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  1100. IWL_ERROR("Bad return from REPLY_ADD_STA (0x%08X)\n",
  1101. res->hdr.flags);
  1102. rc = -EIO;
  1103. }
  1104. if (rc == 0) {
  1105. switch (res->u.add_sta.status) {
  1106. case ADD_STA_SUCCESS_MSK:
  1107. IWL_DEBUG_INFO("REPLY_ADD_STA PASSED\n");
  1108. break;
  1109. default:
  1110. rc = -EIO;
  1111. IWL_WARNING("REPLY_ADD_STA failed\n");
  1112. break;
  1113. }
  1114. }
  1115. priv->alloc_rxb_skb--;
  1116. dev_kfree_skb_any(cmd.meta.u.skb);
  1117. return rc;
  1118. }
  1119. static int iwl3945_update_sta_key_info(struct iwl3945_priv *priv,
  1120. struct ieee80211_key_conf *keyconf,
  1121. u8 sta_id)
  1122. {
  1123. unsigned long flags;
  1124. __le16 key_flags = 0;
  1125. switch (keyconf->alg) {
  1126. case ALG_CCMP:
  1127. key_flags |= STA_KEY_FLG_CCMP;
  1128. key_flags |= cpu_to_le16(
  1129. keyconf->keyidx << STA_KEY_FLG_KEYID_POS);
  1130. key_flags &= ~STA_KEY_FLG_INVALID;
  1131. break;
  1132. case ALG_TKIP:
  1133. case ALG_WEP:
  1134. default:
  1135. return -EINVAL;
  1136. }
  1137. spin_lock_irqsave(&priv->sta_lock, flags);
  1138. priv->stations[sta_id].keyinfo.alg = keyconf->alg;
  1139. priv->stations[sta_id].keyinfo.keylen = keyconf->keylen;
  1140. memcpy(priv->stations[sta_id].keyinfo.key, keyconf->key,
  1141. keyconf->keylen);
  1142. memcpy(priv->stations[sta_id].sta.key.key, keyconf->key,
  1143. keyconf->keylen);
  1144. priv->stations[sta_id].sta.key.key_flags = key_flags;
  1145. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1146. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1147. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1148. IWL_DEBUG_INFO("hwcrypto: modify ucode station key info\n");
  1149. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1150. return 0;
  1151. }
  1152. static int iwl3945_clear_sta_key_info(struct iwl3945_priv *priv, u8 sta_id)
  1153. {
  1154. unsigned long flags;
  1155. spin_lock_irqsave(&priv->sta_lock, flags);
  1156. memset(&priv->stations[sta_id].keyinfo, 0, sizeof(struct iwl3945_hw_key));
  1157. memset(&priv->stations[sta_id].sta.key, 0, sizeof(struct iwl3945_keyinfo));
  1158. priv->stations[sta_id].sta.key.key_flags = STA_KEY_FLG_NO_ENC;
  1159. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK;
  1160. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  1161. spin_unlock_irqrestore(&priv->sta_lock, flags);
  1162. IWL_DEBUG_INFO("hwcrypto: clear ucode station key info\n");
  1163. iwl3945_send_add_station(priv, &priv->stations[sta_id].sta, 0);
  1164. return 0;
  1165. }
  1166. static void iwl3945_clear_free_frames(struct iwl3945_priv *priv)
  1167. {
  1168. struct list_head *element;
  1169. IWL_DEBUG_INFO("%d frames on pre-allocated heap on clear.\n",
  1170. priv->frames_count);
  1171. while (!list_empty(&priv->free_frames)) {
  1172. element = priv->free_frames.next;
  1173. list_del(element);
  1174. kfree(list_entry(element, struct iwl3945_frame, list));
  1175. priv->frames_count--;
  1176. }
  1177. if (priv->frames_count) {
  1178. IWL_WARNING("%d frames still in use. Did we lose one?\n",
  1179. priv->frames_count);
  1180. priv->frames_count = 0;
  1181. }
  1182. }
  1183. static struct iwl3945_frame *iwl3945_get_free_frame(struct iwl3945_priv *priv)
  1184. {
  1185. struct iwl3945_frame *frame;
  1186. struct list_head *element;
  1187. if (list_empty(&priv->free_frames)) {
  1188. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  1189. if (!frame) {
  1190. IWL_ERROR("Could not allocate frame!\n");
  1191. return NULL;
  1192. }
  1193. priv->frames_count++;
  1194. return frame;
  1195. }
  1196. element = priv->free_frames.next;
  1197. list_del(element);
  1198. return list_entry(element, struct iwl3945_frame, list);
  1199. }
  1200. static void iwl3945_free_frame(struct iwl3945_priv *priv, struct iwl3945_frame *frame)
  1201. {
  1202. memset(frame, 0, sizeof(*frame));
  1203. list_add(&frame->list, &priv->free_frames);
  1204. }
  1205. unsigned int iwl3945_fill_beacon_frame(struct iwl3945_priv *priv,
  1206. struct ieee80211_hdr *hdr,
  1207. const u8 *dest, int left)
  1208. {
  1209. if (!iwl3945_is_associated(priv) || !priv->ibss_beacon ||
  1210. ((priv->iw_mode != IEEE80211_IF_TYPE_IBSS) &&
  1211. (priv->iw_mode != IEEE80211_IF_TYPE_AP)))
  1212. return 0;
  1213. if (priv->ibss_beacon->len > left)
  1214. return 0;
  1215. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  1216. return priv->ibss_beacon->len;
  1217. }
  1218. static u8 iwl3945_rate_get_lowest_plcp(int rate_mask)
  1219. {
  1220. u8 i;
  1221. for (i = IWL_RATE_1M_INDEX; i != IWL_RATE_INVALID;
  1222. i = iwl3945_rates[i].next_ieee) {
  1223. if (rate_mask & (1 << i))
  1224. return iwl3945_rates[i].plcp;
  1225. }
  1226. return IWL_RATE_INVALID;
  1227. }
  1228. static int iwl3945_send_beacon_cmd(struct iwl3945_priv *priv)
  1229. {
  1230. struct iwl3945_frame *frame;
  1231. unsigned int frame_size;
  1232. int rc;
  1233. u8 rate;
  1234. frame = iwl3945_get_free_frame(priv);
  1235. if (!frame) {
  1236. IWL_ERROR("Could not obtain free frame buffer for beacon "
  1237. "command.\n");
  1238. return -ENOMEM;
  1239. }
  1240. if (!(priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK)) {
  1241. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic &
  1242. 0xFF0);
  1243. if (rate == IWL_INVALID_RATE)
  1244. rate = IWL_RATE_6M_PLCP;
  1245. } else {
  1246. rate = iwl3945_rate_get_lowest_plcp(priv->active_rate_basic & 0xF);
  1247. if (rate == IWL_INVALID_RATE)
  1248. rate = IWL_RATE_1M_PLCP;
  1249. }
  1250. frame_size = iwl3945_hw_get_beacon_cmd(priv, frame, rate);
  1251. rc = iwl3945_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  1252. &frame->u.cmd[0]);
  1253. iwl3945_free_frame(priv, frame);
  1254. return rc;
  1255. }
  1256. /******************************************************************************
  1257. *
  1258. * EEPROM related functions
  1259. *
  1260. ******************************************************************************/
  1261. static void get_eeprom_mac(struct iwl3945_priv *priv, u8 *mac)
  1262. {
  1263. memcpy(mac, priv->eeprom.mac_address, 6);
  1264. }
  1265. /*
  1266. * Clear the OWNER_MSK, to establish driver (instead of uCode running on
  1267. * embedded controller) as EEPROM reader; each read is a series of pulses
  1268. * to/from the EEPROM chip, not a single event, so even reads could conflict
  1269. * if they weren't arbitrated by some ownership mechanism. Here, the driver
  1270. * simply claims ownership, which should be safe when this function is called
  1271. * (i.e. before loading uCode!).
  1272. */
  1273. static inline int iwl3945_eeprom_acquire_semaphore(struct iwl3945_priv *priv)
  1274. {
  1275. _iwl3945_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
  1276. return 0;
  1277. }
  1278. /**
  1279. * iwl3945_eeprom_init - read EEPROM contents
  1280. *
  1281. * Load the EEPROM contents from adapter into priv->eeprom
  1282. *
  1283. * NOTE: This routine uses the non-debug IO access functions.
  1284. */
  1285. int iwl3945_eeprom_init(struct iwl3945_priv *priv)
  1286. {
  1287. u16 *e = (u16 *)&priv->eeprom;
  1288. u32 gp = iwl3945_read32(priv, CSR_EEPROM_GP);
  1289. u32 r;
  1290. int sz = sizeof(priv->eeprom);
  1291. int rc;
  1292. int i;
  1293. u16 addr;
  1294. /* The EEPROM structure has several padding buffers within it
  1295. * and when adding new EEPROM maps is subject to programmer errors
  1296. * which may be very difficult to identify without explicitly
  1297. * checking the resulting size of the eeprom map. */
  1298. BUILD_BUG_ON(sizeof(priv->eeprom) != IWL_EEPROM_IMAGE_SIZE);
  1299. if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
  1300. IWL_ERROR("EEPROM not found, EEPROM_GP=0x%08x", gp);
  1301. return -ENOENT;
  1302. }
  1303. /* Make sure driver (instead of uCode) is allowed to read EEPROM */
  1304. rc = iwl3945_eeprom_acquire_semaphore(priv);
  1305. if (rc < 0) {
  1306. IWL_ERROR("Failed to acquire EEPROM semaphore.\n");
  1307. return -ENOENT;
  1308. }
  1309. /* eeprom is an array of 16bit values */
  1310. for (addr = 0; addr < sz; addr += sizeof(u16)) {
  1311. _iwl3945_write32(priv, CSR_EEPROM_REG, addr << 1);
  1312. _iwl3945_clear_bit(priv, CSR_EEPROM_REG, CSR_EEPROM_REG_BIT_CMD);
  1313. for (i = 0; i < IWL_EEPROM_ACCESS_TIMEOUT;
  1314. i += IWL_EEPROM_ACCESS_DELAY) {
  1315. r = _iwl3945_read_direct32(priv, CSR_EEPROM_REG);
  1316. if (r & CSR_EEPROM_REG_READ_VALID_MSK)
  1317. break;
  1318. udelay(IWL_EEPROM_ACCESS_DELAY);
  1319. }
  1320. if (!(r & CSR_EEPROM_REG_READ_VALID_MSK)) {
  1321. IWL_ERROR("Time out reading EEPROM[%d]", addr);
  1322. return -ETIMEDOUT;
  1323. }
  1324. e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
  1325. }
  1326. return 0;
  1327. }
  1328. static void iwl3945_unset_hw_setting(struct iwl3945_priv *priv)
  1329. {
  1330. if (priv->hw_setting.shared_virt)
  1331. pci_free_consistent(priv->pci_dev,
  1332. sizeof(struct iwl3945_shared),
  1333. priv->hw_setting.shared_virt,
  1334. priv->hw_setting.shared_phys);
  1335. }
  1336. /**
  1337. * iwl3945_supported_rate_to_ie - fill in the supported rate in IE field
  1338. *
  1339. * return : set the bit for each supported rate insert in ie
  1340. */
  1341. static u16 iwl3945_supported_rate_to_ie(u8 *ie, u16 supported_rate,
  1342. u16 basic_rate, int *left)
  1343. {
  1344. u16 ret_rates = 0, bit;
  1345. int i;
  1346. u8 *cnt = ie;
  1347. u8 *rates = ie + 1;
  1348. for (bit = 1, i = 0; i < IWL_RATE_COUNT; i++, bit <<= 1) {
  1349. if (bit & supported_rate) {
  1350. ret_rates |= bit;
  1351. rates[*cnt] = iwl3945_rates[i].ieee |
  1352. ((bit & basic_rate) ? 0x80 : 0x00);
  1353. (*cnt)++;
  1354. (*left)--;
  1355. if ((*left <= 0) ||
  1356. (*cnt >= IWL_SUPPORTED_RATES_IE_LEN))
  1357. break;
  1358. }
  1359. }
  1360. return ret_rates;
  1361. }
  1362. /**
  1363. * iwl3945_fill_probe_req - fill in all required fields and IE for probe request
  1364. */
  1365. static u16 iwl3945_fill_probe_req(struct iwl3945_priv *priv,
  1366. struct ieee80211_mgmt *frame,
  1367. int left, int is_direct)
  1368. {
  1369. int len = 0;
  1370. u8 *pos = NULL;
  1371. u16 active_rates, ret_rates, cck_rates;
  1372. /* Make sure there is enough space for the probe request,
  1373. * two mandatory IEs and the data */
  1374. left -= 24;
  1375. if (left < 0)
  1376. return 0;
  1377. len += 24;
  1378. frame->frame_control = cpu_to_le16(IEEE80211_STYPE_PROBE_REQ);
  1379. memcpy(frame->da, iwl3945_broadcast_addr, ETH_ALEN);
  1380. memcpy(frame->sa, priv->mac_addr, ETH_ALEN);
  1381. memcpy(frame->bssid, iwl3945_broadcast_addr, ETH_ALEN);
  1382. frame->seq_ctrl = 0;
  1383. /* fill in our indirect SSID IE */
  1384. /* ...next IE... */
  1385. left -= 2;
  1386. if (left < 0)
  1387. return 0;
  1388. len += 2;
  1389. pos = &(frame->u.probe_req.variable[0]);
  1390. *pos++ = WLAN_EID_SSID;
  1391. *pos++ = 0;
  1392. /* fill in our direct SSID IE... */
  1393. if (is_direct) {
  1394. /* ...next IE... */
  1395. left -= 2 + priv->essid_len;
  1396. if (left < 0)
  1397. return 0;
  1398. /* ... fill it in... */
  1399. *pos++ = WLAN_EID_SSID;
  1400. *pos++ = priv->essid_len;
  1401. memcpy(pos, priv->essid, priv->essid_len);
  1402. pos += priv->essid_len;
  1403. len += 2 + priv->essid_len;
  1404. }
  1405. /* fill in supported rate */
  1406. /* ...next IE... */
  1407. left -= 2;
  1408. if (left < 0)
  1409. return 0;
  1410. /* ... fill it in... */
  1411. *pos++ = WLAN_EID_SUPP_RATES;
  1412. *pos = 0;
  1413. priv->active_rate = priv->rates_mask;
  1414. active_rates = priv->active_rate;
  1415. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1416. cck_rates = IWL_CCK_RATES_MASK & active_rates;
  1417. ret_rates = iwl3945_supported_rate_to_ie(pos, cck_rates,
  1418. priv->active_rate_basic, &left);
  1419. active_rates &= ~ret_rates;
  1420. ret_rates = iwl3945_supported_rate_to_ie(pos, active_rates,
  1421. priv->active_rate_basic, &left);
  1422. active_rates &= ~ret_rates;
  1423. len += 2 + *pos;
  1424. pos += (*pos) + 1;
  1425. if (active_rates == 0)
  1426. goto fill_end;
  1427. /* fill in supported extended rate */
  1428. /* ...next IE... */
  1429. left -= 2;
  1430. if (left < 0)
  1431. return 0;
  1432. /* ... fill it in... */
  1433. *pos++ = WLAN_EID_EXT_SUPP_RATES;
  1434. *pos = 0;
  1435. iwl3945_supported_rate_to_ie(pos, active_rates,
  1436. priv->active_rate_basic, &left);
  1437. if (*pos > 0)
  1438. len += 2 + *pos;
  1439. fill_end:
  1440. return (u16)len;
  1441. }
  1442. /*
  1443. * QoS support
  1444. */
  1445. static int iwl3945_send_qos_params_command(struct iwl3945_priv *priv,
  1446. struct iwl3945_qosparam_cmd *qos)
  1447. {
  1448. return iwl3945_send_cmd_pdu(priv, REPLY_QOS_PARAM,
  1449. sizeof(struct iwl3945_qosparam_cmd), qos);
  1450. }
  1451. static void iwl3945_reset_qos(struct iwl3945_priv *priv)
  1452. {
  1453. u16 cw_min = 15;
  1454. u16 cw_max = 1023;
  1455. u8 aifs = 2;
  1456. u8 is_legacy = 0;
  1457. unsigned long flags;
  1458. int i;
  1459. spin_lock_irqsave(&priv->lock, flags);
  1460. priv->qos_data.qos_active = 0;
  1461. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
  1462. if (priv->qos_data.qos_enable)
  1463. priv->qos_data.qos_active = 1;
  1464. if (!(priv->active_rate & 0xfff0)) {
  1465. cw_min = 31;
  1466. is_legacy = 1;
  1467. }
  1468. } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1469. if (priv->qos_data.qos_enable)
  1470. priv->qos_data.qos_active = 1;
  1471. } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
  1472. cw_min = 31;
  1473. is_legacy = 1;
  1474. }
  1475. if (priv->qos_data.qos_active)
  1476. aifs = 3;
  1477. priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
  1478. priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
  1479. priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
  1480. priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
  1481. priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
  1482. if (priv->qos_data.qos_active) {
  1483. i = 1;
  1484. priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
  1485. priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
  1486. priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
  1487. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1488. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1489. i = 2;
  1490. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1491. cpu_to_le16((cw_min + 1) / 2 - 1);
  1492. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1493. cpu_to_le16(cw_max);
  1494. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1495. if (is_legacy)
  1496. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1497. cpu_to_le16(6016);
  1498. else
  1499. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1500. cpu_to_le16(3008);
  1501. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1502. i = 3;
  1503. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1504. cpu_to_le16((cw_min + 1) / 4 - 1);
  1505. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1506. cpu_to_le16((cw_max + 1) / 2 - 1);
  1507. priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
  1508. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1509. if (is_legacy)
  1510. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1511. cpu_to_le16(3264);
  1512. else
  1513. priv->qos_data.def_qos_parm.ac[i].edca_txop =
  1514. cpu_to_le16(1504);
  1515. } else {
  1516. for (i = 1; i < 4; i++) {
  1517. priv->qos_data.def_qos_parm.ac[i].cw_min =
  1518. cpu_to_le16(cw_min);
  1519. priv->qos_data.def_qos_parm.ac[i].cw_max =
  1520. cpu_to_le16(cw_max);
  1521. priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
  1522. priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
  1523. priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
  1524. }
  1525. }
  1526. IWL_DEBUG_QOS("set QoS to default \n");
  1527. spin_unlock_irqrestore(&priv->lock, flags);
  1528. }
  1529. static void iwl3945_activate_qos(struct iwl3945_priv *priv, u8 force)
  1530. {
  1531. unsigned long flags;
  1532. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1533. return;
  1534. if (!priv->qos_data.qos_enable)
  1535. return;
  1536. spin_lock_irqsave(&priv->lock, flags);
  1537. priv->qos_data.def_qos_parm.qos_flags = 0;
  1538. if (priv->qos_data.qos_cap.q_AP.queue_request &&
  1539. !priv->qos_data.qos_cap.q_AP.txop_request)
  1540. priv->qos_data.def_qos_parm.qos_flags |=
  1541. QOS_PARAM_FLG_TXOP_TYPE_MSK;
  1542. if (priv->qos_data.qos_active)
  1543. priv->qos_data.def_qos_parm.qos_flags |=
  1544. QOS_PARAM_FLG_UPDATE_EDCA_MSK;
  1545. spin_unlock_irqrestore(&priv->lock, flags);
  1546. if (force || iwl3945_is_associated(priv)) {
  1547. IWL_DEBUG_QOS("send QoS cmd with Qos active %d \n",
  1548. priv->qos_data.qos_active);
  1549. iwl3945_send_qos_params_command(priv,
  1550. &(priv->qos_data.def_qos_parm));
  1551. }
  1552. }
  1553. /*
  1554. * Power management (not Tx power!) functions
  1555. */
  1556. #define MSEC_TO_USEC 1024
  1557. #define NOSLP __constant_cpu_to_le32(0)
  1558. #define SLP IWL_POWER_DRIVER_ALLOW_SLEEP_MSK
  1559. #define SLP_TIMEOUT(T) __constant_cpu_to_le32((T) * MSEC_TO_USEC)
  1560. #define SLP_VEC(X0, X1, X2, X3, X4) {__constant_cpu_to_le32(X0), \
  1561. __constant_cpu_to_le32(X1), \
  1562. __constant_cpu_to_le32(X2), \
  1563. __constant_cpu_to_le32(X3), \
  1564. __constant_cpu_to_le32(X4)}
  1565. /* default power management (not Tx power) table values */
  1566. /* for tim 0-10 */
  1567. static struct iwl3945_power_vec_entry range_0[IWL_POWER_AC] = {
  1568. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1569. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500), SLP_VEC(1, 2, 3, 4, 4)}, 0},
  1570. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300), SLP_VEC(2, 4, 6, 7, 7)}, 0},
  1571. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100), SLP_VEC(2, 6, 9, 9, 10)}, 0},
  1572. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 10)}, 1},
  1573. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25), SLP_VEC(4, 7, 10, 10, 10)}, 1}
  1574. };
  1575. /* for tim > 10 */
  1576. static struct iwl3945_power_vec_entry range_1[IWL_POWER_AC] = {
  1577. {{NOSLP, SLP_TIMEOUT(0), SLP_TIMEOUT(0), SLP_VEC(0, 0, 0, 0, 0)}, 0},
  1578. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(500),
  1579. SLP_VEC(1, 2, 3, 4, 0xFF)}, 0},
  1580. {{SLP, SLP_TIMEOUT(200), SLP_TIMEOUT(300),
  1581. SLP_VEC(2, 4, 6, 7, 0xFF)}, 0},
  1582. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(100),
  1583. SLP_VEC(2, 6, 9, 9, 0xFF)}, 0},
  1584. {{SLP, SLP_TIMEOUT(50), SLP_TIMEOUT(25), SLP_VEC(2, 7, 9, 9, 0xFF)}, 0},
  1585. {{SLP, SLP_TIMEOUT(25), SLP_TIMEOUT(25),
  1586. SLP_VEC(4, 7, 10, 10, 0xFF)}, 0}
  1587. };
  1588. int iwl3945_power_init_handle(struct iwl3945_priv *priv)
  1589. {
  1590. int rc = 0, i;
  1591. struct iwl3945_power_mgr *pow_data;
  1592. int size = sizeof(struct iwl3945_power_vec_entry) * IWL_POWER_AC;
  1593. u16 pci_pm;
  1594. IWL_DEBUG_POWER("Initialize power \n");
  1595. pow_data = &(priv->power_data);
  1596. memset(pow_data, 0, sizeof(*pow_data));
  1597. pow_data->active_index = IWL_POWER_RANGE_0;
  1598. pow_data->dtim_val = 0xffff;
  1599. memcpy(&pow_data->pwr_range_0[0], &range_0[0], size);
  1600. memcpy(&pow_data->pwr_range_1[0], &range_1[0], size);
  1601. rc = pci_read_config_word(priv->pci_dev, PCI_LINK_CTRL, &pci_pm);
  1602. if (rc != 0)
  1603. return 0;
  1604. else {
  1605. struct iwl3945_powertable_cmd *cmd;
  1606. IWL_DEBUG_POWER("adjust power command flags\n");
  1607. for (i = 0; i < IWL_POWER_AC; i++) {
  1608. cmd = &pow_data->pwr_range_0[i].cmd;
  1609. if (pci_pm & 0x1)
  1610. cmd->flags &= ~IWL_POWER_PCI_PM_MSK;
  1611. else
  1612. cmd->flags |= IWL_POWER_PCI_PM_MSK;
  1613. }
  1614. }
  1615. return rc;
  1616. }
  1617. static int iwl3945_update_power_cmd(struct iwl3945_priv *priv,
  1618. struct iwl3945_powertable_cmd *cmd, u32 mode)
  1619. {
  1620. int rc = 0, i;
  1621. u8 skip;
  1622. u32 max_sleep = 0;
  1623. struct iwl3945_power_vec_entry *range;
  1624. u8 period = 0;
  1625. struct iwl3945_power_mgr *pow_data;
  1626. if (mode > IWL_POWER_INDEX_5) {
  1627. IWL_DEBUG_POWER("Error invalid power mode \n");
  1628. return -1;
  1629. }
  1630. pow_data = &(priv->power_data);
  1631. if (pow_data->active_index == IWL_POWER_RANGE_0)
  1632. range = &pow_data->pwr_range_0[0];
  1633. else
  1634. range = &pow_data->pwr_range_1[1];
  1635. memcpy(cmd, &range[mode].cmd, sizeof(struct iwl3945_powertable_cmd));
  1636. #ifdef IWL_MAC80211_DISABLE
  1637. if (priv->assoc_network != NULL) {
  1638. unsigned long flags;
  1639. period = priv->assoc_network->tim.tim_period;
  1640. }
  1641. #endif /*IWL_MAC80211_DISABLE */
  1642. skip = range[mode].no_dtim;
  1643. if (period == 0) {
  1644. period = 1;
  1645. skip = 0;
  1646. }
  1647. if (skip == 0) {
  1648. max_sleep = period;
  1649. cmd->flags &= ~IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1650. } else {
  1651. __le32 slp_itrvl = cmd->sleep_interval[IWL_POWER_VEC_SIZE - 1];
  1652. max_sleep = (le32_to_cpu(slp_itrvl) / period) * period;
  1653. cmd->flags |= IWL_POWER_SLEEP_OVER_DTIM_MSK;
  1654. }
  1655. for (i = 0; i < IWL_POWER_VEC_SIZE; i++) {
  1656. if (le32_to_cpu(cmd->sleep_interval[i]) > max_sleep)
  1657. cmd->sleep_interval[i] = cpu_to_le32(max_sleep);
  1658. }
  1659. IWL_DEBUG_POWER("Flags value = 0x%08X\n", cmd->flags);
  1660. IWL_DEBUG_POWER("Tx timeout = %u\n", le32_to_cpu(cmd->tx_data_timeout));
  1661. IWL_DEBUG_POWER("Rx timeout = %u\n", le32_to_cpu(cmd->rx_data_timeout));
  1662. IWL_DEBUG_POWER("Sleep interval vector = { %d , %d , %d , %d , %d }\n",
  1663. le32_to_cpu(cmd->sleep_interval[0]),
  1664. le32_to_cpu(cmd->sleep_interval[1]),
  1665. le32_to_cpu(cmd->sleep_interval[2]),
  1666. le32_to_cpu(cmd->sleep_interval[3]),
  1667. le32_to_cpu(cmd->sleep_interval[4]));
  1668. return rc;
  1669. }
  1670. static int iwl3945_send_power_mode(struct iwl3945_priv *priv, u32 mode)
  1671. {
  1672. u32 uninitialized_var(final_mode);
  1673. int rc;
  1674. struct iwl3945_powertable_cmd cmd;
  1675. /* If on battery, set to 3,
  1676. * if plugged into AC power, set to CAM ("continuously aware mode"),
  1677. * else user level */
  1678. switch (mode) {
  1679. case IWL_POWER_BATTERY:
  1680. final_mode = IWL_POWER_INDEX_3;
  1681. break;
  1682. case IWL_POWER_AC:
  1683. final_mode = IWL_POWER_MODE_CAM;
  1684. break;
  1685. default:
  1686. final_mode = mode;
  1687. break;
  1688. }
  1689. iwl3945_update_power_cmd(priv, &cmd, final_mode);
  1690. rc = iwl3945_send_cmd_pdu(priv, POWER_TABLE_CMD, sizeof(cmd), &cmd);
  1691. if (final_mode == IWL_POWER_MODE_CAM)
  1692. clear_bit(STATUS_POWER_PMI, &priv->status);
  1693. else
  1694. set_bit(STATUS_POWER_PMI, &priv->status);
  1695. return rc;
  1696. }
  1697. int iwl3945_is_network_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  1698. {
  1699. /* Filter incoming packets to determine if they are targeted toward
  1700. * this network, discarding packets coming from ourselves */
  1701. switch (priv->iw_mode) {
  1702. case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source | BSSID */
  1703. /* packets from our adapter are dropped (echo) */
  1704. if (!compare_ether_addr(header->addr2, priv->mac_addr))
  1705. return 0;
  1706. /* {broad,multi}cast packets to our IBSS go through */
  1707. if (is_multicast_ether_addr(header->addr1))
  1708. return !compare_ether_addr(header->addr3, priv->bssid);
  1709. /* packets to our adapter go through */
  1710. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1711. case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
  1712. /* packets from our adapter are dropped (echo) */
  1713. if (!compare_ether_addr(header->addr3, priv->mac_addr))
  1714. return 0;
  1715. /* {broad,multi}cast packets to our BSS go through */
  1716. if (is_multicast_ether_addr(header->addr1))
  1717. return !compare_ether_addr(header->addr2, priv->bssid);
  1718. /* packets to our adapter go through */
  1719. return !compare_ether_addr(header->addr1, priv->mac_addr);
  1720. default:
  1721. return 1;
  1722. }
  1723. return 1;
  1724. }
  1725. /**
  1726. * iwl3945_scan_cancel - Cancel any currently executing HW scan
  1727. *
  1728. * NOTE: priv->mutex is not required before calling this function
  1729. */
  1730. static int iwl3945_scan_cancel(struct iwl3945_priv *priv)
  1731. {
  1732. if (!test_bit(STATUS_SCAN_HW, &priv->status)) {
  1733. clear_bit(STATUS_SCANNING, &priv->status);
  1734. return 0;
  1735. }
  1736. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1737. if (!test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1738. IWL_DEBUG_SCAN("Queuing scan abort.\n");
  1739. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  1740. queue_work(priv->workqueue, &priv->abort_scan);
  1741. } else
  1742. IWL_DEBUG_SCAN("Scan abort already in progress.\n");
  1743. return test_bit(STATUS_SCANNING, &priv->status);
  1744. }
  1745. return 0;
  1746. }
  1747. /**
  1748. * iwl3945_scan_cancel_timeout - Cancel any currently executing HW scan
  1749. * @ms: amount of time to wait (in milliseconds) for scan to abort
  1750. *
  1751. * NOTE: priv->mutex must be held before calling this function
  1752. */
  1753. static int iwl3945_scan_cancel_timeout(struct iwl3945_priv *priv, unsigned long ms)
  1754. {
  1755. unsigned long now = jiffies;
  1756. int ret;
  1757. ret = iwl3945_scan_cancel(priv);
  1758. if (ret && ms) {
  1759. mutex_unlock(&priv->mutex);
  1760. while (!time_after(jiffies, now + msecs_to_jiffies(ms)) &&
  1761. test_bit(STATUS_SCANNING, &priv->status))
  1762. msleep(1);
  1763. mutex_lock(&priv->mutex);
  1764. return test_bit(STATUS_SCANNING, &priv->status);
  1765. }
  1766. return ret;
  1767. }
  1768. static void iwl3945_sequence_reset(struct iwl3945_priv *priv)
  1769. {
  1770. /* Reset ieee stats */
  1771. /* We don't reset the net_device_stats (ieee->stats) on
  1772. * re-association */
  1773. priv->last_seq_num = -1;
  1774. priv->last_frag_num = -1;
  1775. priv->last_packet_time = 0;
  1776. iwl3945_scan_cancel(priv);
  1777. }
  1778. #define MAX_UCODE_BEACON_INTERVAL 1024
  1779. #define INTEL_CONN_LISTEN_INTERVAL __constant_cpu_to_le16(0xA)
  1780. static __le16 iwl3945_adjust_beacon_interval(u16 beacon_val)
  1781. {
  1782. u16 new_val = 0;
  1783. u16 beacon_factor = 0;
  1784. beacon_factor =
  1785. (beacon_val + MAX_UCODE_BEACON_INTERVAL)
  1786. / MAX_UCODE_BEACON_INTERVAL;
  1787. new_val = beacon_val / beacon_factor;
  1788. return cpu_to_le16(new_val);
  1789. }
  1790. static void iwl3945_setup_rxon_timing(struct iwl3945_priv *priv)
  1791. {
  1792. u64 interval_tm_unit;
  1793. u64 tsf, result;
  1794. unsigned long flags;
  1795. struct ieee80211_conf *conf = NULL;
  1796. u16 beacon_int = 0;
  1797. conf = ieee80211_get_hw_conf(priv->hw);
  1798. spin_lock_irqsave(&priv->lock, flags);
  1799. priv->rxon_timing.timestamp.dw[1] = cpu_to_le32(priv->timestamp1);
  1800. priv->rxon_timing.timestamp.dw[0] = cpu_to_le32(priv->timestamp0);
  1801. priv->rxon_timing.listen_interval = INTEL_CONN_LISTEN_INTERVAL;
  1802. tsf = priv->timestamp1;
  1803. tsf = ((tsf << 32) | priv->timestamp0);
  1804. beacon_int = priv->beacon_int;
  1805. spin_unlock_irqrestore(&priv->lock, flags);
  1806. if (priv->iw_mode == IEEE80211_IF_TYPE_STA) {
  1807. if (beacon_int == 0) {
  1808. priv->rxon_timing.beacon_interval = cpu_to_le16(100);
  1809. priv->rxon_timing.beacon_init_val = cpu_to_le32(102400);
  1810. } else {
  1811. priv->rxon_timing.beacon_interval =
  1812. cpu_to_le16(beacon_int);
  1813. priv->rxon_timing.beacon_interval =
  1814. iwl3945_adjust_beacon_interval(
  1815. le16_to_cpu(priv->rxon_timing.beacon_interval));
  1816. }
  1817. priv->rxon_timing.atim_window = 0;
  1818. } else {
  1819. priv->rxon_timing.beacon_interval =
  1820. iwl3945_adjust_beacon_interval(conf->beacon_int);
  1821. /* TODO: we need to get atim_window from upper stack
  1822. * for now we set to 0 */
  1823. priv->rxon_timing.atim_window = 0;
  1824. }
  1825. interval_tm_unit =
  1826. (le16_to_cpu(priv->rxon_timing.beacon_interval) * 1024);
  1827. result = do_div(tsf, interval_tm_unit);
  1828. priv->rxon_timing.beacon_init_val =
  1829. cpu_to_le32((u32) ((u64) interval_tm_unit - result));
  1830. IWL_DEBUG_ASSOC
  1831. ("beacon interval %d beacon timer %d beacon tim %d\n",
  1832. le16_to_cpu(priv->rxon_timing.beacon_interval),
  1833. le32_to_cpu(priv->rxon_timing.beacon_init_val),
  1834. le16_to_cpu(priv->rxon_timing.atim_window));
  1835. }
  1836. static int iwl3945_scan_initiate(struct iwl3945_priv *priv)
  1837. {
  1838. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  1839. IWL_ERROR("APs don't scan.\n");
  1840. return 0;
  1841. }
  1842. if (!iwl3945_is_ready_rf(priv)) {
  1843. IWL_DEBUG_SCAN("Aborting scan due to not ready.\n");
  1844. return -EIO;
  1845. }
  1846. if (test_bit(STATUS_SCANNING, &priv->status)) {
  1847. IWL_DEBUG_SCAN("Scan already in progress.\n");
  1848. return -EAGAIN;
  1849. }
  1850. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1851. IWL_DEBUG_SCAN("Scan request while abort pending. "
  1852. "Queuing.\n");
  1853. return -EAGAIN;
  1854. }
  1855. IWL_DEBUG_INFO("Starting scan...\n");
  1856. if (priv->cfg->sku & IWL_SKU_G)
  1857. priv->scan_bands |= BIT(IEEE80211_BAND_2GHZ);
  1858. if (priv->cfg->sku & IWL_SKU_A)
  1859. priv->scan_bands |= BIT(IEEE80211_BAND_5GHZ);
  1860. set_bit(STATUS_SCANNING, &priv->status);
  1861. priv->scan_start = jiffies;
  1862. priv->scan_pass_start = priv->scan_start;
  1863. queue_work(priv->workqueue, &priv->request_scan);
  1864. return 0;
  1865. }
  1866. static int iwl3945_set_rxon_hwcrypto(struct iwl3945_priv *priv, int hw_decrypt)
  1867. {
  1868. struct iwl3945_rxon_cmd *rxon = &priv->staging_rxon;
  1869. if (hw_decrypt)
  1870. rxon->filter_flags &= ~RXON_FILTER_DIS_DECRYPT_MSK;
  1871. else
  1872. rxon->filter_flags |= RXON_FILTER_DIS_DECRYPT_MSK;
  1873. return 0;
  1874. }
  1875. static void iwl3945_set_flags_for_phymode(struct iwl3945_priv *priv,
  1876. enum ieee80211_band band)
  1877. {
  1878. if (band == IEEE80211_BAND_5GHZ) {
  1879. priv->staging_rxon.flags &=
  1880. ~(RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK
  1881. | RXON_FLG_CCK_MSK);
  1882. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1883. } else {
  1884. /* Copied from iwl3945_bg_post_associate() */
  1885. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1886. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1887. else
  1888. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1889. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  1890. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1891. priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
  1892. priv->staging_rxon.flags |= RXON_FLG_AUTO_DETECT_MSK;
  1893. priv->staging_rxon.flags &= ~RXON_FLG_CCK_MSK;
  1894. }
  1895. }
  1896. /*
  1897. * initialize rxon structure with default values from eeprom
  1898. */
  1899. static void iwl3945_connection_init_rx_config(struct iwl3945_priv *priv)
  1900. {
  1901. const struct iwl3945_channel_info *ch_info;
  1902. memset(&priv->staging_rxon, 0, sizeof(priv->staging_rxon));
  1903. switch (priv->iw_mode) {
  1904. case IEEE80211_IF_TYPE_AP:
  1905. priv->staging_rxon.dev_type = RXON_DEV_TYPE_AP;
  1906. break;
  1907. case IEEE80211_IF_TYPE_STA:
  1908. priv->staging_rxon.dev_type = RXON_DEV_TYPE_ESS;
  1909. priv->staging_rxon.filter_flags = RXON_FILTER_ACCEPT_GRP_MSK;
  1910. break;
  1911. case IEEE80211_IF_TYPE_IBSS:
  1912. priv->staging_rxon.dev_type = RXON_DEV_TYPE_IBSS;
  1913. priv->staging_rxon.flags = RXON_FLG_SHORT_PREAMBLE_MSK;
  1914. priv->staging_rxon.filter_flags = RXON_FILTER_BCON_AWARE_MSK |
  1915. RXON_FILTER_ACCEPT_GRP_MSK;
  1916. break;
  1917. case IEEE80211_IF_TYPE_MNTR:
  1918. priv->staging_rxon.dev_type = RXON_DEV_TYPE_SNIFFER;
  1919. priv->staging_rxon.filter_flags = RXON_FILTER_PROMISC_MSK |
  1920. RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_ACCEPT_GRP_MSK;
  1921. break;
  1922. default:
  1923. IWL_ERROR("Unsupported interface type %d\n", priv->iw_mode);
  1924. break;
  1925. }
  1926. #if 0
  1927. /* TODO: Figure out when short_preamble would be set and cache from
  1928. * that */
  1929. if (!hw_to_local(priv->hw)->short_preamble)
  1930. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1931. else
  1932. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1933. #endif
  1934. ch_info = iwl3945_get_channel_info(priv, priv->band,
  1935. le16_to_cpu(priv->staging_rxon.channel));
  1936. if (!ch_info)
  1937. ch_info = &priv->channel_info[0];
  1938. /*
  1939. * in some case A channels are all non IBSS
  1940. * in this case force B/G channel
  1941. */
  1942. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  1943. !(is_channel_ibss(ch_info)))
  1944. ch_info = &priv->channel_info[0];
  1945. priv->staging_rxon.channel = cpu_to_le16(ch_info->channel);
  1946. if (is_channel_a_band(ch_info))
  1947. priv->band = IEEE80211_BAND_5GHZ;
  1948. else
  1949. priv->band = IEEE80211_BAND_2GHZ;
  1950. iwl3945_set_flags_for_phymode(priv, priv->band);
  1951. priv->staging_rxon.ofdm_basic_rates =
  1952. (IWL_OFDM_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  1953. priv->staging_rxon.cck_basic_rates =
  1954. (IWL_CCK_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  1955. }
  1956. static int iwl3945_set_mode(struct iwl3945_priv *priv, int mode)
  1957. {
  1958. if (mode == IEEE80211_IF_TYPE_IBSS) {
  1959. const struct iwl3945_channel_info *ch_info;
  1960. ch_info = iwl3945_get_channel_info(priv,
  1961. priv->band,
  1962. le16_to_cpu(priv->staging_rxon.channel));
  1963. if (!ch_info || !is_channel_ibss(ch_info)) {
  1964. IWL_ERROR("channel %d not IBSS channel\n",
  1965. le16_to_cpu(priv->staging_rxon.channel));
  1966. return -EINVAL;
  1967. }
  1968. }
  1969. priv->iw_mode = mode;
  1970. iwl3945_connection_init_rx_config(priv);
  1971. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1972. iwl3945_clear_stations_table(priv);
  1973. /* dont commit rxon if rf-kill is on*/
  1974. if (!iwl3945_is_ready_rf(priv))
  1975. return -EAGAIN;
  1976. cancel_delayed_work(&priv->scan_check);
  1977. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  1978. IWL_WARNING("Aborted scan still in progress after 100ms\n");
  1979. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  1980. return -EAGAIN;
  1981. }
  1982. iwl3945_commit_rxon(priv);
  1983. return 0;
  1984. }
  1985. static void iwl3945_build_tx_cmd_hwcrypto(struct iwl3945_priv *priv,
  1986. struct ieee80211_tx_info *info,
  1987. struct iwl3945_cmd *cmd,
  1988. struct sk_buff *skb_frag,
  1989. int last_frag)
  1990. {
  1991. struct iwl3945_hw_key *keyinfo =
  1992. &priv->stations[info->control.hw_key->hw_key_idx].keyinfo;
  1993. switch (keyinfo->alg) {
  1994. case ALG_CCMP:
  1995. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_CCM;
  1996. memcpy(cmd->cmd.tx.key, keyinfo->key, keyinfo->keylen);
  1997. IWL_DEBUG_TX("tx_cmd with aes hwcrypto\n");
  1998. break;
  1999. case ALG_TKIP:
  2000. #if 0
  2001. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_TKIP;
  2002. if (last_frag)
  2003. memcpy(cmd->cmd.tx.tkip_mic.byte, skb_frag->tail - 8,
  2004. 8);
  2005. else
  2006. memset(cmd->cmd.tx.tkip_mic.byte, 0, 8);
  2007. #endif
  2008. break;
  2009. case ALG_WEP:
  2010. cmd->cmd.tx.sec_ctl = TX_CMD_SEC_WEP |
  2011. (info->control.hw_key->hw_key_idx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT;
  2012. if (keyinfo->keylen == 13)
  2013. cmd->cmd.tx.sec_ctl |= TX_CMD_SEC_KEY128;
  2014. memcpy(&cmd->cmd.tx.key[3], keyinfo->key, keyinfo->keylen);
  2015. IWL_DEBUG_TX("Configuring packet for WEP encryption "
  2016. "with key %d\n", info->control.hw_key->hw_key_idx);
  2017. break;
  2018. default:
  2019. printk(KERN_ERR "Unknown encode alg %d\n", keyinfo->alg);
  2020. break;
  2021. }
  2022. }
  2023. /*
  2024. * handle build REPLY_TX command notification.
  2025. */
  2026. static void iwl3945_build_tx_cmd_basic(struct iwl3945_priv *priv,
  2027. struct iwl3945_cmd *cmd,
  2028. struct ieee80211_tx_info *info,
  2029. struct ieee80211_hdr *hdr,
  2030. int is_unicast, u8 std_id)
  2031. {
  2032. __le16 fc = hdr->frame_control;
  2033. __le32 tx_flags = cmd->cmd.tx.tx_flags;
  2034. cmd->cmd.tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2035. if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
  2036. tx_flags |= TX_CMD_FLG_ACK_MSK;
  2037. if (ieee80211_is_mgmt(fc))
  2038. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2039. if (ieee80211_is_probe_resp(fc) &&
  2040. !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
  2041. tx_flags |= TX_CMD_FLG_TSF_MSK;
  2042. } else {
  2043. tx_flags &= (~TX_CMD_FLG_ACK_MSK);
  2044. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2045. }
  2046. cmd->cmd.tx.sta_id = std_id;
  2047. if (ieee80211_has_morefrags(fc))
  2048. tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
  2049. if (ieee80211_is_data_qos(fc)) {
  2050. u8 *qc = ieee80211_get_qos_ctl(hdr);
  2051. cmd->cmd.tx.tid_tspec = qc[0] & 0xf;
  2052. tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
  2053. } else {
  2054. tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
  2055. }
  2056. if (info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) {
  2057. tx_flags |= TX_CMD_FLG_RTS_MSK;
  2058. tx_flags &= ~TX_CMD_FLG_CTS_MSK;
  2059. } else if (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT) {
  2060. tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2061. tx_flags |= TX_CMD_FLG_CTS_MSK;
  2062. }
  2063. if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
  2064. tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
  2065. tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
  2066. if (ieee80211_is_mgmt(fc)) {
  2067. if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
  2068. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(3);
  2069. else
  2070. cmd->cmd.tx.timeout.pm_frame_timeout = cpu_to_le16(2);
  2071. } else {
  2072. cmd->cmd.tx.timeout.pm_frame_timeout = 0;
  2073. #ifdef CONFIG_IWL3945_LEDS
  2074. priv->rxtxpackets += le16_to_cpu(cmd->cmd.tx.len);
  2075. #endif
  2076. }
  2077. cmd->cmd.tx.driver_txop = 0;
  2078. cmd->cmd.tx.tx_flags = tx_flags;
  2079. cmd->cmd.tx.next_frame_len = 0;
  2080. }
  2081. /**
  2082. * iwl3945_get_sta_id - Find station's index within station table
  2083. */
  2084. static int iwl3945_get_sta_id(struct iwl3945_priv *priv, struct ieee80211_hdr *hdr)
  2085. {
  2086. int sta_id;
  2087. u16 fc = le16_to_cpu(hdr->frame_control);
  2088. /* If this frame is broadcast or management, use broadcast station id */
  2089. if (((fc & IEEE80211_FCTL_FTYPE) != IEEE80211_FTYPE_DATA) ||
  2090. is_multicast_ether_addr(hdr->addr1))
  2091. return priv->hw_setting.bcast_sta_id;
  2092. switch (priv->iw_mode) {
  2093. /* If we are a client station in a BSS network, use the special
  2094. * AP station entry (that's the only station we communicate with) */
  2095. case IEEE80211_IF_TYPE_STA:
  2096. return IWL_AP_ID;
  2097. /* If we are an AP, then find the station, or use BCAST */
  2098. case IEEE80211_IF_TYPE_AP:
  2099. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2100. if (sta_id != IWL_INVALID_STATION)
  2101. return sta_id;
  2102. return priv->hw_setting.bcast_sta_id;
  2103. /* If this frame is going out to an IBSS network, find the station,
  2104. * or create a new station table entry */
  2105. case IEEE80211_IF_TYPE_IBSS: {
  2106. DECLARE_MAC_BUF(mac);
  2107. /* Create new station table entry */
  2108. sta_id = iwl3945_hw_find_station(priv, hdr->addr1);
  2109. if (sta_id != IWL_INVALID_STATION)
  2110. return sta_id;
  2111. sta_id = iwl3945_add_station(priv, hdr->addr1, 0, CMD_ASYNC);
  2112. if (sta_id != IWL_INVALID_STATION)
  2113. return sta_id;
  2114. IWL_DEBUG_DROP("Station %s not in station map. "
  2115. "Defaulting to broadcast...\n",
  2116. print_mac(mac, hdr->addr1));
  2117. iwl3945_print_hex_dump(IWL_DL_DROP, (u8 *) hdr, sizeof(*hdr));
  2118. return priv->hw_setting.bcast_sta_id;
  2119. }
  2120. default:
  2121. IWL_WARNING("Unknown mode of operation: %d", priv->iw_mode);
  2122. return priv->hw_setting.bcast_sta_id;
  2123. }
  2124. }
  2125. /*
  2126. * start REPLY_TX command process
  2127. */
  2128. static int iwl3945_tx_skb(struct iwl3945_priv *priv, struct sk_buff *skb)
  2129. {
  2130. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  2131. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  2132. struct iwl3945_tfd_frame *tfd;
  2133. u32 *control_flags;
  2134. int txq_id = skb_get_queue_mapping(skb);
  2135. struct iwl3945_tx_queue *txq = NULL;
  2136. struct iwl3945_queue *q = NULL;
  2137. dma_addr_t phys_addr;
  2138. dma_addr_t txcmd_phys;
  2139. struct iwl3945_cmd *out_cmd = NULL;
  2140. u16 len, idx, len_org, hdr_len;
  2141. u8 id;
  2142. u8 unicast;
  2143. u8 sta_id;
  2144. u8 tid = 0;
  2145. u16 seq_number = 0;
  2146. __le16 fc;
  2147. u8 wait_write_ptr = 0;
  2148. u8 *qc = NULL;
  2149. unsigned long flags;
  2150. int rc;
  2151. spin_lock_irqsave(&priv->lock, flags);
  2152. if (iwl3945_is_rfkill(priv)) {
  2153. IWL_DEBUG_DROP("Dropping - RF KILL\n");
  2154. goto drop_unlock;
  2155. }
  2156. if (!priv->vif) {
  2157. IWL_DEBUG_DROP("Dropping - !priv->vif\n");
  2158. goto drop_unlock;
  2159. }
  2160. if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) == IWL_INVALID_RATE) {
  2161. IWL_ERROR("ERROR: No TX rate available.\n");
  2162. goto drop_unlock;
  2163. }
  2164. unicast = !is_multicast_ether_addr(hdr->addr1);
  2165. id = 0;
  2166. fc = hdr->frame_control;
  2167. #ifdef CONFIG_IWL3945_DEBUG
  2168. if (ieee80211_is_auth(fc))
  2169. IWL_DEBUG_TX("Sending AUTH frame\n");
  2170. else if (ieee80211_is_assoc_req(fc))
  2171. IWL_DEBUG_TX("Sending ASSOC frame\n");
  2172. else if (ieee80211_is_reassoc_req(fc))
  2173. IWL_DEBUG_TX("Sending REASSOC frame\n");
  2174. #endif
  2175. /* drop all data frame if we are not associated */
  2176. if ((!iwl3945_is_associated(priv) ||
  2177. ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && !priv->assoc_id)) &&
  2178. ieee80211_is_data(fc)) {
  2179. IWL_DEBUG_DROP("Dropping - !iwl3945_is_associated\n");
  2180. goto drop_unlock;
  2181. }
  2182. spin_unlock_irqrestore(&priv->lock, flags);
  2183. hdr_len = ieee80211_get_hdrlen(le16_to_cpu(fc));
  2184. /* Find (or create) index into station table for destination station */
  2185. sta_id = iwl3945_get_sta_id(priv, hdr);
  2186. if (sta_id == IWL_INVALID_STATION) {
  2187. DECLARE_MAC_BUF(mac);
  2188. IWL_DEBUG_DROP("Dropping - INVALID STATION: %s\n",
  2189. print_mac(mac, hdr->addr1));
  2190. goto drop;
  2191. }
  2192. IWL_DEBUG_RATE("station Id %d\n", sta_id);
  2193. if (ieee80211_is_data_qos(fc)) {
  2194. qc = ieee80211_get_qos_ctl(hdr);
  2195. tid = qc[0] & 0xf;
  2196. seq_number = priv->stations[sta_id].tid[tid].seq_number &
  2197. IEEE80211_SCTL_SEQ;
  2198. hdr->seq_ctrl = cpu_to_le16(seq_number) |
  2199. (hdr->seq_ctrl &
  2200. __constant_cpu_to_le16(IEEE80211_SCTL_FRAG));
  2201. seq_number += 0x10;
  2202. }
  2203. /* Descriptor for chosen Tx queue */
  2204. txq = &priv->txq[txq_id];
  2205. q = &txq->q;
  2206. spin_lock_irqsave(&priv->lock, flags);
  2207. /* Set up first empty TFD within this queue's circular TFD buffer */
  2208. tfd = &txq->bd[q->write_ptr];
  2209. memset(tfd, 0, sizeof(*tfd));
  2210. control_flags = (u32 *) tfd;
  2211. idx = get_cmd_index(q, q->write_ptr, 0);
  2212. /* Set up driver data for this TFD */
  2213. memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl3945_tx_info));
  2214. txq->txb[q->write_ptr].skb[0] = skb;
  2215. /* Init first empty entry in queue's array of Tx/cmd buffers */
  2216. out_cmd = &txq->cmd[idx];
  2217. memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
  2218. memset(&out_cmd->cmd.tx, 0, sizeof(out_cmd->cmd.tx));
  2219. /*
  2220. * Set up the Tx-command (not MAC!) header.
  2221. * Store the chosen Tx queue and TFD index within the sequence field;
  2222. * after Tx, uCode's Tx response will return this value so driver can
  2223. * locate the frame within the tx queue and do post-tx processing.
  2224. */
  2225. out_cmd->hdr.cmd = REPLY_TX;
  2226. out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
  2227. INDEX_TO_SEQ(q->write_ptr)));
  2228. /* Copy MAC header from skb into command buffer */
  2229. memcpy(out_cmd->cmd.tx.hdr, hdr, hdr_len);
  2230. /*
  2231. * Use the first empty entry in this queue's command buffer array
  2232. * to contain the Tx command and MAC header concatenated together
  2233. * (payload data will be in another buffer).
  2234. * Size of this varies, due to varying MAC header length.
  2235. * If end is not dword aligned, we'll have 2 extra bytes at the end
  2236. * of the MAC header (device reads on dword boundaries).
  2237. * We'll tell device about this padding later.
  2238. */
  2239. len = priv->hw_setting.tx_cmd_len +
  2240. sizeof(struct iwl3945_cmd_header) + hdr_len;
  2241. len_org = len;
  2242. len = (len + 3) & ~3;
  2243. if (len_org != len)
  2244. len_org = 1;
  2245. else
  2246. len_org = 0;
  2247. /* Physical address of this Tx command's header (not MAC header!),
  2248. * within command buffer array. */
  2249. txcmd_phys = txq->dma_addr_cmd + sizeof(struct iwl3945_cmd) * idx +
  2250. offsetof(struct iwl3945_cmd, hdr);
  2251. /* Add buffer containing Tx command and MAC(!) header to TFD's
  2252. * first entry */
  2253. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
  2254. if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT))
  2255. iwl3945_build_tx_cmd_hwcrypto(priv, info, out_cmd, skb, 0);
  2256. /* Set up TFD's 2nd entry to point directly to remainder of skb,
  2257. * if any (802.11 null frames have no payload). */
  2258. len = skb->len - hdr_len;
  2259. if (len) {
  2260. phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
  2261. len, PCI_DMA_TODEVICE);
  2262. iwl3945_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
  2263. }
  2264. if (!len)
  2265. /* If there is no payload, then we use only one Tx buffer */
  2266. *control_flags = TFD_CTL_COUNT_SET(1);
  2267. else
  2268. /* Else use 2 buffers.
  2269. * Tell 3945 about any padding after MAC header */
  2270. *control_flags = TFD_CTL_COUNT_SET(2) |
  2271. TFD_CTL_PAD_SET(U32_PAD(len));
  2272. /* Total # bytes to be transmitted */
  2273. len = (u16)skb->len;
  2274. out_cmd->cmd.tx.len = cpu_to_le16(len);
  2275. /* TODO need this for burst mode later on */
  2276. iwl3945_build_tx_cmd_basic(priv, out_cmd, info, hdr, unicast, sta_id);
  2277. /* set is_hcca to 0; it probably will never be implemented */
  2278. iwl3945_hw_build_tx_cmd_rate(priv, out_cmd, info, hdr, sta_id, 0);
  2279. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_A_MSK;
  2280. out_cmd->cmd.tx.tx_flags &= ~TX_CMD_FLG_ANT_B_MSK;
  2281. if (!ieee80211_has_morefrags(hdr->frame_control)) {
  2282. txq->need_update = 1;
  2283. if (qc) {
  2284. priv->stations[sta_id].tid[tid].seq_number = seq_number;
  2285. }
  2286. } else {
  2287. wait_write_ptr = 1;
  2288. txq->need_update = 0;
  2289. }
  2290. iwl3945_print_hex_dump(IWL_DL_TX, out_cmd->cmd.payload,
  2291. sizeof(out_cmd->cmd.tx));
  2292. iwl3945_print_hex_dump(IWL_DL_TX, (u8 *)out_cmd->cmd.tx.hdr,
  2293. ieee80211_get_hdrlen(le16_to_cpu(fc)));
  2294. /* Tell device the write index *just past* this latest filled TFD */
  2295. q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
  2296. rc = iwl3945_tx_queue_update_write_ptr(priv, txq);
  2297. spin_unlock_irqrestore(&priv->lock, flags);
  2298. if (rc)
  2299. return rc;
  2300. if ((iwl3945_queue_space(q) < q->high_mark)
  2301. && priv->mac80211_registered) {
  2302. if (wait_write_ptr) {
  2303. spin_lock_irqsave(&priv->lock, flags);
  2304. txq->need_update = 1;
  2305. iwl3945_tx_queue_update_write_ptr(priv, txq);
  2306. spin_unlock_irqrestore(&priv->lock, flags);
  2307. }
  2308. ieee80211_stop_queue(priv->hw, skb_get_queue_mapping(skb));
  2309. }
  2310. return 0;
  2311. drop_unlock:
  2312. spin_unlock_irqrestore(&priv->lock, flags);
  2313. drop:
  2314. return -1;
  2315. }
  2316. static void iwl3945_set_rate(struct iwl3945_priv *priv)
  2317. {
  2318. const struct ieee80211_supported_band *sband = NULL;
  2319. struct ieee80211_rate *rate;
  2320. int i;
  2321. sband = iwl3945_get_band(priv, priv->band);
  2322. if (!sband) {
  2323. IWL_ERROR("Failed to set rate: unable to get hw mode\n");
  2324. return;
  2325. }
  2326. priv->active_rate = 0;
  2327. priv->active_rate_basic = 0;
  2328. IWL_DEBUG_RATE("Setting rates for %s GHz\n",
  2329. sband->band == IEEE80211_BAND_2GHZ ? "2.4" : "5");
  2330. for (i = 0; i < sband->n_bitrates; i++) {
  2331. rate = &sband->bitrates[i];
  2332. if ((rate->hw_value < IWL_RATE_COUNT) &&
  2333. !(rate->flags & IEEE80211_CHAN_DISABLED)) {
  2334. IWL_DEBUG_RATE("Adding rate index %d (plcp %d)\n",
  2335. rate->hw_value, iwl3945_rates[rate->hw_value].plcp);
  2336. priv->active_rate |= (1 << rate->hw_value);
  2337. }
  2338. }
  2339. IWL_DEBUG_RATE("Set active_rate = %0x, active_rate_basic = %0x\n",
  2340. priv->active_rate, priv->active_rate_basic);
  2341. /*
  2342. * If a basic rate is configured, then use it (adding IWL_RATE_1M_MASK)
  2343. * otherwise set it to the default of all CCK rates and 6, 12, 24 for
  2344. * OFDM
  2345. */
  2346. if (priv->active_rate_basic & IWL_CCK_BASIC_RATES_MASK)
  2347. priv->staging_rxon.cck_basic_rates =
  2348. ((priv->active_rate_basic &
  2349. IWL_CCK_RATES_MASK) >> IWL_FIRST_CCK_RATE) & 0xF;
  2350. else
  2351. priv->staging_rxon.cck_basic_rates =
  2352. (IWL_CCK_BASIC_RATES_MASK >> IWL_FIRST_CCK_RATE) & 0xF;
  2353. if (priv->active_rate_basic & IWL_OFDM_BASIC_RATES_MASK)
  2354. priv->staging_rxon.ofdm_basic_rates =
  2355. ((priv->active_rate_basic &
  2356. (IWL_OFDM_BASIC_RATES_MASK | IWL_RATE_6M_MASK)) >>
  2357. IWL_FIRST_OFDM_RATE) & 0xFF;
  2358. else
  2359. priv->staging_rxon.ofdm_basic_rates =
  2360. (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
  2361. }
  2362. static void iwl3945_radio_kill_sw(struct iwl3945_priv *priv, int disable_radio)
  2363. {
  2364. unsigned long flags;
  2365. if (!!disable_radio == test_bit(STATUS_RF_KILL_SW, &priv->status))
  2366. return;
  2367. IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO %s\n",
  2368. disable_radio ? "OFF" : "ON");
  2369. if (disable_radio) {
  2370. iwl3945_scan_cancel(priv);
  2371. /* FIXME: This is a workaround for AP */
  2372. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  2373. spin_lock_irqsave(&priv->lock, flags);
  2374. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2375. CSR_UCODE_SW_BIT_RFKILL);
  2376. spin_unlock_irqrestore(&priv->lock, flags);
  2377. iwl3945_send_card_state(priv, CARD_STATE_CMD_DISABLE, 0);
  2378. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2379. }
  2380. return;
  2381. }
  2382. spin_lock_irqsave(&priv->lock, flags);
  2383. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2384. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2385. spin_unlock_irqrestore(&priv->lock, flags);
  2386. /* wake up ucode */
  2387. msleep(10);
  2388. spin_lock_irqsave(&priv->lock, flags);
  2389. iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  2390. if (!iwl3945_grab_nic_access(priv))
  2391. iwl3945_release_nic_access(priv);
  2392. spin_unlock_irqrestore(&priv->lock, flags);
  2393. if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
  2394. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  2395. "disabled by HW switch\n");
  2396. return;
  2397. }
  2398. if (priv->is_open)
  2399. queue_work(priv->workqueue, &priv->restart);
  2400. return;
  2401. }
  2402. void iwl3945_set_decrypted_flag(struct iwl3945_priv *priv, struct sk_buff *skb,
  2403. u32 decrypt_res, struct ieee80211_rx_status *stats)
  2404. {
  2405. u16 fc =
  2406. le16_to_cpu(((struct ieee80211_hdr *)skb->data)->frame_control);
  2407. if (priv->active_rxon.filter_flags & RXON_FILTER_DIS_DECRYPT_MSK)
  2408. return;
  2409. if (!(fc & IEEE80211_FCTL_PROTECTED))
  2410. return;
  2411. IWL_DEBUG_RX("decrypt_res:0x%x\n", decrypt_res);
  2412. switch (decrypt_res & RX_RES_STATUS_SEC_TYPE_MSK) {
  2413. case RX_RES_STATUS_SEC_TYPE_TKIP:
  2414. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2415. RX_RES_STATUS_BAD_ICV_MIC)
  2416. stats->flag |= RX_FLAG_MMIC_ERROR;
  2417. case RX_RES_STATUS_SEC_TYPE_WEP:
  2418. case RX_RES_STATUS_SEC_TYPE_CCMP:
  2419. if ((decrypt_res & RX_RES_STATUS_DECRYPT_TYPE_MSK) ==
  2420. RX_RES_STATUS_DECRYPT_OK) {
  2421. IWL_DEBUG_RX("hw decrypt successfully!!!\n");
  2422. stats->flag |= RX_FLAG_DECRYPTED;
  2423. }
  2424. break;
  2425. default:
  2426. break;
  2427. }
  2428. }
  2429. #define IWL_PACKET_RETRY_TIME HZ
  2430. int iwl3945_is_duplicate_packet(struct iwl3945_priv *priv, struct ieee80211_hdr *header)
  2431. {
  2432. u16 sc = le16_to_cpu(header->seq_ctrl);
  2433. u16 seq = (sc & IEEE80211_SCTL_SEQ) >> 4;
  2434. u16 frag = sc & IEEE80211_SCTL_FRAG;
  2435. u16 *last_seq, *last_frag;
  2436. unsigned long *last_time;
  2437. switch (priv->iw_mode) {
  2438. case IEEE80211_IF_TYPE_IBSS:{
  2439. struct list_head *p;
  2440. struct iwl3945_ibss_seq *entry = NULL;
  2441. u8 *mac = header->addr2;
  2442. int index = mac[5] & (IWL_IBSS_MAC_HASH_SIZE - 1);
  2443. __list_for_each(p, &priv->ibss_mac_hash[index]) {
  2444. entry = list_entry(p, struct iwl3945_ibss_seq, list);
  2445. if (!compare_ether_addr(entry->mac, mac))
  2446. break;
  2447. }
  2448. if (p == &priv->ibss_mac_hash[index]) {
  2449. entry = kzalloc(sizeof(*entry), GFP_ATOMIC);
  2450. if (!entry) {
  2451. IWL_ERROR("Cannot malloc new mac entry\n");
  2452. return 0;
  2453. }
  2454. memcpy(entry->mac, mac, ETH_ALEN);
  2455. entry->seq_num = seq;
  2456. entry->frag_num = frag;
  2457. entry->packet_time = jiffies;
  2458. list_add(&entry->list, &priv->ibss_mac_hash[index]);
  2459. return 0;
  2460. }
  2461. last_seq = &entry->seq_num;
  2462. last_frag = &entry->frag_num;
  2463. last_time = &entry->packet_time;
  2464. break;
  2465. }
  2466. case IEEE80211_IF_TYPE_STA:
  2467. last_seq = &priv->last_seq_num;
  2468. last_frag = &priv->last_frag_num;
  2469. last_time = &priv->last_packet_time;
  2470. break;
  2471. default:
  2472. return 0;
  2473. }
  2474. if ((*last_seq == seq) &&
  2475. time_after(*last_time + IWL_PACKET_RETRY_TIME, jiffies)) {
  2476. if (*last_frag == frag)
  2477. goto drop;
  2478. if (*last_frag + 1 != frag)
  2479. /* out-of-order fragment */
  2480. goto drop;
  2481. } else
  2482. *last_seq = seq;
  2483. *last_frag = frag;
  2484. *last_time = jiffies;
  2485. return 0;
  2486. drop:
  2487. return 1;
  2488. }
  2489. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2490. #include "iwl-spectrum.h"
  2491. #define BEACON_TIME_MASK_LOW 0x00FFFFFF
  2492. #define BEACON_TIME_MASK_HIGH 0xFF000000
  2493. #define TIME_UNIT 1024
  2494. /*
  2495. * extended beacon time format
  2496. * time in usec will be changed into a 32-bit value in 8:24 format
  2497. * the high 1 byte is the beacon counts
  2498. * the lower 3 bytes is the time in usec within one beacon interval
  2499. */
  2500. static u32 iwl3945_usecs_to_beacons(u32 usec, u32 beacon_interval)
  2501. {
  2502. u32 quot;
  2503. u32 rem;
  2504. u32 interval = beacon_interval * 1024;
  2505. if (!interval || !usec)
  2506. return 0;
  2507. quot = (usec / interval) & (BEACON_TIME_MASK_HIGH >> 24);
  2508. rem = (usec % interval) & BEACON_TIME_MASK_LOW;
  2509. return (quot << 24) + rem;
  2510. }
  2511. /* base is usually what we get from ucode with each received frame,
  2512. * the same as HW timer counter counting down
  2513. */
  2514. static __le32 iwl3945_add_beacon_time(u32 base, u32 addon, u32 beacon_interval)
  2515. {
  2516. u32 base_low = base & BEACON_TIME_MASK_LOW;
  2517. u32 addon_low = addon & BEACON_TIME_MASK_LOW;
  2518. u32 interval = beacon_interval * TIME_UNIT;
  2519. u32 res = (base & BEACON_TIME_MASK_HIGH) +
  2520. (addon & BEACON_TIME_MASK_HIGH);
  2521. if (base_low > addon_low)
  2522. res += base_low - addon_low;
  2523. else if (base_low < addon_low) {
  2524. res += interval + base_low - addon_low;
  2525. res += (1 << 24);
  2526. } else
  2527. res += (1 << 24);
  2528. return cpu_to_le32(res);
  2529. }
  2530. static int iwl3945_get_measurement(struct iwl3945_priv *priv,
  2531. struct ieee80211_measurement_params *params,
  2532. u8 type)
  2533. {
  2534. struct iwl3945_spectrum_cmd spectrum;
  2535. struct iwl3945_rx_packet *res;
  2536. struct iwl3945_host_cmd cmd = {
  2537. .id = REPLY_SPECTRUM_MEASUREMENT_CMD,
  2538. .data = (void *)&spectrum,
  2539. .meta.flags = CMD_WANT_SKB,
  2540. };
  2541. u32 add_time = le64_to_cpu(params->start_time);
  2542. int rc;
  2543. int spectrum_resp_status;
  2544. int duration = le16_to_cpu(params->duration);
  2545. if (iwl3945_is_associated(priv))
  2546. add_time =
  2547. iwl3945_usecs_to_beacons(
  2548. le64_to_cpu(params->start_time) - priv->last_tsf,
  2549. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2550. memset(&spectrum, 0, sizeof(spectrum));
  2551. spectrum.channel_count = cpu_to_le16(1);
  2552. spectrum.flags =
  2553. RXON_FLG_TSF2HOST_MSK | RXON_FLG_ANT_A_MSK | RXON_FLG_DIS_DIV_MSK;
  2554. spectrum.filter_flags = MEASUREMENT_FILTER_FLAG;
  2555. cmd.len = sizeof(spectrum);
  2556. spectrum.len = cpu_to_le16(cmd.len - sizeof(spectrum.len));
  2557. if (iwl3945_is_associated(priv))
  2558. spectrum.start_time =
  2559. iwl3945_add_beacon_time(priv->last_beacon_time,
  2560. add_time,
  2561. le16_to_cpu(priv->rxon_timing.beacon_interval));
  2562. else
  2563. spectrum.start_time = 0;
  2564. spectrum.channels[0].duration = cpu_to_le32(duration * TIME_UNIT);
  2565. spectrum.channels[0].channel = params->channel;
  2566. spectrum.channels[0].type = type;
  2567. if (priv->active_rxon.flags & RXON_FLG_BAND_24G_MSK)
  2568. spectrum.flags |= RXON_FLG_BAND_24G_MSK |
  2569. RXON_FLG_AUTO_DETECT_MSK | RXON_FLG_TGG_PROTECT_MSK;
  2570. rc = iwl3945_send_cmd_sync(priv, &cmd);
  2571. if (rc)
  2572. return rc;
  2573. res = (struct iwl3945_rx_packet *)cmd.meta.u.skb->data;
  2574. if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
  2575. IWL_ERROR("Bad return from REPLY_RX_ON_ASSOC command\n");
  2576. rc = -EIO;
  2577. }
  2578. spectrum_resp_status = le16_to_cpu(res->u.spectrum.status);
  2579. switch (spectrum_resp_status) {
  2580. case 0: /* Command will be handled */
  2581. if (res->u.spectrum.id != 0xff) {
  2582. IWL_DEBUG_INFO("Replaced existing measurement: %d\n",
  2583. res->u.spectrum.id);
  2584. priv->measurement_status &= ~MEASUREMENT_READY;
  2585. }
  2586. priv->measurement_status |= MEASUREMENT_ACTIVE;
  2587. rc = 0;
  2588. break;
  2589. case 1: /* Command will not be handled */
  2590. rc = -EAGAIN;
  2591. break;
  2592. }
  2593. dev_kfree_skb_any(cmd.meta.u.skb);
  2594. return rc;
  2595. }
  2596. #endif
  2597. static void iwl3945_rx_reply_alive(struct iwl3945_priv *priv,
  2598. struct iwl3945_rx_mem_buffer *rxb)
  2599. {
  2600. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2601. struct iwl3945_alive_resp *palive;
  2602. struct delayed_work *pwork;
  2603. palive = &pkt->u.alive_frame;
  2604. IWL_DEBUG_INFO("Alive ucode status 0x%08X revision "
  2605. "0x%01X 0x%01X\n",
  2606. palive->is_valid, palive->ver_type,
  2607. palive->ver_subtype);
  2608. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  2609. IWL_DEBUG_INFO("Initialization Alive received.\n");
  2610. memcpy(&priv->card_alive_init,
  2611. &pkt->u.alive_frame,
  2612. sizeof(struct iwl3945_init_alive_resp));
  2613. pwork = &priv->init_alive_start;
  2614. } else {
  2615. IWL_DEBUG_INFO("Runtime Alive received.\n");
  2616. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  2617. sizeof(struct iwl3945_alive_resp));
  2618. pwork = &priv->alive_start;
  2619. iwl3945_disable_events(priv);
  2620. }
  2621. /* We delay the ALIVE response by 5ms to
  2622. * give the HW RF Kill time to activate... */
  2623. if (palive->is_valid == UCODE_VALID_OK)
  2624. queue_delayed_work(priv->workqueue, pwork,
  2625. msecs_to_jiffies(5));
  2626. else
  2627. IWL_WARNING("uCode did not respond OK.\n");
  2628. }
  2629. static void iwl3945_rx_reply_add_sta(struct iwl3945_priv *priv,
  2630. struct iwl3945_rx_mem_buffer *rxb)
  2631. {
  2632. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2633. IWL_DEBUG_RX("Received REPLY_ADD_STA: 0x%02X\n", pkt->u.status);
  2634. return;
  2635. }
  2636. static void iwl3945_rx_reply_error(struct iwl3945_priv *priv,
  2637. struct iwl3945_rx_mem_buffer *rxb)
  2638. {
  2639. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2640. IWL_ERROR("Error Reply type 0x%08X cmd %s (0x%02X) "
  2641. "seq 0x%04X ser 0x%08X\n",
  2642. le32_to_cpu(pkt->u.err_resp.error_type),
  2643. get_cmd_string(pkt->u.err_resp.cmd_id),
  2644. pkt->u.err_resp.cmd_id,
  2645. le16_to_cpu(pkt->u.err_resp.bad_cmd_seq_num),
  2646. le32_to_cpu(pkt->u.err_resp.error_info));
  2647. }
  2648. #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
  2649. static void iwl3945_rx_csa(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
  2650. {
  2651. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2652. struct iwl3945_rxon_cmd *rxon = (void *)&priv->active_rxon;
  2653. struct iwl3945_csa_notification *csa = &(pkt->u.csa_notif);
  2654. IWL_DEBUG_11H("CSA notif: channel %d, status %d\n",
  2655. le16_to_cpu(csa->channel), le32_to_cpu(csa->status));
  2656. rxon->channel = csa->channel;
  2657. priv->staging_rxon.channel = csa->channel;
  2658. }
  2659. static void iwl3945_rx_spectrum_measure_notif(struct iwl3945_priv *priv,
  2660. struct iwl3945_rx_mem_buffer *rxb)
  2661. {
  2662. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  2663. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2664. struct iwl3945_spectrum_notification *report = &(pkt->u.spectrum_notif);
  2665. if (!report->state) {
  2666. IWL_DEBUG(IWL_DL_11H | IWL_DL_INFO,
  2667. "Spectrum Measure Notification: Start\n");
  2668. return;
  2669. }
  2670. memcpy(&priv->measure_report, report, sizeof(*report));
  2671. priv->measurement_status |= MEASUREMENT_READY;
  2672. #endif
  2673. }
  2674. static void iwl3945_rx_pm_sleep_notif(struct iwl3945_priv *priv,
  2675. struct iwl3945_rx_mem_buffer *rxb)
  2676. {
  2677. #ifdef CONFIG_IWL3945_DEBUG
  2678. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2679. struct iwl3945_sleep_notification *sleep = &(pkt->u.sleep_notif);
  2680. IWL_DEBUG_RX("sleep mode: %d, src: %d\n",
  2681. sleep->pm_sleep_mode, sleep->pm_wakeup_src);
  2682. #endif
  2683. }
  2684. static void iwl3945_rx_pm_debug_statistics_notif(struct iwl3945_priv *priv,
  2685. struct iwl3945_rx_mem_buffer *rxb)
  2686. {
  2687. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2688. IWL_DEBUG_RADIO("Dumping %d bytes of unhandled "
  2689. "notification for %s:\n",
  2690. le32_to_cpu(pkt->len), get_cmd_string(pkt->hdr.cmd));
  2691. iwl3945_print_hex_dump(IWL_DL_RADIO, pkt->u.raw, le32_to_cpu(pkt->len));
  2692. }
  2693. static void iwl3945_bg_beacon_update(struct work_struct *work)
  2694. {
  2695. struct iwl3945_priv *priv =
  2696. container_of(work, struct iwl3945_priv, beacon_update);
  2697. struct sk_buff *beacon;
  2698. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  2699. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  2700. if (!beacon) {
  2701. IWL_ERROR("update beacon failed\n");
  2702. return;
  2703. }
  2704. mutex_lock(&priv->mutex);
  2705. /* new beacon skb is allocated every time; dispose previous.*/
  2706. if (priv->ibss_beacon)
  2707. dev_kfree_skb(priv->ibss_beacon);
  2708. priv->ibss_beacon = beacon;
  2709. mutex_unlock(&priv->mutex);
  2710. iwl3945_send_beacon_cmd(priv);
  2711. }
  2712. static void iwl3945_rx_beacon_notif(struct iwl3945_priv *priv,
  2713. struct iwl3945_rx_mem_buffer *rxb)
  2714. {
  2715. #ifdef CONFIG_IWL3945_DEBUG
  2716. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2717. struct iwl3945_beacon_notif *beacon = &(pkt->u.beacon_status);
  2718. u8 rate = beacon->beacon_notify_hdr.rate;
  2719. IWL_DEBUG_RX("beacon status %x retries %d iss %d "
  2720. "tsf %d %d rate %d\n",
  2721. le32_to_cpu(beacon->beacon_notify_hdr.status) & TX_STATUS_MSK,
  2722. beacon->beacon_notify_hdr.failure_frame,
  2723. le32_to_cpu(beacon->ibss_mgr_status),
  2724. le32_to_cpu(beacon->high_tsf),
  2725. le32_to_cpu(beacon->low_tsf), rate);
  2726. #endif
  2727. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  2728. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  2729. queue_work(priv->workqueue, &priv->beacon_update);
  2730. }
  2731. /* Service response to REPLY_SCAN_CMD (0x80) */
  2732. static void iwl3945_rx_reply_scan(struct iwl3945_priv *priv,
  2733. struct iwl3945_rx_mem_buffer *rxb)
  2734. {
  2735. #ifdef CONFIG_IWL3945_DEBUG
  2736. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2737. struct iwl3945_scanreq_notification *notif =
  2738. (struct iwl3945_scanreq_notification *)pkt->u.raw;
  2739. IWL_DEBUG_RX("Scan request status = 0x%x\n", notif->status);
  2740. #endif
  2741. }
  2742. /* Service SCAN_START_NOTIFICATION (0x82) */
  2743. static void iwl3945_rx_scan_start_notif(struct iwl3945_priv *priv,
  2744. struct iwl3945_rx_mem_buffer *rxb)
  2745. {
  2746. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2747. struct iwl3945_scanstart_notification *notif =
  2748. (struct iwl3945_scanstart_notification *)pkt->u.raw;
  2749. priv->scan_start_tsf = le32_to_cpu(notif->tsf_low);
  2750. IWL_DEBUG_SCAN("Scan start: "
  2751. "%d [802.11%s] "
  2752. "(TSF: 0x%08X:%08X) - %d (beacon timer %u)\n",
  2753. notif->channel,
  2754. notif->band ? "bg" : "a",
  2755. notif->tsf_high,
  2756. notif->tsf_low, notif->status, notif->beacon_timer);
  2757. }
  2758. /* Service SCAN_RESULTS_NOTIFICATION (0x83) */
  2759. static void iwl3945_rx_scan_results_notif(struct iwl3945_priv *priv,
  2760. struct iwl3945_rx_mem_buffer *rxb)
  2761. {
  2762. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2763. struct iwl3945_scanresults_notification *notif =
  2764. (struct iwl3945_scanresults_notification *)pkt->u.raw;
  2765. IWL_DEBUG_SCAN("Scan ch.res: "
  2766. "%d [802.11%s] "
  2767. "(TSF: 0x%08X:%08X) - %d "
  2768. "elapsed=%lu usec (%dms since last)\n",
  2769. notif->channel,
  2770. notif->band ? "bg" : "a",
  2771. le32_to_cpu(notif->tsf_high),
  2772. le32_to_cpu(notif->tsf_low),
  2773. le32_to_cpu(notif->statistics[0]),
  2774. le32_to_cpu(notif->tsf_low) - priv->scan_start_tsf,
  2775. jiffies_to_msecs(elapsed_jiffies
  2776. (priv->last_scan_jiffies, jiffies)));
  2777. priv->last_scan_jiffies = jiffies;
  2778. priv->next_scan_jiffies = 0;
  2779. }
  2780. /* Service SCAN_COMPLETE_NOTIFICATION (0x84) */
  2781. static void iwl3945_rx_scan_complete_notif(struct iwl3945_priv *priv,
  2782. struct iwl3945_rx_mem_buffer *rxb)
  2783. {
  2784. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2785. struct iwl3945_scancomplete_notification *scan_notif = (void *)pkt->u.raw;
  2786. IWL_DEBUG_SCAN("Scan complete: %d channels (TSF 0x%08X:%08X) - %d\n",
  2787. scan_notif->scanned_channels,
  2788. scan_notif->tsf_low,
  2789. scan_notif->tsf_high, scan_notif->status);
  2790. /* The HW is no longer scanning */
  2791. clear_bit(STATUS_SCAN_HW, &priv->status);
  2792. /* The scan completion notification came in, so kill that timer... */
  2793. cancel_delayed_work(&priv->scan_check);
  2794. IWL_DEBUG_INFO("Scan pass on %sGHz took %dms\n",
  2795. (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) ?
  2796. "2.4" : "5.2",
  2797. jiffies_to_msecs(elapsed_jiffies
  2798. (priv->scan_pass_start, jiffies)));
  2799. /* Remove this scanned band from the list of pending
  2800. * bands to scan, band G precedes A in order of scanning
  2801. * as seen in iwl3945_bg_request_scan */
  2802. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ))
  2803. priv->scan_bands &= ~BIT(IEEE80211_BAND_2GHZ);
  2804. else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ))
  2805. priv->scan_bands &= ~BIT(IEEE80211_BAND_5GHZ);
  2806. /* If a request to abort was given, or the scan did not succeed
  2807. * then we reset the scan state machine and terminate,
  2808. * re-queuing another scan if one has been requested */
  2809. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  2810. IWL_DEBUG_INFO("Aborted scan completed.\n");
  2811. clear_bit(STATUS_SCAN_ABORTING, &priv->status);
  2812. } else {
  2813. /* If there are more bands on this scan pass reschedule */
  2814. if (priv->scan_bands > 0)
  2815. goto reschedule;
  2816. }
  2817. priv->last_scan_jiffies = jiffies;
  2818. priv->next_scan_jiffies = 0;
  2819. IWL_DEBUG_INFO("Setting scan to off\n");
  2820. clear_bit(STATUS_SCANNING, &priv->status);
  2821. IWL_DEBUG_INFO("Scan took %dms\n",
  2822. jiffies_to_msecs(elapsed_jiffies(priv->scan_start, jiffies)));
  2823. queue_work(priv->workqueue, &priv->scan_completed);
  2824. return;
  2825. reschedule:
  2826. priv->scan_pass_start = jiffies;
  2827. queue_work(priv->workqueue, &priv->request_scan);
  2828. }
  2829. /* Handle notification from uCode that card's power state is changing
  2830. * due to software, hardware, or critical temperature RFKILL */
  2831. static void iwl3945_rx_card_state_notif(struct iwl3945_priv *priv,
  2832. struct iwl3945_rx_mem_buffer *rxb)
  2833. {
  2834. struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
  2835. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  2836. unsigned long status = priv->status;
  2837. IWL_DEBUG_RF_KILL("Card state received: HW:%s SW:%s\n",
  2838. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  2839. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  2840. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_SET,
  2841. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2842. if (flags & HW_CARD_DISABLED)
  2843. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2844. else
  2845. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2846. if (flags & SW_CARD_DISABLED)
  2847. set_bit(STATUS_RF_KILL_SW, &priv->status);
  2848. else
  2849. clear_bit(STATUS_RF_KILL_SW, &priv->status);
  2850. iwl3945_scan_cancel(priv);
  2851. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  2852. test_bit(STATUS_RF_KILL_HW, &priv->status)) ||
  2853. (test_bit(STATUS_RF_KILL_SW, &status) !=
  2854. test_bit(STATUS_RF_KILL_SW, &priv->status)))
  2855. queue_work(priv->workqueue, &priv->rf_kill);
  2856. else
  2857. wake_up_interruptible(&priv->wait_command_queue);
  2858. }
  2859. /**
  2860. * iwl3945_setup_rx_handlers - Initialize Rx handler callbacks
  2861. *
  2862. * Setup the RX handlers for each of the reply types sent from the uCode
  2863. * to the host.
  2864. *
  2865. * This function chains into the hardware specific files for them to setup
  2866. * any hardware specific handlers as well.
  2867. */
  2868. static void iwl3945_setup_rx_handlers(struct iwl3945_priv *priv)
  2869. {
  2870. priv->rx_handlers[REPLY_ALIVE] = iwl3945_rx_reply_alive;
  2871. priv->rx_handlers[REPLY_ADD_STA] = iwl3945_rx_reply_add_sta;
  2872. priv->rx_handlers[REPLY_ERROR] = iwl3945_rx_reply_error;
  2873. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl3945_rx_csa;
  2874. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  2875. iwl3945_rx_spectrum_measure_notif;
  2876. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl3945_rx_pm_sleep_notif;
  2877. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  2878. iwl3945_rx_pm_debug_statistics_notif;
  2879. priv->rx_handlers[BEACON_NOTIFICATION] = iwl3945_rx_beacon_notif;
  2880. /*
  2881. * The same handler is used for both the REPLY to a discrete
  2882. * statistics request from the host as well as for the periodic
  2883. * statistics notifications (after received beacons) from the uCode.
  2884. */
  2885. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl3945_hw_rx_statistics;
  2886. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl3945_hw_rx_statistics;
  2887. priv->rx_handlers[REPLY_SCAN_CMD] = iwl3945_rx_reply_scan;
  2888. priv->rx_handlers[SCAN_START_NOTIFICATION] = iwl3945_rx_scan_start_notif;
  2889. priv->rx_handlers[SCAN_RESULTS_NOTIFICATION] =
  2890. iwl3945_rx_scan_results_notif;
  2891. priv->rx_handlers[SCAN_COMPLETE_NOTIFICATION] =
  2892. iwl3945_rx_scan_complete_notif;
  2893. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl3945_rx_card_state_notif;
  2894. /* Set up hardware specific Rx handlers */
  2895. iwl3945_hw_rx_handler_setup(priv);
  2896. }
  2897. /**
  2898. * iwl3945_cmd_queue_reclaim - Reclaim CMD queue entries
  2899. * When FW advances 'R' index, all entries between old and new 'R' index
  2900. * need to be reclaimed.
  2901. */
  2902. static void iwl3945_cmd_queue_reclaim(struct iwl3945_priv *priv,
  2903. int txq_id, int index)
  2904. {
  2905. struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
  2906. struct iwl3945_queue *q = &txq->q;
  2907. int nfreed = 0;
  2908. if ((index >= q->n_bd) || (iwl3945_x2_queue_used(q, index) == 0)) {
  2909. IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
  2910. "is out of range [0-%d] %d %d.\n", txq_id,
  2911. index, q->n_bd, q->write_ptr, q->read_ptr);
  2912. return;
  2913. }
  2914. for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
  2915. q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  2916. if (nfreed > 1) {
  2917. IWL_ERROR("HCMD skipped: index (%d) %d %d\n", index,
  2918. q->write_ptr, q->read_ptr);
  2919. queue_work(priv->workqueue, &priv->restart);
  2920. break;
  2921. }
  2922. nfreed++;
  2923. }
  2924. }
  2925. /**
  2926. * iwl3945_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  2927. * @rxb: Rx buffer to reclaim
  2928. *
  2929. * If an Rx buffer has an async callback associated with it the callback
  2930. * will be executed. The attached skb (if present) will only be freed
  2931. * if the callback returns 1
  2932. */
  2933. static void iwl3945_tx_cmd_complete(struct iwl3945_priv *priv,
  2934. struct iwl3945_rx_mem_buffer *rxb)
  2935. {
  2936. struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  2937. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  2938. int txq_id = SEQ_TO_QUEUE(sequence);
  2939. int index = SEQ_TO_INDEX(sequence);
  2940. int huge = sequence & SEQ_HUGE_FRAME;
  2941. int cmd_index;
  2942. struct iwl3945_cmd *cmd;
  2943. BUG_ON(txq_id != IWL_CMD_QUEUE_NUM);
  2944. cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
  2945. cmd = &priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
  2946. /* Input error checking is done when commands are added to queue. */
  2947. if (cmd->meta.flags & CMD_WANT_SKB) {
  2948. cmd->meta.source->u.skb = rxb->skb;
  2949. rxb->skb = NULL;
  2950. } else if (cmd->meta.u.callback &&
  2951. !cmd->meta.u.callback(priv, cmd, rxb->skb))
  2952. rxb->skb = NULL;
  2953. iwl3945_cmd_queue_reclaim(priv, txq_id, index);
  2954. if (!(cmd->meta.flags & CMD_ASYNC)) {
  2955. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  2956. wake_up_interruptible(&priv->wait_command_queue);
  2957. }
  2958. }
  2959. /************************** RX-FUNCTIONS ****************************/
  2960. /*
  2961. * Rx theory of operation
  2962. *
  2963. * The host allocates 32 DMA target addresses and passes the host address
  2964. * to the firmware at register IWL_RFDS_TABLE_LOWER + N * RFD_SIZE where N is
  2965. * 0 to 31
  2966. *
  2967. * Rx Queue Indexes
  2968. * The host/firmware share two index registers for managing the Rx buffers.
  2969. *
  2970. * The READ index maps to the first position that the firmware may be writing
  2971. * to -- the driver can read up to (but not including) this position and get
  2972. * good data.
  2973. * The READ index is managed by the firmware once the card is enabled.
  2974. *
  2975. * The WRITE index maps to the last position the driver has read from -- the
  2976. * position preceding WRITE is the last slot the firmware can place a packet.
  2977. *
  2978. * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  2979. * WRITE = READ.
  2980. *
  2981. * During initialization, the host sets up the READ queue position to the first
  2982. * INDEX position, and WRITE to the last (READ - 1 wrapped)
  2983. *
  2984. * When the firmware places a packet in a buffer, it will advance the READ index
  2985. * and fire the RX interrupt. The driver can then query the READ index and
  2986. * process as many packets as possible, moving the WRITE index forward as it
  2987. * resets the Rx queue buffers with new memory.
  2988. *
  2989. * The management in the driver is as follows:
  2990. * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
  2991. * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  2992. * to replenish the iwl->rxq->rx_free.
  2993. * + In iwl3945_rx_replenish (scheduled) if 'processed' != 'read' then the
  2994. * iwl->rxq is replenished and the READ INDEX is updated (updating the
  2995. * 'processed' and 'read' driver indexes as well)
  2996. * + A received packet is processed and handed to the kernel network stack,
  2997. * detached from the iwl->rxq. The driver 'processed' index is updated.
  2998. * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  2999. * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  3000. * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
  3001. * were enough free buffers and RX_STALLED is set it is cleared.
  3002. *
  3003. *
  3004. * Driver sequence:
  3005. *
  3006. * iwl3945_rx_queue_alloc() Allocates rx_free
  3007. * iwl3945_rx_replenish() Replenishes rx_free list from rx_used, and calls
  3008. * iwl3945_rx_queue_restock
  3009. * iwl3945_rx_queue_restock() Moves available buffers from rx_free into Rx
  3010. * queue, updates firmware pointers, and updates
  3011. * the WRITE index. If insufficient rx_free buffers
  3012. * are available, schedules iwl3945_rx_replenish
  3013. *
  3014. * -- enable interrupts --
  3015. * ISR - iwl3945_rx() Detach iwl3945_rx_mem_buffers from pool up to the
  3016. * READ INDEX, detaching the SKB from the pool.
  3017. * Moves the packet buffer from queue to rx_used.
  3018. * Calls iwl3945_rx_queue_restock to refill any empty
  3019. * slots.
  3020. * ...
  3021. *
  3022. */
  3023. /**
  3024. * iwl3945_rx_queue_space - Return number of free slots available in queue.
  3025. */
  3026. static int iwl3945_rx_queue_space(const struct iwl3945_rx_queue *q)
  3027. {
  3028. int s = q->read - q->write;
  3029. if (s <= 0)
  3030. s += RX_QUEUE_SIZE;
  3031. /* keep some buffer to not confuse full and empty queue */
  3032. s -= 2;
  3033. if (s < 0)
  3034. s = 0;
  3035. return s;
  3036. }
  3037. /**
  3038. * iwl3945_rx_queue_update_write_ptr - Update the write pointer for the RX queue
  3039. */
  3040. int iwl3945_rx_queue_update_write_ptr(struct iwl3945_priv *priv, struct iwl3945_rx_queue *q)
  3041. {
  3042. u32 reg = 0;
  3043. int rc = 0;
  3044. unsigned long flags;
  3045. spin_lock_irqsave(&q->lock, flags);
  3046. if (q->need_update == 0)
  3047. goto exit_unlock;
  3048. /* If power-saving is in use, make sure device is awake */
  3049. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3050. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3051. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3052. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3053. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3054. goto exit_unlock;
  3055. }
  3056. rc = iwl3945_grab_nic_access(priv);
  3057. if (rc)
  3058. goto exit_unlock;
  3059. /* Device expects a multiple of 8 */
  3060. iwl3945_write_direct32(priv, FH_RSCSR_CHNL0_WPTR,
  3061. q->write & ~0x7);
  3062. iwl3945_release_nic_access(priv);
  3063. /* Else device is assumed to be awake */
  3064. } else
  3065. /* Device expects a multiple of 8 */
  3066. iwl3945_write32(priv, FH_RSCSR_CHNL0_WPTR, q->write & ~0x7);
  3067. q->need_update = 0;
  3068. exit_unlock:
  3069. spin_unlock_irqrestore(&q->lock, flags);
  3070. return rc;
  3071. }
  3072. /**
  3073. * iwl3945_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  3074. */
  3075. static inline __le32 iwl3945_dma_addr2rbd_ptr(struct iwl3945_priv *priv,
  3076. dma_addr_t dma_addr)
  3077. {
  3078. return cpu_to_le32((u32)dma_addr);
  3079. }
  3080. /**
  3081. * iwl3945_rx_queue_restock - refill RX queue from pre-allocated pool
  3082. *
  3083. * If there are slots in the RX queue that need to be restocked,
  3084. * and we have free pre-allocated buffers, fill the ranks as much
  3085. * as we can, pulling from rx_free.
  3086. *
  3087. * This moves the 'write' index forward to catch up with 'processed', and
  3088. * also updates the memory address in the firmware to reference the new
  3089. * target buffer.
  3090. */
  3091. static int iwl3945_rx_queue_restock(struct iwl3945_priv *priv)
  3092. {
  3093. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3094. struct list_head *element;
  3095. struct iwl3945_rx_mem_buffer *rxb;
  3096. unsigned long flags;
  3097. int write, rc;
  3098. spin_lock_irqsave(&rxq->lock, flags);
  3099. write = rxq->write & ~0x7;
  3100. while ((iwl3945_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  3101. /* Get next free Rx buffer, remove from free list */
  3102. element = rxq->rx_free.next;
  3103. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3104. list_del(element);
  3105. /* Point to Rx buffer via next RBD in circular buffer */
  3106. rxq->bd[rxq->write] = iwl3945_dma_addr2rbd_ptr(priv, rxb->dma_addr);
  3107. rxq->queue[rxq->write] = rxb;
  3108. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  3109. rxq->free_count--;
  3110. }
  3111. spin_unlock_irqrestore(&rxq->lock, flags);
  3112. /* If the pre-allocated buffer pool is dropping low, schedule to
  3113. * refill it */
  3114. if (rxq->free_count <= RX_LOW_WATERMARK)
  3115. queue_work(priv->workqueue, &priv->rx_replenish);
  3116. /* If we've added more space for the firmware to place data, tell it.
  3117. * Increment device's write pointer in multiples of 8. */
  3118. if ((write != (rxq->write & ~0x7))
  3119. || (abs(rxq->write - rxq->read) > 7)) {
  3120. spin_lock_irqsave(&rxq->lock, flags);
  3121. rxq->need_update = 1;
  3122. spin_unlock_irqrestore(&rxq->lock, flags);
  3123. rc = iwl3945_rx_queue_update_write_ptr(priv, rxq);
  3124. if (rc)
  3125. return rc;
  3126. }
  3127. return 0;
  3128. }
  3129. /**
  3130. * iwl3945_rx_replenish - Move all used packet from rx_used to rx_free
  3131. *
  3132. * When moving to rx_free an SKB is allocated for the slot.
  3133. *
  3134. * Also restock the Rx queue via iwl3945_rx_queue_restock.
  3135. * This is called as a scheduled work item (except for during initialization)
  3136. */
  3137. static void iwl3945_rx_allocate(struct iwl3945_priv *priv)
  3138. {
  3139. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3140. struct list_head *element;
  3141. struct iwl3945_rx_mem_buffer *rxb;
  3142. unsigned long flags;
  3143. spin_lock_irqsave(&rxq->lock, flags);
  3144. while (!list_empty(&rxq->rx_used)) {
  3145. element = rxq->rx_used.next;
  3146. rxb = list_entry(element, struct iwl3945_rx_mem_buffer, list);
  3147. /* Alloc a new receive buffer */
  3148. rxb->skb =
  3149. alloc_skb(IWL_RX_BUF_SIZE, __GFP_NOWARN | GFP_ATOMIC);
  3150. if (!rxb->skb) {
  3151. if (net_ratelimit())
  3152. printk(KERN_CRIT DRV_NAME
  3153. ": Can not allocate SKB buffers\n");
  3154. /* We don't reschedule replenish work here -- we will
  3155. * call the restock method and if it still needs
  3156. * more buffers it will schedule replenish */
  3157. break;
  3158. }
  3159. /* If radiotap head is required, reserve some headroom here.
  3160. * The physical head count is a variable rx_stats->phy_count.
  3161. * We reserve 4 bytes here. Plus these extra bytes, the
  3162. * headroom of the physical head should be enough for the
  3163. * radiotap head that iwl3945 supported. See iwl3945_rt.
  3164. */
  3165. skb_reserve(rxb->skb, 4);
  3166. priv->alloc_rxb_skb++;
  3167. list_del(element);
  3168. /* Get physical address of RB/SKB */
  3169. rxb->dma_addr =
  3170. pci_map_single(priv->pci_dev, rxb->skb->data,
  3171. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3172. list_add_tail(&rxb->list, &rxq->rx_free);
  3173. rxq->free_count++;
  3174. }
  3175. spin_unlock_irqrestore(&rxq->lock, flags);
  3176. }
  3177. /*
  3178. * this should be called while priv->lock is locked
  3179. */
  3180. static void __iwl3945_rx_replenish(void *data)
  3181. {
  3182. struct iwl3945_priv *priv = data;
  3183. iwl3945_rx_allocate(priv);
  3184. iwl3945_rx_queue_restock(priv);
  3185. }
  3186. void iwl3945_rx_replenish(void *data)
  3187. {
  3188. struct iwl3945_priv *priv = data;
  3189. unsigned long flags;
  3190. iwl3945_rx_allocate(priv);
  3191. spin_lock_irqsave(&priv->lock, flags);
  3192. iwl3945_rx_queue_restock(priv);
  3193. spin_unlock_irqrestore(&priv->lock, flags);
  3194. }
  3195. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  3196. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  3197. * This free routine walks the list of POOL entries and if SKB is set to
  3198. * non NULL it is unmapped and freed
  3199. */
  3200. static void iwl3945_rx_queue_free(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3201. {
  3202. int i;
  3203. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  3204. if (rxq->pool[i].skb != NULL) {
  3205. pci_unmap_single(priv->pci_dev,
  3206. rxq->pool[i].dma_addr,
  3207. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3208. dev_kfree_skb(rxq->pool[i].skb);
  3209. }
  3210. }
  3211. pci_free_consistent(priv->pci_dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  3212. rxq->dma_addr);
  3213. rxq->bd = NULL;
  3214. }
  3215. int iwl3945_rx_queue_alloc(struct iwl3945_priv *priv)
  3216. {
  3217. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3218. struct pci_dev *dev = priv->pci_dev;
  3219. int i;
  3220. spin_lock_init(&rxq->lock);
  3221. INIT_LIST_HEAD(&rxq->rx_free);
  3222. INIT_LIST_HEAD(&rxq->rx_used);
  3223. /* Alloc the circular buffer of Read Buffer Descriptors (RBDs) */
  3224. rxq->bd = pci_alloc_consistent(dev, 4 * RX_QUEUE_SIZE, &rxq->dma_addr);
  3225. if (!rxq->bd)
  3226. return -ENOMEM;
  3227. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3228. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
  3229. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3230. /* Set us so that we have processed and used all buffers, but have
  3231. * not restocked the Rx queue with fresh buffers */
  3232. rxq->read = rxq->write = 0;
  3233. rxq->free_count = 0;
  3234. rxq->need_update = 0;
  3235. return 0;
  3236. }
  3237. void iwl3945_rx_queue_reset(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
  3238. {
  3239. unsigned long flags;
  3240. int i;
  3241. spin_lock_irqsave(&rxq->lock, flags);
  3242. INIT_LIST_HEAD(&rxq->rx_free);
  3243. INIT_LIST_HEAD(&rxq->rx_used);
  3244. /* Fill the rx_used queue with _all_ of the Rx buffers */
  3245. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  3246. /* In the reset function, these buffers may have been allocated
  3247. * to an SKB, so we need to unmap and free potential storage */
  3248. if (rxq->pool[i].skb != NULL) {
  3249. pci_unmap_single(priv->pci_dev,
  3250. rxq->pool[i].dma_addr,
  3251. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3252. priv->alloc_rxb_skb--;
  3253. dev_kfree_skb(rxq->pool[i].skb);
  3254. rxq->pool[i].skb = NULL;
  3255. }
  3256. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  3257. }
  3258. /* Set us so that we have processed and used all buffers, but have
  3259. * not restocked the Rx queue with fresh buffers */
  3260. rxq->read = rxq->write = 0;
  3261. rxq->free_count = 0;
  3262. spin_unlock_irqrestore(&rxq->lock, flags);
  3263. }
  3264. /* Convert linear signal-to-noise ratio into dB */
  3265. static u8 ratio2dB[100] = {
  3266. /* 0 1 2 3 4 5 6 7 8 9 */
  3267. 0, 0, 6, 10, 12, 14, 16, 17, 18, 19, /* 00 - 09 */
  3268. 20, 21, 22, 22, 23, 23, 24, 25, 26, 26, /* 10 - 19 */
  3269. 26, 26, 26, 27, 27, 28, 28, 28, 29, 29, /* 20 - 29 */
  3270. 29, 30, 30, 30, 31, 31, 31, 31, 32, 32, /* 30 - 39 */
  3271. 32, 32, 32, 33, 33, 33, 33, 33, 34, 34, /* 40 - 49 */
  3272. 34, 34, 34, 34, 35, 35, 35, 35, 35, 35, /* 50 - 59 */
  3273. 36, 36, 36, 36, 36, 36, 36, 37, 37, 37, /* 60 - 69 */
  3274. 37, 37, 37, 37, 37, 38, 38, 38, 38, 38, /* 70 - 79 */
  3275. 38, 38, 38, 38, 38, 39, 39, 39, 39, 39, /* 80 - 89 */
  3276. 39, 39, 39, 39, 39, 40, 40, 40, 40, 40 /* 90 - 99 */
  3277. };
  3278. /* Calculates a relative dB value from a ratio of linear
  3279. * (i.e. not dB) signal levels.
  3280. * Conversion assumes that levels are voltages (20*log), not powers (10*log). */
  3281. int iwl3945_calc_db_from_ratio(int sig_ratio)
  3282. {
  3283. /* 1000:1 or higher just report as 60 dB */
  3284. if (sig_ratio >= 1000)
  3285. return 60;
  3286. /* 100:1 or higher, divide by 10 and use table,
  3287. * add 20 dB to make up for divide by 10 */
  3288. if (sig_ratio >= 100)
  3289. return (20 + (int)ratio2dB[sig_ratio/10]);
  3290. /* We shouldn't see this */
  3291. if (sig_ratio < 1)
  3292. return 0;
  3293. /* Use table for ratios 1:1 - 99:1 */
  3294. return (int)ratio2dB[sig_ratio];
  3295. }
  3296. #define PERFECT_RSSI (-20) /* dBm */
  3297. #define WORST_RSSI (-95) /* dBm */
  3298. #define RSSI_RANGE (PERFECT_RSSI - WORST_RSSI)
  3299. /* Calculate an indication of rx signal quality (a percentage, not dBm!).
  3300. * See http://www.ces.clemson.edu/linux/signal_quality.shtml for info
  3301. * about formulas used below. */
  3302. int iwl3945_calc_sig_qual(int rssi_dbm, int noise_dbm)
  3303. {
  3304. int sig_qual;
  3305. int degradation = PERFECT_RSSI - rssi_dbm;
  3306. /* If we get a noise measurement, use signal-to-noise ratio (SNR)
  3307. * as indicator; formula is (signal dbm - noise dbm).
  3308. * SNR at or above 40 is a great signal (100%).
  3309. * Below that, scale to fit SNR of 0 - 40 dB within 0 - 100% indicator.
  3310. * Weakest usable signal is usually 10 - 15 dB SNR. */
  3311. if (noise_dbm) {
  3312. if (rssi_dbm - noise_dbm >= 40)
  3313. return 100;
  3314. else if (rssi_dbm < noise_dbm)
  3315. return 0;
  3316. sig_qual = ((rssi_dbm - noise_dbm) * 5) / 2;
  3317. /* Else use just the signal level.
  3318. * This formula is a least squares fit of data points collected and
  3319. * compared with a reference system that had a percentage (%) display
  3320. * for signal quality. */
  3321. } else
  3322. sig_qual = (100 * (RSSI_RANGE * RSSI_RANGE) - degradation *
  3323. (15 * RSSI_RANGE + 62 * degradation)) /
  3324. (RSSI_RANGE * RSSI_RANGE);
  3325. if (sig_qual > 100)
  3326. sig_qual = 100;
  3327. else if (sig_qual < 1)
  3328. sig_qual = 0;
  3329. return sig_qual;
  3330. }
  3331. /**
  3332. * iwl3945_rx_handle - Main entry function for receiving responses from uCode
  3333. *
  3334. * Uses the priv->rx_handlers callback function array to invoke
  3335. * the appropriate handlers, including command responses,
  3336. * frame-received notifications, and other notifications.
  3337. */
  3338. static void iwl3945_rx_handle(struct iwl3945_priv *priv)
  3339. {
  3340. struct iwl3945_rx_mem_buffer *rxb;
  3341. struct iwl3945_rx_packet *pkt;
  3342. struct iwl3945_rx_queue *rxq = &priv->rxq;
  3343. u32 r, i;
  3344. int reclaim;
  3345. unsigned long flags;
  3346. u8 fill_rx = 0;
  3347. u32 count = 8;
  3348. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  3349. * buffer that the driver may process (last buffer filled by ucode). */
  3350. r = iwl3945_hw_get_rx_read(priv);
  3351. i = rxq->read;
  3352. if (iwl3945_rx_queue_space(rxq) > (RX_QUEUE_SIZE / 2))
  3353. fill_rx = 1;
  3354. /* Rx interrupt, but nothing sent from uCode */
  3355. if (i == r)
  3356. IWL_DEBUG(IWL_DL_RX | IWL_DL_ISR, "r = %d, i = %d\n", r, i);
  3357. while (i != r) {
  3358. rxb = rxq->queue[i];
  3359. /* If an RXB doesn't have a Rx queue slot associated with it,
  3360. * then a bug has been introduced in the queue refilling
  3361. * routines -- catch it here */
  3362. BUG_ON(rxb == NULL);
  3363. rxq->queue[i] = NULL;
  3364. pci_dma_sync_single_for_cpu(priv->pci_dev, rxb->dma_addr,
  3365. IWL_RX_BUF_SIZE,
  3366. PCI_DMA_FROMDEVICE);
  3367. pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
  3368. /* Reclaim a command buffer only if this packet is a response
  3369. * to a (driver-originated) command.
  3370. * If the packet (e.g. Rx frame) originated from uCode,
  3371. * there is no command buffer to reclaim.
  3372. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  3373. * but apparently a few don't get set; catch them here. */
  3374. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  3375. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  3376. (pkt->hdr.cmd != REPLY_TX);
  3377. /* Based on type of command response or notification,
  3378. * handle those that need handling via function in
  3379. * rx_handlers table. See iwl3945_setup_rx_handlers() */
  3380. if (priv->rx_handlers[pkt->hdr.cmd]) {
  3381. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3382. "r = %d, i = %d, %s, 0x%02x\n", r, i,
  3383. get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  3384. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  3385. } else {
  3386. /* No handling needed */
  3387. IWL_DEBUG(IWL_DL_HOST_COMMAND | IWL_DL_RX | IWL_DL_ISR,
  3388. "r %d i %d No handler needed for %s, 0x%02x\n",
  3389. r, i, get_cmd_string(pkt->hdr.cmd),
  3390. pkt->hdr.cmd);
  3391. }
  3392. if (reclaim) {
  3393. /* Invoke any callbacks, transfer the skb to caller, and
  3394. * fire off the (possibly) blocking iwl3945_send_cmd()
  3395. * as we reclaim the driver command queue */
  3396. if (rxb && rxb->skb)
  3397. iwl3945_tx_cmd_complete(priv, rxb);
  3398. else
  3399. IWL_WARNING("Claim null rxb?\n");
  3400. }
  3401. /* For now we just don't re-use anything. We can tweak this
  3402. * later to try and re-use notification packets and SKBs that
  3403. * fail to Rx correctly */
  3404. if (rxb->skb != NULL) {
  3405. priv->alloc_rxb_skb--;
  3406. dev_kfree_skb_any(rxb->skb);
  3407. rxb->skb = NULL;
  3408. }
  3409. pci_unmap_single(priv->pci_dev, rxb->dma_addr,
  3410. IWL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
  3411. spin_lock_irqsave(&rxq->lock, flags);
  3412. list_add_tail(&rxb->list, &priv->rxq.rx_used);
  3413. spin_unlock_irqrestore(&rxq->lock, flags);
  3414. i = (i + 1) & RX_QUEUE_MASK;
  3415. /* If there are a lot of unused frames,
  3416. * restock the Rx queue so ucode won't assert. */
  3417. if (fill_rx) {
  3418. count++;
  3419. if (count >= 8) {
  3420. priv->rxq.read = i;
  3421. __iwl3945_rx_replenish(priv);
  3422. count = 0;
  3423. }
  3424. }
  3425. }
  3426. /* Backtrack one entry */
  3427. priv->rxq.read = i;
  3428. iwl3945_rx_queue_restock(priv);
  3429. }
  3430. /**
  3431. * iwl3945_tx_queue_update_write_ptr - Send new write index to hardware
  3432. */
  3433. static int iwl3945_tx_queue_update_write_ptr(struct iwl3945_priv *priv,
  3434. struct iwl3945_tx_queue *txq)
  3435. {
  3436. u32 reg = 0;
  3437. int rc = 0;
  3438. int txq_id = txq->q.id;
  3439. if (txq->need_update == 0)
  3440. return rc;
  3441. /* if we're trying to save power */
  3442. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  3443. /* wake up nic if it's powered down ...
  3444. * uCode will wake up, and interrupt us again, so next
  3445. * time we'll skip this part. */
  3446. reg = iwl3945_read32(priv, CSR_UCODE_DRV_GP1);
  3447. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  3448. IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
  3449. iwl3945_set_bit(priv, CSR_GP_CNTRL,
  3450. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  3451. return rc;
  3452. }
  3453. /* restore this queue's parameters in nic hardware. */
  3454. rc = iwl3945_grab_nic_access(priv);
  3455. if (rc)
  3456. return rc;
  3457. iwl3945_write_direct32(priv, HBUS_TARG_WRPTR,
  3458. txq->q.write_ptr | (txq_id << 8));
  3459. iwl3945_release_nic_access(priv);
  3460. /* else not in power-save mode, uCode will never sleep when we're
  3461. * trying to tx (during RFKILL, we're not trying to tx). */
  3462. } else
  3463. iwl3945_write32(priv, HBUS_TARG_WRPTR,
  3464. txq->q.write_ptr | (txq_id << 8));
  3465. txq->need_update = 0;
  3466. return rc;
  3467. }
  3468. #ifdef CONFIG_IWL3945_DEBUG
  3469. static void iwl3945_print_rx_config_cmd(struct iwl3945_rxon_cmd *rxon)
  3470. {
  3471. DECLARE_MAC_BUF(mac);
  3472. IWL_DEBUG_RADIO("RX CONFIG:\n");
  3473. iwl3945_print_hex_dump(IWL_DL_RADIO, (u8 *) rxon, sizeof(*rxon));
  3474. IWL_DEBUG_RADIO("u16 channel: 0x%x\n", le16_to_cpu(rxon->channel));
  3475. IWL_DEBUG_RADIO("u32 flags: 0x%08X\n", le32_to_cpu(rxon->flags));
  3476. IWL_DEBUG_RADIO("u32 filter_flags: 0x%08x\n",
  3477. le32_to_cpu(rxon->filter_flags));
  3478. IWL_DEBUG_RADIO("u8 dev_type: 0x%x\n", rxon->dev_type);
  3479. IWL_DEBUG_RADIO("u8 ofdm_basic_rates: 0x%02x\n",
  3480. rxon->ofdm_basic_rates);
  3481. IWL_DEBUG_RADIO("u8 cck_basic_rates: 0x%02x\n", rxon->cck_basic_rates);
  3482. IWL_DEBUG_RADIO("u8[6] node_addr: %s\n",
  3483. print_mac(mac, rxon->node_addr));
  3484. IWL_DEBUG_RADIO("u8[6] bssid_addr: %s\n",
  3485. print_mac(mac, rxon->bssid_addr));
  3486. IWL_DEBUG_RADIO("u16 assoc_id: 0x%x\n", le16_to_cpu(rxon->assoc_id));
  3487. }
  3488. #endif
  3489. static void iwl3945_enable_interrupts(struct iwl3945_priv *priv)
  3490. {
  3491. IWL_DEBUG_ISR("Enabling interrupts\n");
  3492. set_bit(STATUS_INT_ENABLED, &priv->status);
  3493. iwl3945_write32(priv, CSR_INT_MASK, CSR_INI_SET_MASK);
  3494. }
  3495. /* call this function to flush any scheduled tasklet */
  3496. static inline void iwl_synchronize_irq(struct iwl3945_priv *priv)
  3497. {
  3498. /* wait to make sure we flush pedding tasklet*/
  3499. synchronize_irq(priv->pci_dev->irq);
  3500. tasklet_kill(&priv->irq_tasklet);
  3501. }
  3502. static inline void iwl3945_disable_interrupts(struct iwl3945_priv *priv)
  3503. {
  3504. clear_bit(STATUS_INT_ENABLED, &priv->status);
  3505. /* disable interrupts from uCode/NIC to host */
  3506. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3507. /* acknowledge/clear/reset any interrupts still pending
  3508. * from uCode or flow handler (Rx/Tx DMA) */
  3509. iwl3945_write32(priv, CSR_INT, 0xffffffff);
  3510. iwl3945_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
  3511. IWL_DEBUG_ISR("Disabled interrupts\n");
  3512. }
  3513. static const char *desc_lookup(int i)
  3514. {
  3515. switch (i) {
  3516. case 1:
  3517. return "FAIL";
  3518. case 2:
  3519. return "BAD_PARAM";
  3520. case 3:
  3521. return "BAD_CHECKSUM";
  3522. case 4:
  3523. return "NMI_INTERRUPT";
  3524. case 5:
  3525. return "SYSASSERT";
  3526. case 6:
  3527. return "FATAL_ERROR";
  3528. }
  3529. return "UNKNOWN";
  3530. }
  3531. #define ERROR_START_OFFSET (1 * sizeof(u32))
  3532. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  3533. static void iwl3945_dump_nic_error_log(struct iwl3945_priv *priv)
  3534. {
  3535. u32 i;
  3536. u32 desc, time, count, base, data1;
  3537. u32 blink1, blink2, ilink1, ilink2;
  3538. int rc;
  3539. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  3540. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3541. IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
  3542. return;
  3543. }
  3544. rc = iwl3945_grab_nic_access(priv);
  3545. if (rc) {
  3546. IWL_WARNING("Can not read from adapter at this time.\n");
  3547. return;
  3548. }
  3549. count = iwl3945_read_targ_mem(priv, base);
  3550. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  3551. IWL_ERROR("Start IWL Error Log Dump:\n");
  3552. IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
  3553. }
  3554. IWL_ERROR("Desc Time asrtPC blink2 "
  3555. "ilink1 nmiPC Line\n");
  3556. for (i = ERROR_START_OFFSET;
  3557. i < (count * ERROR_ELEM_SIZE) + ERROR_START_OFFSET;
  3558. i += ERROR_ELEM_SIZE) {
  3559. desc = iwl3945_read_targ_mem(priv, base + i);
  3560. time =
  3561. iwl3945_read_targ_mem(priv, base + i + 1 * sizeof(u32));
  3562. blink1 =
  3563. iwl3945_read_targ_mem(priv, base + i + 2 * sizeof(u32));
  3564. blink2 =
  3565. iwl3945_read_targ_mem(priv, base + i + 3 * sizeof(u32));
  3566. ilink1 =
  3567. iwl3945_read_targ_mem(priv, base + i + 4 * sizeof(u32));
  3568. ilink2 =
  3569. iwl3945_read_targ_mem(priv, base + i + 5 * sizeof(u32));
  3570. data1 =
  3571. iwl3945_read_targ_mem(priv, base + i + 6 * sizeof(u32));
  3572. IWL_ERROR
  3573. ("%-13s (#%d) %010u 0x%05X 0x%05X 0x%05X 0x%05X %u\n\n",
  3574. desc_lookup(desc), desc, time, blink1, blink2,
  3575. ilink1, ilink2, data1);
  3576. }
  3577. iwl3945_release_nic_access(priv);
  3578. }
  3579. #define EVENT_START_OFFSET (6 * sizeof(u32))
  3580. /**
  3581. * iwl3945_print_event_log - Dump error event log to syslog
  3582. *
  3583. * NOTE: Must be called with iwl3945_grab_nic_access() already obtained!
  3584. */
  3585. static void iwl3945_print_event_log(struct iwl3945_priv *priv, u32 start_idx,
  3586. u32 num_events, u32 mode)
  3587. {
  3588. u32 i;
  3589. u32 base; /* SRAM byte address of event log header */
  3590. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  3591. u32 ptr; /* SRAM byte address of log data */
  3592. u32 ev, time, data; /* event log data */
  3593. if (num_events == 0)
  3594. return;
  3595. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3596. if (mode == 0)
  3597. event_size = 2 * sizeof(u32);
  3598. else
  3599. event_size = 3 * sizeof(u32);
  3600. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  3601. /* "time" is actually "data" for mode 0 (no timestamp).
  3602. * place event id # at far right for easier visual parsing. */
  3603. for (i = 0; i < num_events; i++) {
  3604. ev = iwl3945_read_targ_mem(priv, ptr);
  3605. ptr += sizeof(u32);
  3606. time = iwl3945_read_targ_mem(priv, ptr);
  3607. ptr += sizeof(u32);
  3608. if (mode == 0)
  3609. IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
  3610. else {
  3611. data = iwl3945_read_targ_mem(priv, ptr);
  3612. ptr += sizeof(u32);
  3613. IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
  3614. }
  3615. }
  3616. }
  3617. static void iwl3945_dump_nic_event_log(struct iwl3945_priv *priv)
  3618. {
  3619. int rc;
  3620. u32 base; /* SRAM byte address of event log header */
  3621. u32 capacity; /* event log capacity in # entries */
  3622. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  3623. u32 num_wraps; /* # times uCode wrapped to top of log */
  3624. u32 next_entry; /* index of next entry to be written by uCode */
  3625. u32 size; /* # entries that we'll print */
  3626. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  3627. if (!iwl3945_hw_valid_rtc_data_addr(base)) {
  3628. IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
  3629. return;
  3630. }
  3631. rc = iwl3945_grab_nic_access(priv);
  3632. if (rc) {
  3633. IWL_WARNING("Can not read from adapter at this time.\n");
  3634. return;
  3635. }
  3636. /* event log header */
  3637. capacity = iwl3945_read_targ_mem(priv, base);
  3638. mode = iwl3945_read_targ_mem(priv, base + (1 * sizeof(u32)));
  3639. num_wraps = iwl3945_read_targ_mem(priv, base + (2 * sizeof(u32)));
  3640. next_entry = iwl3945_read_targ_mem(priv, base + (3 * sizeof(u32)));
  3641. size = num_wraps ? capacity : next_entry;
  3642. /* bail out if nothing in log */
  3643. if (size == 0) {
  3644. IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
  3645. iwl3945_release_nic_access(priv);
  3646. return;
  3647. }
  3648. IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
  3649. size, num_wraps);
  3650. /* if uCode has wrapped back to top of log, start at the oldest entry,
  3651. * i.e the next one that uCode would fill. */
  3652. if (num_wraps)
  3653. iwl3945_print_event_log(priv, next_entry,
  3654. capacity - next_entry, mode);
  3655. /* (then/else) start at top of log */
  3656. iwl3945_print_event_log(priv, 0, next_entry, mode);
  3657. iwl3945_release_nic_access(priv);
  3658. }
  3659. /**
  3660. * iwl3945_irq_handle_error - called for HW or SW error interrupt from card
  3661. */
  3662. static void iwl3945_irq_handle_error(struct iwl3945_priv *priv)
  3663. {
  3664. /* Set the FW error flag -- cleared on iwl3945_down */
  3665. set_bit(STATUS_FW_ERROR, &priv->status);
  3666. /* Cancel currently queued command. */
  3667. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  3668. #ifdef CONFIG_IWL3945_DEBUG
  3669. if (iwl3945_debug_level & IWL_DL_FW_ERRORS) {
  3670. iwl3945_dump_nic_error_log(priv);
  3671. iwl3945_dump_nic_event_log(priv);
  3672. iwl3945_print_rx_config_cmd(&priv->staging_rxon);
  3673. }
  3674. #endif
  3675. wake_up_interruptible(&priv->wait_command_queue);
  3676. /* Keep the restart process from trying to send host
  3677. * commands by clearing the INIT status bit */
  3678. clear_bit(STATUS_READY, &priv->status);
  3679. if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  3680. IWL_DEBUG(IWL_DL_INFO | IWL_DL_FW_ERRORS,
  3681. "Restarting adapter due to uCode error.\n");
  3682. if (iwl3945_is_associated(priv)) {
  3683. memcpy(&priv->recovery_rxon, &priv->active_rxon,
  3684. sizeof(priv->recovery_rxon));
  3685. priv->error_recovering = 1;
  3686. }
  3687. queue_work(priv->workqueue, &priv->restart);
  3688. }
  3689. }
  3690. static void iwl3945_error_recovery(struct iwl3945_priv *priv)
  3691. {
  3692. unsigned long flags;
  3693. memcpy(&priv->staging_rxon, &priv->recovery_rxon,
  3694. sizeof(priv->staging_rxon));
  3695. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  3696. iwl3945_commit_rxon(priv);
  3697. iwl3945_add_station(priv, priv->bssid, 1, 0);
  3698. spin_lock_irqsave(&priv->lock, flags);
  3699. priv->assoc_id = le16_to_cpu(priv->staging_rxon.assoc_id);
  3700. priv->error_recovering = 0;
  3701. spin_unlock_irqrestore(&priv->lock, flags);
  3702. }
  3703. static void iwl3945_irq_tasklet(struct iwl3945_priv *priv)
  3704. {
  3705. u32 inta, handled = 0;
  3706. u32 inta_fh;
  3707. unsigned long flags;
  3708. #ifdef CONFIG_IWL3945_DEBUG
  3709. u32 inta_mask;
  3710. #endif
  3711. spin_lock_irqsave(&priv->lock, flags);
  3712. /* Ack/clear/reset pending uCode interrupts.
  3713. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  3714. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  3715. inta = iwl3945_read32(priv, CSR_INT);
  3716. iwl3945_write32(priv, CSR_INT, inta);
  3717. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  3718. * Any new interrupts that happen after this, either while we're
  3719. * in this tasklet, or later, will show up in next ISR/tasklet. */
  3720. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3721. iwl3945_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  3722. #ifdef CONFIG_IWL3945_DEBUG
  3723. if (iwl3945_debug_level & IWL_DL_ISR) {
  3724. /* just for debug */
  3725. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3726. IWL_DEBUG_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3727. inta, inta_mask, inta_fh);
  3728. }
  3729. #endif
  3730. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  3731. * atomic, make sure that inta covers all the interrupts that
  3732. * we've discovered, even if FH interrupt came in just after
  3733. * reading CSR_INT. */
  3734. if (inta_fh & CSR39_FH_INT_RX_MASK)
  3735. inta |= CSR_INT_BIT_FH_RX;
  3736. if (inta_fh & CSR39_FH_INT_TX_MASK)
  3737. inta |= CSR_INT_BIT_FH_TX;
  3738. /* Now service all interrupt bits discovered above. */
  3739. if (inta & CSR_INT_BIT_HW_ERR) {
  3740. IWL_ERROR("Microcode HW error detected. Restarting.\n");
  3741. /* Tell the device to stop sending interrupts */
  3742. iwl3945_disable_interrupts(priv);
  3743. iwl3945_irq_handle_error(priv);
  3744. handled |= CSR_INT_BIT_HW_ERR;
  3745. spin_unlock_irqrestore(&priv->lock, flags);
  3746. return;
  3747. }
  3748. #ifdef CONFIG_IWL3945_DEBUG
  3749. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3750. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  3751. if (inta & CSR_INT_BIT_SCD)
  3752. IWL_DEBUG_ISR("Scheduler finished to transmit "
  3753. "the frame/frames.\n");
  3754. /* Alive notification via Rx interrupt will do the real work */
  3755. if (inta & CSR_INT_BIT_ALIVE)
  3756. IWL_DEBUG_ISR("Alive interrupt\n");
  3757. }
  3758. #endif
  3759. /* Safely ignore these bits for debug checks below */
  3760. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  3761. /* HW RF KILL switch toggled (4965 only) */
  3762. if (inta & CSR_INT_BIT_RF_KILL) {
  3763. int hw_rf_kill = 0;
  3764. if (!(iwl3945_read32(priv, CSR_GP_CNTRL) &
  3765. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  3766. hw_rf_kill = 1;
  3767. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL | IWL_DL_ISR,
  3768. "RF_KILL bit toggled to %s.\n",
  3769. hw_rf_kill ? "disable radio":"enable radio");
  3770. /* Queue restart only if RF_KILL switch was set to "kill"
  3771. * when we loaded driver, and is now set to "enable".
  3772. * After we're Alive, RF_KILL gets handled by
  3773. * iwl3945_rx_card_state_notif() */
  3774. if (!hw_rf_kill && !test_bit(STATUS_ALIVE, &priv->status)) {
  3775. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3776. queue_work(priv->workqueue, &priv->restart);
  3777. }
  3778. handled |= CSR_INT_BIT_RF_KILL;
  3779. }
  3780. /* Chip got too hot and stopped itself (4965 only) */
  3781. if (inta & CSR_INT_BIT_CT_KILL) {
  3782. IWL_ERROR("Microcode CT kill error detected.\n");
  3783. handled |= CSR_INT_BIT_CT_KILL;
  3784. }
  3785. /* Error detected by uCode */
  3786. if (inta & CSR_INT_BIT_SW_ERR) {
  3787. IWL_ERROR("Microcode SW error detected. Restarting 0x%X.\n",
  3788. inta);
  3789. iwl3945_irq_handle_error(priv);
  3790. handled |= CSR_INT_BIT_SW_ERR;
  3791. }
  3792. /* uCode wakes up after power-down sleep */
  3793. if (inta & CSR_INT_BIT_WAKEUP) {
  3794. IWL_DEBUG_ISR("Wakeup interrupt\n");
  3795. iwl3945_rx_queue_update_write_ptr(priv, &priv->rxq);
  3796. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[0]);
  3797. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[1]);
  3798. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[2]);
  3799. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[3]);
  3800. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[4]);
  3801. iwl3945_tx_queue_update_write_ptr(priv, &priv->txq[5]);
  3802. handled |= CSR_INT_BIT_WAKEUP;
  3803. }
  3804. /* All uCode command responses, including Tx command responses,
  3805. * Rx "responses" (frame-received notification), and other
  3806. * notifications from uCode come through here*/
  3807. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  3808. iwl3945_rx_handle(priv);
  3809. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  3810. }
  3811. if (inta & CSR_INT_BIT_FH_TX) {
  3812. IWL_DEBUG_ISR("Tx interrupt\n");
  3813. iwl3945_write32(priv, CSR_FH_INT_STATUS, (1 << 6));
  3814. if (!iwl3945_grab_nic_access(priv)) {
  3815. iwl3945_write_direct32(priv,
  3816. FH_TCSR_CREDIT
  3817. (ALM_FH_SRVC_CHNL), 0x0);
  3818. iwl3945_release_nic_access(priv);
  3819. }
  3820. handled |= CSR_INT_BIT_FH_TX;
  3821. }
  3822. if (inta & ~handled)
  3823. IWL_ERROR("Unhandled INTA bits 0x%08x\n", inta & ~handled);
  3824. if (inta & ~CSR_INI_SET_MASK) {
  3825. IWL_WARNING("Disabled INTA bits 0x%08x were pending\n",
  3826. inta & ~CSR_INI_SET_MASK);
  3827. IWL_WARNING(" with FH_INT = 0x%08x\n", inta_fh);
  3828. }
  3829. /* Re-enable all interrupts */
  3830. /* only Re-enable if disabled by irq */
  3831. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3832. iwl3945_enable_interrupts(priv);
  3833. #ifdef CONFIG_IWL3945_DEBUG
  3834. if (iwl3945_debug_level & (IWL_DL_ISR)) {
  3835. inta = iwl3945_read32(priv, CSR_INT);
  3836. inta_mask = iwl3945_read32(priv, CSR_INT_MASK);
  3837. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3838. IWL_DEBUG_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  3839. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  3840. }
  3841. #endif
  3842. spin_unlock_irqrestore(&priv->lock, flags);
  3843. }
  3844. static irqreturn_t iwl3945_isr(int irq, void *data)
  3845. {
  3846. struct iwl3945_priv *priv = data;
  3847. u32 inta, inta_mask;
  3848. u32 inta_fh;
  3849. if (!priv)
  3850. return IRQ_NONE;
  3851. spin_lock(&priv->lock);
  3852. /* Disable (but don't clear!) interrupts here to avoid
  3853. * back-to-back ISRs and sporadic interrupts from our NIC.
  3854. * If we have something to service, the tasklet will re-enable ints.
  3855. * If we *don't* have something, we'll re-enable before leaving here. */
  3856. inta_mask = iwl3945_read32(priv, CSR_INT_MASK); /* just for debug */
  3857. iwl3945_write32(priv, CSR_INT_MASK, 0x00000000);
  3858. /* Discover which interrupts are active/pending */
  3859. inta = iwl3945_read32(priv, CSR_INT);
  3860. inta_fh = iwl3945_read32(priv, CSR_FH_INT_STATUS);
  3861. /* Ignore interrupt if there's nothing in NIC to service.
  3862. * This may be due to IRQ shared with another device,
  3863. * or due to sporadic interrupts thrown from our NIC. */
  3864. if (!inta && !inta_fh) {
  3865. IWL_DEBUG_ISR("Ignore interrupt, inta == 0, inta_fh == 0\n");
  3866. goto none;
  3867. }
  3868. if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
  3869. /* Hardware disappeared */
  3870. IWL_WARNING("HARDWARE GONE?? INTA == 0x%080x\n", inta);
  3871. goto unplugged;
  3872. }
  3873. IWL_DEBUG_ISR("ISR inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  3874. inta, inta_mask, inta_fh);
  3875. inta &= ~CSR_INT_BIT_SCD;
  3876. /* iwl3945_irq_tasklet() will service interrupts and re-enable them */
  3877. if (likely(inta || inta_fh))
  3878. tasklet_schedule(&priv->irq_tasklet);
  3879. unplugged:
  3880. spin_unlock(&priv->lock);
  3881. return IRQ_HANDLED;
  3882. none:
  3883. /* re-enable interrupts here since we don't have anything to service. */
  3884. /* only Re-enable if disabled by irq */
  3885. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  3886. iwl3945_enable_interrupts(priv);
  3887. spin_unlock(&priv->lock);
  3888. return IRQ_NONE;
  3889. }
  3890. /************************** EEPROM BANDS ****************************
  3891. *
  3892. * The iwl3945_eeprom_band definitions below provide the mapping from the
  3893. * EEPROM contents to the specific channel number supported for each
  3894. * band.
  3895. *
  3896. * For example, iwl3945_priv->eeprom.band_3_channels[4] from the band_3
  3897. * definition below maps to physical channel 42 in the 5.2GHz spectrum.
  3898. * The specific geography and calibration information for that channel
  3899. * is contained in the eeprom map itself.
  3900. *
  3901. * During init, we copy the eeprom information and channel map
  3902. * information into priv->channel_info_24/52 and priv->channel_map_24/52
  3903. *
  3904. * channel_map_24/52 provides the index in the channel_info array for a
  3905. * given channel. We have to have two separate maps as there is channel
  3906. * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
  3907. * band_2
  3908. *
  3909. * A value of 0xff stored in the channel_map indicates that the channel
  3910. * is not supported by the hardware at all.
  3911. *
  3912. * A value of 0xfe in the channel_map indicates that the channel is not
  3913. * valid for Tx with the current hardware. This means that
  3914. * while the system can tune and receive on a given channel, it may not
  3915. * be able to associate or transmit any frames on that
  3916. * channel. There is no corresponding channel information for that
  3917. * entry.
  3918. *
  3919. *********************************************************************/
  3920. /* 2.4 GHz */
  3921. static const u8 iwl3945_eeprom_band_1[14] = {
  3922. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
  3923. };
  3924. /* 5.2 GHz bands */
  3925. static const u8 iwl3945_eeprom_band_2[] = { /* 4915-5080MHz */
  3926. 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
  3927. };
  3928. static const u8 iwl3945_eeprom_band_3[] = { /* 5170-5320MHz */
  3929. 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
  3930. };
  3931. static const u8 iwl3945_eeprom_band_4[] = { /* 5500-5700MHz */
  3932. 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
  3933. };
  3934. static const u8 iwl3945_eeprom_band_5[] = { /* 5725-5825MHz */
  3935. 145, 149, 153, 157, 161, 165
  3936. };
  3937. static void iwl3945_init_band_reference(const struct iwl3945_priv *priv, int band,
  3938. int *eeprom_ch_count,
  3939. const struct iwl3945_eeprom_channel
  3940. **eeprom_ch_info,
  3941. const u8 **eeprom_ch_index)
  3942. {
  3943. switch (band) {
  3944. case 1: /* 2.4GHz band */
  3945. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_1);
  3946. *eeprom_ch_info = priv->eeprom.band_1_channels;
  3947. *eeprom_ch_index = iwl3945_eeprom_band_1;
  3948. break;
  3949. case 2: /* 4.9GHz band */
  3950. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_2);
  3951. *eeprom_ch_info = priv->eeprom.band_2_channels;
  3952. *eeprom_ch_index = iwl3945_eeprom_band_2;
  3953. break;
  3954. case 3: /* 5.2GHz band */
  3955. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_3);
  3956. *eeprom_ch_info = priv->eeprom.band_3_channels;
  3957. *eeprom_ch_index = iwl3945_eeprom_band_3;
  3958. break;
  3959. case 4: /* 5.5GHz band */
  3960. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_4);
  3961. *eeprom_ch_info = priv->eeprom.band_4_channels;
  3962. *eeprom_ch_index = iwl3945_eeprom_band_4;
  3963. break;
  3964. case 5: /* 5.7GHz band */
  3965. *eeprom_ch_count = ARRAY_SIZE(iwl3945_eeprom_band_5);
  3966. *eeprom_ch_info = priv->eeprom.band_5_channels;
  3967. *eeprom_ch_index = iwl3945_eeprom_band_5;
  3968. break;
  3969. default:
  3970. BUG();
  3971. return;
  3972. }
  3973. }
  3974. /**
  3975. * iwl3945_get_channel_info - Find driver's private channel info
  3976. *
  3977. * Based on band and channel number.
  3978. */
  3979. const struct iwl3945_channel_info *iwl3945_get_channel_info(const struct iwl3945_priv *priv,
  3980. enum ieee80211_band band, u16 channel)
  3981. {
  3982. int i;
  3983. switch (band) {
  3984. case IEEE80211_BAND_5GHZ:
  3985. for (i = 14; i < priv->channel_count; i++) {
  3986. if (priv->channel_info[i].channel == channel)
  3987. return &priv->channel_info[i];
  3988. }
  3989. break;
  3990. case IEEE80211_BAND_2GHZ:
  3991. if (channel >= 1 && channel <= 14)
  3992. return &priv->channel_info[channel - 1];
  3993. break;
  3994. case IEEE80211_NUM_BANDS:
  3995. WARN_ON(1);
  3996. }
  3997. return NULL;
  3998. }
  3999. #define CHECK_AND_PRINT(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
  4000. ? # x " " : "")
  4001. /**
  4002. * iwl3945_init_channel_map - Set up driver's info for all possible channels
  4003. */
  4004. static int iwl3945_init_channel_map(struct iwl3945_priv *priv)
  4005. {
  4006. int eeprom_ch_count = 0;
  4007. const u8 *eeprom_ch_index = NULL;
  4008. const struct iwl3945_eeprom_channel *eeprom_ch_info = NULL;
  4009. int band, ch;
  4010. struct iwl3945_channel_info *ch_info;
  4011. if (priv->channel_count) {
  4012. IWL_DEBUG_INFO("Channel map already initialized.\n");
  4013. return 0;
  4014. }
  4015. if (priv->eeprom.version < 0x2f) {
  4016. IWL_WARNING("Unsupported EEPROM version: 0x%04X\n",
  4017. priv->eeprom.version);
  4018. return -EINVAL;
  4019. }
  4020. IWL_DEBUG_INFO("Initializing regulatory info from EEPROM\n");
  4021. priv->channel_count =
  4022. ARRAY_SIZE(iwl3945_eeprom_band_1) +
  4023. ARRAY_SIZE(iwl3945_eeprom_band_2) +
  4024. ARRAY_SIZE(iwl3945_eeprom_band_3) +
  4025. ARRAY_SIZE(iwl3945_eeprom_band_4) +
  4026. ARRAY_SIZE(iwl3945_eeprom_band_5);
  4027. IWL_DEBUG_INFO("Parsing data for %d channels.\n", priv->channel_count);
  4028. priv->channel_info = kzalloc(sizeof(struct iwl3945_channel_info) *
  4029. priv->channel_count, GFP_KERNEL);
  4030. if (!priv->channel_info) {
  4031. IWL_ERROR("Could not allocate channel_info\n");
  4032. priv->channel_count = 0;
  4033. return -ENOMEM;
  4034. }
  4035. ch_info = priv->channel_info;
  4036. /* Loop through the 5 EEPROM bands adding them in order to the
  4037. * channel map we maintain (that contains additional information than
  4038. * what just in the EEPROM) */
  4039. for (band = 1; band <= 5; band++) {
  4040. iwl3945_init_band_reference(priv, band, &eeprom_ch_count,
  4041. &eeprom_ch_info, &eeprom_ch_index);
  4042. /* Loop through each band adding each of the channels */
  4043. for (ch = 0; ch < eeprom_ch_count; ch++) {
  4044. ch_info->channel = eeprom_ch_index[ch];
  4045. ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
  4046. IEEE80211_BAND_5GHZ;
  4047. /* permanently store EEPROM's channel regulatory flags
  4048. * and max power in channel info database. */
  4049. ch_info->eeprom = eeprom_ch_info[ch];
  4050. /* Copy the run-time flags so they are there even on
  4051. * invalid channels */
  4052. ch_info->flags = eeprom_ch_info[ch].flags;
  4053. if (!(is_channel_valid(ch_info))) {
  4054. IWL_DEBUG_INFO("Ch. %d Flags %x [%sGHz] - "
  4055. "No traffic\n",
  4056. ch_info->channel,
  4057. ch_info->flags,
  4058. is_channel_a_band(ch_info) ?
  4059. "5.2" : "2.4");
  4060. ch_info++;
  4061. continue;
  4062. }
  4063. /* Initialize regulatory-based run-time data */
  4064. ch_info->max_power_avg = ch_info->curr_txpow =
  4065. eeprom_ch_info[ch].max_power_avg;
  4066. ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
  4067. ch_info->min_power = 0;
  4068. IWL_DEBUG_INFO("Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  4069. " %ddBm): Ad-Hoc %ssupported\n",
  4070. ch_info->channel,
  4071. is_channel_a_band(ch_info) ?
  4072. "5.2" : "2.4",
  4073. CHECK_AND_PRINT(VALID),
  4074. CHECK_AND_PRINT(IBSS),
  4075. CHECK_AND_PRINT(ACTIVE),
  4076. CHECK_AND_PRINT(RADAR),
  4077. CHECK_AND_PRINT(WIDE),
  4078. CHECK_AND_PRINT(DFS),
  4079. eeprom_ch_info[ch].flags,
  4080. eeprom_ch_info[ch].max_power_avg,
  4081. ((eeprom_ch_info[ch].
  4082. flags & EEPROM_CHANNEL_IBSS)
  4083. && !(eeprom_ch_info[ch].
  4084. flags & EEPROM_CHANNEL_RADAR))
  4085. ? "" : "not ");
  4086. /* Set the user_txpower_limit to the highest power
  4087. * supported by any channel */
  4088. if (eeprom_ch_info[ch].max_power_avg >
  4089. priv->user_txpower_limit)
  4090. priv->user_txpower_limit =
  4091. eeprom_ch_info[ch].max_power_avg;
  4092. ch_info++;
  4093. }
  4094. }
  4095. /* Set up txpower settings in driver for all channels */
  4096. if (iwl3945_txpower_set_from_eeprom(priv))
  4097. return -EIO;
  4098. return 0;
  4099. }
  4100. /*
  4101. * iwl3945_free_channel_map - undo allocations in iwl3945_init_channel_map
  4102. */
  4103. static void iwl3945_free_channel_map(struct iwl3945_priv *priv)
  4104. {
  4105. kfree(priv->channel_info);
  4106. priv->channel_count = 0;
  4107. }
  4108. /* For active scan, listen ACTIVE_DWELL_TIME (msec) on each channel after
  4109. * sending probe req. This should be set long enough to hear probe responses
  4110. * from more than one AP. */
  4111. #define IWL_ACTIVE_DWELL_TIME_24 (20) /* all times in msec */
  4112. #define IWL_ACTIVE_DWELL_TIME_52 (10)
  4113. /* For faster active scanning, scan will move to the next channel if fewer than
  4114. * PLCP_QUIET_THRESH packets are heard on this channel within
  4115. * ACTIVE_QUIET_TIME after sending probe request. This shortens the dwell
  4116. * time if it's a quiet channel (nothing responded to our probe, and there's
  4117. * no other traffic).
  4118. * Disable "quiet" feature by setting PLCP_QUIET_THRESH to 0. */
  4119. #define IWL_PLCP_QUIET_THRESH __constant_cpu_to_le16(1) /* packets */
  4120. #define IWL_ACTIVE_QUIET_TIME __constant_cpu_to_le16(5) /* msec */
  4121. /* For passive scan, listen PASSIVE_DWELL_TIME (msec) on each channel.
  4122. * Must be set longer than active dwell time.
  4123. * For the most reliable scan, set > AP beacon interval (typically 100msec). */
  4124. #define IWL_PASSIVE_DWELL_TIME_24 (20) /* all times in msec */
  4125. #define IWL_PASSIVE_DWELL_TIME_52 (10)
  4126. #define IWL_PASSIVE_DWELL_BASE (100)
  4127. #define IWL_CHANNEL_TUNE_TIME 5
  4128. static inline u16 iwl3945_get_active_dwell_time(struct iwl3945_priv *priv,
  4129. enum ieee80211_band band)
  4130. {
  4131. if (band == IEEE80211_BAND_5GHZ)
  4132. return IWL_ACTIVE_DWELL_TIME_52;
  4133. else
  4134. return IWL_ACTIVE_DWELL_TIME_24;
  4135. }
  4136. static u16 iwl3945_get_passive_dwell_time(struct iwl3945_priv *priv,
  4137. enum ieee80211_band band)
  4138. {
  4139. u16 active = iwl3945_get_active_dwell_time(priv, band);
  4140. u16 passive = (band == IEEE80211_BAND_2GHZ) ?
  4141. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_24 :
  4142. IWL_PASSIVE_DWELL_BASE + IWL_PASSIVE_DWELL_TIME_52;
  4143. if (iwl3945_is_associated(priv)) {
  4144. /* If we're associated, we clamp the maximum passive
  4145. * dwell time to be 98% of the beacon interval (minus
  4146. * 2 * channel tune time) */
  4147. passive = priv->beacon_int;
  4148. if ((passive > IWL_PASSIVE_DWELL_BASE) || !passive)
  4149. passive = IWL_PASSIVE_DWELL_BASE;
  4150. passive = (passive * 98) / 100 - IWL_CHANNEL_TUNE_TIME * 2;
  4151. }
  4152. if (passive <= active)
  4153. passive = active + 1;
  4154. return passive;
  4155. }
  4156. static int iwl3945_get_channels_for_scan(struct iwl3945_priv *priv,
  4157. enum ieee80211_band band,
  4158. u8 is_active, u8 direct_mask,
  4159. struct iwl3945_scan_channel *scan_ch)
  4160. {
  4161. const struct ieee80211_channel *channels = NULL;
  4162. const struct ieee80211_supported_band *sband;
  4163. const struct iwl3945_channel_info *ch_info;
  4164. u16 passive_dwell = 0;
  4165. u16 active_dwell = 0;
  4166. int added, i;
  4167. sband = iwl3945_get_band(priv, band);
  4168. if (!sband)
  4169. return 0;
  4170. channels = sband->channels;
  4171. active_dwell = iwl3945_get_active_dwell_time(priv, band);
  4172. passive_dwell = iwl3945_get_passive_dwell_time(priv, band);
  4173. for (i = 0, added = 0; i < sband->n_channels; i++) {
  4174. if (channels[i].flags & IEEE80211_CHAN_DISABLED)
  4175. continue;
  4176. scan_ch->channel = channels[i].hw_value;
  4177. ch_info = iwl3945_get_channel_info(priv, band, scan_ch->channel);
  4178. if (!is_channel_valid(ch_info)) {
  4179. IWL_DEBUG_SCAN("Channel %d is INVALID for this band.\n",
  4180. scan_ch->channel);
  4181. continue;
  4182. }
  4183. if (!is_active || is_channel_passive(ch_info) ||
  4184. (channels[i].flags & IEEE80211_CHAN_PASSIVE_SCAN))
  4185. scan_ch->type = 0; /* passive */
  4186. else
  4187. scan_ch->type = 1; /* active */
  4188. if (scan_ch->type & 1)
  4189. scan_ch->type |= (direct_mask << 1);
  4190. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  4191. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  4192. /* Set txpower levels to defaults */
  4193. scan_ch->tpc.dsp_atten = 110;
  4194. /* scan_pwr_info->tpc.dsp_atten; */
  4195. /*scan_pwr_info->tpc.tx_gain; */
  4196. if (band == IEEE80211_BAND_5GHZ)
  4197. scan_ch->tpc.tx_gain = ((1 << 5) | (3 << 3)) | 3;
  4198. else {
  4199. scan_ch->tpc.tx_gain = ((1 << 5) | (5 << 3));
  4200. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  4201. * power level:
  4202. * scan_ch->tpc.tx_gain = ((1 << 5) | (2 << 3)) | 3;
  4203. */
  4204. }
  4205. IWL_DEBUG_SCAN("Scanning %d [%s %d]\n",
  4206. scan_ch->channel,
  4207. (scan_ch->type & 1) ? "ACTIVE" : "PASSIVE",
  4208. (scan_ch->type & 1) ?
  4209. active_dwell : passive_dwell);
  4210. scan_ch++;
  4211. added++;
  4212. }
  4213. IWL_DEBUG_SCAN("total channels to scan %d \n", added);
  4214. return added;
  4215. }
  4216. static void iwl3945_init_hw_rates(struct iwl3945_priv *priv,
  4217. struct ieee80211_rate *rates)
  4218. {
  4219. int i;
  4220. for (i = 0; i < IWL_RATE_COUNT; i++) {
  4221. rates[i].bitrate = iwl3945_rates[i].ieee * 5;
  4222. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  4223. rates[i].hw_value_short = i;
  4224. rates[i].flags = 0;
  4225. if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
  4226. /*
  4227. * If CCK != 1M then set short preamble rate flag.
  4228. */
  4229. rates[i].flags |= (iwl3945_rates[i].plcp == 10) ?
  4230. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  4231. }
  4232. }
  4233. }
  4234. /**
  4235. * iwl3945_init_geos - Initialize mac80211's geo/channel info based from eeprom
  4236. */
  4237. static int iwl3945_init_geos(struct iwl3945_priv *priv)
  4238. {
  4239. struct iwl3945_channel_info *ch;
  4240. struct ieee80211_supported_band *sband;
  4241. struct ieee80211_channel *channels;
  4242. struct ieee80211_channel *geo_ch;
  4243. struct ieee80211_rate *rates;
  4244. int i = 0;
  4245. if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
  4246. priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
  4247. IWL_DEBUG_INFO("Geography modes already initialized.\n");
  4248. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4249. return 0;
  4250. }
  4251. channels = kzalloc(sizeof(struct ieee80211_channel) *
  4252. priv->channel_count, GFP_KERNEL);
  4253. if (!channels)
  4254. return -ENOMEM;
  4255. rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
  4256. GFP_KERNEL);
  4257. if (!rates) {
  4258. kfree(channels);
  4259. return -ENOMEM;
  4260. }
  4261. /* 5.2GHz channels start after the 2.4GHz channels */
  4262. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4263. sband->channels = &channels[ARRAY_SIZE(iwl3945_eeprom_band_1)];
  4264. /* just OFDM */
  4265. sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
  4266. sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
  4267. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4268. sband->channels = channels;
  4269. /* OFDM & CCK */
  4270. sband->bitrates = rates;
  4271. sband->n_bitrates = IWL_RATE_COUNT;
  4272. priv->ieee_channels = channels;
  4273. priv->ieee_rates = rates;
  4274. iwl3945_init_hw_rates(priv, rates);
  4275. for (i = 0; i < priv->channel_count; i++) {
  4276. ch = &priv->channel_info[i];
  4277. /* FIXME: might be removed if scan is OK*/
  4278. if (!is_channel_valid(ch))
  4279. continue;
  4280. if (is_channel_a_band(ch))
  4281. sband = &priv->bands[IEEE80211_BAND_5GHZ];
  4282. else
  4283. sband = &priv->bands[IEEE80211_BAND_2GHZ];
  4284. geo_ch = &sband->channels[sband->n_channels++];
  4285. geo_ch->center_freq = ieee80211_channel_to_frequency(ch->channel);
  4286. geo_ch->max_power = ch->max_power_avg;
  4287. geo_ch->max_antenna_gain = 0xff;
  4288. geo_ch->hw_value = ch->channel;
  4289. if (is_channel_valid(ch)) {
  4290. if (!(ch->flags & EEPROM_CHANNEL_IBSS))
  4291. geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
  4292. if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
  4293. geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
  4294. if (ch->flags & EEPROM_CHANNEL_RADAR)
  4295. geo_ch->flags |= IEEE80211_CHAN_RADAR;
  4296. if (ch->max_power_avg > priv->max_channel_txpower_limit)
  4297. priv->max_channel_txpower_limit =
  4298. ch->max_power_avg;
  4299. } else {
  4300. geo_ch->flags |= IEEE80211_CHAN_DISABLED;
  4301. }
  4302. /* Save flags for reg domain usage */
  4303. geo_ch->orig_flags = geo_ch->flags;
  4304. IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
  4305. ch->channel, geo_ch->center_freq,
  4306. is_channel_a_band(ch) ? "5.2" : "2.4",
  4307. geo_ch->flags & IEEE80211_CHAN_DISABLED ?
  4308. "restricted" : "valid",
  4309. geo_ch->flags);
  4310. }
  4311. if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
  4312. priv->cfg->sku & IWL_SKU_A) {
  4313. printk(KERN_INFO DRV_NAME
  4314. ": Incorrectly detected BG card as ABG. Please send "
  4315. "your PCI ID 0x%04X:0x%04X to maintainer.\n",
  4316. priv->pci_dev->device, priv->pci_dev->subsystem_device);
  4317. priv->cfg->sku &= ~IWL_SKU_A;
  4318. }
  4319. printk(KERN_INFO DRV_NAME
  4320. ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
  4321. priv->bands[IEEE80211_BAND_2GHZ].n_channels,
  4322. priv->bands[IEEE80211_BAND_5GHZ].n_channels);
  4323. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  4324. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  4325. &priv->bands[IEEE80211_BAND_2GHZ];
  4326. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  4327. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  4328. &priv->bands[IEEE80211_BAND_5GHZ];
  4329. set_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4330. return 0;
  4331. }
  4332. /*
  4333. * iwl3945_free_geos - undo allocations in iwl3945_init_geos
  4334. */
  4335. static void iwl3945_free_geos(struct iwl3945_priv *priv)
  4336. {
  4337. kfree(priv->ieee_channels);
  4338. kfree(priv->ieee_rates);
  4339. clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
  4340. }
  4341. /******************************************************************************
  4342. *
  4343. * uCode download functions
  4344. *
  4345. ******************************************************************************/
  4346. static void iwl3945_dealloc_ucode_pci(struct iwl3945_priv *priv)
  4347. {
  4348. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  4349. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  4350. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4351. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  4352. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4353. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4354. }
  4355. /**
  4356. * iwl3945_verify_inst_full - verify runtime uCode image in card vs. host,
  4357. * looking at all data.
  4358. */
  4359. static int iwl3945_verify_inst_full(struct iwl3945_priv *priv, __le32 * image, u32 len)
  4360. {
  4361. u32 val;
  4362. u32 save_len = len;
  4363. int rc = 0;
  4364. u32 errcnt;
  4365. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4366. rc = iwl3945_grab_nic_access(priv);
  4367. if (rc)
  4368. return rc;
  4369. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
  4370. errcnt = 0;
  4371. for (; len > 0; len -= sizeof(u32), image++) {
  4372. /* read data comes through single port, auto-incr addr */
  4373. /* NOTE: Use the debugless read so we don't flood kernel log
  4374. * if IWL_DL_IO is set */
  4375. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4376. if (val != le32_to_cpu(*image)) {
  4377. IWL_ERROR("uCode INST section is invalid at "
  4378. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4379. save_len - len, val, le32_to_cpu(*image));
  4380. rc = -EIO;
  4381. errcnt++;
  4382. if (errcnt >= 20)
  4383. break;
  4384. }
  4385. }
  4386. iwl3945_release_nic_access(priv);
  4387. if (!errcnt)
  4388. IWL_DEBUG_INFO("ucode image in INSTRUCTION memory is good\n");
  4389. return rc;
  4390. }
  4391. /**
  4392. * iwl3945_verify_inst_sparse - verify runtime uCode image in card vs. host,
  4393. * using sample data 100 bytes apart. If these sample points are good,
  4394. * it's a pretty good bet that everything between them is good, too.
  4395. */
  4396. static int iwl3945_verify_inst_sparse(struct iwl3945_priv *priv, __le32 *image, u32 len)
  4397. {
  4398. u32 val;
  4399. int rc = 0;
  4400. u32 errcnt = 0;
  4401. u32 i;
  4402. IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
  4403. rc = iwl3945_grab_nic_access(priv);
  4404. if (rc)
  4405. return rc;
  4406. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  4407. /* read data comes through single port, auto-incr addr */
  4408. /* NOTE: Use the debugless read so we don't flood kernel log
  4409. * if IWL_DL_IO is set */
  4410. iwl3945_write_direct32(priv, HBUS_TARG_MEM_RADDR,
  4411. i + RTC_INST_LOWER_BOUND);
  4412. val = _iwl3945_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  4413. if (val != le32_to_cpu(*image)) {
  4414. #if 0 /* Enable this if you want to see details */
  4415. IWL_ERROR("uCode INST section is invalid at "
  4416. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  4417. i, val, *image);
  4418. #endif
  4419. rc = -EIO;
  4420. errcnt++;
  4421. if (errcnt >= 3)
  4422. break;
  4423. }
  4424. }
  4425. iwl3945_release_nic_access(priv);
  4426. return rc;
  4427. }
  4428. /**
  4429. * iwl3945_verify_ucode - determine which instruction image is in SRAM,
  4430. * and verify its contents
  4431. */
  4432. static int iwl3945_verify_ucode(struct iwl3945_priv *priv)
  4433. {
  4434. __le32 *image;
  4435. u32 len;
  4436. int rc = 0;
  4437. /* Try bootstrap */
  4438. image = (__le32 *)priv->ucode_boot.v_addr;
  4439. len = priv->ucode_boot.len;
  4440. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4441. if (rc == 0) {
  4442. IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
  4443. return 0;
  4444. }
  4445. /* Try initialize */
  4446. image = (__le32 *)priv->ucode_init.v_addr;
  4447. len = priv->ucode_init.len;
  4448. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4449. if (rc == 0) {
  4450. IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
  4451. return 0;
  4452. }
  4453. /* Try runtime/protocol */
  4454. image = (__le32 *)priv->ucode_code.v_addr;
  4455. len = priv->ucode_code.len;
  4456. rc = iwl3945_verify_inst_sparse(priv, image, len);
  4457. if (rc == 0) {
  4458. IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
  4459. return 0;
  4460. }
  4461. IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
  4462. /* Since nothing seems to match, show first several data entries in
  4463. * instruction SRAM, so maybe visual inspection will give a clue.
  4464. * Selection of bootstrap image (vs. other images) is arbitrary. */
  4465. image = (__le32 *)priv->ucode_boot.v_addr;
  4466. len = priv->ucode_boot.len;
  4467. rc = iwl3945_verify_inst_full(priv, image, len);
  4468. return rc;
  4469. }
  4470. /* check contents of special bootstrap uCode SRAM */
  4471. static int iwl3945_verify_bsm(struct iwl3945_priv *priv)
  4472. {
  4473. __le32 *image = priv->ucode_boot.v_addr;
  4474. u32 len = priv->ucode_boot.len;
  4475. u32 reg;
  4476. u32 val;
  4477. IWL_DEBUG_INFO("Begin verify bsm\n");
  4478. /* verify BSM SRAM contents */
  4479. val = iwl3945_read_prph(priv, BSM_WR_DWCOUNT_REG);
  4480. for (reg = BSM_SRAM_LOWER_BOUND;
  4481. reg < BSM_SRAM_LOWER_BOUND + len;
  4482. reg += sizeof(u32), image ++) {
  4483. val = iwl3945_read_prph(priv, reg);
  4484. if (val != le32_to_cpu(*image)) {
  4485. IWL_ERROR("BSM uCode verification failed at "
  4486. "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
  4487. BSM_SRAM_LOWER_BOUND,
  4488. reg - BSM_SRAM_LOWER_BOUND, len,
  4489. val, le32_to_cpu(*image));
  4490. return -EIO;
  4491. }
  4492. }
  4493. IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
  4494. return 0;
  4495. }
  4496. /**
  4497. * iwl3945_load_bsm - Load bootstrap instructions
  4498. *
  4499. * BSM operation:
  4500. *
  4501. * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
  4502. * in special SRAM that does not power down during RFKILL. When powering back
  4503. * up after power-saving sleeps (or during initial uCode load), the BSM loads
  4504. * the bootstrap program into the on-board processor, and starts it.
  4505. *
  4506. * The bootstrap program loads (via DMA) instructions and data for a new
  4507. * program from host DRAM locations indicated by the host driver in the
  4508. * BSM_DRAM_* registers. Once the new program is loaded, it starts
  4509. * automatically.
  4510. *
  4511. * When initializing the NIC, the host driver points the BSM to the
  4512. * "initialize" uCode image. This uCode sets up some internal data, then
  4513. * notifies host via "initialize alive" that it is complete.
  4514. *
  4515. * The host then replaces the BSM_DRAM_* pointer values to point to the
  4516. * normal runtime uCode instructions and a backup uCode data cache buffer
  4517. * (filled initially with starting data values for the on-board processor),
  4518. * then triggers the "initialize" uCode to load and launch the runtime uCode,
  4519. * which begins normal operation.
  4520. *
  4521. * When doing a power-save shutdown, runtime uCode saves data SRAM into
  4522. * the backup data cache in DRAM before SRAM is powered down.
  4523. *
  4524. * When powering back up, the BSM loads the bootstrap program. This reloads
  4525. * the runtime uCode instructions and the backup data cache into SRAM,
  4526. * and re-launches the runtime uCode from where it left off.
  4527. */
  4528. static int iwl3945_load_bsm(struct iwl3945_priv *priv)
  4529. {
  4530. __le32 *image = priv->ucode_boot.v_addr;
  4531. u32 len = priv->ucode_boot.len;
  4532. dma_addr_t pinst;
  4533. dma_addr_t pdata;
  4534. u32 inst_len;
  4535. u32 data_len;
  4536. int rc;
  4537. int i;
  4538. u32 done;
  4539. u32 reg_offset;
  4540. IWL_DEBUG_INFO("Begin load bsm\n");
  4541. /* make sure bootstrap program is no larger than BSM's SRAM size */
  4542. if (len > IWL_MAX_BSM_SIZE)
  4543. return -EINVAL;
  4544. /* Tell bootstrap uCode where to find the "Initialize" uCode
  4545. * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
  4546. * NOTE: iwl3945_initialize_alive_start() will replace these values,
  4547. * after the "initialize" uCode has run, to point to
  4548. * runtime/protocol instructions and backup data cache. */
  4549. pinst = priv->ucode_init.p_addr;
  4550. pdata = priv->ucode_init_data.p_addr;
  4551. inst_len = priv->ucode_init.len;
  4552. data_len = priv->ucode_init_data.len;
  4553. rc = iwl3945_grab_nic_access(priv);
  4554. if (rc)
  4555. return rc;
  4556. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4557. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4558. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
  4559. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
  4560. /* Fill BSM memory with bootstrap instructions */
  4561. for (reg_offset = BSM_SRAM_LOWER_BOUND;
  4562. reg_offset < BSM_SRAM_LOWER_BOUND + len;
  4563. reg_offset += sizeof(u32), image++)
  4564. _iwl3945_write_prph(priv, reg_offset,
  4565. le32_to_cpu(*image));
  4566. rc = iwl3945_verify_bsm(priv);
  4567. if (rc) {
  4568. iwl3945_release_nic_access(priv);
  4569. return rc;
  4570. }
  4571. /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
  4572. iwl3945_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
  4573. iwl3945_write_prph(priv, BSM_WR_MEM_DST_REG,
  4574. RTC_INST_LOWER_BOUND);
  4575. iwl3945_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
  4576. /* Load bootstrap code into instruction SRAM now,
  4577. * to prepare to load "initialize" uCode */
  4578. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4579. BSM_WR_CTRL_REG_BIT_START);
  4580. /* Wait for load of bootstrap uCode to finish */
  4581. for (i = 0; i < 100; i++) {
  4582. done = iwl3945_read_prph(priv, BSM_WR_CTRL_REG);
  4583. if (!(done & BSM_WR_CTRL_REG_BIT_START))
  4584. break;
  4585. udelay(10);
  4586. }
  4587. if (i < 100)
  4588. IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
  4589. else {
  4590. IWL_ERROR("BSM write did not complete!\n");
  4591. return -EIO;
  4592. }
  4593. /* Enable future boot loads whenever power management unit triggers it
  4594. * (e.g. when powering back up after power-save shutdown) */
  4595. iwl3945_write_prph(priv, BSM_WR_CTRL_REG,
  4596. BSM_WR_CTRL_REG_BIT_START_EN);
  4597. iwl3945_release_nic_access(priv);
  4598. return 0;
  4599. }
  4600. static void iwl3945_nic_start(struct iwl3945_priv *priv)
  4601. {
  4602. /* Remove all resets to allow NIC to operate */
  4603. iwl3945_write32(priv, CSR_RESET, 0);
  4604. }
  4605. /**
  4606. * iwl3945_read_ucode - Read uCode images from disk file.
  4607. *
  4608. * Copy into buffers for card to fetch via bus-mastering
  4609. */
  4610. static int iwl3945_read_ucode(struct iwl3945_priv *priv)
  4611. {
  4612. struct iwl3945_ucode *ucode;
  4613. int ret = 0;
  4614. const struct firmware *ucode_raw;
  4615. /* firmware file name contains uCode/driver compatibility version */
  4616. const char *name = priv->cfg->fw_name;
  4617. u8 *src;
  4618. size_t len;
  4619. u32 ver, inst_size, data_size, init_size, init_data_size, boot_size;
  4620. /* Ask kernel firmware_class module to get the boot firmware off disk.
  4621. * request_firmware() is synchronous, file is in memory on return. */
  4622. ret = request_firmware(&ucode_raw, name, &priv->pci_dev->dev);
  4623. if (ret < 0) {
  4624. IWL_ERROR("%s firmware file req failed: Reason %d\n",
  4625. name, ret);
  4626. goto error;
  4627. }
  4628. IWL_DEBUG_INFO("Got firmware '%s' file (%zd bytes) from disk\n",
  4629. name, ucode_raw->size);
  4630. /* Make sure that we got at least our header! */
  4631. if (ucode_raw->size < sizeof(*ucode)) {
  4632. IWL_ERROR("File size way too small!\n");
  4633. ret = -EINVAL;
  4634. goto err_release;
  4635. }
  4636. /* Data from ucode file: header followed by uCode images */
  4637. ucode = (void *)ucode_raw->data;
  4638. ver = le32_to_cpu(ucode->ver);
  4639. inst_size = le32_to_cpu(ucode->inst_size);
  4640. data_size = le32_to_cpu(ucode->data_size);
  4641. init_size = le32_to_cpu(ucode->init_size);
  4642. init_data_size = le32_to_cpu(ucode->init_data_size);
  4643. boot_size = le32_to_cpu(ucode->boot_size);
  4644. IWL_DEBUG_INFO("f/w package hdr ucode version = 0x%x\n", ver);
  4645. IWL_DEBUG_INFO("f/w package hdr runtime inst size = %u\n", inst_size);
  4646. IWL_DEBUG_INFO("f/w package hdr runtime data size = %u\n", data_size);
  4647. IWL_DEBUG_INFO("f/w package hdr init inst size = %u\n", init_size);
  4648. IWL_DEBUG_INFO("f/w package hdr init data size = %u\n", init_data_size);
  4649. IWL_DEBUG_INFO("f/w package hdr boot inst size = %u\n", boot_size);
  4650. /* Verify size of file vs. image size info in file's header */
  4651. if (ucode_raw->size < sizeof(*ucode) +
  4652. inst_size + data_size + init_size +
  4653. init_data_size + boot_size) {
  4654. IWL_DEBUG_INFO("uCode file size %d too small\n",
  4655. (int)ucode_raw->size);
  4656. ret = -EINVAL;
  4657. goto err_release;
  4658. }
  4659. /* Verify that uCode images will fit in card's SRAM */
  4660. if (inst_size > IWL_MAX_INST_SIZE) {
  4661. IWL_DEBUG_INFO("uCode instr len %d too large to fit in\n",
  4662. inst_size);
  4663. ret = -EINVAL;
  4664. goto err_release;
  4665. }
  4666. if (data_size > IWL_MAX_DATA_SIZE) {
  4667. IWL_DEBUG_INFO("uCode data len %d too large to fit in\n",
  4668. data_size);
  4669. ret = -EINVAL;
  4670. goto err_release;
  4671. }
  4672. if (init_size > IWL_MAX_INST_SIZE) {
  4673. IWL_DEBUG_INFO("uCode init instr len %d too large to fit in\n",
  4674. init_size);
  4675. ret = -EINVAL;
  4676. goto err_release;
  4677. }
  4678. if (init_data_size > IWL_MAX_DATA_SIZE) {
  4679. IWL_DEBUG_INFO("uCode init data len %d too large to fit in\n",
  4680. init_data_size);
  4681. ret = -EINVAL;
  4682. goto err_release;
  4683. }
  4684. if (boot_size > IWL_MAX_BSM_SIZE) {
  4685. IWL_DEBUG_INFO("uCode boot instr len %d too large to fit in\n",
  4686. boot_size);
  4687. ret = -EINVAL;
  4688. goto err_release;
  4689. }
  4690. /* Allocate ucode buffers for card's bus-master loading ... */
  4691. /* Runtime instructions and 2 copies of data:
  4692. * 1) unmodified from disk
  4693. * 2) backup cache for save/restore during power-downs */
  4694. priv->ucode_code.len = inst_size;
  4695. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  4696. priv->ucode_data.len = data_size;
  4697. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  4698. priv->ucode_data_backup.len = data_size;
  4699. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  4700. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  4701. !priv->ucode_data_backup.v_addr)
  4702. goto err_pci_alloc;
  4703. /* Initialization instructions and data */
  4704. if (init_size && init_data_size) {
  4705. priv->ucode_init.len = init_size;
  4706. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  4707. priv->ucode_init_data.len = init_data_size;
  4708. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  4709. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  4710. goto err_pci_alloc;
  4711. }
  4712. /* Bootstrap (instructions only, no data) */
  4713. if (boot_size) {
  4714. priv->ucode_boot.len = boot_size;
  4715. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  4716. if (!priv->ucode_boot.v_addr)
  4717. goto err_pci_alloc;
  4718. }
  4719. /* Copy images into buffers for card's bus-master reads ... */
  4720. /* Runtime instructions (first block of data in file) */
  4721. src = &ucode->data[0];
  4722. len = priv->ucode_code.len;
  4723. IWL_DEBUG_INFO("Copying (but not loading) uCode instr len %Zd\n", len);
  4724. memcpy(priv->ucode_code.v_addr, src, len);
  4725. IWL_DEBUG_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  4726. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  4727. /* Runtime data (2nd block)
  4728. * NOTE: Copy into backup buffer will be done in iwl3945_up() */
  4729. src = &ucode->data[inst_size];
  4730. len = priv->ucode_data.len;
  4731. IWL_DEBUG_INFO("Copying (but not loading) uCode data len %Zd\n", len);
  4732. memcpy(priv->ucode_data.v_addr, src, len);
  4733. memcpy(priv->ucode_data_backup.v_addr, src, len);
  4734. /* Initialization instructions (3rd block) */
  4735. if (init_size) {
  4736. src = &ucode->data[inst_size + data_size];
  4737. len = priv->ucode_init.len;
  4738. IWL_DEBUG_INFO("Copying (but not loading) init instr len %Zd\n",
  4739. len);
  4740. memcpy(priv->ucode_init.v_addr, src, len);
  4741. }
  4742. /* Initialization data (4th block) */
  4743. if (init_data_size) {
  4744. src = &ucode->data[inst_size + data_size + init_size];
  4745. len = priv->ucode_init_data.len;
  4746. IWL_DEBUG_INFO("Copying (but not loading) init data len %d\n",
  4747. (int)len);
  4748. memcpy(priv->ucode_init_data.v_addr, src, len);
  4749. }
  4750. /* Bootstrap instructions (5th block) */
  4751. src = &ucode->data[inst_size + data_size + init_size + init_data_size];
  4752. len = priv->ucode_boot.len;
  4753. IWL_DEBUG_INFO("Copying (but not loading) boot instr len %d\n",
  4754. (int)len);
  4755. memcpy(priv->ucode_boot.v_addr, src, len);
  4756. /* We have our copies now, allow OS release its copies */
  4757. release_firmware(ucode_raw);
  4758. return 0;
  4759. err_pci_alloc:
  4760. IWL_ERROR("failed to allocate pci memory\n");
  4761. ret = -ENOMEM;
  4762. iwl3945_dealloc_ucode_pci(priv);
  4763. err_release:
  4764. release_firmware(ucode_raw);
  4765. error:
  4766. return ret;
  4767. }
  4768. /**
  4769. * iwl3945_set_ucode_ptrs - Set uCode address location
  4770. *
  4771. * Tell initialization uCode where to find runtime uCode.
  4772. *
  4773. * BSM registers initially contain pointers to initialization uCode.
  4774. * We need to replace them to load runtime uCode inst and data,
  4775. * and to save runtime data when powering down.
  4776. */
  4777. static int iwl3945_set_ucode_ptrs(struct iwl3945_priv *priv)
  4778. {
  4779. dma_addr_t pinst;
  4780. dma_addr_t pdata;
  4781. int rc = 0;
  4782. unsigned long flags;
  4783. /* bits 31:0 for 3945 */
  4784. pinst = priv->ucode_code.p_addr;
  4785. pdata = priv->ucode_data_backup.p_addr;
  4786. spin_lock_irqsave(&priv->lock, flags);
  4787. rc = iwl3945_grab_nic_access(priv);
  4788. if (rc) {
  4789. spin_unlock_irqrestore(&priv->lock, flags);
  4790. return rc;
  4791. }
  4792. /* Tell bootstrap uCode where to find image to load */
  4793. iwl3945_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
  4794. iwl3945_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
  4795. iwl3945_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
  4796. priv->ucode_data.len);
  4797. /* Inst bytecount must be last to set up, bit 31 signals uCode
  4798. * that all new ptr/size info is in place */
  4799. iwl3945_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
  4800. priv->ucode_code.len | BSM_DRAM_INST_LOAD);
  4801. iwl3945_release_nic_access(priv);
  4802. spin_unlock_irqrestore(&priv->lock, flags);
  4803. IWL_DEBUG_INFO("Runtime uCode pointers are set.\n");
  4804. return rc;
  4805. }
  4806. /**
  4807. * iwl3945_init_alive_start - Called after REPLY_ALIVE notification received
  4808. *
  4809. * Called after REPLY_ALIVE notification received from "initialize" uCode.
  4810. *
  4811. * Tell "initialize" uCode to go ahead and load the runtime uCode.
  4812. */
  4813. static void iwl3945_init_alive_start(struct iwl3945_priv *priv)
  4814. {
  4815. /* Check alive response for "valid" sign from uCode */
  4816. if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
  4817. /* We had an error bringing up the hardware, so take it
  4818. * all the way back down so we can try again */
  4819. IWL_DEBUG_INFO("Initialize Alive failed.\n");
  4820. goto restart;
  4821. }
  4822. /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
  4823. * This is a paranoid check, because we would not have gotten the
  4824. * "initialize" alive if code weren't properly loaded. */
  4825. if (iwl3945_verify_ucode(priv)) {
  4826. /* Runtime instruction load was bad;
  4827. * take it all the way back down so we can try again */
  4828. IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
  4829. goto restart;
  4830. }
  4831. /* Send pointers to protocol/runtime uCode image ... init code will
  4832. * load and launch runtime uCode, which will send us another "Alive"
  4833. * notification. */
  4834. IWL_DEBUG_INFO("Initialization Alive received.\n");
  4835. if (iwl3945_set_ucode_ptrs(priv)) {
  4836. /* Runtime instruction load won't happen;
  4837. * take it all the way back down so we can try again */
  4838. IWL_DEBUG_INFO("Couldn't set up uCode pointers.\n");
  4839. goto restart;
  4840. }
  4841. return;
  4842. restart:
  4843. queue_work(priv->workqueue, &priv->restart);
  4844. }
  4845. /**
  4846. * iwl3945_alive_start - called after REPLY_ALIVE notification received
  4847. * from protocol/runtime uCode (initialization uCode's
  4848. * Alive gets handled by iwl3945_init_alive_start()).
  4849. */
  4850. static void iwl3945_alive_start(struct iwl3945_priv *priv)
  4851. {
  4852. int rc = 0;
  4853. int thermal_spin = 0;
  4854. u32 rfkill;
  4855. IWL_DEBUG_INFO("Runtime Alive received.\n");
  4856. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  4857. /* We had an error bringing up the hardware, so take it
  4858. * all the way back down so we can try again */
  4859. IWL_DEBUG_INFO("Alive failed.\n");
  4860. goto restart;
  4861. }
  4862. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  4863. * This is a paranoid check, because we would not have gotten the
  4864. * "runtime" alive if code weren't properly loaded. */
  4865. if (iwl3945_verify_ucode(priv)) {
  4866. /* Runtime instruction load was bad;
  4867. * take it all the way back down so we can try again */
  4868. IWL_DEBUG_INFO("Bad runtime uCode load.\n");
  4869. goto restart;
  4870. }
  4871. iwl3945_clear_stations_table(priv);
  4872. rc = iwl3945_grab_nic_access(priv);
  4873. if (rc) {
  4874. IWL_WARNING("Can not read rfkill status from adapter\n");
  4875. return;
  4876. }
  4877. rfkill = iwl3945_read_prph(priv, APMG_RFKILL_REG);
  4878. IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
  4879. iwl3945_release_nic_access(priv);
  4880. if (rfkill & 0x1) {
  4881. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  4882. /* if rfkill is not on, then wait for thermal
  4883. * sensor in adapter to kick in */
  4884. while (iwl3945_hw_get_temperature(priv) == 0) {
  4885. thermal_spin++;
  4886. udelay(10);
  4887. }
  4888. if (thermal_spin)
  4889. IWL_DEBUG_INFO("Thermal calibration took %dus\n",
  4890. thermal_spin * 10);
  4891. } else
  4892. set_bit(STATUS_RF_KILL_HW, &priv->status);
  4893. /* After the ALIVE response, we can send commands to 3945 uCode */
  4894. set_bit(STATUS_ALIVE, &priv->status);
  4895. /* Clear out the uCode error bit if it is set */
  4896. clear_bit(STATUS_FW_ERROR, &priv->status);
  4897. if (iwl3945_is_rfkill(priv))
  4898. return;
  4899. ieee80211_wake_queues(priv->hw);
  4900. priv->active_rate = priv->rates_mask;
  4901. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  4902. iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(priv->power_mode));
  4903. if (iwl3945_is_associated(priv)) {
  4904. struct iwl3945_rxon_cmd *active_rxon =
  4905. (struct iwl3945_rxon_cmd *)(&priv->active_rxon);
  4906. memcpy(&priv->staging_rxon, &priv->active_rxon,
  4907. sizeof(priv->staging_rxon));
  4908. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  4909. } else {
  4910. /* Initialize our rx_config data */
  4911. iwl3945_connection_init_rx_config(priv);
  4912. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  4913. }
  4914. /* Configure Bluetooth device coexistence support */
  4915. iwl3945_send_bt_config(priv);
  4916. /* Configure the adapter for unassociated operation */
  4917. iwl3945_commit_rxon(priv);
  4918. iwl3945_reg_txpower_periodic(priv);
  4919. iwl3945_led_register(priv);
  4920. IWL_DEBUG_INFO("ALIVE processing complete.\n");
  4921. set_bit(STATUS_READY, &priv->status);
  4922. wake_up_interruptible(&priv->wait_command_queue);
  4923. if (priv->error_recovering)
  4924. iwl3945_error_recovery(priv);
  4925. ieee80211_notify_mac(priv->hw, IEEE80211_NOTIFY_RE_ASSOC);
  4926. return;
  4927. restart:
  4928. queue_work(priv->workqueue, &priv->restart);
  4929. }
  4930. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv);
  4931. static void __iwl3945_down(struct iwl3945_priv *priv)
  4932. {
  4933. unsigned long flags;
  4934. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  4935. struct ieee80211_conf *conf = NULL;
  4936. IWL_DEBUG_INFO(DRV_NAME " is going down\n");
  4937. conf = ieee80211_get_hw_conf(priv->hw);
  4938. if (!exit_pending)
  4939. set_bit(STATUS_EXIT_PENDING, &priv->status);
  4940. iwl3945_led_unregister(priv);
  4941. iwl3945_clear_stations_table(priv);
  4942. /* Unblock any waiting calls */
  4943. wake_up_interruptible_all(&priv->wait_command_queue);
  4944. /* Wipe out the EXIT_PENDING status bit if we are not actually
  4945. * exiting the module */
  4946. if (!exit_pending)
  4947. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  4948. /* stop and reset the on-board processor */
  4949. iwl3945_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  4950. /* tell the device to stop sending interrupts */
  4951. spin_lock_irqsave(&priv->lock, flags);
  4952. iwl3945_disable_interrupts(priv);
  4953. spin_unlock_irqrestore(&priv->lock, flags);
  4954. iwl_synchronize_irq(priv);
  4955. if (priv->mac80211_registered)
  4956. ieee80211_stop_queues(priv->hw);
  4957. /* If we have not previously called iwl3945_init() then
  4958. * clear all bits but the RF Kill and SUSPEND bits and return */
  4959. if (!iwl3945_is_init(priv)) {
  4960. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4961. STATUS_RF_KILL_HW |
  4962. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4963. STATUS_RF_KILL_SW |
  4964. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4965. STATUS_GEO_CONFIGURED |
  4966. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4967. STATUS_IN_SUSPEND;
  4968. goto exit;
  4969. }
  4970. /* ...otherwise clear out all the status bits but the RF Kill and
  4971. * SUSPEND bits and continue taking the NIC down. */
  4972. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  4973. STATUS_RF_KILL_HW |
  4974. test_bit(STATUS_RF_KILL_SW, &priv->status) <<
  4975. STATUS_RF_KILL_SW |
  4976. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  4977. STATUS_GEO_CONFIGURED |
  4978. test_bit(STATUS_IN_SUSPEND, &priv->status) <<
  4979. STATUS_IN_SUSPEND |
  4980. test_bit(STATUS_FW_ERROR, &priv->status) <<
  4981. STATUS_FW_ERROR;
  4982. spin_lock_irqsave(&priv->lock, flags);
  4983. iwl3945_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  4984. spin_unlock_irqrestore(&priv->lock, flags);
  4985. iwl3945_hw_txq_ctx_stop(priv);
  4986. iwl3945_hw_rxq_stop(priv);
  4987. spin_lock_irqsave(&priv->lock, flags);
  4988. if (!iwl3945_grab_nic_access(priv)) {
  4989. iwl3945_write_prph(priv, APMG_CLK_DIS_REG,
  4990. APMG_CLK_VAL_DMA_CLK_RQT);
  4991. iwl3945_release_nic_access(priv);
  4992. }
  4993. spin_unlock_irqrestore(&priv->lock, flags);
  4994. udelay(5);
  4995. iwl3945_hw_nic_stop_master(priv);
  4996. iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  4997. iwl3945_hw_nic_reset(priv);
  4998. exit:
  4999. memset(&priv->card_alive, 0, sizeof(struct iwl3945_alive_resp));
  5000. if (priv->ibss_beacon)
  5001. dev_kfree_skb(priv->ibss_beacon);
  5002. priv->ibss_beacon = NULL;
  5003. /* clear out any free frames */
  5004. iwl3945_clear_free_frames(priv);
  5005. }
  5006. static void iwl3945_down(struct iwl3945_priv *priv)
  5007. {
  5008. mutex_lock(&priv->mutex);
  5009. __iwl3945_down(priv);
  5010. mutex_unlock(&priv->mutex);
  5011. iwl3945_cancel_deferred_work(priv);
  5012. }
  5013. #define MAX_HW_RESTARTS 5
  5014. static int __iwl3945_up(struct iwl3945_priv *priv)
  5015. {
  5016. int rc, i;
  5017. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5018. IWL_WARNING("Exit pending; will not bring the NIC up\n");
  5019. return -EIO;
  5020. }
  5021. if (test_bit(STATUS_RF_KILL_SW, &priv->status)) {
  5022. IWL_WARNING("Radio disabled by SW RF kill (module "
  5023. "parameter)\n");
  5024. return -ENODEV;
  5025. }
  5026. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  5027. IWL_ERROR("ucode not available for device bringup\n");
  5028. return -EIO;
  5029. }
  5030. /* If platform's RF_KILL switch is NOT set to KILL */
  5031. if (iwl3945_read32(priv, CSR_GP_CNTRL) &
  5032. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  5033. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  5034. else {
  5035. set_bit(STATUS_RF_KILL_HW, &priv->status);
  5036. if (!test_bit(STATUS_IN_SUSPEND, &priv->status)) {
  5037. IWL_WARNING("Radio disabled by HW RF Kill switch\n");
  5038. return -ENODEV;
  5039. }
  5040. }
  5041. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5042. rc = iwl3945_hw_nic_init(priv);
  5043. if (rc) {
  5044. IWL_ERROR("Unable to int nic\n");
  5045. return rc;
  5046. }
  5047. /* make sure rfkill handshake bits are cleared */
  5048. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5049. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  5050. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  5051. /* clear (again), then enable host interrupts */
  5052. iwl3945_write32(priv, CSR_INT, 0xFFFFFFFF);
  5053. iwl3945_enable_interrupts(priv);
  5054. /* really make sure rfkill handshake bits are cleared */
  5055. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5056. iwl3945_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  5057. /* Copy original ucode data image from disk into backup cache.
  5058. * This will be used to initialize the on-board processor's
  5059. * data SRAM for a clean start when the runtime program first loads. */
  5060. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  5061. priv->ucode_data.len);
  5062. /* We return success when we resume from suspend and rf_kill is on. */
  5063. if (test_bit(STATUS_RF_KILL_HW, &priv->status))
  5064. return 0;
  5065. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  5066. iwl3945_clear_stations_table(priv);
  5067. /* load bootstrap state machine,
  5068. * load bootstrap program into processor's memory,
  5069. * prepare to load the "initialize" uCode */
  5070. rc = iwl3945_load_bsm(priv);
  5071. if (rc) {
  5072. IWL_ERROR("Unable to set up bootstrap uCode: %d\n", rc);
  5073. continue;
  5074. }
  5075. /* start card; "initialize" will load runtime ucode */
  5076. iwl3945_nic_start(priv);
  5077. IWL_DEBUG_INFO(DRV_NAME " is coming up\n");
  5078. return 0;
  5079. }
  5080. set_bit(STATUS_EXIT_PENDING, &priv->status);
  5081. __iwl3945_down(priv);
  5082. /* tried to restart and config the device for as long as our
  5083. * patience could withstand */
  5084. IWL_ERROR("Unable to initialize device after %d attempts.\n", i);
  5085. return -EIO;
  5086. }
  5087. /*****************************************************************************
  5088. *
  5089. * Workqueue callbacks
  5090. *
  5091. *****************************************************************************/
  5092. static void iwl3945_bg_init_alive_start(struct work_struct *data)
  5093. {
  5094. struct iwl3945_priv *priv =
  5095. container_of(data, struct iwl3945_priv, init_alive_start.work);
  5096. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5097. return;
  5098. mutex_lock(&priv->mutex);
  5099. iwl3945_init_alive_start(priv);
  5100. mutex_unlock(&priv->mutex);
  5101. }
  5102. static void iwl3945_bg_alive_start(struct work_struct *data)
  5103. {
  5104. struct iwl3945_priv *priv =
  5105. container_of(data, struct iwl3945_priv, alive_start.work);
  5106. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5107. return;
  5108. mutex_lock(&priv->mutex);
  5109. iwl3945_alive_start(priv);
  5110. mutex_unlock(&priv->mutex);
  5111. }
  5112. static void iwl3945_bg_rf_kill(struct work_struct *work)
  5113. {
  5114. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, rf_kill);
  5115. wake_up_interruptible(&priv->wait_command_queue);
  5116. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5117. return;
  5118. mutex_lock(&priv->mutex);
  5119. if (!iwl3945_is_rfkill(priv)) {
  5120. IWL_DEBUG(IWL_DL_INFO | IWL_DL_RF_KILL,
  5121. "HW and/or SW RF Kill no longer active, restarting "
  5122. "device\n");
  5123. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5124. queue_work(priv->workqueue, &priv->restart);
  5125. } else {
  5126. if (!test_bit(STATUS_RF_KILL_HW, &priv->status))
  5127. IWL_DEBUG_RF_KILL("Can not turn radio back on - "
  5128. "disabled by SW switch\n");
  5129. else
  5130. IWL_WARNING("Radio Frequency Kill Switch is On:\n"
  5131. "Kill switch must be turned off for "
  5132. "wireless networking to work.\n");
  5133. }
  5134. mutex_unlock(&priv->mutex);
  5135. }
  5136. static void iwl3945_bg_set_monitor(struct work_struct *work)
  5137. {
  5138. struct iwl3945_priv *priv = container_of(work,
  5139. struct iwl3945_priv, set_monitor);
  5140. IWL_DEBUG(IWL_DL_STATE, "setting monitor mode\n");
  5141. mutex_lock(&priv->mutex);
  5142. if (!iwl3945_is_ready(priv))
  5143. IWL_DEBUG(IWL_DL_STATE, "leave - not ready\n");
  5144. else
  5145. if (iwl3945_set_mode(priv, IEEE80211_IF_TYPE_MNTR) != 0)
  5146. IWL_ERROR("iwl3945_set_mode() failed\n");
  5147. mutex_unlock(&priv->mutex);
  5148. }
  5149. #define IWL_SCAN_CHECK_WATCHDOG (7 * HZ)
  5150. static void iwl3945_bg_scan_check(struct work_struct *data)
  5151. {
  5152. struct iwl3945_priv *priv =
  5153. container_of(data, struct iwl3945_priv, scan_check.work);
  5154. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5155. return;
  5156. mutex_lock(&priv->mutex);
  5157. if (test_bit(STATUS_SCANNING, &priv->status) ||
  5158. test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5159. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN,
  5160. "Scan completion watchdog resetting adapter (%dms)\n",
  5161. jiffies_to_msecs(IWL_SCAN_CHECK_WATCHDOG));
  5162. if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
  5163. iwl3945_send_scan_abort(priv);
  5164. }
  5165. mutex_unlock(&priv->mutex);
  5166. }
  5167. static void iwl3945_bg_request_scan(struct work_struct *data)
  5168. {
  5169. struct iwl3945_priv *priv =
  5170. container_of(data, struct iwl3945_priv, request_scan);
  5171. struct iwl3945_host_cmd cmd = {
  5172. .id = REPLY_SCAN_CMD,
  5173. .len = sizeof(struct iwl3945_scan_cmd),
  5174. .meta.flags = CMD_SIZE_HUGE,
  5175. };
  5176. int rc = 0;
  5177. struct iwl3945_scan_cmd *scan;
  5178. struct ieee80211_conf *conf = NULL;
  5179. u8 direct_mask;
  5180. enum ieee80211_band band;
  5181. conf = ieee80211_get_hw_conf(priv->hw);
  5182. mutex_lock(&priv->mutex);
  5183. if (!iwl3945_is_ready(priv)) {
  5184. IWL_WARNING("request scan called when driver not ready.\n");
  5185. goto done;
  5186. }
  5187. /* Make sure the scan wasn't cancelled before this queued work
  5188. * was given the chance to run... */
  5189. if (!test_bit(STATUS_SCANNING, &priv->status))
  5190. goto done;
  5191. /* This should never be called or scheduled if there is currently
  5192. * a scan active in the hardware. */
  5193. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  5194. IWL_DEBUG_INFO("Multiple concurrent scan requests in parallel. "
  5195. "Ignoring second request.\n");
  5196. rc = -EIO;
  5197. goto done;
  5198. }
  5199. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  5200. IWL_DEBUG_SCAN("Aborting scan due to device shutdown\n");
  5201. goto done;
  5202. }
  5203. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  5204. IWL_DEBUG_HC("Scan request while abort pending. Queuing.\n");
  5205. goto done;
  5206. }
  5207. if (iwl3945_is_rfkill(priv)) {
  5208. IWL_DEBUG_HC("Aborting scan due to RF Kill activation\n");
  5209. goto done;
  5210. }
  5211. if (!test_bit(STATUS_READY, &priv->status)) {
  5212. IWL_DEBUG_HC("Scan request while uninitialized. Queuing.\n");
  5213. goto done;
  5214. }
  5215. if (!priv->scan_bands) {
  5216. IWL_DEBUG_HC("Aborting scan due to no requested bands\n");
  5217. goto done;
  5218. }
  5219. if (!priv->scan) {
  5220. priv->scan = kmalloc(sizeof(struct iwl3945_scan_cmd) +
  5221. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  5222. if (!priv->scan) {
  5223. rc = -ENOMEM;
  5224. goto done;
  5225. }
  5226. }
  5227. scan = priv->scan;
  5228. memset(scan, 0, sizeof(struct iwl3945_scan_cmd) + IWL_MAX_SCAN_SIZE);
  5229. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  5230. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  5231. if (iwl3945_is_associated(priv)) {
  5232. u16 interval = 0;
  5233. u32 extra;
  5234. u32 suspend_time = 100;
  5235. u32 scan_suspend_time = 100;
  5236. unsigned long flags;
  5237. IWL_DEBUG_INFO("Scanning while associated...\n");
  5238. spin_lock_irqsave(&priv->lock, flags);
  5239. interval = priv->beacon_int;
  5240. spin_unlock_irqrestore(&priv->lock, flags);
  5241. scan->suspend_time = 0;
  5242. scan->max_out_time = cpu_to_le32(200 * 1024);
  5243. if (!interval)
  5244. interval = suspend_time;
  5245. /*
  5246. * suspend time format:
  5247. * 0-19: beacon interval in usec (time before exec.)
  5248. * 20-23: 0
  5249. * 24-31: number of beacons (suspend between channels)
  5250. */
  5251. extra = (suspend_time / interval) << 24;
  5252. scan_suspend_time = 0xFF0FFFFF &
  5253. (extra | ((suspend_time % interval) * 1024));
  5254. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  5255. IWL_DEBUG_SCAN("suspend_time 0x%X beacon interval %d\n",
  5256. scan_suspend_time, interval);
  5257. }
  5258. /* We should add the ability for user to lock to PASSIVE ONLY */
  5259. if (priv->one_direct_scan) {
  5260. IWL_DEBUG_SCAN
  5261. ("Kicking off one direct scan for '%s'\n",
  5262. iwl3945_escape_essid(priv->direct_ssid,
  5263. priv->direct_ssid_len));
  5264. scan->direct_scan[0].id = WLAN_EID_SSID;
  5265. scan->direct_scan[0].len = priv->direct_ssid_len;
  5266. memcpy(scan->direct_scan[0].ssid,
  5267. priv->direct_ssid, priv->direct_ssid_len);
  5268. direct_mask = 1;
  5269. } else if (!iwl3945_is_associated(priv) && priv->essid_len) {
  5270. IWL_DEBUG_SCAN
  5271. ("Kicking off one direct scan for '%s' when not associated\n",
  5272. iwl3945_escape_essid(priv->essid, priv->essid_len));
  5273. scan->direct_scan[0].id = WLAN_EID_SSID;
  5274. scan->direct_scan[0].len = priv->essid_len;
  5275. memcpy(scan->direct_scan[0].ssid, priv->essid, priv->essid_len);
  5276. direct_mask = 1;
  5277. } else {
  5278. IWL_DEBUG_SCAN("Kicking off one indirect scan.\n");
  5279. direct_mask = 0;
  5280. }
  5281. /* We don't build a direct scan probe request; the uCode will do
  5282. * that based on the direct_mask added to each channel entry */
  5283. scan->tx_cmd.len = cpu_to_le16(
  5284. iwl3945_fill_probe_req(priv, (struct ieee80211_mgmt *)scan->data,
  5285. IWL_MAX_SCAN_SIZE - sizeof(*scan), 0));
  5286. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  5287. scan->tx_cmd.sta_id = priv->hw_setting.bcast_sta_id;
  5288. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  5289. /* flags + rate selection */
  5290. if (priv->scan_bands & BIT(IEEE80211_BAND_2GHZ)) {
  5291. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  5292. scan->tx_cmd.rate = IWL_RATE_1M_PLCP;
  5293. scan->good_CRC_th = 0;
  5294. band = IEEE80211_BAND_2GHZ;
  5295. } else if (priv->scan_bands & BIT(IEEE80211_BAND_5GHZ)) {
  5296. scan->tx_cmd.rate = IWL_RATE_6M_PLCP;
  5297. scan->good_CRC_th = IWL_GOOD_CRC_TH;
  5298. band = IEEE80211_BAND_5GHZ;
  5299. } else {
  5300. IWL_WARNING("Invalid scan band count\n");
  5301. goto done;
  5302. }
  5303. /* select Rx antennas */
  5304. scan->flags |= iwl3945_get_antenna_flags(priv);
  5305. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR)
  5306. scan->filter_flags = RXON_FILTER_PROMISC_MSK;
  5307. if (direct_mask)
  5308. scan->channel_count =
  5309. iwl3945_get_channels_for_scan(
  5310. priv, band, 1, /* active */
  5311. direct_mask,
  5312. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5313. else
  5314. scan->channel_count =
  5315. iwl3945_get_channels_for_scan(
  5316. priv, band, 0, /* passive */
  5317. direct_mask,
  5318. (void *)&scan->data[le16_to_cpu(scan->tx_cmd.len)]);
  5319. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  5320. scan->channel_count * sizeof(struct iwl3945_scan_channel);
  5321. cmd.data = scan;
  5322. scan->len = cpu_to_le16(cmd.len);
  5323. set_bit(STATUS_SCAN_HW, &priv->status);
  5324. rc = iwl3945_send_cmd_sync(priv, &cmd);
  5325. if (rc)
  5326. goto done;
  5327. queue_delayed_work(priv->workqueue, &priv->scan_check,
  5328. IWL_SCAN_CHECK_WATCHDOG);
  5329. mutex_unlock(&priv->mutex);
  5330. return;
  5331. done:
  5332. /* inform mac80211 scan aborted */
  5333. queue_work(priv->workqueue, &priv->scan_completed);
  5334. mutex_unlock(&priv->mutex);
  5335. }
  5336. static void iwl3945_bg_up(struct work_struct *data)
  5337. {
  5338. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, up);
  5339. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5340. return;
  5341. mutex_lock(&priv->mutex);
  5342. __iwl3945_up(priv);
  5343. mutex_unlock(&priv->mutex);
  5344. }
  5345. static void iwl3945_bg_restart(struct work_struct *data)
  5346. {
  5347. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv, restart);
  5348. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5349. return;
  5350. iwl3945_down(priv);
  5351. queue_work(priv->workqueue, &priv->up);
  5352. }
  5353. static void iwl3945_bg_rx_replenish(struct work_struct *data)
  5354. {
  5355. struct iwl3945_priv *priv =
  5356. container_of(data, struct iwl3945_priv, rx_replenish);
  5357. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5358. return;
  5359. mutex_lock(&priv->mutex);
  5360. iwl3945_rx_replenish(priv);
  5361. mutex_unlock(&priv->mutex);
  5362. }
  5363. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  5364. static void iwl3945_bg_post_associate(struct work_struct *data)
  5365. {
  5366. struct iwl3945_priv *priv = container_of(data, struct iwl3945_priv,
  5367. post_associate.work);
  5368. int rc = 0;
  5369. struct ieee80211_conf *conf = NULL;
  5370. DECLARE_MAC_BUF(mac);
  5371. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5372. IWL_ERROR("%s Should not be called in AP mode\n", __FUNCTION__);
  5373. return;
  5374. }
  5375. IWL_DEBUG_ASSOC("Associated as %d to: %s\n",
  5376. priv->assoc_id,
  5377. print_mac(mac, priv->active_rxon.bssid_addr));
  5378. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5379. return;
  5380. mutex_lock(&priv->mutex);
  5381. if (!priv->vif || !priv->is_open) {
  5382. mutex_unlock(&priv->mutex);
  5383. return;
  5384. }
  5385. iwl3945_scan_cancel_timeout(priv, 200);
  5386. conf = ieee80211_get_hw_conf(priv->hw);
  5387. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5388. iwl3945_commit_rxon(priv);
  5389. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5390. iwl3945_setup_rxon_timing(priv);
  5391. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5392. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5393. if (rc)
  5394. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5395. "Attempting to continue.\n");
  5396. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5397. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5398. IWL_DEBUG_ASSOC("assoc id %d beacon interval %d\n",
  5399. priv->assoc_id, priv->beacon_int);
  5400. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5401. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  5402. else
  5403. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5404. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5405. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5406. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  5407. else
  5408. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5409. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5410. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  5411. }
  5412. iwl3945_commit_rxon(priv);
  5413. switch (priv->iw_mode) {
  5414. case IEEE80211_IF_TYPE_STA:
  5415. iwl3945_rate_scale_init(priv->hw, IWL_AP_ID);
  5416. break;
  5417. case IEEE80211_IF_TYPE_IBSS:
  5418. /* clear out the station table */
  5419. iwl3945_clear_stations_table(priv);
  5420. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5421. iwl3945_add_station(priv, priv->bssid, 0, 0);
  5422. iwl3945_sync_sta(priv, IWL_STA_ID,
  5423. (priv->band == IEEE80211_BAND_5GHZ) ?
  5424. IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP,
  5425. CMD_ASYNC);
  5426. iwl3945_rate_scale_init(priv->hw, IWL_STA_ID);
  5427. iwl3945_send_beacon_cmd(priv);
  5428. break;
  5429. default:
  5430. IWL_ERROR("%s Should not be called in %d mode\n",
  5431. __FUNCTION__, priv->iw_mode);
  5432. break;
  5433. }
  5434. iwl3945_sequence_reset(priv);
  5435. iwl3945_activate_qos(priv, 0);
  5436. /* we have just associated, don't start scan too early */
  5437. priv->next_scan_jiffies = jiffies + IWL_DELAY_NEXT_SCAN;
  5438. mutex_unlock(&priv->mutex);
  5439. }
  5440. static void iwl3945_bg_abort_scan(struct work_struct *work)
  5441. {
  5442. struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv, abort_scan);
  5443. if (!iwl3945_is_ready(priv))
  5444. return;
  5445. mutex_lock(&priv->mutex);
  5446. set_bit(STATUS_SCAN_ABORTING, &priv->status);
  5447. iwl3945_send_scan_abort(priv);
  5448. mutex_unlock(&priv->mutex);
  5449. }
  5450. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf);
  5451. static void iwl3945_bg_scan_completed(struct work_struct *work)
  5452. {
  5453. struct iwl3945_priv *priv =
  5454. container_of(work, struct iwl3945_priv, scan_completed);
  5455. IWL_DEBUG(IWL_DL_INFO | IWL_DL_SCAN, "SCAN complete scan\n");
  5456. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5457. return;
  5458. if (test_bit(STATUS_CONF_PENDING, &priv->status))
  5459. iwl3945_mac_config(priv->hw, ieee80211_get_hw_conf(priv->hw));
  5460. ieee80211_scan_completed(priv->hw);
  5461. /* Since setting the TXPOWER may have been deferred while
  5462. * performing the scan, fire one off */
  5463. mutex_lock(&priv->mutex);
  5464. iwl3945_hw_reg_send_txpower(priv);
  5465. mutex_unlock(&priv->mutex);
  5466. }
  5467. /*****************************************************************************
  5468. *
  5469. * mac80211 entry point functions
  5470. *
  5471. *****************************************************************************/
  5472. #define UCODE_READY_TIMEOUT (2 * HZ)
  5473. static int iwl3945_mac_start(struct ieee80211_hw *hw)
  5474. {
  5475. struct iwl3945_priv *priv = hw->priv;
  5476. int ret;
  5477. IWL_DEBUG_MAC80211("enter\n");
  5478. if (pci_enable_device(priv->pci_dev)) {
  5479. IWL_ERROR("Fail to pci_enable_device\n");
  5480. return -ENODEV;
  5481. }
  5482. pci_restore_state(priv->pci_dev);
  5483. pci_enable_msi(priv->pci_dev);
  5484. ret = request_irq(priv->pci_dev->irq, iwl3945_isr, IRQF_SHARED,
  5485. DRV_NAME, priv);
  5486. if (ret) {
  5487. IWL_ERROR("Error allocating IRQ %d\n", priv->pci_dev->irq);
  5488. goto out_disable_msi;
  5489. }
  5490. /* we should be verifying the device is ready to be opened */
  5491. mutex_lock(&priv->mutex);
  5492. memset(&priv->staging_rxon, 0, sizeof(struct iwl3945_rxon_cmd));
  5493. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  5494. * ucode filename and max sizes are card-specific. */
  5495. if (!priv->ucode_code.len) {
  5496. ret = iwl3945_read_ucode(priv);
  5497. if (ret) {
  5498. IWL_ERROR("Could not read microcode: %d\n", ret);
  5499. mutex_unlock(&priv->mutex);
  5500. goto out_release_irq;
  5501. }
  5502. }
  5503. ret = __iwl3945_up(priv);
  5504. mutex_unlock(&priv->mutex);
  5505. if (ret)
  5506. goto out_release_irq;
  5507. IWL_DEBUG_INFO("Start UP work.\n");
  5508. if (test_bit(STATUS_IN_SUSPEND, &priv->status))
  5509. return 0;
  5510. /* Wait for START_ALIVE from ucode. Otherwise callbacks from
  5511. * mac80211 will not be run successfully. */
  5512. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  5513. test_bit(STATUS_READY, &priv->status),
  5514. UCODE_READY_TIMEOUT);
  5515. if (!ret) {
  5516. if (!test_bit(STATUS_READY, &priv->status)) {
  5517. IWL_ERROR("Wait for START_ALIVE timeout after %dms.\n",
  5518. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  5519. ret = -ETIMEDOUT;
  5520. goto out_release_irq;
  5521. }
  5522. }
  5523. priv->is_open = 1;
  5524. IWL_DEBUG_MAC80211("leave\n");
  5525. return 0;
  5526. out_release_irq:
  5527. free_irq(priv->pci_dev->irq, priv);
  5528. out_disable_msi:
  5529. pci_disable_msi(priv->pci_dev);
  5530. pci_disable_device(priv->pci_dev);
  5531. priv->is_open = 0;
  5532. IWL_DEBUG_MAC80211("leave - failed\n");
  5533. return ret;
  5534. }
  5535. static void iwl3945_mac_stop(struct ieee80211_hw *hw)
  5536. {
  5537. struct iwl3945_priv *priv = hw->priv;
  5538. IWL_DEBUG_MAC80211("enter\n");
  5539. if (!priv->is_open) {
  5540. IWL_DEBUG_MAC80211("leave - skip\n");
  5541. return;
  5542. }
  5543. priv->is_open = 0;
  5544. if (iwl3945_is_ready_rf(priv)) {
  5545. /* stop mac, cancel any scan request and clear
  5546. * RXON_FILTER_ASSOC_MSK BIT
  5547. */
  5548. mutex_lock(&priv->mutex);
  5549. iwl3945_scan_cancel_timeout(priv, 100);
  5550. cancel_delayed_work(&priv->post_associate);
  5551. mutex_unlock(&priv->mutex);
  5552. }
  5553. iwl3945_down(priv);
  5554. flush_workqueue(priv->workqueue);
  5555. free_irq(priv->pci_dev->irq, priv);
  5556. pci_disable_msi(priv->pci_dev);
  5557. pci_save_state(priv->pci_dev);
  5558. pci_disable_device(priv->pci_dev);
  5559. IWL_DEBUG_MAC80211("leave\n");
  5560. }
  5561. static int iwl3945_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  5562. {
  5563. struct iwl3945_priv *priv = hw->priv;
  5564. IWL_DEBUG_MAC80211("enter\n");
  5565. if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
  5566. IWL_DEBUG_MAC80211("leave - monitor\n");
  5567. return -1;
  5568. }
  5569. IWL_DEBUG_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  5570. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  5571. if (iwl3945_tx_skb(priv, skb))
  5572. dev_kfree_skb_any(skb);
  5573. IWL_DEBUG_MAC80211("leave\n");
  5574. return 0;
  5575. }
  5576. static int iwl3945_mac_add_interface(struct ieee80211_hw *hw,
  5577. struct ieee80211_if_init_conf *conf)
  5578. {
  5579. struct iwl3945_priv *priv = hw->priv;
  5580. unsigned long flags;
  5581. DECLARE_MAC_BUF(mac);
  5582. IWL_DEBUG_MAC80211("enter: type %d\n", conf->type);
  5583. if (priv->vif) {
  5584. IWL_DEBUG_MAC80211("leave - vif != NULL\n");
  5585. return -EOPNOTSUPP;
  5586. }
  5587. spin_lock_irqsave(&priv->lock, flags);
  5588. priv->vif = conf->vif;
  5589. spin_unlock_irqrestore(&priv->lock, flags);
  5590. mutex_lock(&priv->mutex);
  5591. if (conf->mac_addr) {
  5592. IWL_DEBUG_MAC80211("Set: %s\n", print_mac(mac, conf->mac_addr));
  5593. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  5594. }
  5595. if (iwl3945_is_ready(priv))
  5596. iwl3945_set_mode(priv, conf->type);
  5597. mutex_unlock(&priv->mutex);
  5598. IWL_DEBUG_MAC80211("leave\n");
  5599. return 0;
  5600. }
  5601. /**
  5602. * iwl3945_mac_config - mac80211 config callback
  5603. *
  5604. * We ignore conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME since it seems to
  5605. * be set inappropriately and the driver currently sets the hardware up to
  5606. * use it whenever needed.
  5607. */
  5608. static int iwl3945_mac_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
  5609. {
  5610. struct iwl3945_priv *priv = hw->priv;
  5611. const struct iwl3945_channel_info *ch_info;
  5612. unsigned long flags;
  5613. int ret = 0;
  5614. mutex_lock(&priv->mutex);
  5615. IWL_DEBUG_MAC80211("enter to channel %d\n", conf->channel->hw_value);
  5616. priv->add_radiotap = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
  5617. if (!iwl3945_is_ready(priv)) {
  5618. IWL_DEBUG_MAC80211("leave - not ready\n");
  5619. ret = -EIO;
  5620. goto out;
  5621. }
  5622. if (unlikely(!iwl3945_param_disable_hw_scan &&
  5623. test_bit(STATUS_SCANNING, &priv->status))) {
  5624. IWL_DEBUG_MAC80211("leave - scanning\n");
  5625. set_bit(STATUS_CONF_PENDING, &priv->status);
  5626. mutex_unlock(&priv->mutex);
  5627. return 0;
  5628. }
  5629. spin_lock_irqsave(&priv->lock, flags);
  5630. ch_info = iwl3945_get_channel_info(priv, conf->channel->band,
  5631. conf->channel->hw_value);
  5632. if (!is_channel_valid(ch_info)) {
  5633. IWL_DEBUG_SCAN("Channel %d [%d] is INVALID for this band.\n",
  5634. conf->channel->hw_value, conf->channel->band);
  5635. IWL_DEBUG_MAC80211("leave - invalid channel\n");
  5636. spin_unlock_irqrestore(&priv->lock, flags);
  5637. ret = -EINVAL;
  5638. goto out;
  5639. }
  5640. iwl3945_set_rxon_channel(priv, conf->channel->band, conf->channel->hw_value);
  5641. iwl3945_set_flags_for_phymode(priv, conf->channel->band);
  5642. /* The list of supported rates and rate mask can be different
  5643. * for each phymode; since the phymode may have changed, reset
  5644. * the rate mask to what mac80211 lists */
  5645. iwl3945_set_rate(priv);
  5646. spin_unlock_irqrestore(&priv->lock, flags);
  5647. #ifdef IEEE80211_CONF_CHANNEL_SWITCH
  5648. if (conf->flags & IEEE80211_CONF_CHANNEL_SWITCH) {
  5649. iwl3945_hw_channel_switch(priv, conf->channel);
  5650. goto out;
  5651. }
  5652. #endif
  5653. iwl3945_radio_kill_sw(priv, !conf->radio_enabled);
  5654. if (!conf->radio_enabled) {
  5655. IWL_DEBUG_MAC80211("leave - radio disabled\n");
  5656. goto out;
  5657. }
  5658. if (iwl3945_is_rfkill(priv)) {
  5659. IWL_DEBUG_MAC80211("leave - RF kill\n");
  5660. ret = -EIO;
  5661. goto out;
  5662. }
  5663. iwl3945_set_rate(priv);
  5664. if (memcmp(&priv->active_rxon,
  5665. &priv->staging_rxon, sizeof(priv->staging_rxon)))
  5666. iwl3945_commit_rxon(priv);
  5667. else
  5668. IWL_DEBUG_INFO("No re-sending same RXON configuration.\n");
  5669. IWL_DEBUG_MAC80211("leave\n");
  5670. out:
  5671. clear_bit(STATUS_CONF_PENDING, &priv->status);
  5672. mutex_unlock(&priv->mutex);
  5673. return ret;
  5674. }
  5675. static void iwl3945_config_ap(struct iwl3945_priv *priv)
  5676. {
  5677. int rc = 0;
  5678. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  5679. return;
  5680. /* The following should be done only at AP bring up */
  5681. if ((priv->active_rxon.filter_flags & RXON_FILTER_ASSOC_MSK) == 0) {
  5682. /* RXON - unassoc (to set timing command) */
  5683. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5684. iwl3945_commit_rxon(priv);
  5685. /* RXON Timing */
  5686. memset(&priv->rxon_timing, 0, sizeof(struct iwl3945_rxon_time_cmd));
  5687. iwl3945_setup_rxon_timing(priv);
  5688. rc = iwl3945_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  5689. sizeof(priv->rxon_timing), &priv->rxon_timing);
  5690. if (rc)
  5691. IWL_WARNING("REPLY_RXON_TIMING failed - "
  5692. "Attempting to continue.\n");
  5693. /* FIXME: what should be the assoc_id for AP? */
  5694. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  5695. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  5696. priv->staging_rxon.flags |=
  5697. RXON_FLG_SHORT_PREAMBLE_MSK;
  5698. else
  5699. priv->staging_rxon.flags &=
  5700. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  5701. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  5702. if (priv->assoc_capability &
  5703. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  5704. priv->staging_rxon.flags |=
  5705. RXON_FLG_SHORT_SLOT_MSK;
  5706. else
  5707. priv->staging_rxon.flags &=
  5708. ~RXON_FLG_SHORT_SLOT_MSK;
  5709. if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
  5710. priv->staging_rxon.flags &=
  5711. ~RXON_FLG_SHORT_SLOT_MSK;
  5712. }
  5713. /* restore RXON assoc */
  5714. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  5715. iwl3945_commit_rxon(priv);
  5716. iwl3945_add_station(priv, iwl3945_broadcast_addr, 0, 0);
  5717. }
  5718. iwl3945_send_beacon_cmd(priv);
  5719. /* FIXME - we need to add code here to detect a totally new
  5720. * configuration, reset the AP, unassoc, rxon timing, assoc,
  5721. * clear sta table, add BCAST sta... */
  5722. }
  5723. static int iwl3945_mac_config_interface(struct ieee80211_hw *hw,
  5724. struct ieee80211_vif *vif,
  5725. struct ieee80211_if_conf *conf)
  5726. {
  5727. struct iwl3945_priv *priv = hw->priv;
  5728. DECLARE_MAC_BUF(mac);
  5729. unsigned long flags;
  5730. int rc;
  5731. if (conf == NULL)
  5732. return -EIO;
  5733. if (priv->vif != vif) {
  5734. IWL_DEBUG_MAC80211("leave - priv->vif != vif\n");
  5735. return 0;
  5736. }
  5737. /* XXX: this MUST use conf->mac_addr */
  5738. if ((priv->iw_mode == IEEE80211_IF_TYPE_AP) &&
  5739. (!conf->beacon || !conf->ssid_len)) {
  5740. IWL_DEBUG_MAC80211
  5741. ("Leaving in AP mode because HostAPD is not ready.\n");
  5742. return 0;
  5743. }
  5744. if (!iwl3945_is_alive(priv))
  5745. return -EAGAIN;
  5746. mutex_lock(&priv->mutex);
  5747. if (conf->bssid)
  5748. IWL_DEBUG_MAC80211("bssid: %s\n",
  5749. print_mac(mac, conf->bssid));
  5750. /*
  5751. * very dubious code was here; the probe filtering flag is never set:
  5752. *
  5753. if (unlikely(test_bit(STATUS_SCANNING, &priv->status)) &&
  5754. !(priv->hw->flags & IEEE80211_HW_NO_PROBE_FILTERING)) {
  5755. */
  5756. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
  5757. if (!conf->bssid) {
  5758. conf->bssid = priv->mac_addr;
  5759. memcpy(priv->bssid, priv->mac_addr, ETH_ALEN);
  5760. IWL_DEBUG_MAC80211("bssid was set to: %s\n",
  5761. print_mac(mac, conf->bssid));
  5762. }
  5763. if (priv->ibss_beacon)
  5764. dev_kfree_skb(priv->ibss_beacon);
  5765. priv->ibss_beacon = conf->beacon;
  5766. }
  5767. if (iwl3945_is_rfkill(priv))
  5768. goto done;
  5769. if (conf->bssid && !is_zero_ether_addr(conf->bssid) &&
  5770. !is_multicast_ether_addr(conf->bssid)) {
  5771. /* If there is currently a HW scan going on in the background
  5772. * then we need to cancel it else the RXON below will fail. */
  5773. if (iwl3945_scan_cancel_timeout(priv, 100)) {
  5774. IWL_WARNING("Aborted scan still in progress "
  5775. "after 100ms\n");
  5776. IWL_DEBUG_MAC80211("leaving - scan abort failed.\n");
  5777. mutex_unlock(&priv->mutex);
  5778. return -EAGAIN;
  5779. }
  5780. memcpy(priv->staging_rxon.bssid_addr, conf->bssid, ETH_ALEN);
  5781. /* TODO: Audit driver for usage of these members and see
  5782. * if mac80211 deprecates them (priv->bssid looks like it
  5783. * shouldn't be there, but I haven't scanned the IBSS code
  5784. * to verify) - jpk */
  5785. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  5786. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5787. iwl3945_config_ap(priv);
  5788. else {
  5789. rc = iwl3945_commit_rxon(priv);
  5790. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA) && rc)
  5791. iwl3945_add_station(priv,
  5792. priv->active_rxon.bssid_addr, 1, 0);
  5793. }
  5794. } else {
  5795. iwl3945_scan_cancel_timeout(priv, 100);
  5796. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5797. iwl3945_commit_rxon(priv);
  5798. }
  5799. done:
  5800. spin_lock_irqsave(&priv->lock, flags);
  5801. if (!conf->ssid_len)
  5802. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5803. else
  5804. memcpy(priv->essid, conf->ssid, conf->ssid_len);
  5805. priv->essid_len = conf->ssid_len;
  5806. spin_unlock_irqrestore(&priv->lock, flags);
  5807. IWL_DEBUG_MAC80211("leave\n");
  5808. mutex_unlock(&priv->mutex);
  5809. return 0;
  5810. }
  5811. static void iwl3945_configure_filter(struct ieee80211_hw *hw,
  5812. unsigned int changed_flags,
  5813. unsigned int *total_flags,
  5814. int mc_count, struct dev_addr_list *mc_list)
  5815. {
  5816. /*
  5817. * XXX: dummy
  5818. * see also iwl3945_connection_init_rx_config
  5819. */
  5820. struct iwl3945_priv *priv = hw->priv;
  5821. int new_flags = 0;
  5822. if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  5823. if (*total_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
  5824. IWL_DEBUG_MAC80211("Enter: type %d (0x%x, 0x%x)\n",
  5825. IEEE80211_IF_TYPE_MNTR,
  5826. changed_flags, *total_flags);
  5827. /* queue work 'cuz mac80211 is holding a lock which
  5828. * prevents us from issuing (synchronous) f/w cmds */
  5829. queue_work(priv->workqueue, &priv->set_monitor);
  5830. new_flags &= FIF_PROMISC_IN_BSS |
  5831. FIF_OTHER_BSS |
  5832. FIF_ALLMULTI;
  5833. }
  5834. }
  5835. *total_flags = new_flags;
  5836. }
  5837. static void iwl3945_mac_remove_interface(struct ieee80211_hw *hw,
  5838. struct ieee80211_if_init_conf *conf)
  5839. {
  5840. struct iwl3945_priv *priv = hw->priv;
  5841. IWL_DEBUG_MAC80211("enter\n");
  5842. mutex_lock(&priv->mutex);
  5843. if (iwl3945_is_ready_rf(priv)) {
  5844. iwl3945_scan_cancel_timeout(priv, 100);
  5845. cancel_delayed_work(&priv->post_associate);
  5846. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  5847. iwl3945_commit_rxon(priv);
  5848. }
  5849. if (priv->vif == conf->vif) {
  5850. priv->vif = NULL;
  5851. memset(priv->bssid, 0, ETH_ALEN);
  5852. memset(priv->essid, 0, IW_ESSID_MAX_SIZE);
  5853. priv->essid_len = 0;
  5854. }
  5855. mutex_unlock(&priv->mutex);
  5856. IWL_DEBUG_MAC80211("leave\n");
  5857. }
  5858. static int iwl3945_mac_hw_scan(struct ieee80211_hw *hw, u8 *ssid, size_t len)
  5859. {
  5860. int rc = 0;
  5861. unsigned long flags;
  5862. struct iwl3945_priv *priv = hw->priv;
  5863. IWL_DEBUG_MAC80211("enter\n");
  5864. mutex_lock(&priv->mutex);
  5865. spin_lock_irqsave(&priv->lock, flags);
  5866. if (!iwl3945_is_ready_rf(priv)) {
  5867. rc = -EIO;
  5868. IWL_DEBUG_MAC80211("leave - not ready or exit pending\n");
  5869. goto out_unlock;
  5870. }
  5871. if (priv->iw_mode == IEEE80211_IF_TYPE_AP) { /* APs don't scan */
  5872. rc = -EIO;
  5873. IWL_ERROR("ERROR: APs don't scan\n");
  5874. goto out_unlock;
  5875. }
  5876. /* we don't schedule scan within next_scan_jiffies period */
  5877. if (priv->next_scan_jiffies &&
  5878. time_after(priv->next_scan_jiffies, jiffies)) {
  5879. rc = -EAGAIN;
  5880. goto out_unlock;
  5881. }
  5882. /* if we just finished scan ask for delay for a broadcast scan */
  5883. if ((len == 0) && priv->last_scan_jiffies &&
  5884. time_after(priv->last_scan_jiffies + IWL_DELAY_NEXT_SCAN,
  5885. jiffies)) {
  5886. rc = -EAGAIN;
  5887. goto out_unlock;
  5888. }
  5889. if (len) {
  5890. IWL_DEBUG_SCAN("direct scan for %s [%d]\n ",
  5891. iwl3945_escape_essid(ssid, len), (int)len);
  5892. priv->one_direct_scan = 1;
  5893. priv->direct_ssid_len = (u8)
  5894. min((u8) len, (u8) IW_ESSID_MAX_SIZE);
  5895. memcpy(priv->direct_ssid, ssid, priv->direct_ssid_len);
  5896. } else
  5897. priv->one_direct_scan = 0;
  5898. rc = iwl3945_scan_initiate(priv);
  5899. IWL_DEBUG_MAC80211("leave\n");
  5900. out_unlock:
  5901. spin_unlock_irqrestore(&priv->lock, flags);
  5902. mutex_unlock(&priv->mutex);
  5903. return rc;
  5904. }
  5905. static int iwl3945_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  5906. const u8 *local_addr, const u8 *addr,
  5907. struct ieee80211_key_conf *key)
  5908. {
  5909. struct iwl3945_priv *priv = hw->priv;
  5910. int rc = 0;
  5911. u8 sta_id;
  5912. IWL_DEBUG_MAC80211("enter\n");
  5913. if (!iwl3945_param_hwcrypto) {
  5914. IWL_DEBUG_MAC80211("leave - hwcrypto disabled\n");
  5915. return -EOPNOTSUPP;
  5916. }
  5917. if (is_zero_ether_addr(addr))
  5918. /* only support pairwise keys */
  5919. return -EOPNOTSUPP;
  5920. sta_id = iwl3945_hw_find_station(priv, addr);
  5921. if (sta_id == IWL_INVALID_STATION) {
  5922. DECLARE_MAC_BUF(mac);
  5923. IWL_DEBUG_MAC80211("leave - %s not in station map.\n",
  5924. print_mac(mac, addr));
  5925. return -EINVAL;
  5926. }
  5927. mutex_lock(&priv->mutex);
  5928. iwl3945_scan_cancel_timeout(priv, 100);
  5929. switch (cmd) {
  5930. case SET_KEY:
  5931. rc = iwl3945_update_sta_key_info(priv, key, sta_id);
  5932. if (!rc) {
  5933. iwl3945_set_rxon_hwcrypto(priv, 1);
  5934. iwl3945_commit_rxon(priv);
  5935. key->hw_key_idx = sta_id;
  5936. IWL_DEBUG_MAC80211("set_key success, using hwcrypto\n");
  5937. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  5938. }
  5939. break;
  5940. case DISABLE_KEY:
  5941. rc = iwl3945_clear_sta_key_info(priv, sta_id);
  5942. if (!rc) {
  5943. iwl3945_set_rxon_hwcrypto(priv, 0);
  5944. iwl3945_commit_rxon(priv);
  5945. IWL_DEBUG_MAC80211("disable hwcrypto key\n");
  5946. }
  5947. break;
  5948. default:
  5949. rc = -EINVAL;
  5950. }
  5951. IWL_DEBUG_MAC80211("leave\n");
  5952. mutex_unlock(&priv->mutex);
  5953. return rc;
  5954. }
  5955. static int iwl3945_mac_conf_tx(struct ieee80211_hw *hw, u16 queue,
  5956. const struct ieee80211_tx_queue_params *params)
  5957. {
  5958. struct iwl3945_priv *priv = hw->priv;
  5959. unsigned long flags;
  5960. int q;
  5961. IWL_DEBUG_MAC80211("enter\n");
  5962. if (!iwl3945_is_ready_rf(priv)) {
  5963. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  5964. return -EIO;
  5965. }
  5966. if (queue >= AC_NUM) {
  5967. IWL_DEBUG_MAC80211("leave - queue >= AC_NUM %d\n", queue);
  5968. return 0;
  5969. }
  5970. if (!priv->qos_data.qos_enable) {
  5971. priv->qos_data.qos_active = 0;
  5972. IWL_DEBUG_MAC80211("leave - qos not enabled\n");
  5973. return 0;
  5974. }
  5975. q = AC_NUM - 1 - queue;
  5976. spin_lock_irqsave(&priv->lock, flags);
  5977. priv->qos_data.def_qos_parm.ac[q].cw_min = cpu_to_le16(params->cw_min);
  5978. priv->qos_data.def_qos_parm.ac[q].cw_max = cpu_to_le16(params->cw_max);
  5979. priv->qos_data.def_qos_parm.ac[q].aifsn = params->aifs;
  5980. priv->qos_data.def_qos_parm.ac[q].edca_txop =
  5981. cpu_to_le16((params->txop * 32));
  5982. priv->qos_data.def_qos_parm.ac[q].reserved1 = 0;
  5983. priv->qos_data.qos_active = 1;
  5984. spin_unlock_irqrestore(&priv->lock, flags);
  5985. mutex_lock(&priv->mutex);
  5986. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  5987. iwl3945_activate_qos(priv, 1);
  5988. else if (priv->assoc_id && iwl3945_is_associated(priv))
  5989. iwl3945_activate_qos(priv, 0);
  5990. mutex_unlock(&priv->mutex);
  5991. IWL_DEBUG_MAC80211("leave\n");
  5992. return 0;
  5993. }
  5994. static int iwl3945_mac_get_tx_stats(struct ieee80211_hw *hw,
  5995. struct ieee80211_tx_queue_stats *stats)
  5996. {
  5997. struct iwl3945_priv *priv = hw->priv;
  5998. int i, avail;
  5999. struct iwl3945_tx_queue *txq;
  6000. struct iwl3945_queue *q;
  6001. unsigned long flags;
  6002. IWL_DEBUG_MAC80211("enter\n");
  6003. if (!iwl3945_is_ready_rf(priv)) {
  6004. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6005. return -EIO;
  6006. }
  6007. spin_lock_irqsave(&priv->lock, flags);
  6008. for (i = 0; i < AC_NUM; i++) {
  6009. txq = &priv->txq[i];
  6010. q = &txq->q;
  6011. avail = iwl3945_queue_space(q);
  6012. stats[i].len = q->n_window - avail;
  6013. stats[i].limit = q->n_window - q->high_mark;
  6014. stats[i].count = q->n_window;
  6015. }
  6016. spin_unlock_irqrestore(&priv->lock, flags);
  6017. IWL_DEBUG_MAC80211("leave\n");
  6018. return 0;
  6019. }
  6020. static int iwl3945_mac_get_stats(struct ieee80211_hw *hw,
  6021. struct ieee80211_low_level_stats *stats)
  6022. {
  6023. IWL_DEBUG_MAC80211("enter\n");
  6024. IWL_DEBUG_MAC80211("leave\n");
  6025. return 0;
  6026. }
  6027. static u64 iwl3945_mac_get_tsf(struct ieee80211_hw *hw)
  6028. {
  6029. IWL_DEBUG_MAC80211("enter\n");
  6030. IWL_DEBUG_MAC80211("leave\n");
  6031. return 0;
  6032. }
  6033. static void iwl3945_mac_reset_tsf(struct ieee80211_hw *hw)
  6034. {
  6035. struct iwl3945_priv *priv = hw->priv;
  6036. unsigned long flags;
  6037. mutex_lock(&priv->mutex);
  6038. IWL_DEBUG_MAC80211("enter\n");
  6039. iwl3945_reset_qos(priv);
  6040. cancel_delayed_work(&priv->post_associate);
  6041. spin_lock_irqsave(&priv->lock, flags);
  6042. priv->assoc_id = 0;
  6043. priv->assoc_capability = 0;
  6044. priv->call_post_assoc_from_beacon = 0;
  6045. /* new association get rid of ibss beacon skb */
  6046. if (priv->ibss_beacon)
  6047. dev_kfree_skb(priv->ibss_beacon);
  6048. priv->ibss_beacon = NULL;
  6049. priv->beacon_int = priv->hw->conf.beacon_int;
  6050. priv->timestamp1 = 0;
  6051. priv->timestamp0 = 0;
  6052. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA))
  6053. priv->beacon_int = 0;
  6054. spin_unlock_irqrestore(&priv->lock, flags);
  6055. if (!iwl3945_is_ready_rf(priv)) {
  6056. IWL_DEBUG_MAC80211("leave - not ready\n");
  6057. mutex_unlock(&priv->mutex);
  6058. return;
  6059. }
  6060. /* we are restarting association process
  6061. * clear RXON_FILTER_ASSOC_MSK bit
  6062. */
  6063. if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
  6064. iwl3945_scan_cancel_timeout(priv, 100);
  6065. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  6066. iwl3945_commit_rxon(priv);
  6067. }
  6068. /* Per mac80211.h: This is only used in IBSS mode... */
  6069. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6070. IWL_DEBUG_MAC80211("leave - not in IBSS\n");
  6071. mutex_unlock(&priv->mutex);
  6072. return;
  6073. }
  6074. iwl3945_set_rate(priv);
  6075. mutex_unlock(&priv->mutex);
  6076. IWL_DEBUG_MAC80211("leave\n");
  6077. }
  6078. static int iwl3945_mac_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
  6079. {
  6080. struct iwl3945_priv *priv = hw->priv;
  6081. unsigned long flags;
  6082. mutex_lock(&priv->mutex);
  6083. IWL_DEBUG_MAC80211("enter\n");
  6084. if (!iwl3945_is_ready_rf(priv)) {
  6085. IWL_DEBUG_MAC80211("leave - RF not ready\n");
  6086. mutex_unlock(&priv->mutex);
  6087. return -EIO;
  6088. }
  6089. if (priv->iw_mode != IEEE80211_IF_TYPE_IBSS) {
  6090. IWL_DEBUG_MAC80211("leave - not IBSS\n");
  6091. mutex_unlock(&priv->mutex);
  6092. return -EIO;
  6093. }
  6094. spin_lock_irqsave(&priv->lock, flags);
  6095. if (priv->ibss_beacon)
  6096. dev_kfree_skb(priv->ibss_beacon);
  6097. priv->ibss_beacon = skb;
  6098. priv->assoc_id = 0;
  6099. IWL_DEBUG_MAC80211("leave\n");
  6100. spin_unlock_irqrestore(&priv->lock, flags);
  6101. iwl3945_reset_qos(priv);
  6102. queue_work(priv->workqueue, &priv->post_associate.work);
  6103. mutex_unlock(&priv->mutex);
  6104. return 0;
  6105. }
  6106. /*****************************************************************************
  6107. *
  6108. * sysfs attributes
  6109. *
  6110. *****************************************************************************/
  6111. #ifdef CONFIG_IWL3945_DEBUG
  6112. /*
  6113. * The following adds a new attribute to the sysfs representation
  6114. * of this device driver (i.e. a new file in /sys/bus/pci/drivers/iwl/)
  6115. * used for controlling the debug level.
  6116. *
  6117. * See the level definitions in iwl for details.
  6118. */
  6119. static ssize_t show_debug_level(struct device_driver *d, char *buf)
  6120. {
  6121. return sprintf(buf, "0x%08X\n", iwl3945_debug_level);
  6122. }
  6123. static ssize_t store_debug_level(struct device_driver *d,
  6124. const char *buf, size_t count)
  6125. {
  6126. char *p = (char *)buf;
  6127. u32 val;
  6128. val = simple_strtoul(p, &p, 0);
  6129. if (p == buf)
  6130. printk(KERN_INFO DRV_NAME
  6131. ": %s is not in hex or decimal form.\n", buf);
  6132. else
  6133. iwl3945_debug_level = val;
  6134. return strnlen(buf, count);
  6135. }
  6136. static DRIVER_ATTR(debug_level, S_IWUSR | S_IRUGO,
  6137. show_debug_level, store_debug_level);
  6138. #endif /* CONFIG_IWL3945_DEBUG */
  6139. static ssize_t show_rf_kill(struct device *d,
  6140. struct device_attribute *attr, char *buf)
  6141. {
  6142. /*
  6143. * 0 - RF kill not enabled
  6144. * 1 - SW based RF kill active (sysfs)
  6145. * 2 - HW based RF kill active
  6146. * 3 - Both HW and SW based RF kill active
  6147. */
  6148. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6149. int val = (test_bit(STATUS_RF_KILL_SW, &priv->status) ? 0x1 : 0x0) |
  6150. (test_bit(STATUS_RF_KILL_HW, &priv->status) ? 0x2 : 0x0);
  6151. return sprintf(buf, "%i\n", val);
  6152. }
  6153. static ssize_t store_rf_kill(struct device *d,
  6154. struct device_attribute *attr,
  6155. const char *buf, size_t count)
  6156. {
  6157. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6158. mutex_lock(&priv->mutex);
  6159. iwl3945_radio_kill_sw(priv, buf[0] == '1');
  6160. mutex_unlock(&priv->mutex);
  6161. return count;
  6162. }
  6163. static DEVICE_ATTR(rf_kill, S_IWUSR | S_IRUGO, show_rf_kill, store_rf_kill);
  6164. static ssize_t show_temperature(struct device *d,
  6165. struct device_attribute *attr, char *buf)
  6166. {
  6167. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6168. if (!iwl3945_is_alive(priv))
  6169. return -EAGAIN;
  6170. return sprintf(buf, "%d\n", iwl3945_hw_get_temperature(priv));
  6171. }
  6172. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  6173. static ssize_t show_rs_window(struct device *d,
  6174. struct device_attribute *attr,
  6175. char *buf)
  6176. {
  6177. struct iwl3945_priv *priv = d->driver_data;
  6178. return iwl3945_fill_rs_info(priv->hw, buf, IWL_AP_ID);
  6179. }
  6180. static DEVICE_ATTR(rs_window, S_IRUGO, show_rs_window, NULL);
  6181. static ssize_t show_tx_power(struct device *d,
  6182. struct device_attribute *attr, char *buf)
  6183. {
  6184. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6185. return sprintf(buf, "%d\n", priv->user_txpower_limit);
  6186. }
  6187. static ssize_t store_tx_power(struct device *d,
  6188. struct device_attribute *attr,
  6189. const char *buf, size_t count)
  6190. {
  6191. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6192. char *p = (char *)buf;
  6193. u32 val;
  6194. val = simple_strtoul(p, &p, 10);
  6195. if (p == buf)
  6196. printk(KERN_INFO DRV_NAME
  6197. ": %s is not in decimal form.\n", buf);
  6198. else
  6199. iwl3945_hw_reg_set_txpower(priv, val);
  6200. return count;
  6201. }
  6202. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  6203. static ssize_t show_flags(struct device *d,
  6204. struct device_attribute *attr, char *buf)
  6205. {
  6206. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6207. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  6208. }
  6209. static ssize_t store_flags(struct device *d,
  6210. struct device_attribute *attr,
  6211. const char *buf, size_t count)
  6212. {
  6213. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6214. u32 flags = simple_strtoul(buf, NULL, 0);
  6215. mutex_lock(&priv->mutex);
  6216. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  6217. /* Cancel any currently running scans... */
  6218. if (iwl3945_scan_cancel_timeout(priv, 100))
  6219. IWL_WARNING("Could not cancel scan.\n");
  6220. else {
  6221. IWL_DEBUG_INFO("Committing rxon.flags = 0x%04X\n",
  6222. flags);
  6223. priv->staging_rxon.flags = cpu_to_le32(flags);
  6224. iwl3945_commit_rxon(priv);
  6225. }
  6226. }
  6227. mutex_unlock(&priv->mutex);
  6228. return count;
  6229. }
  6230. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  6231. static ssize_t show_filter_flags(struct device *d,
  6232. struct device_attribute *attr, char *buf)
  6233. {
  6234. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6235. return sprintf(buf, "0x%04X\n",
  6236. le32_to_cpu(priv->active_rxon.filter_flags));
  6237. }
  6238. static ssize_t store_filter_flags(struct device *d,
  6239. struct device_attribute *attr,
  6240. const char *buf, size_t count)
  6241. {
  6242. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6243. u32 filter_flags = simple_strtoul(buf, NULL, 0);
  6244. mutex_lock(&priv->mutex);
  6245. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  6246. /* Cancel any currently running scans... */
  6247. if (iwl3945_scan_cancel_timeout(priv, 100))
  6248. IWL_WARNING("Could not cancel scan.\n");
  6249. else {
  6250. IWL_DEBUG_INFO("Committing rxon.filter_flags = "
  6251. "0x%04X\n", filter_flags);
  6252. priv->staging_rxon.filter_flags =
  6253. cpu_to_le32(filter_flags);
  6254. iwl3945_commit_rxon(priv);
  6255. }
  6256. }
  6257. mutex_unlock(&priv->mutex);
  6258. return count;
  6259. }
  6260. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  6261. store_filter_flags);
  6262. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6263. static ssize_t show_measurement(struct device *d,
  6264. struct device_attribute *attr, char *buf)
  6265. {
  6266. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6267. struct iwl3945_spectrum_notification measure_report;
  6268. u32 size = sizeof(measure_report), len = 0, ofs = 0;
  6269. u8 *data = (u8 *) & measure_report;
  6270. unsigned long flags;
  6271. spin_lock_irqsave(&priv->lock, flags);
  6272. if (!(priv->measurement_status & MEASUREMENT_READY)) {
  6273. spin_unlock_irqrestore(&priv->lock, flags);
  6274. return 0;
  6275. }
  6276. memcpy(&measure_report, &priv->measure_report, size);
  6277. priv->measurement_status = 0;
  6278. spin_unlock_irqrestore(&priv->lock, flags);
  6279. while (size && (PAGE_SIZE - len)) {
  6280. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6281. PAGE_SIZE - len, 1);
  6282. len = strlen(buf);
  6283. if (PAGE_SIZE - len)
  6284. buf[len++] = '\n';
  6285. ofs += 16;
  6286. size -= min(size, 16U);
  6287. }
  6288. return len;
  6289. }
  6290. static ssize_t store_measurement(struct device *d,
  6291. struct device_attribute *attr,
  6292. const char *buf, size_t count)
  6293. {
  6294. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6295. struct ieee80211_measurement_params params = {
  6296. .channel = le16_to_cpu(priv->active_rxon.channel),
  6297. .start_time = cpu_to_le64(priv->last_tsf),
  6298. .duration = cpu_to_le16(1),
  6299. };
  6300. u8 type = IWL_MEASURE_BASIC;
  6301. u8 buffer[32];
  6302. u8 channel;
  6303. if (count) {
  6304. char *p = buffer;
  6305. strncpy(buffer, buf, min(sizeof(buffer), count));
  6306. channel = simple_strtoul(p, NULL, 0);
  6307. if (channel)
  6308. params.channel = channel;
  6309. p = buffer;
  6310. while (*p && *p != ' ')
  6311. p++;
  6312. if (*p)
  6313. type = simple_strtoul(p + 1, NULL, 0);
  6314. }
  6315. IWL_DEBUG_INFO("Invoking measurement of type %d on "
  6316. "channel %d (for '%s')\n", type, params.channel, buf);
  6317. iwl3945_get_measurement(priv, &params, type);
  6318. return count;
  6319. }
  6320. static DEVICE_ATTR(measurement, S_IRUSR | S_IWUSR,
  6321. show_measurement, store_measurement);
  6322. #endif /* CONFIG_IWL3945_SPECTRUM_MEASUREMENT */
  6323. static ssize_t store_retry_rate(struct device *d,
  6324. struct device_attribute *attr,
  6325. const char *buf, size_t count)
  6326. {
  6327. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6328. priv->retry_rate = simple_strtoul(buf, NULL, 0);
  6329. if (priv->retry_rate <= 0)
  6330. priv->retry_rate = 1;
  6331. return count;
  6332. }
  6333. static ssize_t show_retry_rate(struct device *d,
  6334. struct device_attribute *attr, char *buf)
  6335. {
  6336. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6337. return sprintf(buf, "%d", priv->retry_rate);
  6338. }
  6339. static DEVICE_ATTR(retry_rate, S_IWUSR | S_IRUSR, show_retry_rate,
  6340. store_retry_rate);
  6341. static ssize_t store_power_level(struct device *d,
  6342. struct device_attribute *attr,
  6343. const char *buf, size_t count)
  6344. {
  6345. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6346. int rc;
  6347. int mode;
  6348. mode = simple_strtoul(buf, NULL, 0);
  6349. mutex_lock(&priv->mutex);
  6350. if (!iwl3945_is_ready(priv)) {
  6351. rc = -EAGAIN;
  6352. goto out;
  6353. }
  6354. if ((mode < 1) || (mode > IWL_POWER_LIMIT) || (mode == IWL_POWER_AC))
  6355. mode = IWL_POWER_AC;
  6356. else
  6357. mode |= IWL_POWER_ENABLED;
  6358. if (mode != priv->power_mode) {
  6359. rc = iwl3945_send_power_mode(priv, IWL_POWER_LEVEL(mode));
  6360. if (rc) {
  6361. IWL_DEBUG_MAC80211("failed setting power mode.\n");
  6362. goto out;
  6363. }
  6364. priv->power_mode = mode;
  6365. }
  6366. rc = count;
  6367. out:
  6368. mutex_unlock(&priv->mutex);
  6369. return rc;
  6370. }
  6371. #define MAX_WX_STRING 80
  6372. /* Values are in microsecond */
  6373. static const s32 timeout_duration[] = {
  6374. 350000,
  6375. 250000,
  6376. 75000,
  6377. 37000,
  6378. 25000,
  6379. };
  6380. static const s32 period_duration[] = {
  6381. 400000,
  6382. 700000,
  6383. 1000000,
  6384. 1000000,
  6385. 1000000
  6386. };
  6387. static ssize_t show_power_level(struct device *d,
  6388. struct device_attribute *attr, char *buf)
  6389. {
  6390. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6391. int level = IWL_POWER_LEVEL(priv->power_mode);
  6392. char *p = buf;
  6393. p += sprintf(p, "%d ", level);
  6394. switch (level) {
  6395. case IWL_POWER_MODE_CAM:
  6396. case IWL_POWER_AC:
  6397. p += sprintf(p, "(AC)");
  6398. break;
  6399. case IWL_POWER_BATTERY:
  6400. p += sprintf(p, "(BATTERY)");
  6401. break;
  6402. default:
  6403. p += sprintf(p,
  6404. "(Timeout %dms, Period %dms)",
  6405. timeout_duration[level - 1] / 1000,
  6406. period_duration[level - 1] / 1000);
  6407. }
  6408. if (!(priv->power_mode & IWL_POWER_ENABLED))
  6409. p += sprintf(p, " OFF\n");
  6410. else
  6411. p += sprintf(p, " \n");
  6412. return (p - buf + 1);
  6413. }
  6414. static DEVICE_ATTR(power_level, S_IWUSR | S_IRUSR, show_power_level,
  6415. store_power_level);
  6416. static ssize_t show_channels(struct device *d,
  6417. struct device_attribute *attr, char *buf)
  6418. {
  6419. /* all this shit doesn't belong into sysfs anyway */
  6420. return 0;
  6421. }
  6422. static DEVICE_ATTR(channels, S_IRUSR, show_channels, NULL);
  6423. static ssize_t show_statistics(struct device *d,
  6424. struct device_attribute *attr, char *buf)
  6425. {
  6426. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6427. u32 size = sizeof(struct iwl3945_notif_statistics);
  6428. u32 len = 0, ofs = 0;
  6429. u8 *data = (u8 *) & priv->statistics;
  6430. int rc = 0;
  6431. if (!iwl3945_is_alive(priv))
  6432. return -EAGAIN;
  6433. mutex_lock(&priv->mutex);
  6434. rc = iwl3945_send_statistics_request(priv);
  6435. mutex_unlock(&priv->mutex);
  6436. if (rc) {
  6437. len = sprintf(buf,
  6438. "Error sending statistics request: 0x%08X\n", rc);
  6439. return len;
  6440. }
  6441. while (size && (PAGE_SIZE - len)) {
  6442. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  6443. PAGE_SIZE - len, 1);
  6444. len = strlen(buf);
  6445. if (PAGE_SIZE - len)
  6446. buf[len++] = '\n';
  6447. ofs += 16;
  6448. size -= min(size, 16U);
  6449. }
  6450. return len;
  6451. }
  6452. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  6453. static ssize_t show_antenna(struct device *d,
  6454. struct device_attribute *attr, char *buf)
  6455. {
  6456. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6457. if (!iwl3945_is_alive(priv))
  6458. return -EAGAIN;
  6459. return sprintf(buf, "%d\n", priv->antenna);
  6460. }
  6461. static ssize_t store_antenna(struct device *d,
  6462. struct device_attribute *attr,
  6463. const char *buf, size_t count)
  6464. {
  6465. int ant;
  6466. struct iwl3945_priv *priv = dev_get_drvdata(d);
  6467. if (count == 0)
  6468. return 0;
  6469. if (sscanf(buf, "%1i", &ant) != 1) {
  6470. IWL_DEBUG_INFO("not in hex or decimal form.\n");
  6471. return count;
  6472. }
  6473. if ((ant >= 0) && (ant <= 2)) {
  6474. IWL_DEBUG_INFO("Setting antenna select to %d.\n", ant);
  6475. priv->antenna = (enum iwl3945_antenna)ant;
  6476. } else
  6477. IWL_DEBUG_INFO("Bad antenna select value %d.\n", ant);
  6478. return count;
  6479. }
  6480. static DEVICE_ATTR(antenna, S_IWUSR | S_IRUGO, show_antenna, store_antenna);
  6481. static ssize_t show_status(struct device *d,
  6482. struct device_attribute *attr, char *buf)
  6483. {
  6484. struct iwl3945_priv *priv = (struct iwl3945_priv *)d->driver_data;
  6485. if (!iwl3945_is_alive(priv))
  6486. return -EAGAIN;
  6487. return sprintf(buf, "0x%08x\n", (int)priv->status);
  6488. }
  6489. static DEVICE_ATTR(status, S_IRUGO, show_status, NULL);
  6490. static ssize_t dump_error_log(struct device *d,
  6491. struct device_attribute *attr,
  6492. const char *buf, size_t count)
  6493. {
  6494. char *p = (char *)buf;
  6495. if (p[0] == '1')
  6496. iwl3945_dump_nic_error_log((struct iwl3945_priv *)d->driver_data);
  6497. return strnlen(buf, count);
  6498. }
  6499. static DEVICE_ATTR(dump_errors, S_IWUSR, NULL, dump_error_log);
  6500. static ssize_t dump_event_log(struct device *d,
  6501. struct device_attribute *attr,
  6502. const char *buf, size_t count)
  6503. {
  6504. char *p = (char *)buf;
  6505. if (p[0] == '1')
  6506. iwl3945_dump_nic_event_log((struct iwl3945_priv *)d->driver_data);
  6507. return strnlen(buf, count);
  6508. }
  6509. static DEVICE_ATTR(dump_events, S_IWUSR, NULL, dump_event_log);
  6510. /*****************************************************************************
  6511. *
  6512. * driver setup and teardown
  6513. *
  6514. *****************************************************************************/
  6515. static void iwl3945_setup_deferred_work(struct iwl3945_priv *priv)
  6516. {
  6517. priv->workqueue = create_workqueue(DRV_NAME);
  6518. init_waitqueue_head(&priv->wait_command_queue);
  6519. INIT_WORK(&priv->up, iwl3945_bg_up);
  6520. INIT_WORK(&priv->restart, iwl3945_bg_restart);
  6521. INIT_WORK(&priv->rx_replenish, iwl3945_bg_rx_replenish);
  6522. INIT_WORK(&priv->scan_completed, iwl3945_bg_scan_completed);
  6523. INIT_WORK(&priv->request_scan, iwl3945_bg_request_scan);
  6524. INIT_WORK(&priv->abort_scan, iwl3945_bg_abort_scan);
  6525. INIT_WORK(&priv->rf_kill, iwl3945_bg_rf_kill);
  6526. INIT_WORK(&priv->beacon_update, iwl3945_bg_beacon_update);
  6527. INIT_WORK(&priv->set_monitor, iwl3945_bg_set_monitor);
  6528. INIT_DELAYED_WORK(&priv->post_associate, iwl3945_bg_post_associate);
  6529. INIT_DELAYED_WORK(&priv->init_alive_start, iwl3945_bg_init_alive_start);
  6530. INIT_DELAYED_WORK(&priv->alive_start, iwl3945_bg_alive_start);
  6531. INIT_DELAYED_WORK(&priv->scan_check, iwl3945_bg_scan_check);
  6532. iwl3945_hw_setup_deferred_work(priv);
  6533. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  6534. iwl3945_irq_tasklet, (unsigned long)priv);
  6535. }
  6536. static void iwl3945_cancel_deferred_work(struct iwl3945_priv *priv)
  6537. {
  6538. iwl3945_hw_cancel_deferred_work(priv);
  6539. cancel_delayed_work_sync(&priv->init_alive_start);
  6540. cancel_delayed_work(&priv->scan_check);
  6541. cancel_delayed_work(&priv->alive_start);
  6542. cancel_delayed_work(&priv->post_associate);
  6543. cancel_work_sync(&priv->beacon_update);
  6544. }
  6545. static struct attribute *iwl3945_sysfs_entries[] = {
  6546. &dev_attr_antenna.attr,
  6547. &dev_attr_channels.attr,
  6548. &dev_attr_dump_errors.attr,
  6549. &dev_attr_dump_events.attr,
  6550. &dev_attr_flags.attr,
  6551. &dev_attr_filter_flags.attr,
  6552. #ifdef CONFIG_IWL3945_SPECTRUM_MEASUREMENT
  6553. &dev_attr_measurement.attr,
  6554. #endif
  6555. &dev_attr_power_level.attr,
  6556. &dev_attr_retry_rate.attr,
  6557. &dev_attr_rf_kill.attr,
  6558. &dev_attr_rs_window.attr,
  6559. &dev_attr_statistics.attr,
  6560. &dev_attr_status.attr,
  6561. &dev_attr_temperature.attr,
  6562. &dev_attr_tx_power.attr,
  6563. NULL
  6564. };
  6565. static struct attribute_group iwl3945_attribute_group = {
  6566. .name = NULL, /* put in device directory */
  6567. .attrs = iwl3945_sysfs_entries,
  6568. };
  6569. static struct ieee80211_ops iwl3945_hw_ops = {
  6570. .tx = iwl3945_mac_tx,
  6571. .start = iwl3945_mac_start,
  6572. .stop = iwl3945_mac_stop,
  6573. .add_interface = iwl3945_mac_add_interface,
  6574. .remove_interface = iwl3945_mac_remove_interface,
  6575. .config = iwl3945_mac_config,
  6576. .config_interface = iwl3945_mac_config_interface,
  6577. .configure_filter = iwl3945_configure_filter,
  6578. .set_key = iwl3945_mac_set_key,
  6579. .get_stats = iwl3945_mac_get_stats,
  6580. .get_tx_stats = iwl3945_mac_get_tx_stats,
  6581. .conf_tx = iwl3945_mac_conf_tx,
  6582. .get_tsf = iwl3945_mac_get_tsf,
  6583. .reset_tsf = iwl3945_mac_reset_tsf,
  6584. .beacon_update = iwl3945_mac_beacon_update,
  6585. .hw_scan = iwl3945_mac_hw_scan
  6586. };
  6587. static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  6588. {
  6589. int err = 0;
  6590. struct iwl3945_priv *priv;
  6591. struct ieee80211_hw *hw;
  6592. struct iwl_3945_cfg *cfg = (struct iwl_3945_cfg *)(ent->driver_data);
  6593. int i;
  6594. unsigned long flags;
  6595. DECLARE_MAC_BUF(mac);
  6596. /* Disabling hardware scan means that mac80211 will perform scans
  6597. * "the hard way", rather than using device's scan. */
  6598. if (iwl3945_param_disable_hw_scan) {
  6599. IWL_DEBUG_INFO("Disabling hw_scan\n");
  6600. iwl3945_hw_ops.hw_scan = NULL;
  6601. }
  6602. if ((iwl3945_param_queues_num > IWL39_MAX_NUM_QUEUES) ||
  6603. (iwl3945_param_queues_num < IWL_MIN_NUM_QUEUES)) {
  6604. IWL_ERROR("invalid queues_num, should be between %d and %d\n",
  6605. IWL_MIN_NUM_QUEUES, IWL39_MAX_NUM_QUEUES);
  6606. err = -EINVAL;
  6607. goto out;
  6608. }
  6609. /* mac80211 allocates memory for this device instance, including
  6610. * space for this driver's private structure */
  6611. hw = ieee80211_alloc_hw(sizeof(struct iwl3945_priv), &iwl3945_hw_ops);
  6612. if (hw == NULL) {
  6613. IWL_ERROR("Can not allocate network device\n");
  6614. err = -ENOMEM;
  6615. goto out;
  6616. }
  6617. SET_IEEE80211_DEV(hw, &pdev->dev);
  6618. hw->rate_control_algorithm = "iwl-3945-rs";
  6619. IWL_DEBUG_INFO("*** LOAD DRIVER ***\n");
  6620. priv = hw->priv;
  6621. priv->hw = hw;
  6622. priv->pci_dev = pdev;
  6623. priv->cfg = cfg;
  6624. /* Select antenna (may be helpful if only one antenna is connected) */
  6625. priv->antenna = (enum iwl3945_antenna)iwl3945_param_antenna;
  6626. #ifdef CONFIG_IWL3945_DEBUG
  6627. iwl3945_debug_level = iwl3945_param_debug;
  6628. atomic_set(&priv->restrict_refcnt, 0);
  6629. #endif
  6630. priv->retry_rate = 1;
  6631. priv->ibss_beacon = NULL;
  6632. /* Tell mac80211 our characteristics */
  6633. hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
  6634. IEEE80211_HW_SIGNAL_DBM |
  6635. IEEE80211_HW_NOISE_DBM;
  6636. /* 4 EDCA QOS priorities */
  6637. hw->queues = 4;
  6638. spin_lock_init(&priv->lock);
  6639. spin_lock_init(&priv->power_data.lock);
  6640. spin_lock_init(&priv->sta_lock);
  6641. spin_lock_init(&priv->hcmd_lock);
  6642. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
  6643. INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
  6644. INIT_LIST_HEAD(&priv->free_frames);
  6645. mutex_init(&priv->mutex);
  6646. if (pci_enable_device(pdev)) {
  6647. err = -ENODEV;
  6648. goto out_ieee80211_free_hw;
  6649. }
  6650. pci_set_master(pdev);
  6651. /* Clear the driver's (not device's) station table */
  6652. iwl3945_clear_stations_table(priv);
  6653. priv->data_retry_limit = -1;
  6654. priv->ieee_channels = NULL;
  6655. priv->ieee_rates = NULL;
  6656. priv->band = IEEE80211_BAND_2GHZ;
  6657. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  6658. if (!err)
  6659. err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
  6660. if (err) {
  6661. printk(KERN_WARNING DRV_NAME ": No suitable DMA available.\n");
  6662. goto out_pci_disable_device;
  6663. }
  6664. pci_set_drvdata(pdev, priv);
  6665. err = pci_request_regions(pdev, DRV_NAME);
  6666. if (err)
  6667. goto out_pci_disable_device;
  6668. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  6669. * PCI Tx retries from interfering with C3 CPU state */
  6670. pci_write_config_byte(pdev, 0x41, 0x00);
  6671. priv->hw_base = pci_iomap(pdev, 0, 0);
  6672. if (!priv->hw_base) {
  6673. err = -ENODEV;
  6674. goto out_pci_release_regions;
  6675. }
  6676. IWL_DEBUG_INFO("pci_resource_len = 0x%08llx\n",
  6677. (unsigned long long) pci_resource_len(pdev, 0));
  6678. IWL_DEBUG_INFO("pci_resource_base = %p\n", priv->hw_base);
  6679. /* Initialize module parameter values here */
  6680. /* Disable radio (SW RF KILL) via parameter when loading driver */
  6681. if (iwl3945_param_disable) {
  6682. set_bit(STATUS_RF_KILL_SW, &priv->status);
  6683. IWL_DEBUG_INFO("Radio disabled.\n");
  6684. }
  6685. priv->iw_mode = IEEE80211_IF_TYPE_STA;
  6686. printk(KERN_INFO DRV_NAME
  6687. ": Detected Intel Wireless WiFi Link %s\n", priv->cfg->name);
  6688. /* Device-specific setup */
  6689. if (iwl3945_hw_set_hw_setting(priv)) {
  6690. IWL_ERROR("failed to set hw settings\n");
  6691. goto out_iounmap;
  6692. }
  6693. if (iwl3945_param_qos_enable)
  6694. priv->qos_data.qos_enable = 1;
  6695. iwl3945_reset_qos(priv);
  6696. priv->qos_data.qos_active = 0;
  6697. priv->qos_data.qos_cap.val = 0;
  6698. iwl3945_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
  6699. iwl3945_setup_deferred_work(priv);
  6700. iwl3945_setup_rx_handlers(priv);
  6701. priv->rates_mask = IWL_RATES_MASK;
  6702. /* If power management is turned on, default to AC mode */
  6703. priv->power_mode = IWL_POWER_AC;
  6704. priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
  6705. spin_lock_irqsave(&priv->lock, flags);
  6706. iwl3945_disable_interrupts(priv);
  6707. spin_unlock_irqrestore(&priv->lock, flags);
  6708. err = sysfs_create_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6709. if (err) {
  6710. IWL_ERROR("failed to create sysfs device attributes\n");
  6711. goto out_release_irq;
  6712. }
  6713. /* nic init */
  6714. iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  6715. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  6716. iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  6717. err = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
  6718. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  6719. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  6720. if (err < 0) {
  6721. IWL_DEBUG_INFO("Failed to init the card\n");
  6722. goto out_remove_sysfs;
  6723. }
  6724. /* Read the EEPROM */
  6725. err = iwl3945_eeprom_init(priv);
  6726. if (err) {
  6727. IWL_ERROR("Unable to init EEPROM\n");
  6728. goto out_remove_sysfs;
  6729. }
  6730. /* MAC Address location in EEPROM same for 3945/4965 */
  6731. get_eeprom_mac(priv, priv->mac_addr);
  6732. IWL_DEBUG_INFO("MAC address: %s\n", print_mac(mac, priv->mac_addr));
  6733. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  6734. err = iwl3945_init_channel_map(priv);
  6735. if (err) {
  6736. IWL_ERROR("initializing regulatory failed: %d\n", err);
  6737. goto out_remove_sysfs;
  6738. }
  6739. err = iwl3945_init_geos(priv);
  6740. if (err) {
  6741. IWL_ERROR("initializing geos failed: %d\n", err);
  6742. goto out_free_channel_map;
  6743. }
  6744. err = ieee80211_register_hw(priv->hw);
  6745. if (err) {
  6746. IWL_ERROR("Failed to register network device (error %d)\n", err);
  6747. goto out_free_geos;
  6748. }
  6749. priv->hw->conf.beacon_int = 100;
  6750. priv->mac80211_registered = 1;
  6751. pci_save_state(pdev);
  6752. pci_disable_device(pdev);
  6753. return 0;
  6754. out_free_geos:
  6755. iwl3945_free_geos(priv);
  6756. out_free_channel_map:
  6757. iwl3945_free_channel_map(priv);
  6758. out_remove_sysfs:
  6759. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6760. out_release_irq:
  6761. destroy_workqueue(priv->workqueue);
  6762. priv->workqueue = NULL;
  6763. iwl3945_unset_hw_setting(priv);
  6764. out_iounmap:
  6765. pci_iounmap(pdev, priv->hw_base);
  6766. out_pci_release_regions:
  6767. pci_release_regions(pdev);
  6768. out_pci_disable_device:
  6769. pci_disable_device(pdev);
  6770. pci_set_drvdata(pdev, NULL);
  6771. out_ieee80211_free_hw:
  6772. ieee80211_free_hw(priv->hw);
  6773. out:
  6774. return err;
  6775. }
  6776. static void __devexit iwl3945_pci_remove(struct pci_dev *pdev)
  6777. {
  6778. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6779. struct list_head *p, *q;
  6780. int i;
  6781. unsigned long flags;
  6782. if (!priv)
  6783. return;
  6784. IWL_DEBUG_INFO("*** UNLOAD DRIVER ***\n");
  6785. set_bit(STATUS_EXIT_PENDING, &priv->status);
  6786. iwl3945_down(priv);
  6787. /* make sure we flush any pending irq or
  6788. * tasklet for the driver
  6789. */
  6790. spin_lock_irqsave(&priv->lock, flags);
  6791. iwl3945_disable_interrupts(priv);
  6792. spin_unlock_irqrestore(&priv->lock, flags);
  6793. iwl_synchronize_irq(priv);
  6794. /* Free MAC hash list for ADHOC */
  6795. for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++) {
  6796. list_for_each_safe(p, q, &priv->ibss_mac_hash[i]) {
  6797. list_del(p);
  6798. kfree(list_entry(p, struct iwl3945_ibss_seq, list));
  6799. }
  6800. }
  6801. sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group);
  6802. iwl3945_dealloc_ucode_pci(priv);
  6803. if (priv->rxq.bd)
  6804. iwl3945_rx_queue_free(priv, &priv->rxq);
  6805. iwl3945_hw_txq_ctx_free(priv);
  6806. iwl3945_unset_hw_setting(priv);
  6807. iwl3945_clear_stations_table(priv);
  6808. if (priv->mac80211_registered) {
  6809. ieee80211_unregister_hw(priv->hw);
  6810. }
  6811. /*netif_stop_queue(dev); */
  6812. flush_workqueue(priv->workqueue);
  6813. /* ieee80211_unregister_hw calls iwl3945_mac_stop, which flushes
  6814. * priv->workqueue... so we can't take down the workqueue
  6815. * until now... */
  6816. destroy_workqueue(priv->workqueue);
  6817. priv->workqueue = NULL;
  6818. pci_iounmap(pdev, priv->hw_base);
  6819. pci_release_regions(pdev);
  6820. pci_disable_device(pdev);
  6821. pci_set_drvdata(pdev, NULL);
  6822. iwl3945_free_channel_map(priv);
  6823. iwl3945_free_geos(priv);
  6824. kfree(priv->scan);
  6825. if (priv->ibss_beacon)
  6826. dev_kfree_skb(priv->ibss_beacon);
  6827. ieee80211_free_hw(priv->hw);
  6828. }
  6829. #ifdef CONFIG_PM
  6830. static int iwl3945_pci_suspend(struct pci_dev *pdev, pm_message_t state)
  6831. {
  6832. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6833. if (priv->is_open) {
  6834. set_bit(STATUS_IN_SUSPEND, &priv->status);
  6835. iwl3945_mac_stop(priv->hw);
  6836. priv->is_open = 1;
  6837. }
  6838. pci_set_power_state(pdev, PCI_D3hot);
  6839. return 0;
  6840. }
  6841. static int iwl3945_pci_resume(struct pci_dev *pdev)
  6842. {
  6843. struct iwl3945_priv *priv = pci_get_drvdata(pdev);
  6844. pci_set_power_state(pdev, PCI_D0);
  6845. if (priv->is_open)
  6846. iwl3945_mac_start(priv->hw);
  6847. clear_bit(STATUS_IN_SUSPEND, &priv->status);
  6848. return 0;
  6849. }
  6850. #endif /* CONFIG_PM */
  6851. /*****************************************************************************
  6852. *
  6853. * driver and module entry point
  6854. *
  6855. *****************************************************************************/
  6856. static struct pci_driver iwl3945_driver = {
  6857. .name = DRV_NAME,
  6858. .id_table = iwl3945_hw_card_ids,
  6859. .probe = iwl3945_pci_probe,
  6860. .remove = __devexit_p(iwl3945_pci_remove),
  6861. #ifdef CONFIG_PM
  6862. .suspend = iwl3945_pci_suspend,
  6863. .resume = iwl3945_pci_resume,
  6864. #endif
  6865. };
  6866. static int __init iwl3945_init(void)
  6867. {
  6868. int ret;
  6869. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  6870. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  6871. ret = iwl3945_rate_control_register();
  6872. if (ret) {
  6873. IWL_ERROR("Unable to register rate control algorithm: %d\n", ret);
  6874. return ret;
  6875. }
  6876. ret = pci_register_driver(&iwl3945_driver);
  6877. if (ret) {
  6878. IWL_ERROR("Unable to initialize PCI module\n");
  6879. goto error_register;
  6880. }
  6881. #ifdef CONFIG_IWL3945_DEBUG
  6882. ret = driver_create_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6883. if (ret) {
  6884. IWL_ERROR("Unable to create driver sysfs file\n");
  6885. goto error_debug;
  6886. }
  6887. #endif
  6888. return ret;
  6889. #ifdef CONFIG_IWL3945_DEBUG
  6890. error_debug:
  6891. pci_unregister_driver(&iwl3945_driver);
  6892. #endif
  6893. error_register:
  6894. iwl3945_rate_control_unregister();
  6895. return ret;
  6896. }
  6897. static void __exit iwl3945_exit(void)
  6898. {
  6899. #ifdef CONFIG_IWL3945_DEBUG
  6900. driver_remove_file(&iwl3945_driver.driver, &driver_attr_debug_level);
  6901. #endif
  6902. pci_unregister_driver(&iwl3945_driver);
  6903. iwl3945_rate_control_unregister();
  6904. }
  6905. module_param_named(antenna, iwl3945_param_antenna, int, 0444);
  6906. MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
  6907. module_param_named(disable, iwl3945_param_disable, int, 0444);
  6908. MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
  6909. module_param_named(hwcrypto, iwl3945_param_hwcrypto, int, 0444);
  6910. MODULE_PARM_DESC(hwcrypto,
  6911. "using hardware crypto engine (default 0 [software])\n");
  6912. module_param_named(debug, iwl3945_param_debug, int, 0444);
  6913. MODULE_PARM_DESC(debug, "debug output mask");
  6914. module_param_named(disable_hw_scan, iwl3945_param_disable_hw_scan, int, 0444);
  6915. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  6916. module_param_named(queues_num, iwl3945_param_queues_num, int, 0444);
  6917. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  6918. /* QoS */
  6919. module_param_named(qos_enable, iwl3945_param_qos_enable, int, 0444);
  6920. MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
  6921. module_exit(iwl3945_exit);
  6922. module_init(iwl3945_init);