longhaul.c 21 KB

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  1. /*
  2. * (C) 2001-2004 Dave Jones. <davej@codemonkey.org.uk>
  3. * (C) 2002 Padraig Brady. <padraig@antefacto.com>
  4. *
  5. * Licensed under the terms of the GNU GPL License version 2.
  6. * Based upon datasheets & sample CPUs kindly provided by VIA.
  7. *
  8. * VIA have currently 3 different versions of Longhaul.
  9. * Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
  10. * It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
  11. * Version 2 of longhaul is the same as v1, but adds voltage scaling.
  12. * Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C)
  13. * voltage scaling support has currently been disabled in this driver
  14. * until we have code that gets it right.
  15. * Version 3 of longhaul got renamed to Powersaver and redesigned
  16. * to use the POWERSAVER MSR at 0x110a.
  17. * It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
  18. * It's pretty much the same feature wise to longhaul v2, though
  19. * there is provision for scaling FSB too, but this doesn't work
  20. * too well in practice so we don't even try to use this.
  21. *
  22. * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/module.h>
  26. #include <linux/moduleparam.h>
  27. #include <linux/init.h>
  28. #include <linux/cpufreq.h>
  29. #include <linux/pci.h>
  30. #include <linux/slab.h>
  31. #include <linux/string.h>
  32. #include <asm/msr.h>
  33. #include <asm/timex.h>
  34. #include <asm/io.h>
  35. #include <asm/acpi.h>
  36. #include <linux/acpi.h>
  37. #include <acpi/processor.h>
  38. #include "longhaul.h"
  39. #define PFX "longhaul: "
  40. #define TYPE_LONGHAUL_V1 1
  41. #define TYPE_LONGHAUL_V2 2
  42. #define TYPE_POWERSAVER 3
  43. #define CPU_SAMUEL 1
  44. #define CPU_SAMUEL2 2
  45. #define CPU_EZRA 3
  46. #define CPU_EZRA_T 4
  47. #define CPU_NEHEMIAH 5
  48. /* Flags */
  49. #define USE_ACPI_C3 (1 << 1)
  50. #define USE_NORTHBRIDGE (1 << 2)
  51. static int cpu_model;
  52. static unsigned int numscales=16;
  53. static unsigned int fsb;
  54. static struct mV_pos *vrm_mV_table;
  55. static unsigned char *mV_vrm_table;
  56. struct f_msr {
  57. unsigned char vrm;
  58. };
  59. static struct f_msr f_msr_table[32];
  60. static unsigned int highest_speed, lowest_speed; /* kHz */
  61. static unsigned int minmult, maxmult;
  62. static int can_scale_voltage;
  63. static struct acpi_processor *pr = NULL;
  64. static struct acpi_processor_cx *cx = NULL;
  65. static u8 longhaul_flags;
  66. /* Module parameters */
  67. static int scale_voltage;
  68. static int ignore_latency;
  69. #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
  70. /* Clock ratios multiplied by 10 */
  71. static int clock_ratio[32];
  72. static int eblcr_table[32];
  73. static int longhaul_version;
  74. static struct cpufreq_frequency_table *longhaul_table;
  75. #ifdef CONFIG_CPU_FREQ_DEBUG
  76. static char speedbuffer[8];
  77. static char *print_speed(int speed)
  78. {
  79. if (speed < 1000) {
  80. snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
  81. return speedbuffer;
  82. }
  83. if (speed%1000 == 0)
  84. snprintf(speedbuffer, sizeof(speedbuffer),
  85. "%dGHz", speed/1000);
  86. else
  87. snprintf(speedbuffer, sizeof(speedbuffer),
  88. "%d.%dGHz", speed/1000, (speed%1000)/100);
  89. return speedbuffer;
  90. }
  91. #endif
  92. static unsigned int calc_speed(int mult)
  93. {
  94. int khz;
  95. khz = (mult/10)*fsb;
  96. if (mult%10)
  97. khz += fsb/2;
  98. khz *= 1000;
  99. return khz;
  100. }
  101. static int longhaul_get_cpu_mult(void)
  102. {
  103. unsigned long invalue=0,lo, hi;
  104. rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
  105. invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
  106. if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
  107. if (lo & (1<<27))
  108. invalue+=16;
  109. }
  110. return eblcr_table[invalue];
  111. }
  112. /* For processor with BCR2 MSR */
  113. static void do_longhaul1(unsigned int clock_ratio_index)
  114. {
  115. union msr_bcr2 bcr2;
  116. rdmsrl(MSR_VIA_BCR2, bcr2.val);
  117. /* Enable software clock multiplier */
  118. bcr2.bits.ESOFTBF = 1;
  119. bcr2.bits.CLOCKMUL = clock_ratio_index;
  120. /* Sync to timer tick */
  121. safe_halt();
  122. /* Change frequency on next halt or sleep */
  123. wrmsrl(MSR_VIA_BCR2, bcr2.val);
  124. /* Invoke transition */
  125. ACPI_FLUSH_CPU_CACHE();
  126. halt();
  127. /* Disable software clock multiplier */
  128. local_irq_disable();
  129. rdmsrl(MSR_VIA_BCR2, bcr2.val);
  130. bcr2.bits.ESOFTBF = 0;
  131. wrmsrl(MSR_VIA_BCR2, bcr2.val);
  132. }
  133. /* For processor with Longhaul MSR */
  134. static void do_powersaver(int cx_address, unsigned int clock_ratio_index)
  135. {
  136. union msr_longhaul longhaul;
  137. u32 t;
  138. rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  139. longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
  140. longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
  141. longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
  142. longhaul.bits.EnableSoftBusRatio = 1;
  143. if (can_scale_voltage) {
  144. longhaul.bits.SoftVID = f_msr_table[clock_ratio_index].vrm;
  145. longhaul.bits.EnableSoftVID = 1;
  146. }
  147. /* Sync to timer tick */
  148. safe_halt();
  149. /* Change frequency on next halt or sleep */
  150. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  151. if (!cx_address) {
  152. ACPI_FLUSH_CPU_CACHE();
  153. /* Invoke C1 */
  154. halt();
  155. } else {
  156. ACPI_FLUSH_CPU_CACHE();
  157. /* Invoke C3 */
  158. inb(cx_address);
  159. /* Dummy op - must do something useless after P_LVL3 read */
  160. t = inl(acpi_gbl_FADT.xpm_timer_block.address);
  161. }
  162. /* Disable bus ratio bit */
  163. local_irq_disable();
  164. longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
  165. longhaul.bits.EnableSoftBusRatio = 0;
  166. longhaul.bits.EnableSoftBSEL = 0;
  167. longhaul.bits.EnableSoftVID = 0;
  168. wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  169. }
  170. /**
  171. * longhaul_set_cpu_frequency()
  172. * @clock_ratio_index : bitpattern of the new multiplier.
  173. *
  174. * Sets a new clock ratio.
  175. */
  176. static void longhaul_setstate(unsigned int clock_ratio_index)
  177. {
  178. int speed, mult;
  179. struct cpufreq_freqs freqs;
  180. static unsigned int old_ratio=-1;
  181. unsigned long flags;
  182. unsigned int pic1_mask, pic2_mask;
  183. if (old_ratio == clock_ratio_index)
  184. return;
  185. old_ratio = clock_ratio_index;
  186. mult = clock_ratio[clock_ratio_index];
  187. if (mult == -1)
  188. return;
  189. speed = calc_speed(mult);
  190. if ((speed > highest_speed) || (speed < lowest_speed))
  191. return;
  192. freqs.old = calc_speed(longhaul_get_cpu_mult());
  193. freqs.new = speed;
  194. freqs.cpu = 0; /* longhaul.c is UP only driver */
  195. cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
  196. dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
  197. fsb, mult/10, mult%10, print_speed(speed/1000));
  198. preempt_disable();
  199. local_irq_save(flags);
  200. pic2_mask = inb(0xA1);
  201. pic1_mask = inb(0x21); /* works on C3. save mask. */
  202. outb(0xFF,0xA1); /* Overkill */
  203. outb(0xFE,0x21); /* TMR0 only */
  204. if (longhaul_flags & USE_NORTHBRIDGE) {
  205. /* Disable AGP and PCI arbiters */
  206. outb(3, 0x22);
  207. } else if ((pr != NULL) && pr->flags.bm_control) {
  208. /* Disable bus master arbitration */
  209. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1);
  210. }
  211. switch (longhaul_version) {
  212. /*
  213. * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
  214. * Software controlled multipliers only.
  215. *
  216. * *NB* Until we get voltage scaling working v1 & v2 are the same code.
  217. * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5b] and Ezra [C5C]
  218. */
  219. case TYPE_LONGHAUL_V1:
  220. case TYPE_LONGHAUL_V2:
  221. do_longhaul1(clock_ratio_index);
  222. break;
  223. /*
  224. * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
  225. * We can scale voltage with this too, but that's currently
  226. * disabled until we come up with a decent 'match freq to voltage'
  227. * algorithm.
  228. * When we add voltage scaling, we will also need to do the
  229. * voltage/freq setting in order depending on the direction
  230. * of scaling (like we do in powernow-k7.c)
  231. * Nehemiah can do FSB scaling too, but this has never been proven
  232. * to work in practice.
  233. */
  234. case TYPE_POWERSAVER:
  235. if (longhaul_flags & USE_ACPI_C3) {
  236. /* Don't allow wakeup */
  237. acpi_set_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
  238. do_powersaver(cx->address, clock_ratio_index);
  239. } else {
  240. do_powersaver(0, clock_ratio_index);
  241. }
  242. break;
  243. }
  244. if (longhaul_flags & USE_NORTHBRIDGE) {
  245. /* Enable arbiters */
  246. outb(0, 0x22);
  247. } else if ((pr != NULL) && pr->flags.bm_control) {
  248. /* Enable bus master arbitration */
  249. acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
  250. }
  251. outb(pic2_mask,0xA1); /* restore mask */
  252. outb(pic1_mask,0x21);
  253. local_irq_restore(flags);
  254. preempt_enable();
  255. cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
  256. }
  257. /*
  258. * Centaur decided to make life a little more tricky.
  259. * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
  260. * Samuel2 and above have to try and guess what the FSB is.
  261. * We do this by assuming we booted at maximum multiplier, and interpolate
  262. * between that value multiplied by possible FSBs and cpu_mhz which
  263. * was calculated at boot time. Really ugly, but no other way to do this.
  264. */
  265. #define ROUNDING 0xf
  266. static int _guess(int guess, int mult)
  267. {
  268. int target;
  269. target = ((mult/10)*guess);
  270. if (mult%10 != 0)
  271. target += (guess/2);
  272. target += ROUNDING/2;
  273. target &= ~ROUNDING;
  274. return target;
  275. }
  276. static int guess_fsb(int mult)
  277. {
  278. int speed = (cpu_khz/1000);
  279. int i;
  280. int speeds[] = { 66, 100, 133, 200 };
  281. speed += ROUNDING/2;
  282. speed &= ~ROUNDING;
  283. for (i=0; i<4; i++) {
  284. if (_guess(speeds[i], mult) == speed)
  285. return speeds[i];
  286. }
  287. return 0;
  288. }
  289. static int __init longhaul_get_ranges(void)
  290. {
  291. unsigned long invalue;
  292. unsigned int ezra_t_multipliers[32]= {
  293. 90, 30, 40, 100, 55, 35, 45, 95,
  294. 50, 70, 80, 60, 120, 75, 85, 65,
  295. -1, 110, 120, -1, 135, 115, 125, 105,
  296. 130, 150, 160, 140, -1, 155, -1, 145 };
  297. unsigned int j, k = 0;
  298. union msr_longhaul longhaul;
  299. int mult = 0;
  300. switch (longhaul_version) {
  301. case TYPE_LONGHAUL_V1:
  302. case TYPE_LONGHAUL_V2:
  303. /* Ugh, Longhaul v1 didn't have the min/max MSRs.
  304. Assume min=3.0x & max = whatever we booted at. */
  305. minmult = 30;
  306. maxmult = mult = longhaul_get_cpu_mult();
  307. break;
  308. case TYPE_POWERSAVER:
  309. /* Ezra-T */
  310. if (cpu_model==CPU_EZRA_T) {
  311. minmult = 30;
  312. rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
  313. invalue = longhaul.bits.MaxMHzBR;
  314. if (longhaul.bits.MaxMHzBR4)
  315. invalue += 16;
  316. maxmult = mult = ezra_t_multipliers[invalue];
  317. break;
  318. }
  319. /* Nehemiah */
  320. if (cpu_model==CPU_NEHEMIAH) {
  321. rdmsrl (MSR_VIA_LONGHAUL, longhaul.val);
  322. /*
  323. * TODO: This code works, but raises a lot of questions.
  324. * - Some Nehemiah's seem to have broken Min/MaxMHzBR's.
  325. * We get around this by using a hardcoded multiplier of 4.0x
  326. * for the minimimum speed, and the speed we booted up at for the max.
  327. * This is done in longhaul_get_cpu_mult() by reading the EBLCR register.
  328. * - According to some VIA documentation EBLCR is only
  329. * in pre-Nehemiah C3s. How this still works is a mystery.
  330. * We're possibly using something undocumented and unsupported,
  331. * But it works, so we don't grumble.
  332. */
  333. minmult=40;
  334. maxmult = mult = longhaul_get_cpu_mult();
  335. break;
  336. }
  337. }
  338. fsb = guess_fsb(mult);
  339. dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
  340. minmult/10, minmult%10, maxmult/10, maxmult%10);
  341. if (fsb == 0) {
  342. printk (KERN_INFO PFX "Invalid (reserved) FSB!\n");
  343. return -EINVAL;
  344. }
  345. highest_speed = calc_speed(maxmult);
  346. lowest_speed = calc_speed(minmult);
  347. dprintk ("FSB:%dMHz Lowest speed: %s Highest speed:%s\n", fsb,
  348. print_speed(lowest_speed/1000),
  349. print_speed(highest_speed/1000));
  350. if (lowest_speed == highest_speed) {
  351. printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
  352. return -EINVAL;
  353. }
  354. if (lowest_speed > highest_speed) {
  355. printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
  356. lowest_speed, highest_speed);
  357. return -EINVAL;
  358. }
  359. longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
  360. if(!longhaul_table)
  361. return -ENOMEM;
  362. for (j=0; j < numscales; j++) {
  363. unsigned int ratio;
  364. ratio = clock_ratio[j];
  365. if (ratio == -1)
  366. continue;
  367. if (ratio > maxmult || ratio < minmult)
  368. continue;
  369. longhaul_table[k].frequency = calc_speed(ratio);
  370. longhaul_table[k].index = j;
  371. k++;
  372. }
  373. longhaul_table[k].frequency = CPUFREQ_TABLE_END;
  374. if (!k) {
  375. kfree (longhaul_table);
  376. return -EINVAL;
  377. }
  378. return 0;
  379. }
  380. static void __init longhaul_setup_voltagescaling(void)
  381. {
  382. union msr_longhaul longhaul;
  383. struct mV_pos minvid, maxvid;
  384. unsigned int j, speed, pos, kHz_step, numvscales;
  385. rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
  386. if (!(longhaul.bits.RevisionID & 1)) {
  387. printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
  388. return;
  389. }
  390. if (!longhaul.bits.VRMRev) {
  391. printk (KERN_INFO PFX "VRM 8.5\n");
  392. vrm_mV_table = &vrm85_mV[0];
  393. mV_vrm_table = &mV_vrm85[0];
  394. } else {
  395. printk (KERN_INFO PFX "Mobile VRM\n");
  396. vrm_mV_table = &mobilevrm_mV[0];
  397. mV_vrm_table = &mV_mobilevrm[0];
  398. }
  399. minvid = vrm_mV_table[longhaul.bits.MinimumVID];
  400. maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
  401. numvscales = maxvid.pos - minvid.pos + 1;
  402. kHz_step = (highest_speed - lowest_speed) / numvscales;
  403. if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
  404. printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
  405. "Voltage scaling disabled.\n",
  406. minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
  407. return;
  408. }
  409. if (minvid.mV == maxvid.mV) {
  410. printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
  411. "both %d.%03d. Voltage scaling disabled\n",
  412. maxvid.mV/1000, maxvid.mV%1000);
  413. return;
  414. }
  415. printk(KERN_INFO PFX "Max VID=%d.%03d Min VID=%d.%03d, %d possible voltage scales\n",
  416. maxvid.mV/1000, maxvid.mV%1000,
  417. minvid.mV/1000, minvid.mV%1000,
  418. numvscales);
  419. j = 0;
  420. while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
  421. speed = longhaul_table[j].frequency;
  422. pos = (speed - lowest_speed) / kHz_step + minvid.pos;
  423. f_msr_table[longhaul_table[j].index].vrm = mV_vrm_table[pos];
  424. j++;
  425. }
  426. can_scale_voltage = 1;
  427. }
  428. static int longhaul_verify(struct cpufreq_policy *policy)
  429. {
  430. return cpufreq_frequency_table_verify(policy, longhaul_table);
  431. }
  432. static int longhaul_target(struct cpufreq_policy *policy,
  433. unsigned int target_freq, unsigned int relation)
  434. {
  435. unsigned int table_index = 0;
  436. unsigned int new_clock_ratio = 0;
  437. if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
  438. return -EINVAL;
  439. new_clock_ratio = longhaul_table[table_index].index & 0xFF;
  440. longhaul_setstate(new_clock_ratio);
  441. return 0;
  442. }
  443. static unsigned int longhaul_get(unsigned int cpu)
  444. {
  445. if (cpu)
  446. return 0;
  447. return calc_speed(longhaul_get_cpu_mult());
  448. }
  449. static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
  450. u32 nesting_level,
  451. void *context, void **return_value)
  452. {
  453. struct acpi_device *d;
  454. if ( acpi_bus_get_device(obj_handle, &d) ) {
  455. return 0;
  456. }
  457. *return_value = (void *)acpi_driver_data(d);
  458. return 1;
  459. }
  460. /* VIA don't support PM2 reg, but have something similar */
  461. static int enable_arbiter_disable(void)
  462. {
  463. struct pci_dev *dev;
  464. int reg;
  465. u8 pci_cmd;
  466. /* Find PLE133 host bridge */
  467. reg = 0x78;
  468. dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0, NULL);
  469. /* Find CLE266 host bridge */
  470. if (dev == NULL) {
  471. reg = 0x76;
  472. dev = pci_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_862X_0, NULL);
  473. /* Find CN400 V-Link host bridge */
  474. if (dev == NULL)
  475. dev = pci_find_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
  476. }
  477. if (dev != NULL) {
  478. /* Enable access to port 0x22 */
  479. pci_read_config_byte(dev, reg, &pci_cmd);
  480. if ( !(pci_cmd & 1<<7) ) {
  481. pci_cmd |= 1<<7;
  482. pci_write_config_byte(dev, reg, pci_cmd);
  483. }
  484. return 1;
  485. }
  486. return 0;
  487. }
  488. static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
  489. {
  490. struct cpuinfo_x86 *c = cpu_data;
  491. char *cpuname=NULL;
  492. int ret;
  493. /* Check what we have on this motherboard */
  494. switch (c->x86_model) {
  495. case 6:
  496. cpu_model = CPU_SAMUEL;
  497. cpuname = "C3 'Samuel' [C5A]";
  498. longhaul_version = TYPE_LONGHAUL_V1;
  499. memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
  500. memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
  501. break;
  502. case 7:
  503. longhaul_version = TYPE_LONGHAUL_V1;
  504. switch (c->x86_mask) {
  505. case 0:
  506. cpu_model = CPU_SAMUEL2;
  507. cpuname = "C3 'Samuel 2' [C5B]";
  508. /* Note, this is not a typo, early Samuel2's had Samuel1 ratios. */
  509. memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
  510. memcpy (eblcr_table, samuel2_eblcr, sizeof(samuel2_eblcr));
  511. break;
  512. case 1 ... 15:
  513. if (c->x86_mask < 8) {
  514. cpu_model = CPU_SAMUEL2;
  515. cpuname = "C3 'Samuel 2' [C5B]";
  516. } else {
  517. cpu_model = CPU_EZRA;
  518. cpuname = "C3 'Ezra' [C5C]";
  519. }
  520. memcpy (clock_ratio, ezra_clock_ratio, sizeof(ezra_clock_ratio));
  521. memcpy (eblcr_table, ezra_eblcr, sizeof(ezra_eblcr));
  522. break;
  523. }
  524. break;
  525. case 8:
  526. cpu_model = CPU_EZRA_T;
  527. cpuname = "C3 'Ezra-T' [C5M]";
  528. longhaul_version = TYPE_POWERSAVER;
  529. numscales=32;
  530. memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
  531. memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
  532. break;
  533. case 9:
  534. cpu_model = CPU_NEHEMIAH;
  535. longhaul_version = TYPE_POWERSAVER;
  536. numscales=32;
  537. switch (c->x86_mask) {
  538. case 0 ... 1:
  539. cpuname = "C3 'Nehemiah A' [C5N]";
  540. memcpy (clock_ratio, nehemiah_a_clock_ratio, sizeof(nehemiah_a_clock_ratio));
  541. memcpy (eblcr_table, nehemiah_a_eblcr, sizeof(nehemiah_a_eblcr));
  542. break;
  543. case 2 ... 4:
  544. cpuname = "C3 'Nehemiah B' [C5N]";
  545. memcpy (clock_ratio, nehemiah_b_clock_ratio, sizeof(nehemiah_b_clock_ratio));
  546. memcpy (eblcr_table, nehemiah_b_eblcr, sizeof(nehemiah_b_eblcr));
  547. break;
  548. case 5 ... 15:
  549. cpuname = "C3 'Nehemiah C' [C5N]";
  550. memcpy (clock_ratio, nehemiah_c_clock_ratio, sizeof(nehemiah_c_clock_ratio));
  551. memcpy (eblcr_table, nehemiah_c_eblcr, sizeof(nehemiah_c_eblcr));
  552. break;
  553. }
  554. break;
  555. default:
  556. cpuname = "Unknown";
  557. break;
  558. }
  559. printk (KERN_INFO PFX "VIA %s CPU detected. ", cpuname);
  560. switch (longhaul_version) {
  561. case TYPE_LONGHAUL_V1:
  562. case TYPE_LONGHAUL_V2:
  563. printk ("Longhaul v%d supported.\n", longhaul_version);
  564. break;
  565. case TYPE_POWERSAVER:
  566. printk ("Powersaver supported.\n");
  567. break;
  568. };
  569. /* Find ACPI data for processor */
  570. acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
  571. &longhaul_walk_callback, NULL, (void *)&pr);
  572. /* Check ACPI support for C3 state */
  573. if ((pr != NULL) && (longhaul_version == TYPE_POWERSAVER)) {
  574. cx = &pr->power.states[ACPI_STATE_C3];
  575. if (cx->address > 0 &&
  576. (cx->latency <= 1000 || ignore_latency != 0) ) {
  577. longhaul_flags |= USE_ACPI_C3;
  578. goto print_support_type;
  579. }
  580. }
  581. /* Check if northbridge is friendly */
  582. if (enable_arbiter_disable()) {
  583. longhaul_flags |= USE_NORTHBRIDGE;
  584. goto print_support_type;
  585. }
  586. /* No ACPI C3 or we can't use it */
  587. /* Check ACPI support for bus master arbiter disable */
  588. if ((pr == NULL) || !(pr->flags.bm_control)) {
  589. printk(KERN_ERR PFX
  590. "No ACPI support. Unsupported northbridge.\n");
  591. return -ENODEV;
  592. }
  593. print_support_type:
  594. if (!(longhaul_flags & USE_NORTHBRIDGE)) {
  595. printk (KERN_INFO PFX "Using ACPI support.\n");
  596. } else {
  597. printk (KERN_INFO PFX "Using northbridge support.\n");
  598. }
  599. ret = longhaul_get_ranges();
  600. if (ret != 0)
  601. return ret;
  602. if ((longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) &&
  603. (scale_voltage != 0))
  604. longhaul_setup_voltagescaling();
  605. policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
  606. policy->cpuinfo.transition_latency = 200000; /* nsec */
  607. policy->cur = calc_speed(longhaul_get_cpu_mult());
  608. ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
  609. if (ret)
  610. return ret;
  611. cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
  612. return 0;
  613. }
  614. static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
  615. {
  616. cpufreq_frequency_table_put_attr(policy->cpu);
  617. return 0;
  618. }
  619. static struct freq_attr* longhaul_attr[] = {
  620. &cpufreq_freq_attr_scaling_available_freqs,
  621. NULL,
  622. };
  623. static struct cpufreq_driver longhaul_driver = {
  624. .verify = longhaul_verify,
  625. .target = longhaul_target,
  626. .get = longhaul_get,
  627. .init = longhaul_cpu_init,
  628. .exit = __devexit_p(longhaul_cpu_exit),
  629. .name = "longhaul",
  630. .owner = THIS_MODULE,
  631. .attr = longhaul_attr,
  632. };
  633. static int __init longhaul_init(void)
  634. {
  635. struct cpuinfo_x86 *c = cpu_data;
  636. if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
  637. return -ENODEV;
  638. #ifdef CONFIG_SMP
  639. if (num_online_cpus() > 1) {
  640. printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
  641. return -ENODEV;
  642. }
  643. #endif
  644. #ifdef CONFIG_X86_IO_APIC
  645. if (cpu_has_apic) {
  646. printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
  647. return -ENODEV;
  648. }
  649. #endif
  650. switch (c->x86_model) {
  651. case 6 ... 9:
  652. return cpufreq_register_driver(&longhaul_driver);
  653. case 10:
  654. printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
  655. default:
  656. ;;
  657. }
  658. return -ENODEV;
  659. }
  660. static void __exit longhaul_exit(void)
  661. {
  662. int i;
  663. for (i=0; i < numscales; i++) {
  664. if (clock_ratio[i] == maxmult) {
  665. longhaul_setstate(i);
  666. break;
  667. }
  668. }
  669. cpufreq_unregister_driver(&longhaul_driver);
  670. kfree(longhaul_table);
  671. }
  672. module_param (scale_voltage, int, 0644);
  673. MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
  674. module_param(ignore_latency, int, 0644);
  675. MODULE_PARM_DESC(ignore_latency, "Skip ACPI C3 latency test");
  676. MODULE_AUTHOR ("Dave Jones <davej@codemonkey.org.uk>");
  677. MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
  678. MODULE_LICENSE ("GPL");
  679. late_initcall(longhaul_init);
  680. module_exit(longhaul_exit);