patch_hdmi.c 56 KB

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  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. *
  10. * Authors:
  11. * Wu Fengguang <wfg@linux.intel.com>
  12. *
  13. * Maintained by:
  14. * Wu Fengguang <wfg@linux.intel.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the Free
  18. * Software Foundation; either version 2 of the License, or (at your option)
  19. * any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful, but
  22. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  23. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  24. * for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software Foundation,
  28. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29. */
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/slab.h>
  33. #include <linux/module.h>
  34. #include <sound/core.h>
  35. #include <sound/jack.h>
  36. #include "hda_codec.h"
  37. #include "hda_local.h"
  38. #include "hda_jack.h"
  39. static bool static_hdmi_pcm;
  40. module_param(static_hdmi_pcm, bool, 0644);
  41. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  42. /*
  43. * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
  44. * could support N independent pipes, each of them can be connected to one or
  45. * more ports (DVI, HDMI or DisplayPort).
  46. *
  47. * The HDA correspondence of pipes/ports are converter/pin nodes.
  48. */
  49. #define MAX_HDMI_CVTS 8
  50. #define MAX_HDMI_PINS 8
  51. struct hdmi_spec_per_cvt {
  52. hda_nid_t cvt_nid;
  53. int assigned;
  54. unsigned int channels_min;
  55. unsigned int channels_max;
  56. u32 rates;
  57. u64 formats;
  58. unsigned int maxbps;
  59. };
  60. struct hdmi_spec_per_pin {
  61. hda_nid_t pin_nid;
  62. int num_mux_nids;
  63. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  64. struct hda_codec *codec;
  65. struct hdmi_eld sink_eld;
  66. struct delayed_work work;
  67. int repoll_count;
  68. };
  69. struct hdmi_spec {
  70. int num_cvts;
  71. struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
  72. int num_pins;
  73. struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
  74. struct hda_pcm pcm_rec[MAX_HDMI_PINS];
  75. /*
  76. * Non-generic ATI/NVIDIA specific
  77. */
  78. struct hda_multi_out multiout;
  79. struct hda_pcm_stream pcm_playback;
  80. };
  81. struct hdmi_audio_infoframe {
  82. u8 type; /* 0x84 */
  83. u8 ver; /* 0x01 */
  84. u8 len; /* 0x0a */
  85. u8 checksum;
  86. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  87. u8 SS01_SF24;
  88. u8 CXT04;
  89. u8 CA;
  90. u8 LFEPBL01_LSV36_DM_INH7;
  91. };
  92. struct dp_audio_infoframe {
  93. u8 type; /* 0x84 */
  94. u8 len; /* 0x1b */
  95. u8 ver; /* 0x11 << 2 */
  96. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  97. u8 SS01_SF24;
  98. u8 CXT04;
  99. u8 CA;
  100. u8 LFEPBL01_LSV36_DM_INH7;
  101. };
  102. union audio_infoframe {
  103. struct hdmi_audio_infoframe hdmi;
  104. struct dp_audio_infoframe dp;
  105. u8 bytes[0];
  106. };
  107. /*
  108. * CEA speaker placement:
  109. *
  110. * FLH FCH FRH
  111. * FLW FL FLC FC FRC FR FRW
  112. *
  113. * LFE
  114. * TC
  115. *
  116. * RL RLC RC RRC RR
  117. *
  118. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  119. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  120. */
  121. enum cea_speaker_placement {
  122. FL = (1 << 0), /* Front Left */
  123. FC = (1 << 1), /* Front Center */
  124. FR = (1 << 2), /* Front Right */
  125. FLC = (1 << 3), /* Front Left Center */
  126. FRC = (1 << 4), /* Front Right Center */
  127. RL = (1 << 5), /* Rear Left */
  128. RC = (1 << 6), /* Rear Center */
  129. RR = (1 << 7), /* Rear Right */
  130. RLC = (1 << 8), /* Rear Left Center */
  131. RRC = (1 << 9), /* Rear Right Center */
  132. LFE = (1 << 10), /* Low Frequency Effect */
  133. FLW = (1 << 11), /* Front Left Wide */
  134. FRW = (1 << 12), /* Front Right Wide */
  135. FLH = (1 << 13), /* Front Left High */
  136. FCH = (1 << 14), /* Front Center High */
  137. FRH = (1 << 15), /* Front Right High */
  138. TC = (1 << 16), /* Top Center */
  139. };
  140. /*
  141. * ELD SA bits in the CEA Speaker Allocation data block
  142. */
  143. static int eld_speaker_allocation_bits[] = {
  144. [0] = FL | FR,
  145. [1] = LFE,
  146. [2] = FC,
  147. [3] = RL | RR,
  148. [4] = RC,
  149. [5] = FLC | FRC,
  150. [6] = RLC | RRC,
  151. /* the following are not defined in ELD yet */
  152. [7] = FLW | FRW,
  153. [8] = FLH | FRH,
  154. [9] = TC,
  155. [10] = FCH,
  156. };
  157. struct cea_channel_speaker_allocation {
  158. int ca_index;
  159. int speakers[8];
  160. /* derived values, just for convenience */
  161. int channels;
  162. int spk_mask;
  163. };
  164. /*
  165. * ALSA sequence is:
  166. *
  167. * surround40 surround41 surround50 surround51 surround71
  168. * ch0 front left = = = =
  169. * ch1 front right = = = =
  170. * ch2 rear left = = = =
  171. * ch3 rear right = = = =
  172. * ch4 LFE center center center
  173. * ch5 LFE LFE
  174. * ch6 side left
  175. * ch7 side right
  176. *
  177. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  178. */
  179. static int hdmi_channel_mapping[0x32][8] = {
  180. /* stereo */
  181. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  182. /* 2.1 */
  183. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  184. /* Dolby Surround */
  185. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  186. /* surround40 */
  187. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  188. /* 4ch */
  189. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  190. /* surround41 */
  191. [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
  192. /* surround50 */
  193. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  194. /* surround51 */
  195. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  196. /* 7.1 */
  197. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  198. };
  199. /*
  200. * This is an ordered list!
  201. *
  202. * The preceding ones have better chances to be selected by
  203. * hdmi_channel_allocation().
  204. */
  205. static struct cea_channel_speaker_allocation channel_allocations[] = {
  206. /* channel: 7 6 5 4 3 2 1 0 */
  207. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  208. /* 2.1 */
  209. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  210. /* Dolby Surround */
  211. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  212. /* surround40 */
  213. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  214. /* surround41 */
  215. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  216. /* surround50 */
  217. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  218. /* surround51 */
  219. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  220. /* 6.1 */
  221. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  222. /* surround71 */
  223. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  224. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  225. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  226. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  227. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  228. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  229. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  230. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  231. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  232. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  233. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  234. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  235. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  236. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  237. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  238. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  239. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  240. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  241. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  242. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  243. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  244. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  245. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  246. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  247. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  248. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  249. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  250. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  251. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  252. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  253. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  254. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  255. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  256. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  257. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  258. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  259. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  260. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  261. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  262. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  263. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  264. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  265. };
  266. /*
  267. * HDMI routines
  268. */
  269. static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
  270. {
  271. int pin_idx;
  272. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  273. if (spec->pins[pin_idx].pin_nid == pin_nid)
  274. return pin_idx;
  275. snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
  276. return -EINVAL;
  277. }
  278. static int hinfo_to_pin_index(struct hdmi_spec *spec,
  279. struct hda_pcm_stream *hinfo)
  280. {
  281. int pin_idx;
  282. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  283. if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
  284. return pin_idx;
  285. snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
  286. return -EINVAL;
  287. }
  288. static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
  289. {
  290. int cvt_idx;
  291. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  292. if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
  293. return cvt_idx;
  294. snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
  295. return -EINVAL;
  296. }
  297. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  298. struct snd_ctl_elem_info *uinfo)
  299. {
  300. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  301. struct hdmi_spec *spec;
  302. int pin_idx;
  303. spec = codec->spec;
  304. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  305. pin_idx = kcontrol->private_value;
  306. uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
  307. return 0;
  308. }
  309. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  310. struct snd_ctl_elem_value *ucontrol)
  311. {
  312. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  313. struct hdmi_spec *spec;
  314. int pin_idx;
  315. spec = codec->spec;
  316. pin_idx = kcontrol->private_value;
  317. memcpy(ucontrol->value.bytes.data,
  318. spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
  319. return 0;
  320. }
  321. static struct snd_kcontrol_new eld_bytes_ctl = {
  322. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  323. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  324. .name = "ELD",
  325. .info = hdmi_eld_ctl_info,
  326. .get = hdmi_eld_ctl_get,
  327. };
  328. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
  329. int device)
  330. {
  331. struct snd_kcontrol *kctl;
  332. struct hdmi_spec *spec = codec->spec;
  333. int err;
  334. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  335. if (!kctl)
  336. return -ENOMEM;
  337. kctl->private_value = pin_idx;
  338. kctl->id.device = device;
  339. err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
  340. if (err < 0)
  341. return err;
  342. return 0;
  343. }
  344. #ifdef BE_PARANOID
  345. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  346. int *packet_index, int *byte_index)
  347. {
  348. int val;
  349. val = snd_hda_codec_read(codec, pin_nid, 0,
  350. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  351. *packet_index = val >> 5;
  352. *byte_index = val & 0x1f;
  353. }
  354. #endif
  355. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  356. int packet_index, int byte_index)
  357. {
  358. int val;
  359. val = (packet_index << 5) | (byte_index & 0x1f);
  360. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  361. }
  362. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  363. unsigned char val)
  364. {
  365. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  366. }
  367. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  368. {
  369. /* Unmute */
  370. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  371. snd_hda_codec_write(codec, pin_nid, 0,
  372. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  373. /* Disable pin out until stream is active*/
  374. snd_hda_codec_write(codec, pin_nid, 0,
  375. AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
  376. }
  377. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
  378. {
  379. return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
  380. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  381. }
  382. static void hdmi_set_channel_count(struct hda_codec *codec,
  383. hda_nid_t cvt_nid, int chs)
  384. {
  385. if (chs != hdmi_get_channel_count(codec, cvt_nid))
  386. snd_hda_codec_write(codec, cvt_nid, 0,
  387. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  388. }
  389. /*
  390. * Channel mapping routines
  391. */
  392. /*
  393. * Compute derived values in channel_allocations[].
  394. */
  395. static void init_channel_allocations(void)
  396. {
  397. int i, j;
  398. struct cea_channel_speaker_allocation *p;
  399. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  400. p = channel_allocations + i;
  401. p->channels = 0;
  402. p->spk_mask = 0;
  403. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  404. if (p->speakers[j]) {
  405. p->channels++;
  406. p->spk_mask |= p->speakers[j];
  407. }
  408. }
  409. }
  410. /*
  411. * The transformation takes two steps:
  412. *
  413. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  414. * spk_mask => (channel_allocations[]) => ai->CA
  415. *
  416. * TODO: it could select the wrong CA from multiple candidates.
  417. */
  418. static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
  419. {
  420. int i;
  421. int ca = 0;
  422. int spk_mask = 0;
  423. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  424. /*
  425. * CA defaults to 0 for basic stereo audio
  426. */
  427. if (channels <= 2)
  428. return 0;
  429. /*
  430. * expand ELD's speaker allocation mask
  431. *
  432. * ELD tells the speaker mask in a compact(paired) form,
  433. * expand ELD's notions to match the ones used by Audio InfoFrame.
  434. */
  435. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  436. if (eld->spk_alloc & (1 << i))
  437. spk_mask |= eld_speaker_allocation_bits[i];
  438. }
  439. /* search for the first working match in the CA table */
  440. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  441. if (channels == channel_allocations[i].channels &&
  442. (spk_mask & channel_allocations[i].spk_mask) ==
  443. channel_allocations[i].spk_mask) {
  444. ca = channel_allocations[i].ca_index;
  445. break;
  446. }
  447. }
  448. snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
  449. snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  450. ca, channels, buf);
  451. return ca;
  452. }
  453. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  454. hda_nid_t pin_nid)
  455. {
  456. #ifdef CONFIG_SND_DEBUG_VERBOSE
  457. int i;
  458. int slot;
  459. for (i = 0; i < 8; i++) {
  460. slot = snd_hda_codec_read(codec, pin_nid, 0,
  461. AC_VERB_GET_HDMI_CHAN_SLOT, i);
  462. printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
  463. slot >> 4, slot & 0xf);
  464. }
  465. #endif
  466. }
  467. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  468. hda_nid_t pin_nid,
  469. int ca)
  470. {
  471. int i;
  472. int err;
  473. if (hdmi_channel_mapping[ca][1] == 0) {
  474. for (i = 0; i < channel_allocations[ca].channels; i++)
  475. hdmi_channel_mapping[ca][i] = i | (i << 4);
  476. for (; i < 8; i++)
  477. hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
  478. }
  479. for (i = 0; i < 8; i++) {
  480. err = snd_hda_codec_write(codec, pin_nid, 0,
  481. AC_VERB_SET_HDMI_CHAN_SLOT,
  482. hdmi_channel_mapping[ca][i]);
  483. if (err) {
  484. snd_printdd(KERN_NOTICE
  485. "HDMI: channel mapping failed\n");
  486. break;
  487. }
  488. }
  489. hdmi_debug_channel_mapping(codec, pin_nid);
  490. }
  491. /*
  492. * Audio InfoFrame routines
  493. */
  494. /*
  495. * Enable Audio InfoFrame Transmission
  496. */
  497. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  498. hda_nid_t pin_nid)
  499. {
  500. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  501. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  502. AC_DIPXMIT_BEST);
  503. }
  504. /*
  505. * Disable Audio InfoFrame Transmission
  506. */
  507. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  508. hda_nid_t pin_nid)
  509. {
  510. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  511. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  512. AC_DIPXMIT_DISABLE);
  513. }
  514. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  515. {
  516. #ifdef CONFIG_SND_DEBUG_VERBOSE
  517. int i;
  518. int size;
  519. size = snd_hdmi_get_eld_size(codec, pin_nid);
  520. printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
  521. for (i = 0; i < 8; i++) {
  522. size = snd_hda_codec_read(codec, pin_nid, 0,
  523. AC_VERB_GET_HDMI_DIP_SIZE, i);
  524. printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  525. }
  526. #endif
  527. }
  528. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  529. {
  530. #ifdef BE_PARANOID
  531. int i, j;
  532. int size;
  533. int pi, bi;
  534. for (i = 0; i < 8; i++) {
  535. size = snd_hda_codec_read(codec, pin_nid, 0,
  536. AC_VERB_GET_HDMI_DIP_SIZE, i);
  537. if (size == 0)
  538. continue;
  539. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  540. for (j = 1; j < 1000; j++) {
  541. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  542. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  543. if (pi != i)
  544. snd_printd(KERN_INFO "dip index %d: %d != %d\n",
  545. bi, pi, i);
  546. if (bi == 0) /* byte index wrapped around */
  547. break;
  548. }
  549. snd_printd(KERN_INFO
  550. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  551. i, size, j);
  552. }
  553. #endif
  554. }
  555. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  556. {
  557. u8 *bytes = (u8 *)hdmi_ai;
  558. u8 sum = 0;
  559. int i;
  560. hdmi_ai->checksum = 0;
  561. for (i = 0; i < sizeof(*hdmi_ai); i++)
  562. sum += bytes[i];
  563. hdmi_ai->checksum = -sum;
  564. }
  565. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  566. hda_nid_t pin_nid,
  567. u8 *dip, int size)
  568. {
  569. int i;
  570. hdmi_debug_dip_size(codec, pin_nid);
  571. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  572. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  573. for (i = 0; i < size; i++)
  574. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  575. }
  576. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  577. u8 *dip, int size)
  578. {
  579. u8 val;
  580. int i;
  581. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  582. != AC_DIPXMIT_BEST)
  583. return false;
  584. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  585. for (i = 0; i < size; i++) {
  586. val = snd_hda_codec_read(codec, pin_nid, 0,
  587. AC_VERB_GET_HDMI_DIP_DATA, 0);
  588. if (val != dip[i])
  589. return false;
  590. }
  591. return true;
  592. }
  593. static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
  594. struct snd_pcm_substream *substream)
  595. {
  596. struct hdmi_spec *spec = codec->spec;
  597. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  598. hda_nid_t pin_nid = per_pin->pin_nid;
  599. int channels = substream->runtime->channels;
  600. struct hdmi_eld *eld;
  601. int ca;
  602. union audio_infoframe ai;
  603. eld = &spec->pins[pin_idx].sink_eld;
  604. if (!eld->monitor_present)
  605. return;
  606. ca = hdmi_channel_allocation(eld, channels);
  607. memset(&ai, 0, sizeof(ai));
  608. if (eld->conn_type == 0) { /* HDMI */
  609. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  610. hdmi_ai->type = 0x84;
  611. hdmi_ai->ver = 0x01;
  612. hdmi_ai->len = 0x0a;
  613. hdmi_ai->CC02_CT47 = channels - 1;
  614. hdmi_ai->CA = ca;
  615. hdmi_checksum_audio_infoframe(hdmi_ai);
  616. } else if (eld->conn_type == 1) { /* DisplayPort */
  617. struct dp_audio_infoframe *dp_ai = &ai.dp;
  618. dp_ai->type = 0x84;
  619. dp_ai->len = 0x1b;
  620. dp_ai->ver = 0x11 << 2;
  621. dp_ai->CC02_CT47 = channels - 1;
  622. dp_ai->CA = ca;
  623. } else {
  624. snd_printd("HDMI: unknown connection type at pin %d\n",
  625. pin_nid);
  626. return;
  627. }
  628. /*
  629. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  630. * sizeof(*dp_ai) to avoid partial match/update problems when
  631. * the user switches between HDMI/DP monitors.
  632. */
  633. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  634. sizeof(ai))) {
  635. snd_printdd("hdmi_setup_audio_infoframe: "
  636. "pin=%d channels=%d\n",
  637. pin_nid,
  638. channels);
  639. hdmi_setup_channel_mapping(codec, pin_nid, ca);
  640. hdmi_stop_infoframe_trans(codec, pin_nid);
  641. hdmi_fill_audio_infoframe(codec, pin_nid,
  642. ai.bytes, sizeof(ai));
  643. hdmi_start_infoframe_trans(codec, pin_nid);
  644. }
  645. }
  646. /*
  647. * Unsolicited events
  648. */
  649. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
  650. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  651. {
  652. struct hdmi_spec *spec = codec->spec;
  653. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  654. int pin_nid;
  655. int pin_idx;
  656. struct hda_jack_tbl *jack;
  657. jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
  658. if (!jack)
  659. return;
  660. pin_nid = jack->nid;
  661. jack->jack_dirty = 1;
  662. _snd_printd(SND_PR_VERBOSE,
  663. "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  664. codec->addr, pin_nid,
  665. !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
  666. pin_idx = pin_nid_to_pin_index(spec, pin_nid);
  667. if (pin_idx < 0)
  668. return;
  669. hdmi_present_sense(&spec->pins[pin_idx], 1);
  670. snd_hda_jack_report_sync(codec);
  671. }
  672. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  673. {
  674. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  675. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  676. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  677. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  678. printk(KERN_INFO
  679. "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  680. codec->addr,
  681. tag,
  682. subtag,
  683. cp_state,
  684. cp_ready);
  685. /* TODO */
  686. if (cp_state)
  687. ;
  688. if (cp_ready)
  689. ;
  690. }
  691. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  692. {
  693. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  694. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  695. if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
  696. snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
  697. return;
  698. }
  699. if (subtag == 0)
  700. hdmi_intrinsic_event(codec, res);
  701. else
  702. hdmi_non_intrinsic_event(codec, res);
  703. }
  704. /*
  705. * Callbacks
  706. */
  707. /* HBR should be Non-PCM, 8 channels */
  708. #define is_hbr_format(format) \
  709. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  710. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  711. hda_nid_t pin_nid, u32 stream_tag, int format)
  712. {
  713. int pinctl;
  714. int new_pinctl = 0;
  715. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  716. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  717. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  718. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  719. if (is_hbr_format(format))
  720. new_pinctl |= AC_PINCTL_EPT_HBR;
  721. else
  722. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  723. snd_printdd("hdmi_setup_stream: "
  724. "NID=0x%x, %spinctl=0x%x\n",
  725. pin_nid,
  726. pinctl == new_pinctl ? "" : "new-",
  727. new_pinctl);
  728. if (pinctl != new_pinctl)
  729. snd_hda_codec_write(codec, pin_nid, 0,
  730. AC_VERB_SET_PIN_WIDGET_CONTROL,
  731. new_pinctl);
  732. }
  733. if (is_hbr_format(format) && !new_pinctl) {
  734. snd_printdd("hdmi_setup_stream: HBR is not supported\n");
  735. return -EINVAL;
  736. }
  737. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  738. return 0;
  739. }
  740. /*
  741. * HDA PCM callbacks
  742. */
  743. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  744. struct hda_codec *codec,
  745. struct snd_pcm_substream *substream)
  746. {
  747. struct hdmi_spec *spec = codec->spec;
  748. struct snd_pcm_runtime *runtime = substream->runtime;
  749. int pin_idx, cvt_idx, mux_idx = 0;
  750. struct hdmi_spec_per_pin *per_pin;
  751. struct hdmi_eld *eld;
  752. struct hdmi_spec_per_cvt *per_cvt = NULL;
  753. hinfo->nid = 0; /* clear the leftover value */
  754. /* Validate hinfo */
  755. pin_idx = hinfo_to_pin_index(spec, hinfo);
  756. if (snd_BUG_ON(pin_idx < 0))
  757. return -EINVAL;
  758. per_pin = &spec->pins[pin_idx];
  759. eld = &per_pin->sink_eld;
  760. /* Dynamically assign converter to stream */
  761. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  762. per_cvt = &spec->cvts[cvt_idx];
  763. /* Must not already be assigned */
  764. if (per_cvt->assigned)
  765. continue;
  766. /* Must be in pin's mux's list of converters */
  767. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  768. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  769. break;
  770. /* Not in mux list */
  771. if (mux_idx == per_pin->num_mux_nids)
  772. continue;
  773. break;
  774. }
  775. /* No free converters */
  776. if (cvt_idx == spec->num_cvts)
  777. return -ENODEV;
  778. /* Claim converter */
  779. per_cvt->assigned = 1;
  780. hinfo->nid = per_cvt->cvt_nid;
  781. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  782. AC_VERB_SET_CONNECT_SEL,
  783. mux_idx);
  784. snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
  785. /* Initially set the converter's capabilities */
  786. hinfo->channels_min = per_cvt->channels_min;
  787. hinfo->channels_max = per_cvt->channels_max;
  788. hinfo->rates = per_cvt->rates;
  789. hinfo->formats = per_cvt->formats;
  790. hinfo->maxbps = per_cvt->maxbps;
  791. /* Restrict capabilities by ELD if this isn't disabled */
  792. if (!static_hdmi_pcm && eld->eld_valid) {
  793. snd_hdmi_eld_update_pcm_info(eld, hinfo);
  794. if (hinfo->channels_min > hinfo->channels_max ||
  795. !hinfo->rates || !hinfo->formats)
  796. return -ENODEV;
  797. }
  798. /* Store the updated parameters */
  799. runtime->hw.channels_min = hinfo->channels_min;
  800. runtime->hw.channels_max = hinfo->channels_max;
  801. runtime->hw.formats = hinfo->formats;
  802. runtime->hw.rates = hinfo->rates;
  803. snd_pcm_hw_constraint_step(substream->runtime, 0,
  804. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  805. return 0;
  806. }
  807. /*
  808. * HDA/HDMI auto parsing
  809. */
  810. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  811. {
  812. struct hdmi_spec *spec = codec->spec;
  813. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  814. hda_nid_t pin_nid = per_pin->pin_nid;
  815. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  816. snd_printk(KERN_WARNING
  817. "HDMI: pin %d wcaps %#x "
  818. "does not support connection list\n",
  819. pin_nid, get_wcaps(codec, pin_nid));
  820. return -EINVAL;
  821. }
  822. per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
  823. per_pin->mux_nids,
  824. HDA_MAX_CONNECTIONS);
  825. return 0;
  826. }
  827. static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
  828. {
  829. struct hda_codec *codec = per_pin->codec;
  830. struct hdmi_eld *eld = &per_pin->sink_eld;
  831. hda_nid_t pin_nid = per_pin->pin_nid;
  832. /*
  833. * Always execute a GetPinSense verb here, even when called from
  834. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  835. * response's PD bit is not the real PD value, but indicates that
  836. * the real PD value changed. An older version of the HD-audio
  837. * specification worked this way. Hence, we just ignore the data in
  838. * the unsolicited response to avoid custom WARs.
  839. */
  840. int present = snd_hda_pin_sense(codec, pin_nid);
  841. bool eld_valid = false;
  842. memset(eld, 0, offsetof(struct hdmi_eld, eld_buffer));
  843. eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  844. if (eld->monitor_present)
  845. eld_valid = !!(present & AC_PINSENSE_ELDV);
  846. _snd_printd(SND_PR_VERBOSE,
  847. "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  848. codec->addr, pin_nid, eld->monitor_present, eld_valid);
  849. if (eld_valid) {
  850. if (!snd_hdmi_get_eld(eld, codec, pin_nid))
  851. snd_hdmi_show_eld(eld);
  852. else if (repoll) {
  853. queue_delayed_work(codec->bus->workq,
  854. &per_pin->work,
  855. msecs_to_jiffies(300));
  856. }
  857. }
  858. }
  859. static void hdmi_repoll_eld(struct work_struct *work)
  860. {
  861. struct hdmi_spec_per_pin *per_pin =
  862. container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
  863. if (per_pin->repoll_count++ > 6)
  864. per_pin->repoll_count = 0;
  865. hdmi_present_sense(per_pin, per_pin->repoll_count);
  866. }
  867. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  868. {
  869. struct hdmi_spec *spec = codec->spec;
  870. unsigned int caps, config;
  871. int pin_idx;
  872. struct hdmi_spec_per_pin *per_pin;
  873. int err;
  874. caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
  875. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  876. return 0;
  877. config = snd_hda_codec_read(codec, pin_nid, 0,
  878. AC_VERB_GET_CONFIG_DEFAULT, 0);
  879. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
  880. return 0;
  881. if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
  882. return -E2BIG;
  883. pin_idx = spec->num_pins;
  884. per_pin = &spec->pins[pin_idx];
  885. per_pin->pin_nid = pin_nid;
  886. err = hdmi_read_pin_conn(codec, pin_idx);
  887. if (err < 0)
  888. return err;
  889. spec->num_pins++;
  890. return 0;
  891. }
  892. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  893. {
  894. struct hdmi_spec *spec = codec->spec;
  895. int cvt_idx;
  896. struct hdmi_spec_per_cvt *per_cvt;
  897. unsigned int chans;
  898. int err;
  899. if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
  900. return -E2BIG;
  901. chans = get_wcaps(codec, cvt_nid);
  902. chans = get_wcaps_channels(chans);
  903. cvt_idx = spec->num_cvts;
  904. per_cvt = &spec->cvts[cvt_idx];
  905. per_cvt->cvt_nid = cvt_nid;
  906. per_cvt->channels_min = 2;
  907. if (chans <= 16)
  908. per_cvt->channels_max = chans;
  909. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  910. &per_cvt->rates,
  911. &per_cvt->formats,
  912. &per_cvt->maxbps);
  913. if (err < 0)
  914. return err;
  915. spec->num_cvts++;
  916. return 0;
  917. }
  918. static int hdmi_parse_codec(struct hda_codec *codec)
  919. {
  920. hda_nid_t nid;
  921. int i, nodes;
  922. nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
  923. if (!nid || nodes < 0) {
  924. snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
  925. return -EINVAL;
  926. }
  927. for (i = 0; i < nodes; i++, nid++) {
  928. unsigned int caps;
  929. unsigned int type;
  930. caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
  931. type = get_wcaps_type(caps);
  932. if (!(caps & AC_WCAP_DIGITAL))
  933. continue;
  934. switch (type) {
  935. case AC_WID_AUD_OUT:
  936. hdmi_add_cvt(codec, nid);
  937. break;
  938. case AC_WID_PIN:
  939. hdmi_add_pin(codec, nid);
  940. break;
  941. }
  942. }
  943. /*
  944. * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
  945. * can be lost and presence sense verb will become inaccurate if the
  946. * HDA link is powered off at hot plug or hw initialization time.
  947. */
  948. #ifdef CONFIG_SND_HDA_POWER_SAVE
  949. if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
  950. AC_PWRST_EPSS))
  951. codec->bus->power_keep_link_on = 1;
  952. #endif
  953. return 0;
  954. }
  955. /*
  956. */
  957. static char *get_hdmi_pcm_name(int idx)
  958. {
  959. static char names[MAX_HDMI_PINS][8];
  960. sprintf(&names[idx][0], "HDMI %d", idx);
  961. return &names[idx][0];
  962. }
  963. /*
  964. * HDMI callbacks
  965. */
  966. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  967. struct hda_codec *codec,
  968. unsigned int stream_tag,
  969. unsigned int format,
  970. struct snd_pcm_substream *substream)
  971. {
  972. hda_nid_t cvt_nid = hinfo->nid;
  973. struct hdmi_spec *spec = codec->spec;
  974. int pin_idx = hinfo_to_pin_index(spec, hinfo);
  975. hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
  976. int pinctl;
  977. hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
  978. hdmi_setup_audio_infoframe(codec, pin_idx, substream);
  979. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  980. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  981. snd_hda_codec_write(codec, pin_nid, 0,
  982. AC_VERB_SET_PIN_WIDGET_CONTROL, pinctl | PIN_OUT);
  983. return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  984. }
  985. static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
  986. struct hda_codec *codec,
  987. struct snd_pcm_substream *substream)
  988. {
  989. struct hdmi_spec *spec = codec->spec;
  990. int cvt_idx, pin_idx;
  991. struct hdmi_spec_per_cvt *per_cvt;
  992. struct hdmi_spec_per_pin *per_pin;
  993. int pinctl;
  994. if (hinfo->nid) {
  995. cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
  996. if (snd_BUG_ON(cvt_idx < 0))
  997. return -EINVAL;
  998. per_cvt = &spec->cvts[cvt_idx];
  999. snd_BUG_ON(!per_cvt->assigned);
  1000. per_cvt->assigned = 0;
  1001. hinfo->nid = 0;
  1002. pin_idx = hinfo_to_pin_index(spec, hinfo);
  1003. if (snd_BUG_ON(pin_idx < 0))
  1004. return -EINVAL;
  1005. per_pin = &spec->pins[pin_idx];
  1006. pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
  1007. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1008. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  1009. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1010. pinctl & ~PIN_OUT);
  1011. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1012. }
  1013. return 0;
  1014. }
  1015. static const struct hda_pcm_ops generic_ops = {
  1016. .open = hdmi_pcm_open,
  1017. .close = hdmi_pcm_close,
  1018. .prepare = generic_hdmi_playback_pcm_prepare,
  1019. };
  1020. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1021. {
  1022. struct hdmi_spec *spec = codec->spec;
  1023. int pin_idx;
  1024. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1025. struct hda_pcm *info;
  1026. struct hda_pcm_stream *pstr;
  1027. info = &spec->pcm_rec[pin_idx];
  1028. info->name = get_hdmi_pcm_name(pin_idx);
  1029. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1030. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1031. pstr->substreams = 1;
  1032. pstr->ops = generic_ops;
  1033. pstr->nid = 1; /* FIXME: just for avoiding a debug WARNING */
  1034. /* other pstr fields are set in open */
  1035. }
  1036. codec->num_pcms = spec->num_pins;
  1037. codec->pcm_info = spec->pcm_rec;
  1038. return 0;
  1039. }
  1040. static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
  1041. {
  1042. char hdmi_str[32] = "HDMI/DP";
  1043. struct hdmi_spec *spec = codec->spec;
  1044. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1045. int pcmdev = spec->pcm_rec[pin_idx].device;
  1046. if (pcmdev > 0)
  1047. sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
  1048. return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str, 0);
  1049. }
  1050. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1051. {
  1052. struct hdmi_spec *spec = codec->spec;
  1053. int err;
  1054. int pin_idx;
  1055. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1056. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1057. err = generic_hdmi_build_jack(codec, pin_idx);
  1058. if (err < 0)
  1059. return err;
  1060. err = snd_hda_create_spdif_out_ctls(codec,
  1061. per_pin->pin_nid,
  1062. per_pin->mux_nids[0]);
  1063. if (err < 0)
  1064. return err;
  1065. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1066. /* add control for ELD Bytes */
  1067. err = hdmi_create_eld_ctl(codec,
  1068. pin_idx,
  1069. spec->pcm_rec[pin_idx].device);
  1070. if (err < 0)
  1071. return err;
  1072. hdmi_present_sense(per_pin, 0);
  1073. }
  1074. return 0;
  1075. }
  1076. static int generic_hdmi_init_per_pins(struct hda_codec *codec)
  1077. {
  1078. struct hdmi_spec *spec = codec->spec;
  1079. int pin_idx;
  1080. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1081. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1082. struct hdmi_eld *eld = &per_pin->sink_eld;
  1083. per_pin->codec = codec;
  1084. INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
  1085. snd_hda_eld_proc_new(codec, eld, pin_idx);
  1086. }
  1087. return 0;
  1088. }
  1089. static int generic_hdmi_init(struct hda_codec *codec)
  1090. {
  1091. struct hdmi_spec *spec = codec->spec;
  1092. int pin_idx;
  1093. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1094. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1095. hda_nid_t pin_nid = per_pin->pin_nid;
  1096. hdmi_init_pin(codec, pin_nid);
  1097. snd_hda_jack_detect_enable(codec, pin_nid, pin_nid);
  1098. }
  1099. snd_hda_jack_report_sync(codec);
  1100. return 0;
  1101. }
  1102. static void generic_hdmi_free(struct hda_codec *codec)
  1103. {
  1104. struct hdmi_spec *spec = codec->spec;
  1105. int pin_idx;
  1106. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1107. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1108. struct hdmi_eld *eld = &per_pin->sink_eld;
  1109. cancel_delayed_work(&per_pin->work);
  1110. snd_hda_eld_proc_free(codec, eld);
  1111. }
  1112. flush_workqueue(codec->bus->workq);
  1113. kfree(spec);
  1114. }
  1115. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  1116. .init = generic_hdmi_init,
  1117. .free = generic_hdmi_free,
  1118. .build_pcms = generic_hdmi_build_pcms,
  1119. .build_controls = generic_hdmi_build_controls,
  1120. .unsol_event = hdmi_unsol_event,
  1121. };
  1122. static int patch_generic_hdmi(struct hda_codec *codec)
  1123. {
  1124. struct hdmi_spec *spec;
  1125. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1126. if (spec == NULL)
  1127. return -ENOMEM;
  1128. codec->spec = spec;
  1129. if (hdmi_parse_codec(codec) < 0) {
  1130. codec->spec = NULL;
  1131. kfree(spec);
  1132. return -EINVAL;
  1133. }
  1134. codec->patch_ops = generic_hdmi_patch_ops;
  1135. generic_hdmi_init_per_pins(codec);
  1136. init_channel_allocations();
  1137. return 0;
  1138. }
  1139. /*
  1140. * Shared non-generic implementations
  1141. */
  1142. static int simple_playback_build_pcms(struct hda_codec *codec)
  1143. {
  1144. struct hdmi_spec *spec = codec->spec;
  1145. struct hda_pcm *info = spec->pcm_rec;
  1146. unsigned int chans;
  1147. struct hda_pcm_stream *pstr;
  1148. codec->num_pcms = 1;
  1149. codec->pcm_info = info;
  1150. chans = get_wcaps(codec, spec->cvts[0].cvt_nid);
  1151. chans = get_wcaps_channels(chans);
  1152. info->name = get_hdmi_pcm_name(0);
  1153. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1154. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1155. *pstr = spec->pcm_playback;
  1156. pstr->nid = spec->cvts[0].cvt_nid;
  1157. if (pstr->channels_max <= 2 && chans && chans <= 16)
  1158. pstr->channels_max = chans;
  1159. return 0;
  1160. }
  1161. /* unsolicited event for jack sensing */
  1162. static void simple_hdmi_unsol_event(struct hda_codec *codec,
  1163. unsigned int res)
  1164. {
  1165. snd_hda_jack_set_dirty_all(codec);
  1166. snd_hda_jack_report_sync(codec);
  1167. }
  1168. /* generic_hdmi_build_jack can be used for simple_hdmi, too,
  1169. * as long as spec->pins[] is set correctly
  1170. */
  1171. #define simple_hdmi_build_jack generic_hdmi_build_jack
  1172. static int simple_playback_build_controls(struct hda_codec *codec)
  1173. {
  1174. struct hdmi_spec *spec = codec->spec;
  1175. int err;
  1176. err = snd_hda_create_spdif_out_ctls(codec,
  1177. spec->cvts[0].cvt_nid,
  1178. spec->cvts[0].cvt_nid);
  1179. if (err < 0)
  1180. return err;
  1181. return simple_hdmi_build_jack(codec, 0);
  1182. }
  1183. static int simple_playback_init(struct hda_codec *codec)
  1184. {
  1185. struct hdmi_spec *spec = codec->spec;
  1186. hda_nid_t pin = spec->pins[0].pin_nid;
  1187. snd_hda_codec_write(codec, pin, 0,
  1188. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  1189. /* some codecs require to unmute the pin */
  1190. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  1191. snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  1192. AMP_OUT_UNMUTE);
  1193. snd_hda_jack_detect_enable(codec, pin, pin);
  1194. snd_hda_jack_report_sync(codec);
  1195. return 0;
  1196. }
  1197. static void simple_playback_free(struct hda_codec *codec)
  1198. {
  1199. struct hdmi_spec *spec = codec->spec;
  1200. kfree(spec);
  1201. }
  1202. /*
  1203. * Nvidia specific implementations
  1204. */
  1205. #define Nv_VERB_SET_Channel_Allocation 0xF79
  1206. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  1207. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  1208. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  1209. #define nvhdmi_master_con_nid_7x 0x04
  1210. #define nvhdmi_master_pin_nid_7x 0x05
  1211. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  1212. /*front, rear, clfe, rear_surr */
  1213. 0x6, 0x8, 0xa, 0xc,
  1214. };
  1215. static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
  1216. /* set audio protect on */
  1217. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1218. /* enable digital output on pin widget */
  1219. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1220. {} /* terminator */
  1221. };
  1222. static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
  1223. /* set audio protect on */
  1224. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1225. /* enable digital output on pin widget */
  1226. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1227. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1228. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1229. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1230. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1231. {} /* terminator */
  1232. };
  1233. #ifdef LIMITED_RATE_FMT_SUPPORT
  1234. /* support only the safe format and rate */
  1235. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  1236. #define SUPPORTED_MAXBPS 16
  1237. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  1238. #else
  1239. /* support all rates and formats */
  1240. #define SUPPORTED_RATES \
  1241. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  1242. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  1243. SNDRV_PCM_RATE_192000)
  1244. #define SUPPORTED_MAXBPS 24
  1245. #define SUPPORTED_FORMATS \
  1246. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1247. #endif
  1248. static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
  1249. {
  1250. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
  1251. return 0;
  1252. }
  1253. static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
  1254. {
  1255. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
  1256. return 0;
  1257. }
  1258. static unsigned int channels_2_6_8[] = {
  1259. 2, 6, 8
  1260. };
  1261. static unsigned int channels_2_8[] = {
  1262. 2, 8
  1263. };
  1264. static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  1265. .count = ARRAY_SIZE(channels_2_6_8),
  1266. .list = channels_2_6_8,
  1267. .mask = 0,
  1268. };
  1269. static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  1270. .count = ARRAY_SIZE(channels_2_8),
  1271. .list = channels_2_8,
  1272. .mask = 0,
  1273. };
  1274. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  1275. struct hda_codec *codec,
  1276. struct snd_pcm_substream *substream)
  1277. {
  1278. struct hdmi_spec *spec = codec->spec;
  1279. struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  1280. switch (codec->preset->id) {
  1281. case 0x10de0002:
  1282. case 0x10de0003:
  1283. case 0x10de0005:
  1284. case 0x10de0006:
  1285. hw_constraints_channels = &hw_constraints_2_8_channels;
  1286. break;
  1287. case 0x10de0007:
  1288. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  1289. break;
  1290. default:
  1291. break;
  1292. }
  1293. if (hw_constraints_channels != NULL) {
  1294. snd_pcm_hw_constraint_list(substream->runtime, 0,
  1295. SNDRV_PCM_HW_PARAM_CHANNELS,
  1296. hw_constraints_channels);
  1297. } else {
  1298. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1299. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1300. }
  1301. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  1302. }
  1303. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  1304. struct hda_codec *codec,
  1305. struct snd_pcm_substream *substream)
  1306. {
  1307. struct hdmi_spec *spec = codec->spec;
  1308. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1309. }
  1310. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1311. struct hda_codec *codec,
  1312. unsigned int stream_tag,
  1313. unsigned int format,
  1314. struct snd_pcm_substream *substream)
  1315. {
  1316. struct hdmi_spec *spec = codec->spec;
  1317. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  1318. stream_tag, format, substream);
  1319. }
  1320. static const struct hda_pcm_stream simple_pcm_playback = {
  1321. .substreams = 1,
  1322. .channels_min = 2,
  1323. .channels_max = 2,
  1324. .ops = {
  1325. .open = simple_playback_pcm_open,
  1326. .close = simple_playback_pcm_close,
  1327. .prepare = simple_playback_pcm_prepare
  1328. },
  1329. };
  1330. static const struct hda_codec_ops simple_hdmi_patch_ops = {
  1331. .build_controls = simple_playback_build_controls,
  1332. .build_pcms = simple_playback_build_pcms,
  1333. .init = simple_playback_init,
  1334. .free = simple_playback_free,
  1335. .unsol_event = simple_hdmi_unsol_event,
  1336. };
  1337. static int patch_simple_hdmi(struct hda_codec *codec,
  1338. hda_nid_t cvt_nid, hda_nid_t pin_nid)
  1339. {
  1340. struct hdmi_spec *spec;
  1341. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1342. if (!spec)
  1343. return -ENOMEM;
  1344. codec->spec = spec;
  1345. spec->multiout.num_dacs = 0; /* no analog */
  1346. spec->multiout.max_channels = 2;
  1347. spec->multiout.dig_out_nid = cvt_nid;
  1348. spec->num_cvts = 1;
  1349. spec->num_pins = 1;
  1350. spec->cvts[0].cvt_nid = cvt_nid;
  1351. spec->pins[0].pin_nid = pin_nid;
  1352. spec->pcm_playback = simple_pcm_playback;
  1353. codec->patch_ops = simple_hdmi_patch_ops;
  1354. return 0;
  1355. }
  1356. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  1357. int channels)
  1358. {
  1359. unsigned int chanmask;
  1360. int chan = channels ? (channels - 1) : 1;
  1361. switch (channels) {
  1362. default:
  1363. case 0:
  1364. case 2:
  1365. chanmask = 0x00;
  1366. break;
  1367. case 4:
  1368. chanmask = 0x08;
  1369. break;
  1370. case 6:
  1371. chanmask = 0x0b;
  1372. break;
  1373. case 8:
  1374. chanmask = 0x13;
  1375. break;
  1376. }
  1377. /* Set the audio infoframe channel allocation and checksum fields. The
  1378. * channel count is computed implicitly by the hardware. */
  1379. snd_hda_codec_write(codec, 0x1, 0,
  1380. Nv_VERB_SET_Channel_Allocation, chanmask);
  1381. snd_hda_codec_write(codec, 0x1, 0,
  1382. Nv_VERB_SET_Info_Frame_Checksum,
  1383. (0x71 - chan - chanmask));
  1384. }
  1385. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  1386. struct hda_codec *codec,
  1387. struct snd_pcm_substream *substream)
  1388. {
  1389. struct hdmi_spec *spec = codec->spec;
  1390. int i;
  1391. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  1392. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  1393. for (i = 0; i < 4; i++) {
  1394. /* set the stream id */
  1395. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1396. AC_VERB_SET_CHANNEL_STREAMID, 0);
  1397. /* set the stream format */
  1398. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1399. AC_VERB_SET_STREAM_FORMAT, 0);
  1400. }
  1401. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  1402. * streams are disabled. */
  1403. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  1404. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1405. }
  1406. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  1407. struct hda_codec *codec,
  1408. unsigned int stream_tag,
  1409. unsigned int format,
  1410. struct snd_pcm_substream *substream)
  1411. {
  1412. int chs;
  1413. unsigned int dataDCC2, channel_id;
  1414. int i;
  1415. struct hdmi_spec *spec = codec->spec;
  1416. struct hda_spdif_out *spdif;
  1417. mutex_lock(&codec->spdif_mutex);
  1418. spdif = snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
  1419. chs = substream->runtime->channels;
  1420. dataDCC2 = 0x2;
  1421. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  1422. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  1423. snd_hda_codec_write(codec,
  1424. nvhdmi_master_con_nid_7x,
  1425. 0,
  1426. AC_VERB_SET_DIGI_CONVERT_1,
  1427. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  1428. /* set the stream id */
  1429. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1430. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  1431. /* set the stream format */
  1432. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1433. AC_VERB_SET_STREAM_FORMAT, format);
  1434. /* turn on again (if needed) */
  1435. /* enable and set the channel status audio/data flag */
  1436. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  1437. snd_hda_codec_write(codec,
  1438. nvhdmi_master_con_nid_7x,
  1439. 0,
  1440. AC_VERB_SET_DIGI_CONVERT_1,
  1441. spdif->ctls & 0xff);
  1442. snd_hda_codec_write(codec,
  1443. nvhdmi_master_con_nid_7x,
  1444. 0,
  1445. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1446. }
  1447. for (i = 0; i < 4; i++) {
  1448. if (chs == 2)
  1449. channel_id = 0;
  1450. else
  1451. channel_id = i * 2;
  1452. /* turn off SPDIF once;
  1453. *otherwise the IEC958 bits won't be updated
  1454. */
  1455. if (codec->spdif_status_reset &&
  1456. (spdif->ctls & AC_DIG1_ENABLE))
  1457. snd_hda_codec_write(codec,
  1458. nvhdmi_con_nids_7x[i],
  1459. 0,
  1460. AC_VERB_SET_DIGI_CONVERT_1,
  1461. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  1462. /* set the stream id */
  1463. snd_hda_codec_write(codec,
  1464. nvhdmi_con_nids_7x[i],
  1465. 0,
  1466. AC_VERB_SET_CHANNEL_STREAMID,
  1467. (stream_tag << 4) | channel_id);
  1468. /* set the stream format */
  1469. snd_hda_codec_write(codec,
  1470. nvhdmi_con_nids_7x[i],
  1471. 0,
  1472. AC_VERB_SET_STREAM_FORMAT,
  1473. format);
  1474. /* turn on again (if needed) */
  1475. /* enable and set the channel status audio/data flag */
  1476. if (codec->spdif_status_reset &&
  1477. (spdif->ctls & AC_DIG1_ENABLE)) {
  1478. snd_hda_codec_write(codec,
  1479. nvhdmi_con_nids_7x[i],
  1480. 0,
  1481. AC_VERB_SET_DIGI_CONVERT_1,
  1482. spdif->ctls & 0xff);
  1483. snd_hda_codec_write(codec,
  1484. nvhdmi_con_nids_7x[i],
  1485. 0,
  1486. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1487. }
  1488. }
  1489. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  1490. mutex_unlock(&codec->spdif_mutex);
  1491. return 0;
  1492. }
  1493. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  1494. .substreams = 1,
  1495. .channels_min = 2,
  1496. .channels_max = 8,
  1497. .nid = nvhdmi_master_con_nid_7x,
  1498. .rates = SUPPORTED_RATES,
  1499. .maxbps = SUPPORTED_MAXBPS,
  1500. .formats = SUPPORTED_FORMATS,
  1501. .ops = {
  1502. .open = simple_playback_pcm_open,
  1503. .close = nvhdmi_8ch_7x_pcm_close,
  1504. .prepare = nvhdmi_8ch_7x_pcm_prepare
  1505. },
  1506. };
  1507. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  1508. {
  1509. struct hdmi_spec *spec;
  1510. int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
  1511. nvhdmi_master_pin_nid_7x);
  1512. if (err < 0)
  1513. return err;
  1514. codec->patch_ops.init = nvhdmi_7x_init_2ch;
  1515. /* override the PCM rates, etc, as the codec doesn't give full list */
  1516. spec = codec->spec;
  1517. spec->pcm_playback.rates = SUPPORTED_RATES;
  1518. spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
  1519. spec->pcm_playback.formats = SUPPORTED_FORMATS;
  1520. return 0;
  1521. }
  1522. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  1523. {
  1524. struct hdmi_spec *spec;
  1525. int err = patch_nvhdmi_2ch(codec);
  1526. if (err < 0)
  1527. return err;
  1528. spec = codec->spec;
  1529. spec->multiout.max_channels = 8;
  1530. spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
  1531. codec->patch_ops.init = nvhdmi_7x_init_8ch;
  1532. /* Initialize the audio infoframe channel mask and checksum to something
  1533. * valid */
  1534. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  1535. return 0;
  1536. }
  1537. /*
  1538. * ATI-specific implementations
  1539. *
  1540. * FIXME: we may omit the whole this and use the generic code once after
  1541. * it's confirmed to work.
  1542. */
  1543. #define ATIHDMI_CVT_NID 0x02 /* audio converter */
  1544. #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
  1545. static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1546. struct hda_codec *codec,
  1547. unsigned int stream_tag,
  1548. unsigned int format,
  1549. struct snd_pcm_substream *substream)
  1550. {
  1551. struct hdmi_spec *spec = codec->spec;
  1552. int chans = substream->runtime->channels;
  1553. int i, err;
  1554. err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
  1555. substream);
  1556. if (err < 0)
  1557. return err;
  1558. snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
  1559. AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
  1560. /* FIXME: XXX */
  1561. for (i = 0; i < chans; i++) {
  1562. snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
  1563. AC_VERB_SET_HDMI_CHAN_SLOT,
  1564. (i << 4) | i);
  1565. }
  1566. return 0;
  1567. }
  1568. static int patch_atihdmi(struct hda_codec *codec)
  1569. {
  1570. struct hdmi_spec *spec;
  1571. int err = patch_simple_hdmi(codec, ATIHDMI_CVT_NID, ATIHDMI_PIN_NID);
  1572. if (err < 0)
  1573. return err;
  1574. spec = codec->spec;
  1575. spec->pcm_playback.ops.prepare = atihdmi_playback_pcm_prepare;
  1576. return 0;
  1577. }
  1578. /* VIA HDMI Implementation */
  1579. #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
  1580. #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
  1581. static int patch_via_hdmi(struct hda_codec *codec)
  1582. {
  1583. return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
  1584. }
  1585. /*
  1586. * patch entries
  1587. */
  1588. static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
  1589. { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
  1590. { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
  1591. { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
  1592. { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
  1593. { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
  1594. { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
  1595. { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
  1596. { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1597. { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1598. { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1599. { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1600. { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
  1601. { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
  1602. { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
  1603. { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
  1604. { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
  1605. { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
  1606. { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
  1607. { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
  1608. { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
  1609. { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
  1610. { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
  1611. { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
  1612. /* 17 is known to be absent */
  1613. { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
  1614. { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
  1615. { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
  1616. { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
  1617. { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
  1618. { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
  1619. { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
  1620. { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
  1621. { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
  1622. { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
  1623. { .id = 0x10de0051, .name = "GPU 51 HDMI/DP", .patch = patch_generic_hdmi },
  1624. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  1625. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  1626. { .id = 0x11069f80, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  1627. { .id = 0x11069f81, .name = "VX900 HDMI/DP", .patch = patch_via_hdmi },
  1628. { .id = 0x11069f84, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  1629. { .id = 0x11069f85, .name = "VX11 HDMI/DP", .patch = patch_generic_hdmi },
  1630. { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  1631. { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
  1632. { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
  1633. { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
  1634. { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  1635. { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
  1636. { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
  1637. { .id = 0x80862807, .name = "Haswell HDMI", .patch = patch_generic_hdmi },
  1638. { .id = 0x80862880, .name = "CedarTrail HDMI", .patch = patch_generic_hdmi },
  1639. { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
  1640. {} /* terminator */
  1641. };
  1642. MODULE_ALIAS("snd-hda-codec-id:1002793c");
  1643. MODULE_ALIAS("snd-hda-codec-id:10027919");
  1644. MODULE_ALIAS("snd-hda-codec-id:1002791a");
  1645. MODULE_ALIAS("snd-hda-codec-id:1002aa01");
  1646. MODULE_ALIAS("snd-hda-codec-id:10951390");
  1647. MODULE_ALIAS("snd-hda-codec-id:10951392");
  1648. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  1649. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  1650. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  1651. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  1652. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  1653. MODULE_ALIAS("snd-hda-codec-id:10de000a");
  1654. MODULE_ALIAS("snd-hda-codec-id:10de000b");
  1655. MODULE_ALIAS("snd-hda-codec-id:10de000c");
  1656. MODULE_ALIAS("snd-hda-codec-id:10de000d");
  1657. MODULE_ALIAS("snd-hda-codec-id:10de0010");
  1658. MODULE_ALIAS("snd-hda-codec-id:10de0011");
  1659. MODULE_ALIAS("snd-hda-codec-id:10de0012");
  1660. MODULE_ALIAS("snd-hda-codec-id:10de0013");
  1661. MODULE_ALIAS("snd-hda-codec-id:10de0014");
  1662. MODULE_ALIAS("snd-hda-codec-id:10de0015");
  1663. MODULE_ALIAS("snd-hda-codec-id:10de0016");
  1664. MODULE_ALIAS("snd-hda-codec-id:10de0018");
  1665. MODULE_ALIAS("snd-hda-codec-id:10de0019");
  1666. MODULE_ALIAS("snd-hda-codec-id:10de001a");
  1667. MODULE_ALIAS("snd-hda-codec-id:10de001b");
  1668. MODULE_ALIAS("snd-hda-codec-id:10de001c");
  1669. MODULE_ALIAS("snd-hda-codec-id:10de0040");
  1670. MODULE_ALIAS("snd-hda-codec-id:10de0041");
  1671. MODULE_ALIAS("snd-hda-codec-id:10de0042");
  1672. MODULE_ALIAS("snd-hda-codec-id:10de0043");
  1673. MODULE_ALIAS("snd-hda-codec-id:10de0044");
  1674. MODULE_ALIAS("snd-hda-codec-id:10de0051");
  1675. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  1676. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  1677. MODULE_ALIAS("snd-hda-codec-id:11069f80");
  1678. MODULE_ALIAS("snd-hda-codec-id:11069f81");
  1679. MODULE_ALIAS("snd-hda-codec-id:11069f84");
  1680. MODULE_ALIAS("snd-hda-codec-id:11069f85");
  1681. MODULE_ALIAS("snd-hda-codec-id:17e80047");
  1682. MODULE_ALIAS("snd-hda-codec-id:80860054");
  1683. MODULE_ALIAS("snd-hda-codec-id:80862801");
  1684. MODULE_ALIAS("snd-hda-codec-id:80862802");
  1685. MODULE_ALIAS("snd-hda-codec-id:80862803");
  1686. MODULE_ALIAS("snd-hda-codec-id:80862804");
  1687. MODULE_ALIAS("snd-hda-codec-id:80862805");
  1688. MODULE_ALIAS("snd-hda-codec-id:80862806");
  1689. MODULE_ALIAS("snd-hda-codec-id:80862807");
  1690. MODULE_ALIAS("snd-hda-codec-id:80862880");
  1691. MODULE_ALIAS("snd-hda-codec-id:808629fb");
  1692. MODULE_LICENSE("GPL");
  1693. MODULE_DESCRIPTION("HDMI HD-audio codec");
  1694. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  1695. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  1696. MODULE_ALIAS("snd-hda-codec-atihdmi");
  1697. static struct hda_codec_preset_list intel_list = {
  1698. .preset = snd_hda_preset_hdmi,
  1699. .owner = THIS_MODULE,
  1700. };
  1701. static int __init patch_hdmi_init(void)
  1702. {
  1703. return snd_hda_add_codec_preset(&intel_list);
  1704. }
  1705. static void __exit patch_hdmi_exit(void)
  1706. {
  1707. snd_hda_delete_codec_preset(&intel_list);
  1708. }
  1709. module_init(patch_hdmi_init)
  1710. module_exit(patch_hdmi_exit)