cpsw.c 30 KB

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  1. /*
  2. * Texas Instruments Ethernet Switch Driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <linux/timer.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/irqreturn.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/if_ether.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/phy.h>
  27. #include <linux/workqueue.h>
  28. #include <linux/delay.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/of.h>
  31. #include <linux/of_net.h>
  32. #include <linux/of_device.h>
  33. #include <linux/platform_data/cpsw.h>
  34. #include "cpsw_ale.h"
  35. #include "davinci_cpdma.h"
  36. #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
  37. NETIF_MSG_DRV | NETIF_MSG_LINK | \
  38. NETIF_MSG_IFUP | NETIF_MSG_INTR | \
  39. NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
  40. NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
  41. NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
  42. NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
  43. NETIF_MSG_RX_STATUS)
  44. #define cpsw_info(priv, type, format, ...) \
  45. do { \
  46. if (netif_msg_##type(priv) && net_ratelimit()) \
  47. dev_info(priv->dev, format, ## __VA_ARGS__); \
  48. } while (0)
  49. #define cpsw_err(priv, type, format, ...) \
  50. do { \
  51. if (netif_msg_##type(priv) && net_ratelimit()) \
  52. dev_err(priv->dev, format, ## __VA_ARGS__); \
  53. } while (0)
  54. #define cpsw_dbg(priv, type, format, ...) \
  55. do { \
  56. if (netif_msg_##type(priv) && net_ratelimit()) \
  57. dev_dbg(priv->dev, format, ## __VA_ARGS__); \
  58. } while (0)
  59. #define cpsw_notice(priv, type, format, ...) \
  60. do { \
  61. if (netif_msg_##type(priv) && net_ratelimit()) \
  62. dev_notice(priv->dev, format, ## __VA_ARGS__); \
  63. } while (0)
  64. #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
  65. #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
  66. #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
  67. #define CPDMA_RXTHRESH 0x0c0
  68. #define CPDMA_RXFREE 0x0e0
  69. #define CPDMA_TXHDP 0x00
  70. #define CPDMA_RXHDP 0x20
  71. #define CPDMA_TXCP 0x40
  72. #define CPDMA_RXCP 0x60
  73. #define cpsw_dma_regs(base, offset) \
  74. (void __iomem *)((base) + (offset))
  75. #define cpsw_dma_rxthresh(base, offset) \
  76. (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
  77. #define cpsw_dma_rxfree(base, offset) \
  78. (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
  79. #define cpsw_dma_txhdp(base, offset) \
  80. (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
  81. #define cpsw_dma_rxhdp(base, offset) \
  82. (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
  83. #define cpsw_dma_txcp(base, offset) \
  84. (void __iomem *)((base) + (offset) + CPDMA_TXCP)
  85. #define cpsw_dma_rxcp(base, offset) \
  86. (void __iomem *)((base) + (offset) + CPDMA_RXCP)
  87. #define CPSW_POLL_WEIGHT 64
  88. #define CPSW_MIN_PACKET_SIZE 60
  89. #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
  90. #define RX_PRIORITY_MAPPING 0x76543210
  91. #define TX_PRIORITY_MAPPING 0x33221100
  92. #define CPDMA_TX_PRIORITY_MAP 0x76543210
  93. #define cpsw_enable_irq(priv) \
  94. do { \
  95. u32 i; \
  96. for (i = 0; i < priv->num_irqs; i++) \
  97. enable_irq(priv->irqs_table[i]); \
  98. } while (0);
  99. #define cpsw_disable_irq(priv) \
  100. do { \
  101. u32 i; \
  102. for (i = 0; i < priv->num_irqs; i++) \
  103. disable_irq_nosync(priv->irqs_table[i]); \
  104. } while (0);
  105. static int debug_level;
  106. module_param(debug_level, int, 0);
  107. MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
  108. static int ale_ageout = 10;
  109. module_param(ale_ageout, int, 0);
  110. MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
  111. static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
  112. module_param(rx_packet_max, int, 0);
  113. MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
  114. struct cpsw_ss_regs {
  115. u32 id_ver;
  116. u32 soft_reset;
  117. u32 control;
  118. u32 int_control;
  119. u32 rx_thresh_en;
  120. u32 rx_en;
  121. u32 tx_en;
  122. u32 misc_en;
  123. };
  124. struct cpsw_regs {
  125. u32 id_ver;
  126. u32 control;
  127. u32 soft_reset;
  128. u32 stat_port_en;
  129. u32 ptype;
  130. };
  131. struct cpsw_slave_regs {
  132. u32 max_blks;
  133. u32 blk_cnt;
  134. u32 flow_thresh;
  135. u32 port_vlan;
  136. u32 tx_pri_map;
  137. u32 ts_ctl;
  138. u32 ts_seq_ltype;
  139. u32 ts_vlan;
  140. u32 sa_lo;
  141. u32 sa_hi;
  142. };
  143. struct cpsw_host_regs {
  144. u32 max_blks;
  145. u32 blk_cnt;
  146. u32 flow_thresh;
  147. u32 port_vlan;
  148. u32 tx_pri_map;
  149. u32 cpdma_tx_pri_map;
  150. u32 cpdma_rx_chan_map;
  151. };
  152. struct cpsw_sliver_regs {
  153. u32 id_ver;
  154. u32 mac_control;
  155. u32 mac_status;
  156. u32 soft_reset;
  157. u32 rx_maxlen;
  158. u32 __reserved_0;
  159. u32 rx_pause;
  160. u32 tx_pause;
  161. u32 __reserved_1;
  162. u32 rx_pri_map;
  163. };
  164. struct cpsw_slave {
  165. struct cpsw_slave_regs __iomem *regs;
  166. struct cpsw_sliver_regs __iomem *sliver;
  167. int slave_num;
  168. u32 mac_control;
  169. struct cpsw_slave_data *data;
  170. struct phy_device *phy;
  171. };
  172. struct cpsw_priv {
  173. spinlock_t lock;
  174. struct platform_device *pdev;
  175. struct net_device *ndev;
  176. struct resource *cpsw_res;
  177. struct resource *cpsw_ss_res;
  178. struct napi_struct napi;
  179. struct device *dev;
  180. struct cpsw_platform_data data;
  181. struct cpsw_regs __iomem *regs;
  182. struct cpsw_ss_regs __iomem *ss_regs;
  183. struct cpsw_host_regs __iomem *host_port_regs;
  184. u32 msg_enable;
  185. struct net_device_stats stats;
  186. int rx_packet_max;
  187. int host_port;
  188. struct clk *clk;
  189. u8 mac_addr[ETH_ALEN];
  190. struct cpsw_slave *slaves;
  191. struct cpdma_ctlr *dma;
  192. struct cpdma_chan *txch, *rxch;
  193. struct cpsw_ale *ale;
  194. /* snapshot of IRQ numbers */
  195. u32 irqs_table[4];
  196. u32 num_irqs;
  197. };
  198. #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
  199. #define for_each_slave(priv, func, arg...) \
  200. do { \
  201. int idx; \
  202. for (idx = 0; idx < (priv)->data.slaves; idx++) \
  203. (func)((priv)->slaves + idx, ##arg); \
  204. } while (0)
  205. static void cpsw_intr_enable(struct cpsw_priv *priv)
  206. {
  207. __raw_writel(0xFF, &priv->ss_regs->tx_en);
  208. __raw_writel(0xFF, &priv->ss_regs->rx_en);
  209. cpdma_ctlr_int_ctrl(priv->dma, true);
  210. return;
  211. }
  212. static void cpsw_intr_disable(struct cpsw_priv *priv)
  213. {
  214. __raw_writel(0, &priv->ss_regs->tx_en);
  215. __raw_writel(0, &priv->ss_regs->rx_en);
  216. cpdma_ctlr_int_ctrl(priv->dma, false);
  217. return;
  218. }
  219. void cpsw_tx_handler(void *token, int len, int status)
  220. {
  221. struct sk_buff *skb = token;
  222. struct net_device *ndev = skb->dev;
  223. struct cpsw_priv *priv = netdev_priv(ndev);
  224. if (unlikely(netif_queue_stopped(ndev)))
  225. netif_start_queue(ndev);
  226. priv->stats.tx_packets++;
  227. priv->stats.tx_bytes += len;
  228. dev_kfree_skb_any(skb);
  229. }
  230. void cpsw_rx_handler(void *token, int len, int status)
  231. {
  232. struct sk_buff *skb = token;
  233. struct net_device *ndev = skb->dev;
  234. struct cpsw_priv *priv = netdev_priv(ndev);
  235. int ret = 0;
  236. /* free and bail if we are shutting down */
  237. if (unlikely(!netif_running(ndev)) ||
  238. unlikely(!netif_carrier_ok(ndev))) {
  239. dev_kfree_skb_any(skb);
  240. return;
  241. }
  242. if (likely(status >= 0)) {
  243. skb_put(skb, len);
  244. skb->protocol = eth_type_trans(skb, ndev);
  245. netif_receive_skb(skb);
  246. priv->stats.rx_bytes += len;
  247. priv->stats.rx_packets++;
  248. skb = NULL;
  249. }
  250. if (unlikely(!netif_running(ndev))) {
  251. if (skb)
  252. dev_kfree_skb_any(skb);
  253. return;
  254. }
  255. if (likely(!skb)) {
  256. skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
  257. if (WARN_ON(!skb))
  258. return;
  259. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  260. skb_tailroom(skb), GFP_KERNEL);
  261. }
  262. WARN_ON(ret < 0);
  263. }
  264. static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
  265. {
  266. struct cpsw_priv *priv = dev_id;
  267. if (likely(netif_running(priv->ndev))) {
  268. cpsw_intr_disable(priv);
  269. cpsw_disable_irq(priv);
  270. napi_schedule(&priv->napi);
  271. }
  272. return IRQ_HANDLED;
  273. }
  274. static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  275. {
  276. if (priv->host_port == 0)
  277. return slave_num + 1;
  278. else
  279. return slave_num;
  280. }
  281. static int cpsw_poll(struct napi_struct *napi, int budget)
  282. {
  283. struct cpsw_priv *priv = napi_to_priv(napi);
  284. int num_tx, num_rx;
  285. num_tx = cpdma_chan_process(priv->txch, 128);
  286. num_rx = cpdma_chan_process(priv->rxch, budget);
  287. if (num_rx || num_tx)
  288. cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
  289. num_rx, num_tx);
  290. if (num_rx < budget) {
  291. napi_complete(napi);
  292. cpsw_intr_enable(priv);
  293. cpdma_ctlr_eoi(priv->dma);
  294. cpsw_enable_irq(priv);
  295. }
  296. return num_rx;
  297. }
  298. static inline void soft_reset(const char *module, void __iomem *reg)
  299. {
  300. unsigned long timeout = jiffies + HZ;
  301. __raw_writel(1, reg);
  302. do {
  303. cpu_relax();
  304. } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
  305. WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
  306. }
  307. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  308. ((mac)[2] << 16) | ((mac)[3] << 24))
  309. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  310. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  311. struct cpsw_priv *priv)
  312. {
  313. __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi);
  314. __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo);
  315. }
  316. static void _cpsw_adjust_link(struct cpsw_slave *slave,
  317. struct cpsw_priv *priv, bool *link)
  318. {
  319. struct phy_device *phy = slave->phy;
  320. u32 mac_control = 0;
  321. u32 slave_port;
  322. if (!phy)
  323. return;
  324. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  325. if (phy->link) {
  326. mac_control = priv->data.mac_control;
  327. /* enable forwarding */
  328. cpsw_ale_control_set(priv->ale, slave_port,
  329. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  330. if (phy->speed == 1000)
  331. mac_control |= BIT(7); /* GIGABITEN */
  332. if (phy->duplex)
  333. mac_control |= BIT(0); /* FULLDUPLEXEN */
  334. *link = true;
  335. } else {
  336. mac_control = 0;
  337. /* disable forwarding */
  338. cpsw_ale_control_set(priv->ale, slave_port,
  339. ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
  340. }
  341. if (mac_control != slave->mac_control) {
  342. phy_print_status(phy);
  343. __raw_writel(mac_control, &slave->sliver->mac_control);
  344. }
  345. slave->mac_control = mac_control;
  346. }
  347. static void cpsw_adjust_link(struct net_device *ndev)
  348. {
  349. struct cpsw_priv *priv = netdev_priv(ndev);
  350. bool link = false;
  351. for_each_slave(priv, _cpsw_adjust_link, priv, &link);
  352. if (link) {
  353. netif_carrier_on(ndev);
  354. if (netif_running(ndev))
  355. netif_wake_queue(ndev);
  356. } else {
  357. netif_carrier_off(ndev);
  358. netif_stop_queue(ndev);
  359. }
  360. }
  361. static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
  362. {
  363. static char *leader = "........................................";
  364. if (!val)
  365. return 0;
  366. else
  367. return snprintf(buf, maxlen, "%s %s %10d\n", name,
  368. leader + strlen(name), val);
  369. }
  370. static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
  371. {
  372. char name[32];
  373. u32 slave_port;
  374. sprintf(name, "slave-%d", slave->slave_num);
  375. soft_reset(name, &slave->sliver->soft_reset);
  376. /* setup priority mapping */
  377. __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
  378. __raw_writel(TX_PRIORITY_MAPPING, &slave->regs->tx_pri_map);
  379. /* setup max packet size, and mac address */
  380. __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
  381. cpsw_set_slave_mac(slave, priv);
  382. slave->mac_control = 0; /* no link yet */
  383. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  384. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  385. 1 << slave_port, 0, ALE_MCAST_FWD_2);
  386. slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
  387. &cpsw_adjust_link, 0, slave->data->phy_if);
  388. if (IS_ERR(slave->phy)) {
  389. dev_err(priv->dev, "phy %s not found on slave %d\n",
  390. slave->data->phy_id, slave->slave_num);
  391. slave->phy = NULL;
  392. } else {
  393. dev_info(priv->dev, "phy found : id is : 0x%x\n",
  394. slave->phy->phy_id);
  395. phy_start(slave->phy);
  396. }
  397. }
  398. static void cpsw_init_host_port(struct cpsw_priv *priv)
  399. {
  400. /* soft reset the controller and initialize ale */
  401. soft_reset("cpsw", &priv->regs->soft_reset);
  402. cpsw_ale_start(priv->ale);
  403. /* switch to vlan unaware mode */
  404. cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
  405. /* setup host port priority mapping */
  406. __raw_writel(CPDMA_TX_PRIORITY_MAP,
  407. &priv->host_port_regs->cpdma_tx_pri_map);
  408. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  409. cpsw_ale_control_set(priv->ale, priv->host_port,
  410. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  411. cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
  412. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  413. 1 << priv->host_port, 0, ALE_MCAST_FWD_2);
  414. }
  415. static int cpsw_ndo_open(struct net_device *ndev)
  416. {
  417. struct cpsw_priv *priv = netdev_priv(ndev);
  418. int i, ret;
  419. u32 reg;
  420. cpsw_intr_disable(priv);
  421. netif_carrier_off(ndev);
  422. pm_runtime_get_sync(&priv->pdev->dev);
  423. reg = __raw_readl(&priv->regs->id_ver);
  424. dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
  425. CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
  426. CPSW_RTL_VERSION(reg));
  427. /* initialize host and slave ports */
  428. cpsw_init_host_port(priv);
  429. for_each_slave(priv, cpsw_slave_open, priv);
  430. /* setup tx dma to fixed prio and zero offset */
  431. cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
  432. cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
  433. /* disable priority elevation and enable statistics on all ports */
  434. __raw_writel(0, &priv->regs->ptype);
  435. /* enable statistics collection only on the host port */
  436. __raw_writel(0x7, &priv->regs->stat_port_en);
  437. if (WARN_ON(!priv->data.rx_descs))
  438. priv->data.rx_descs = 128;
  439. for (i = 0; i < priv->data.rx_descs; i++) {
  440. struct sk_buff *skb;
  441. ret = -ENOMEM;
  442. skb = netdev_alloc_skb_ip_align(priv->ndev,
  443. priv->rx_packet_max);
  444. if (!skb)
  445. break;
  446. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  447. skb_tailroom(skb), GFP_KERNEL);
  448. if (WARN_ON(ret < 0))
  449. break;
  450. }
  451. /* continue even if we didn't manage to submit all receive descs */
  452. cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
  453. cpdma_ctlr_start(priv->dma);
  454. cpsw_intr_enable(priv);
  455. napi_enable(&priv->napi);
  456. cpdma_ctlr_eoi(priv->dma);
  457. return 0;
  458. }
  459. static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
  460. {
  461. if (!slave->phy)
  462. return;
  463. phy_stop(slave->phy);
  464. phy_disconnect(slave->phy);
  465. slave->phy = NULL;
  466. }
  467. static int cpsw_ndo_stop(struct net_device *ndev)
  468. {
  469. struct cpsw_priv *priv = netdev_priv(ndev);
  470. cpsw_info(priv, ifdown, "shutting down cpsw device\n");
  471. cpsw_intr_disable(priv);
  472. cpdma_ctlr_int_ctrl(priv->dma, false);
  473. cpdma_ctlr_stop(priv->dma);
  474. netif_stop_queue(priv->ndev);
  475. napi_disable(&priv->napi);
  476. netif_carrier_off(priv->ndev);
  477. cpsw_ale_stop(priv->ale);
  478. for_each_slave(priv, cpsw_slave_stop, priv);
  479. pm_runtime_put_sync(&priv->pdev->dev);
  480. return 0;
  481. }
  482. static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
  483. struct net_device *ndev)
  484. {
  485. struct cpsw_priv *priv = netdev_priv(ndev);
  486. int ret;
  487. ndev->trans_start = jiffies;
  488. if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
  489. cpsw_err(priv, tx_err, "packet pad failed\n");
  490. priv->stats.tx_dropped++;
  491. return NETDEV_TX_OK;
  492. }
  493. ret = cpdma_chan_submit(priv->txch, skb, skb->data,
  494. skb->len, GFP_KERNEL);
  495. if (unlikely(ret != 0)) {
  496. cpsw_err(priv, tx_err, "desc submit failed\n");
  497. goto fail;
  498. }
  499. return NETDEV_TX_OK;
  500. fail:
  501. priv->stats.tx_dropped++;
  502. netif_stop_queue(ndev);
  503. return NETDEV_TX_BUSY;
  504. }
  505. static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
  506. {
  507. /*
  508. * The switch cannot operate in promiscuous mode without substantial
  509. * headache. For promiscuous mode to work, we would need to put the
  510. * ALE in bypass mode and route all traffic to the host port.
  511. * Subsequently, the host will need to operate as a "bridge", learn,
  512. * and flood as needed. For now, we simply complain here and
  513. * do nothing about it :-)
  514. */
  515. if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
  516. dev_err(&ndev->dev, "promiscuity ignored!\n");
  517. /*
  518. * The switch cannot filter multicast traffic unless it is configured
  519. * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
  520. * whole bunch of additional logic that this driver does not implement
  521. * at present.
  522. */
  523. if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
  524. dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
  525. }
  526. static void cpsw_ndo_tx_timeout(struct net_device *ndev)
  527. {
  528. struct cpsw_priv *priv = netdev_priv(ndev);
  529. cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
  530. priv->stats.tx_errors++;
  531. cpsw_intr_disable(priv);
  532. cpdma_ctlr_int_ctrl(priv->dma, false);
  533. cpdma_chan_stop(priv->txch);
  534. cpdma_chan_start(priv->txch);
  535. cpdma_ctlr_int_ctrl(priv->dma, true);
  536. cpsw_intr_enable(priv);
  537. cpdma_ctlr_eoi(priv->dma);
  538. }
  539. static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
  540. {
  541. struct cpsw_priv *priv = netdev_priv(ndev);
  542. return &priv->stats;
  543. }
  544. #ifdef CONFIG_NET_POLL_CONTROLLER
  545. static void cpsw_ndo_poll_controller(struct net_device *ndev)
  546. {
  547. struct cpsw_priv *priv = netdev_priv(ndev);
  548. cpsw_intr_disable(priv);
  549. cpdma_ctlr_int_ctrl(priv->dma, false);
  550. cpsw_interrupt(ndev->irq, priv);
  551. cpdma_ctlr_int_ctrl(priv->dma, true);
  552. cpsw_intr_enable(priv);
  553. cpdma_ctlr_eoi(priv->dma);
  554. }
  555. #endif
  556. static const struct net_device_ops cpsw_netdev_ops = {
  557. .ndo_open = cpsw_ndo_open,
  558. .ndo_stop = cpsw_ndo_stop,
  559. .ndo_start_xmit = cpsw_ndo_start_xmit,
  560. .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
  561. .ndo_validate_addr = eth_validate_addr,
  562. .ndo_change_mtu = eth_change_mtu,
  563. .ndo_tx_timeout = cpsw_ndo_tx_timeout,
  564. .ndo_get_stats = cpsw_ndo_get_stats,
  565. #ifdef CONFIG_NET_POLL_CONTROLLER
  566. .ndo_poll_controller = cpsw_ndo_poll_controller,
  567. #endif
  568. };
  569. static void cpsw_get_drvinfo(struct net_device *ndev,
  570. struct ethtool_drvinfo *info)
  571. {
  572. struct cpsw_priv *priv = netdev_priv(ndev);
  573. strcpy(info->driver, "TI CPSW Driver v1.0");
  574. strcpy(info->version, "1.0");
  575. strcpy(info->bus_info, priv->pdev->name);
  576. }
  577. static u32 cpsw_get_msglevel(struct net_device *ndev)
  578. {
  579. struct cpsw_priv *priv = netdev_priv(ndev);
  580. return priv->msg_enable;
  581. }
  582. static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
  583. {
  584. struct cpsw_priv *priv = netdev_priv(ndev);
  585. priv->msg_enable = value;
  586. }
  587. static const struct ethtool_ops cpsw_ethtool_ops = {
  588. .get_drvinfo = cpsw_get_drvinfo,
  589. .get_msglevel = cpsw_get_msglevel,
  590. .set_msglevel = cpsw_set_msglevel,
  591. .get_link = ethtool_op_get_link,
  592. };
  593. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  594. {
  595. void __iomem *regs = priv->regs;
  596. int slave_num = slave->slave_num;
  597. struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
  598. slave->data = data;
  599. slave->regs = regs + data->slave_reg_ofs;
  600. slave->sliver = regs + data->sliver_reg_ofs;
  601. }
  602. static int cpsw_probe_dt(struct cpsw_platform_data *data,
  603. struct platform_device *pdev)
  604. {
  605. struct device_node *node = pdev->dev.of_node;
  606. struct device_node *slave_node;
  607. int i = 0, ret;
  608. u32 prop;
  609. if (!node)
  610. return -EINVAL;
  611. if (of_property_read_u32(node, "slaves", &prop)) {
  612. pr_err("Missing slaves property in the DT.\n");
  613. return -EINVAL;
  614. }
  615. data->slaves = prop;
  616. data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) *
  617. data->slaves, GFP_KERNEL);
  618. if (!data->slave_data) {
  619. pr_err("Could not allocate slave memory.\n");
  620. return -EINVAL;
  621. }
  622. data->no_bd_ram = of_property_read_bool(node, "no_bd_ram");
  623. if (of_property_read_u32(node, "cpdma_channels", &prop)) {
  624. pr_err("Missing cpdma_channels property in the DT.\n");
  625. ret = -EINVAL;
  626. goto error_ret;
  627. }
  628. data->channels = prop;
  629. if (of_property_read_u32(node, "host_port_no", &prop)) {
  630. pr_err("Missing host_port_no property in the DT.\n");
  631. ret = -EINVAL;
  632. goto error_ret;
  633. }
  634. data->host_port_num = prop;
  635. if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) {
  636. pr_err("Missing cpdma_reg_ofs property in the DT.\n");
  637. ret = -EINVAL;
  638. goto error_ret;
  639. }
  640. data->cpdma_reg_ofs = prop;
  641. if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) {
  642. pr_err("Missing cpdma_sram_ofs property in the DT.\n");
  643. ret = -EINVAL;
  644. goto error_ret;
  645. }
  646. data->cpdma_sram_ofs = prop;
  647. if (of_property_read_u32(node, "ale_reg_ofs", &prop)) {
  648. pr_err("Missing ale_reg_ofs property in the DT.\n");
  649. ret = -EINVAL;
  650. goto error_ret;
  651. }
  652. data->ale_reg_ofs = prop;
  653. if (of_property_read_u32(node, "ale_entries", &prop)) {
  654. pr_err("Missing ale_entries property in the DT.\n");
  655. ret = -EINVAL;
  656. goto error_ret;
  657. }
  658. data->ale_entries = prop;
  659. if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) {
  660. pr_err("Missing host_port_reg_ofs property in the DT.\n");
  661. ret = -EINVAL;
  662. goto error_ret;
  663. }
  664. data->host_port_reg_ofs = prop;
  665. if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) {
  666. pr_err("Missing hw_stats_reg_ofs property in the DT.\n");
  667. ret = -EINVAL;
  668. goto error_ret;
  669. }
  670. data->hw_stats_reg_ofs = prop;
  671. if (of_property_read_u32(node, "bd_ram_ofs", &prop)) {
  672. pr_err("Missing bd_ram_ofs property in the DT.\n");
  673. ret = -EINVAL;
  674. goto error_ret;
  675. }
  676. data->bd_ram_ofs = prop;
  677. if (of_property_read_u32(node, "bd_ram_size", &prop)) {
  678. pr_err("Missing bd_ram_size property in the DT.\n");
  679. ret = -EINVAL;
  680. goto error_ret;
  681. }
  682. data->bd_ram_size = prop;
  683. if (of_property_read_u32(node, "rx_descs", &prop)) {
  684. pr_err("Missing rx_descs property in the DT.\n");
  685. ret = -EINVAL;
  686. goto error_ret;
  687. }
  688. data->rx_descs = prop;
  689. if (of_property_read_u32(node, "mac_control", &prop)) {
  690. pr_err("Missing mac_control property in the DT.\n");
  691. ret = -EINVAL;
  692. goto error_ret;
  693. }
  694. data->mac_control = prop;
  695. for_each_child_of_node(node, slave_node) {
  696. struct cpsw_slave_data *slave_data = data->slave_data + i;
  697. const char *phy_id = NULL;
  698. const void *mac_addr = NULL;
  699. if (of_property_read_string(slave_node, "phy_id", &phy_id)) {
  700. pr_err("Missing slave[%d] phy_id property\n", i);
  701. ret = -EINVAL;
  702. goto error_ret;
  703. }
  704. slave_data->phy_id = phy_id;
  705. if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) {
  706. pr_err("Missing slave[%d] slave_reg_ofs property\n", i);
  707. ret = -EINVAL;
  708. goto error_ret;
  709. }
  710. slave_data->slave_reg_ofs = prop;
  711. if (of_property_read_u32(slave_node, "sliver_reg_ofs",
  712. &prop)) {
  713. pr_err("Missing slave[%d] sliver_reg_ofs property\n",
  714. i);
  715. ret = -EINVAL;
  716. goto error_ret;
  717. }
  718. slave_data->sliver_reg_ofs = prop;
  719. mac_addr = of_get_mac_address(slave_node);
  720. if (mac_addr)
  721. memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
  722. i++;
  723. }
  724. return 0;
  725. error_ret:
  726. kfree(data->slave_data);
  727. return ret;
  728. }
  729. static int __devinit cpsw_probe(struct platform_device *pdev)
  730. {
  731. struct cpsw_platform_data *data = pdev->dev.platform_data;
  732. struct net_device *ndev;
  733. struct cpsw_priv *priv;
  734. struct cpdma_params dma_params;
  735. struct cpsw_ale_params ale_params;
  736. void __iomem *regs;
  737. struct resource *res;
  738. int ret = 0, i, k = 0;
  739. ndev = alloc_etherdev(sizeof(struct cpsw_priv));
  740. if (!ndev) {
  741. pr_err("error allocating net_device\n");
  742. return -ENOMEM;
  743. }
  744. platform_set_drvdata(pdev, ndev);
  745. priv = netdev_priv(ndev);
  746. spin_lock_init(&priv->lock);
  747. priv->pdev = pdev;
  748. priv->ndev = ndev;
  749. priv->dev = &ndev->dev;
  750. priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
  751. priv->rx_packet_max = max(rx_packet_max, 128);
  752. if (cpsw_probe_dt(&priv->data, pdev)) {
  753. pr_err("cpsw: platform data missing\n");
  754. ret = -ENODEV;
  755. goto clean_ndev_ret;
  756. }
  757. data = &priv->data;
  758. if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
  759. memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
  760. pr_info("Detected MACID = %pM", priv->mac_addr);
  761. } else {
  762. eth_random_addr(priv->mac_addr);
  763. pr_info("Random MACID = %pM", priv->mac_addr);
  764. }
  765. memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
  766. priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
  767. GFP_KERNEL);
  768. if (!priv->slaves) {
  769. ret = -EBUSY;
  770. goto clean_ndev_ret;
  771. }
  772. for (i = 0; i < data->slaves; i++)
  773. priv->slaves[i].slave_num = i;
  774. pm_runtime_enable(&pdev->dev);
  775. priv->clk = clk_get(&pdev->dev, "fck");
  776. if (IS_ERR(priv->clk)) {
  777. dev_err(&pdev->dev, "fck is not found\n");
  778. ret = -ENODEV;
  779. goto clean_slave_ret;
  780. }
  781. priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  782. if (!priv->cpsw_res) {
  783. dev_err(priv->dev, "error getting i/o resource\n");
  784. ret = -ENOENT;
  785. goto clean_clk_ret;
  786. }
  787. if (!request_mem_region(priv->cpsw_res->start,
  788. resource_size(priv->cpsw_res), ndev->name)) {
  789. dev_err(priv->dev, "failed request i/o region\n");
  790. ret = -ENXIO;
  791. goto clean_clk_ret;
  792. }
  793. regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
  794. if (!regs) {
  795. dev_err(priv->dev, "unable to map i/o region\n");
  796. goto clean_cpsw_iores_ret;
  797. }
  798. priv->regs = regs;
  799. priv->host_port = data->host_port_num;
  800. priv->host_port_regs = regs + data->host_port_reg_ofs;
  801. priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  802. if (!priv->cpsw_ss_res) {
  803. dev_err(priv->dev, "error getting i/o resource\n");
  804. ret = -ENOENT;
  805. goto clean_clk_ret;
  806. }
  807. if (!request_mem_region(priv->cpsw_ss_res->start,
  808. resource_size(priv->cpsw_ss_res), ndev->name)) {
  809. dev_err(priv->dev, "failed request i/o region\n");
  810. ret = -ENXIO;
  811. goto clean_clk_ret;
  812. }
  813. regs = ioremap(priv->cpsw_ss_res->start,
  814. resource_size(priv->cpsw_ss_res));
  815. if (!regs) {
  816. dev_err(priv->dev, "unable to map i/o region\n");
  817. goto clean_cpsw_ss_iores_ret;
  818. }
  819. priv->ss_regs = regs;
  820. for_each_slave(priv, cpsw_slave_init, priv);
  821. memset(&dma_params, 0, sizeof(dma_params));
  822. dma_params.dev = &pdev->dev;
  823. dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs,
  824. data->cpdma_reg_ofs);
  825. dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs,
  826. data->cpdma_reg_ofs);
  827. dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs,
  828. data->cpdma_reg_ofs);
  829. dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs,
  830. data->cpdma_sram_ofs);
  831. dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs,
  832. data->cpdma_sram_ofs);
  833. dma_params.txcp = cpsw_dma_txcp((u32)priv->regs,
  834. data->cpdma_sram_ofs);
  835. dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs,
  836. data->cpdma_sram_ofs);
  837. dma_params.num_chan = data->channels;
  838. dma_params.has_soft_reset = true;
  839. dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
  840. dma_params.desc_mem_size = data->bd_ram_size;
  841. dma_params.desc_align = 16;
  842. dma_params.has_ext_regs = true;
  843. dma_params.desc_mem_phys = data->no_bd_ram ? 0 :
  844. (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
  845. dma_params.desc_hw_addr = data->hw_ram_addr ?
  846. data->hw_ram_addr : dma_params.desc_mem_phys ;
  847. priv->dma = cpdma_ctlr_create(&dma_params);
  848. if (!priv->dma) {
  849. dev_err(priv->dev, "error initializing dma\n");
  850. ret = -ENOMEM;
  851. goto clean_iomap_ret;
  852. }
  853. priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
  854. cpsw_tx_handler);
  855. priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
  856. cpsw_rx_handler);
  857. if (WARN_ON(!priv->txch || !priv->rxch)) {
  858. dev_err(priv->dev, "error initializing dma channels\n");
  859. ret = -ENOMEM;
  860. goto clean_dma_ret;
  861. }
  862. memset(&ale_params, 0, sizeof(ale_params));
  863. ale_params.dev = &ndev->dev;
  864. ale_params.ale_regs = (void *)((u32)priv->regs) +
  865. ((u32)data->ale_reg_ofs);
  866. ale_params.ale_ageout = ale_ageout;
  867. ale_params.ale_entries = data->ale_entries;
  868. ale_params.ale_ports = data->slaves;
  869. priv->ale = cpsw_ale_create(&ale_params);
  870. if (!priv->ale) {
  871. dev_err(priv->dev, "error initializing ale engine\n");
  872. ret = -ENODEV;
  873. goto clean_dma_ret;
  874. }
  875. ndev->irq = platform_get_irq(pdev, 0);
  876. if (ndev->irq < 0) {
  877. dev_err(priv->dev, "error getting irq resource\n");
  878. ret = -ENOENT;
  879. goto clean_ale_ret;
  880. }
  881. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
  882. for (i = res->start; i <= res->end; i++) {
  883. if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
  884. dev_name(&pdev->dev), priv)) {
  885. dev_err(priv->dev, "error attaching irq\n");
  886. goto clean_ale_ret;
  887. }
  888. priv->irqs_table[k] = i;
  889. priv->num_irqs = k;
  890. }
  891. k++;
  892. }
  893. ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */
  894. ndev->netdev_ops = &cpsw_netdev_ops;
  895. SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
  896. netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
  897. /* register the network device */
  898. SET_NETDEV_DEV(ndev, &pdev->dev);
  899. ret = register_netdev(ndev);
  900. if (ret) {
  901. dev_err(priv->dev, "error registering net device\n");
  902. ret = -ENODEV;
  903. goto clean_irq_ret;
  904. }
  905. cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
  906. priv->cpsw_res->start, ndev->irq);
  907. return 0;
  908. clean_irq_ret:
  909. free_irq(ndev->irq, priv);
  910. clean_ale_ret:
  911. cpsw_ale_destroy(priv->ale);
  912. clean_dma_ret:
  913. cpdma_chan_destroy(priv->txch);
  914. cpdma_chan_destroy(priv->rxch);
  915. cpdma_ctlr_destroy(priv->dma);
  916. clean_iomap_ret:
  917. iounmap(priv->regs);
  918. clean_cpsw_ss_iores_ret:
  919. release_mem_region(priv->cpsw_ss_res->start,
  920. resource_size(priv->cpsw_ss_res));
  921. clean_cpsw_iores_ret:
  922. release_mem_region(priv->cpsw_res->start,
  923. resource_size(priv->cpsw_res));
  924. clean_clk_ret:
  925. clk_put(priv->clk);
  926. clean_slave_ret:
  927. pm_runtime_disable(&pdev->dev);
  928. kfree(priv->slaves);
  929. clean_ndev_ret:
  930. free_netdev(ndev);
  931. return ret;
  932. }
  933. static int __devexit cpsw_remove(struct platform_device *pdev)
  934. {
  935. struct net_device *ndev = platform_get_drvdata(pdev);
  936. struct cpsw_priv *priv = netdev_priv(ndev);
  937. pr_info("removing device");
  938. platform_set_drvdata(pdev, NULL);
  939. free_irq(ndev->irq, priv);
  940. cpsw_ale_destroy(priv->ale);
  941. cpdma_chan_destroy(priv->txch);
  942. cpdma_chan_destroy(priv->rxch);
  943. cpdma_ctlr_destroy(priv->dma);
  944. iounmap(priv->regs);
  945. release_mem_region(priv->cpsw_res->start,
  946. resource_size(priv->cpsw_res));
  947. release_mem_region(priv->cpsw_ss_res->start,
  948. resource_size(priv->cpsw_ss_res));
  949. pm_runtime_disable(&pdev->dev);
  950. clk_put(priv->clk);
  951. kfree(priv->slaves);
  952. free_netdev(ndev);
  953. return 0;
  954. }
  955. static int cpsw_suspend(struct device *dev)
  956. {
  957. struct platform_device *pdev = to_platform_device(dev);
  958. struct net_device *ndev = platform_get_drvdata(pdev);
  959. if (netif_running(ndev))
  960. cpsw_ndo_stop(ndev);
  961. pm_runtime_put_sync(&pdev->dev);
  962. return 0;
  963. }
  964. static int cpsw_resume(struct device *dev)
  965. {
  966. struct platform_device *pdev = to_platform_device(dev);
  967. struct net_device *ndev = platform_get_drvdata(pdev);
  968. pm_runtime_get_sync(&pdev->dev);
  969. if (netif_running(ndev))
  970. cpsw_ndo_open(ndev);
  971. return 0;
  972. }
  973. static const struct dev_pm_ops cpsw_pm_ops = {
  974. .suspend = cpsw_suspend,
  975. .resume = cpsw_resume,
  976. };
  977. static const struct of_device_id cpsw_of_mtable[] = {
  978. { .compatible = "ti,cpsw", },
  979. { /* sentinel */ },
  980. };
  981. static struct platform_driver cpsw_driver = {
  982. .driver = {
  983. .name = "cpsw",
  984. .owner = THIS_MODULE,
  985. .pm = &cpsw_pm_ops,
  986. .of_match_table = of_match_ptr(cpsw_of_mtable),
  987. },
  988. .probe = cpsw_probe,
  989. .remove = __devexit_p(cpsw_remove),
  990. };
  991. static int __init cpsw_init(void)
  992. {
  993. return platform_driver_register(&cpsw_driver);
  994. }
  995. late_initcall(cpsw_init);
  996. static void __exit cpsw_exit(void)
  997. {
  998. platform_driver_unregister(&cpsw_driver);
  999. }
  1000. module_exit(cpsw_exit);
  1001. MODULE_LICENSE("GPL");
  1002. MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
  1003. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  1004. MODULE_DESCRIPTION("TI CPSW Ethernet driver");