drv_mpipe_intf.h 23 KB

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  1. /*
  2. * Copyright 2011 Tilera Corporation. All Rights Reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation, version 2.
  7. *
  8. * This program is distributed in the hope that it will be useful, but
  9. * WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11. * NON INFRINGEMENT. See the GNU General Public License for
  12. * more details.
  13. */
  14. /**
  15. * Interface definitions for the mpipe driver.
  16. */
  17. #ifndef _SYS_HV_DRV_MPIPE_INTF_H
  18. #define _SYS_HV_DRV_MPIPE_INTF_H
  19. #include <arch/mpipe.h>
  20. #include <arch/mpipe_constants.h>
  21. /** Number of buffer stacks (32). */
  22. #define HV_MPIPE_NUM_BUFFER_STACKS \
  23. (MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH)
  24. /** Number of NotifRings (256). */
  25. #define HV_MPIPE_NUM_NOTIF_RINGS (MPIPE_NUM_NOTIF_RINGS)
  26. /** Number of NotifGroups (32). */
  27. #define HV_MPIPE_NUM_NOTIF_GROUPS (MPIPE_NUM_NOTIF_GROUPS)
  28. /** Number of buckets (4160). */
  29. #define HV_MPIPE_NUM_BUCKETS (MPIPE_NUM_BUCKETS)
  30. /** Number of "lo" buckets (4096). */
  31. #define HV_MPIPE_NUM_LO_BUCKETS 4096
  32. /** Number of "hi" buckets (64). */
  33. #define HV_MPIPE_NUM_HI_BUCKETS \
  34. (HV_MPIPE_NUM_BUCKETS - HV_MPIPE_NUM_LO_BUCKETS)
  35. /** Number of edma rings (24). */
  36. #define HV_MPIPE_NUM_EDMA_RINGS \
  37. (MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH)
  38. /** A flag bit indicating a fixed resource allocation. */
  39. #define HV_MPIPE_ALLOC_FIXED 0x01
  40. /** Offset for the config register MMIO region. */
  41. #define HV_MPIPE_CONFIG_MMIO_OFFSET \
  42. (MPIPE_MMIO_ADDR__REGION_VAL_CFG << MPIPE_MMIO_ADDR__REGION_SHIFT)
  43. /** Size of the config register MMIO region. */
  44. #define HV_MPIPE_CONFIG_MMIO_SIZE (64 * 1024)
  45. /** Offset for the config register MMIO region. */
  46. #define HV_MPIPE_FAST_MMIO_OFFSET \
  47. (MPIPE_MMIO_ADDR__REGION_VAL_IDMA << MPIPE_MMIO_ADDR__REGION_SHIFT)
  48. /** Size of the fast register MMIO region (IDMA, EDMA, buffer stack). */
  49. #define HV_MPIPE_FAST_MMIO_SIZE \
  50. ((MPIPE_MMIO_ADDR__REGION_VAL_BSM + 1 - MPIPE_MMIO_ADDR__REGION_VAL_IDMA) \
  51. << MPIPE_MMIO_ADDR__REGION_SHIFT)
  52. /*
  53. * Each type of resource allocation comes in quantized chunks, where
  54. * XXX_BITS is the number of chunks, and XXX_RES_PER_BIT is the number
  55. * of resources in each chunk.
  56. */
  57. /** Number of buffer stack chunks available (32). */
  58. #define HV_MPIPE_ALLOC_BUFFER_STACKS_BITS \
  59. MPIPE_MMIO_INIT_DAT_GX36_1__BUFFER_STACK_MASK_WIDTH
  60. /** Granularity of buffer stack allocation (1). */
  61. #define HV_MPIPE_ALLOC_BUFFER_STACKS_RES_PER_BIT \
  62. (HV_MPIPE_NUM_BUFFER_STACKS / HV_MPIPE_ALLOC_BUFFER_STACKS_BITS)
  63. /** Number of NotifRing chunks available (32). */
  64. #define HV_MPIPE_ALLOC_NOTIF_RINGS_BITS \
  65. MPIPE_MMIO_INIT_DAT_GX36_0__NOTIF_RING_MASK_WIDTH
  66. /** Granularity of NotifRing allocation (8). */
  67. #define HV_MPIPE_ALLOC_NOTIF_RINGS_RES_PER_BIT \
  68. (HV_MPIPE_NUM_NOTIF_RINGS / HV_MPIPE_ALLOC_NOTIF_RINGS_BITS)
  69. /** Number of NotifGroup chunks available (32). */
  70. #define HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS \
  71. HV_MPIPE_NUM_NOTIF_GROUPS
  72. /** Granularity of NotifGroup allocation (1). */
  73. #define HV_MPIPE_ALLOC_NOTIF_GROUPS_RES_PER_BIT \
  74. (HV_MPIPE_NUM_NOTIF_GROUPS / HV_MPIPE_ALLOC_NOTIF_GROUPS_BITS)
  75. /** Number of lo bucket chunks available (16). */
  76. #define HV_MPIPE_ALLOC_LO_BUCKETS_BITS \
  77. MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_LO_WIDTH
  78. /** Granularity of lo bucket allocation (256). */
  79. #define HV_MPIPE_ALLOC_LO_BUCKETS_RES_PER_BIT \
  80. (HV_MPIPE_NUM_LO_BUCKETS / HV_MPIPE_ALLOC_LO_BUCKETS_BITS)
  81. /** Number of hi bucket chunks available (16). */
  82. #define HV_MPIPE_ALLOC_HI_BUCKETS_BITS \
  83. MPIPE_MMIO_INIT_DAT_GX36_0__BUCKET_RELEASE_MASK_HI_WIDTH
  84. /** Granularity of hi bucket allocation (4). */
  85. #define HV_MPIPE_ALLOC_HI_BUCKETS_RES_PER_BIT \
  86. (HV_MPIPE_NUM_HI_BUCKETS / HV_MPIPE_ALLOC_HI_BUCKETS_BITS)
  87. /** Number of eDMA ring chunks available (24). */
  88. #define HV_MPIPE_ALLOC_EDMA_RINGS_BITS \
  89. MPIPE_MMIO_INIT_DAT_GX36_1__EDMA_POST_MASK_WIDTH
  90. /** Granularity of eDMA ring allocation (1). */
  91. #define HV_MPIPE_ALLOC_EDMA_RINGS_RES_PER_BIT \
  92. (HV_MPIPE_NUM_EDMA_RINGS / HV_MPIPE_ALLOC_EDMA_RINGS_BITS)
  93. /** Bit vector encoding which NotifRings are in a NotifGroup. */
  94. typedef struct
  95. {
  96. /** The actual bits. */
  97. uint64_t ring_mask[4];
  98. } gxio_mpipe_notif_group_bits_t;
  99. /** Another name for MPIPE_LBL_INIT_DAT_BSTS_TBL_t. */
  100. typedef MPIPE_LBL_INIT_DAT_BSTS_TBL_t gxio_mpipe_bucket_info_t;
  101. /** Eight buffer stack ids. */
  102. typedef struct
  103. {
  104. /** The stacks. */
  105. uint8_t stacks[8];
  106. } gxio_mpipe_rules_stacks_t;
  107. /** A destination mac address. */
  108. typedef struct
  109. {
  110. /** The octets. */
  111. uint8_t octets[6];
  112. } gxio_mpipe_rules_dmac_t;
  113. /** A vlan. */
  114. typedef uint16_t gxio_mpipe_rules_vlan_t;
  115. /** Maximum number of characters in a link name. */
  116. #define GXIO_MPIPE_LINK_NAME_LEN 32
  117. /** Structure holding a link name. Only needed, and only typedef'ed,
  118. * because the IORPC stub generator only handles types which are single
  119. * words coming before the parameter name. */
  120. typedef struct
  121. {
  122. /** The name itself. */
  123. char name[GXIO_MPIPE_LINK_NAME_LEN];
  124. }
  125. _gxio_mpipe_link_name_t;
  126. /** Maximum number of characters in a symbol name. */
  127. #define GXIO_MPIPE_SYMBOL_NAME_LEN 128
  128. /** Structure holding a symbol name. Only needed, and only typedef'ed,
  129. * because the IORPC stub generator only handles types which are single
  130. * words coming before the parameter name. */
  131. typedef struct
  132. {
  133. /** The name itself. */
  134. char name[GXIO_MPIPE_SYMBOL_NAME_LEN];
  135. }
  136. _gxio_mpipe_symbol_name_t;
  137. /** Structure holding a MAC address. */
  138. typedef struct
  139. {
  140. /** The address. */
  141. uint8_t mac[6];
  142. }
  143. _gxio_mpipe_link_mac_t;
  144. /** Request shared data permission -- that is, the ability to send and
  145. * receive packets -- on the specified link. Other processes may also
  146. * request shared data permission on the same link.
  147. *
  148. * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
  149. * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
  150. * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
  151. */
  152. #define GXIO_MPIPE_LINK_DATA 0x00000001UL
  153. /** Do not request data permission on the specified link.
  154. *
  155. * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
  156. * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
  157. * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
  158. */
  159. #define GXIO_MPIPE_LINK_NO_DATA 0x00000002UL
  160. /** Request exclusive data permission -- that is, the ability to send and
  161. * receive packets -- on the specified link. No other processes may
  162. * request data permission on this link, and if any process already has
  163. * data permission on it, this open will fail.
  164. *
  165. * No more than one of ::GXIO_MPIPE_LINK_DATA, ::GXIO_MPIPE_LINK_NO_DATA,
  166. * or ::GXIO_MPIPE_LINK_EXCL_DATA may be specifed in a gxio_mpipe_link_open()
  167. * call. If none are specified, ::GXIO_MPIPE_LINK_DATA is assumed.
  168. */
  169. #define GXIO_MPIPE_LINK_EXCL_DATA 0x00000004UL
  170. /** Request shared stats permission -- that is, the ability to read and write
  171. * registers which contain link statistics, and to get link attributes --
  172. * on the specified link. Other processes may also request shared stats
  173. * permission on the same link.
  174. *
  175. * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
  176. * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
  177. * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
  178. */
  179. #define GXIO_MPIPE_LINK_STATS 0x00000008UL
  180. /** Do not request stats permission on the specified link.
  181. *
  182. * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
  183. * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
  184. * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
  185. */
  186. #define GXIO_MPIPE_LINK_NO_STATS 0x00000010UL
  187. /** Request exclusive stats permission -- that is, the ability to read and
  188. * write registers which contain link statistics, and to get link
  189. * attributes -- on the specified link. No other processes may request
  190. * stats permission on this link, and if any process already
  191. * has stats permission on it, this open will fail.
  192. *
  193. * Requesting exclusive stats permission is normally a very bad idea, since
  194. * it prevents programs like mpipe-stat from providing information on this
  195. * link. Applications should only do this if they use MAC statistics
  196. * registers, and cannot tolerate any of the clear-on-read registers being
  197. * reset by other statistics programs.
  198. *
  199. * No more than one of ::GXIO_MPIPE_LINK_STATS, ::GXIO_MPIPE_LINK_NO_STATS,
  200. * or ::GXIO_MPIPE_LINK_EXCL_STATS may be specifed in a gxio_mpipe_link_open()
  201. * call. If none are specified, ::GXIO_MPIPE_LINK_STATS is assumed.
  202. */
  203. #define GXIO_MPIPE_LINK_EXCL_STATS 0x00000020UL
  204. /** Request shared control permission -- that is, the ability to modify link
  205. * attributes, and read and write MAC and MDIO registers -- on the
  206. * specified link. Other processes may also request shared control
  207. * permission on the same link.
  208. *
  209. * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
  210. * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
  211. * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
  212. */
  213. #define GXIO_MPIPE_LINK_CTL 0x00000040UL
  214. /** Do not request control permission on the specified link.
  215. *
  216. * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
  217. * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
  218. * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
  219. */
  220. #define GXIO_MPIPE_LINK_NO_CTL 0x00000080UL
  221. /** Request exclusive control permission -- that is, the ability to modify
  222. * link attributes, and read and write MAC and MDIO registers -- on the
  223. * specified link. No other processes may request control permission on
  224. * this link, and if any process already has control permission on it,
  225. * this open will fail.
  226. *
  227. * Requesting exclusive control permission is not always a good idea, since
  228. * it prevents programs like mpipe-link from configuring the link.
  229. *
  230. * No more than one of ::GXIO_MPIPE_LINK_CTL, ::GXIO_MPIPE_LINK_NO_CTL,
  231. * or ::GXIO_MPIPE_LINK_EXCL_CTL may be specifed in a gxio_mpipe_link_open()
  232. * call. If none are specified, ::GXIO_MPIPE_LINK_CTL is assumed.
  233. */
  234. #define GXIO_MPIPE_LINK_EXCL_CTL 0x00000100UL
  235. /** Set the desired state of the link to up, allowing any speeds which are
  236. * supported by the link hardware, as part of this open operation; do not
  237. * change the desired state of the link when it is closed or the process
  238. * exits. No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
  239. * ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
  240. * ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
  241. * call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
  242. */
  243. #define GXIO_MPIPE_LINK_AUTO_UP 0x00000200UL
  244. /** Set the desired state of the link to up, allowing any speeds which are
  245. * supported by the link hardware, as part of this open operation; when the
  246. * link is closed or this process exits, if no other process has the link
  247. * open, set the desired state of the link to down. No more than one of
  248. * ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
  249. * ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
  250. * specifed in a gxio_mpipe_link_open() call. If none are specified,
  251. * ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
  252. */
  253. #define GXIO_MPIPE_LINK_AUTO_UPDOWN 0x00000400UL
  254. /** Do not change the desired state of the link as part of the open
  255. * operation; when the link is closed or this process exits, if no other
  256. * process has the link open, set the desired state of the link to down.
  257. * No more than one of ::GXIO_MPIPE_LINK_AUTO_UP,
  258. * ::GXIO_MPIPE_LINK_AUTO_UPDOWN, ::GXIO_MPIPE_LINK_AUTO_DOWN, or
  259. * ::GXIO_MPIPE_LINK_AUTO_NONE may be specifed in a gxio_mpipe_link_open()
  260. * call. If none are specified, ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
  261. */
  262. #define GXIO_MPIPE_LINK_AUTO_DOWN 0x00000800UL
  263. /** Do not change the desired state of the link as part of the open
  264. * operation; do not change the desired state of the link when it is
  265. * closed or the process exits. No more than one of
  266. * ::GXIO_MPIPE_LINK_AUTO_UP, ::GXIO_MPIPE_LINK_AUTO_UPDOWN,
  267. * ::GXIO_MPIPE_LINK_AUTO_DOWN, or ::GXIO_MPIPE_LINK_AUTO_NONE may be
  268. * specifed in a gxio_mpipe_link_open() call. If none are specified,
  269. * ::GXIO_MPIPE_LINK_AUTO_UPDOWN is assumed.
  270. */
  271. #define GXIO_MPIPE_LINK_AUTO_NONE 0x00001000UL
  272. /** Request that this open call not complete until the network link is up.
  273. * The process will wait as long as necessary for this to happen;
  274. * applications which wish to abandon waiting for the link after a
  275. * specific time period should not specify this flag when opening a link,
  276. * but should instead call gxio_mpipe_link_wait() afterward. The link
  277. * must be opened with stats permission. Note that this flag by itself
  278. * does not change the desired link state; if other open flags or previous
  279. * link state changes have not requested a desired state of up, the open
  280. * call will never complete. This flag is not available to kernel
  281. * clients.
  282. */
  283. #define GXIO_MPIPE_LINK_WAIT 0x00002000UL
  284. /*
  285. * Note: link attributes must fit in 24 bits, since we use the top 8 bits
  286. * of the IORPC offset word for the channel number.
  287. */
  288. /** Determine whether jumbo frames may be received. If this attribute's
  289. * value value is nonzero, the MAC will accept frames of up to 10240 bytes.
  290. * If the value is zero, the MAC will only accept frames of up to 1544
  291. * bytes. The default value is zero. */
  292. #define GXIO_MPIPE_LINK_RECEIVE_JUMBO 0x010000
  293. /** Determine whether to send pause frames on this link if the mPIPE packet
  294. * FIFO is nearly full. If the value is zero, pause frames are not sent.
  295. * If the value is nonzero, it is the delay value which will be sent in any
  296. * pause frames which are output, in units of 512 bit times.
  297. *
  298. * Bear in mind that in almost all circumstances, the mPIPE packet FIFO
  299. * will never fill up, since mPIPE will empty it as fast as or faster than
  300. * the incoming data rate, by either delivering or dropping packets. The
  301. * only situation in which this is not true is if the memory and cache
  302. * subsystem is extremely heavily loaded, and mPIPE cannot perform DMA of
  303. * packet data to memory in a timely fashion. In particular, pause frames
  304. * will <em>not</em> be sent if packets cannot be delivered because
  305. * NotifRings are full, buckets are full, or buffers are not available in
  306. * a buffer stack. */
  307. #define GXIO_MPIPE_LINK_SEND_PAUSE 0x020000
  308. /** Determine whether to suspend output on the receipt of pause frames.
  309. * If the value is nonzero, mPIPE shim will suspend output on the link's
  310. * channel when a pause frame is received. If the value is zero, pause
  311. * frames will be ignored. The default value is zero. */
  312. #define GXIO_MPIPE_LINK_RECEIVE_PAUSE 0x030000
  313. /** Interface MAC address. The value is a 6-byte MAC address, in the least
  314. * significant 48 bits of the value; in other words, an address which would
  315. * be printed as '12:34:56:78:90:AB' in IEEE 802 canonical format would
  316. * be returned as 0x12345678ab.
  317. *
  318. * Depending upon the overall system design, a MAC address may or may not
  319. * be available for each interface. Note that the interface's MAC address
  320. * does not limit the packets received on its channel, although the
  321. * classifier's rules could be configured to do that. Similarly, the MAC
  322. * address is not used when transmitting packets, although applications
  323. * could certainly decide to use the assigned address as a source MAC
  324. * address when doing so. This attribute may only be retrieved with
  325. * gxio_mpipe_link_get_attr(); it may not be modified.
  326. */
  327. #define GXIO_MPIPE_LINK_MAC 0x040000
  328. /** Determine whether to discard egress packets on link down. If this value
  329. * is nonzero, packets sent on this link while the link is down will be
  330. * discarded. If this value is zero, no packets will be sent on this link
  331. * while it is down. The default value is one. */
  332. #define GXIO_MPIPE_LINK_DISCARD_IF_DOWN 0x050000
  333. /** Possible link state. The value is a combination of link state flags,
  334. * ORed together, that indicate link modes which are actually supported by
  335. * the hardware. This attribute may only be retrieved with
  336. * gxio_mpipe_link_get_attr(); it may not be modified. */
  337. #define GXIO_MPIPE_LINK_POSSIBLE_STATE 0x060000
  338. /** Current link state. The value is a combination of link state flags,
  339. * ORed together, that indicate the current state of the hardware. If the
  340. * link is down, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will be zero;
  341. * if the link is up, the value ANDed with ::GXIO_MPIPE_LINK_SPEED will
  342. * result in exactly one of the speed values, indicating the current speed.
  343. * This attribute may only be retrieved with gxio_mpipe_link_get_attr(); it
  344. * may not be modified. */
  345. #define GXIO_MPIPE_LINK_CURRENT_STATE 0x070000
  346. /** Desired link state. The value is a conbination of flags, which specify
  347. * the desired state for the link. With gxio_mpipe_link_set_attr(), this
  348. * will, in the background, attempt to bring up the link using whichever of
  349. * the requested flags are reasonable, or take down the link if the flags
  350. * are zero. The actual link up or down operation may happen after this
  351. * call completes. If the link state changes in the future, the system
  352. * will continue to try to get back to the desired link state; for
  353. * instance, if the link is brought up successfully, and then the network
  354. * cable is disconnected, the link will go down. However, the desired
  355. * state of the link is still up, so if the cable is reconnected, the link
  356. * will be brought up again.
  357. *
  358. * With gxio_mpipe_link_set_attr(), this will indicate the desired state
  359. * for the link, as set with a previous gxio_mpipe_link_set_attr() call,
  360. * or implicitly by a gxio_mpipe_link_open() or link close operation.
  361. * This may not reflect the current state of the link; to get that, use
  362. * ::GXIO_MPIPE_LINK_CURRENT_STATE.
  363. */
  364. #define GXIO_MPIPE_LINK_DESIRED_STATE 0x080000
  365. /** Link can run, should run, or is running at 10 Mbps. */
  366. #define GXIO_MPIPE_LINK_10M 0x0000000000000001UL
  367. /** Link can run, should run, or is running at 100 Mbps. */
  368. #define GXIO_MPIPE_LINK_100M 0x0000000000000002UL
  369. /** Link can run, should run, or is running at 1 Gbps. */
  370. #define GXIO_MPIPE_LINK_1G 0x0000000000000004UL
  371. /** Link can run, should run, or is running at 10 Gbps. */
  372. #define GXIO_MPIPE_LINK_10G 0x0000000000000008UL
  373. /** Link can run, should run, or is running at 20 Gbps. */
  374. #define GXIO_MPIPE_LINK_20G 0x0000000000000010UL
  375. /** Link can run, should run, or is running at 25 Gbps. */
  376. #define GXIO_MPIPE_LINK_25G 0x0000000000000020UL
  377. /** Link can run, should run, or is running at 50 Gbps. */
  378. #define GXIO_MPIPE_LINK_50G 0x0000000000000040UL
  379. /** Link should run at the highest speed supported by the link and by
  380. * the device connected to the link. Only usable as a value for
  381. * the link's desired state; never returned as a value for the current
  382. * or possible states. */
  383. #define GXIO_MPIPE_LINK_ANYSPEED 0x0000000000000800UL
  384. /** All legal link speeds. This value is provided for use in extracting
  385. * the speed-related subset of the link state flags; it is not intended
  386. * to be set directly as a value for one of the GXIO_MPIPE_LINK_xxx_STATE
  387. * attributes. A link is up or is requested to be up if its current or
  388. * desired state, respectively, ANDED with this value, is nonzero. */
  389. #define GXIO_MPIPE_LINK_SPEED_MASK 0x0000000000000FFFUL
  390. /** Link can run, should run, or is running in MAC loopback mode. This
  391. * loops transmitted packets back to the receiver, inside the Tile
  392. * Processor. */
  393. #define GXIO_MPIPE_LINK_LOOP_MAC 0x0000000000001000UL
  394. /** Link can run, should run, or is running in PHY loopback mode. This
  395. * loops transmitted packets back to the receiver, inside the external
  396. * PHY chip. */
  397. #define GXIO_MPIPE_LINK_LOOP_PHY 0x0000000000002000UL
  398. /** Link can run, should run, or is running in external loopback mode.
  399. * This requires that an external loopback plug be installed on the
  400. * Ethernet port. Note that only some links require that this be
  401. * configured via the gxio_mpipe_link routines; other links can do
  402. * external loopack with the plug and no special configuration. */
  403. #define GXIO_MPIPE_LINK_LOOP_EXT 0x0000000000004000UL
  404. /** All legal loopback types. */
  405. #define GXIO_MPIPE_LINK_LOOP_MASK 0x000000000000F000UL
  406. /** Link can run, should run, or is running in full-duplex mode.
  407. * If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
  408. * specified in a set of desired state flags, both are assumed. */
  409. #define GXIO_MPIPE_LINK_FDX 0x0000000000010000UL
  410. /** Link can run, should run, or is running in half-duplex mode.
  411. * If neither ::GXIO_MPIPE_LINK_FDX nor ::GXIO_MPIPE_LINK_HDX are
  412. * specified in a set of desired state flags, both are assumed. */
  413. #define GXIO_MPIPE_LINK_HDX 0x0000000000020000UL
  414. /** An individual rule. */
  415. typedef struct
  416. {
  417. /** The total size. */
  418. uint16_t size;
  419. /** The priority. */
  420. int16_t priority;
  421. /** The "headroom" in each buffer. */
  422. uint8_t headroom;
  423. /** The "tailroom" in each buffer. */
  424. uint8_t tailroom;
  425. /** The "capacity" of the largest buffer. */
  426. uint16_t capacity;
  427. /** The mask for converting a flow hash into a bucket. */
  428. uint16_t bucket_mask;
  429. /** The offset for converting a flow hash into a bucket. */
  430. uint16_t bucket_first;
  431. /** The buffer stack ids. */
  432. gxio_mpipe_rules_stacks_t stacks;
  433. /** The actual channels. */
  434. uint32_t channel_bits;
  435. /** The number of dmacs. */
  436. uint16_t num_dmacs;
  437. /** The number of vlans. */
  438. uint16_t num_vlans;
  439. /** The actual dmacs and vlans. */
  440. uint8_t dmacs_and_vlans[];
  441. } gxio_mpipe_rules_rule_t;
  442. /** A list of classifier rules. */
  443. typedef struct
  444. {
  445. /** The offset to the end of the current rule. */
  446. uint16_t tail;
  447. /** The offset to the start of the current rule. */
  448. uint16_t head;
  449. /** The actual rules. */
  450. uint8_t rules[4096 - 4];
  451. } gxio_mpipe_rules_list_t;
  452. /** mPIPE statistics structure. These counters include all relevant
  453. * events occurring on all links within the mPIPE shim. */
  454. typedef struct
  455. {
  456. /** Number of ingress packets dropped for any reason. */
  457. uint64_t ingress_drops;
  458. /** Number of ingress packets dropped because a buffer stack was empty. */
  459. uint64_t ingress_drops_no_buf;
  460. /** Number of ingress packets dropped or truncated due to lack of space in
  461. * the iPkt buffer. */
  462. uint64_t ingress_drops_ipkt;
  463. /** Number of ingress packets dropped by the classifier or load balancer */
  464. uint64_t ingress_drops_cls_lb;
  465. /** Total number of ingress packets. */
  466. uint64_t ingress_packets;
  467. /** Total number of egress packets. */
  468. uint64_t egress_packets;
  469. /** Total number of ingress bytes. */
  470. uint64_t ingress_bytes;
  471. /** Total number of egress bytes. */
  472. uint64_t egress_bytes;
  473. }
  474. gxio_mpipe_stats_t;
  475. #endif /* _SYS_HV_DRV_MPIPE_INTF_H */