book3s_hv_interrupts.S 4.5 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License, version 2, as
  4. * published by the Free Software Foundation.
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * You should have received a copy of the GNU General Public License
  12. * along with this program; if not, write to the Free Software
  13. * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  14. *
  15. * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
  16. *
  17. * Derived from book3s_interrupts.S, which is:
  18. * Copyright SUSE Linux Products GmbH 2009
  19. *
  20. * Authors: Alexander Graf <agraf@suse.de>
  21. */
  22. #include <asm/ppc_asm.h>
  23. #include <asm/kvm_asm.h>
  24. #include <asm/reg.h>
  25. #include <asm/page.h>
  26. #include <asm/asm-offsets.h>
  27. #include <asm/exception-64s.h>
  28. #include <asm/ppc-opcode.h>
  29. /*****************************************************************************
  30. * *
  31. * Guest entry / exit code that is in kernel module memory (vmalloc) *
  32. * *
  33. ****************************************************************************/
  34. /* Registers:
  35. * r4: vcpu pointer
  36. */
  37. _GLOBAL(__kvmppc_vcore_entry)
  38. /* Write correct stack frame */
  39. mflr r0
  40. std r0,PPC_LR_STKOFF(r1)
  41. /* Save host state to the stack */
  42. stdu r1, -SWITCH_FRAME_SIZE(r1)
  43. /* Save non-volatile registers (r14 - r31) and CR */
  44. SAVE_NVGPRS(r1)
  45. mfcr r3
  46. std r3, _CCR(r1)
  47. /* Save host DSCR */
  48. BEGIN_FTR_SECTION
  49. mfspr r3, SPRN_DSCR
  50. std r3, HSTATE_DSCR(r13)
  51. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
  52. /* Save host DABR */
  53. mfspr r3, SPRN_DABR
  54. std r3, HSTATE_DABR(r13)
  55. /* Hard-disable interrupts */
  56. mfmsr r10
  57. std r10, HSTATE_HOST_MSR(r13)
  58. rldicl r10,r10,48,1
  59. rotldi r10,r10,16
  60. mtmsrd r10,1
  61. /* Save host PMU registers */
  62. /* R4 is live here (vcpu pointer) but not r3 or r5 */
  63. li r3, 1
  64. sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
  65. mfspr r7, SPRN_MMCR0 /* save MMCR0 */
  66. mtspr SPRN_MMCR0, r3 /* freeze all counters, disable interrupts */
  67. mfspr r6, SPRN_MMCRA
  68. BEGIN_FTR_SECTION
  69. /* On P7, clear MMCRA in order to disable SDAR updates */
  70. li r5, 0
  71. mtspr SPRN_MMCRA, r5
  72. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
  73. isync
  74. ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
  75. lbz r5, LPPACA_PMCINUSE(r3)
  76. cmpwi r5, 0
  77. beq 31f /* skip if not */
  78. mfspr r5, SPRN_MMCR1
  79. std r7, HSTATE_MMCR(r13)
  80. std r5, HSTATE_MMCR + 8(r13)
  81. std r6, HSTATE_MMCR + 16(r13)
  82. mfspr r3, SPRN_PMC1
  83. mfspr r5, SPRN_PMC2
  84. mfspr r6, SPRN_PMC3
  85. mfspr r7, SPRN_PMC4
  86. mfspr r8, SPRN_PMC5
  87. mfspr r9, SPRN_PMC6
  88. BEGIN_FTR_SECTION
  89. mfspr r10, SPRN_PMC7
  90. mfspr r11, SPRN_PMC8
  91. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  92. stw r3, HSTATE_PMC(r13)
  93. stw r5, HSTATE_PMC + 4(r13)
  94. stw r6, HSTATE_PMC + 8(r13)
  95. stw r7, HSTATE_PMC + 12(r13)
  96. stw r8, HSTATE_PMC + 16(r13)
  97. stw r9, HSTATE_PMC + 20(r13)
  98. BEGIN_FTR_SECTION
  99. stw r10, HSTATE_PMC + 24(r13)
  100. stw r11, HSTATE_PMC + 28(r13)
  101. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  102. 31:
  103. /*
  104. * Put whatever is in the decrementer into the
  105. * hypervisor decrementer.
  106. */
  107. mfspr r8,SPRN_DEC
  108. mftb r7
  109. mtspr SPRN_HDEC,r8
  110. extsw r8,r8
  111. add r8,r8,r7
  112. std r8,HSTATE_DECEXP(r13)
  113. /*
  114. * On PPC970, if the guest vcpu has an external interrupt pending,
  115. * send ourselves an IPI so as to interrupt the guest once it
  116. * enables interrupts. (It must have interrupts disabled,
  117. * otherwise we would already have delivered the interrupt.)
  118. */
  119. BEGIN_FTR_SECTION
  120. ld r0, VCPU_PENDING_EXC(r4)
  121. li r7, (1 << BOOK3S_IRQPRIO_EXTERNAL)
  122. oris r7, r7, (1 << BOOK3S_IRQPRIO_EXTERNAL_LEVEL)@h
  123. and. r0, r0, r7
  124. beq 32f
  125. mr r31, r4
  126. lhz r3, PACAPACAINDEX(r13)
  127. bl smp_send_reschedule
  128. nop
  129. mr r4, r31
  130. 32:
  131. END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
  132. /* Jump to partition switch code */
  133. bl .kvmppc_hv_entry_trampoline
  134. nop
  135. /*
  136. * We return here in virtual mode after the guest exits
  137. * with something that we can't handle in real mode.
  138. * Interrupts are enabled again at this point.
  139. */
  140. .global kvmppc_handler_highmem
  141. kvmppc_handler_highmem:
  142. /*
  143. * Register usage at this point:
  144. *
  145. * R1 = host R1
  146. * R2 = host R2
  147. * R12 = exit handler id
  148. * R13 = PACA
  149. */
  150. /* Restore non-volatile host registers (r14 - r31) and CR */
  151. REST_NVGPRS(r1)
  152. ld r4, _CCR(r1)
  153. mtcr r4
  154. addi r1, r1, SWITCH_FRAME_SIZE
  155. ld r0, PPC_LR_STKOFF(r1)
  156. mtlr r0
  157. blr