pci-xlr.c 9.6 KB

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  1. /*
  2. * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
  3. * reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the NetLogic
  9. * license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions
  13. * are met:
  14. *
  15. * 1. Redistributions of source code must retain the above copyright
  16. * notice, this list of conditions and the following disclaimer.
  17. * 2. Redistributions in binary form must reproduce the above copyright
  18. * notice, this list of conditions and the following disclaimer in
  19. * the documentation and/or other materials provided with the
  20. * distribution.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
  23. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25. * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
  26. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29. * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30. * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31. * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32. * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33. */
  34. #include <linux/types.h>
  35. #include <linux/pci.h>
  36. #include <linux/kernel.h>
  37. #include <linux/init.h>
  38. #include <linux/msi.h>
  39. #include <linux/mm.h>
  40. #include <linux/irq.h>
  41. #include <linux/irqdesc.h>
  42. #include <linux/console.h>
  43. #include <linux/pci_regs.h>
  44. #include <asm/io.h>
  45. #include <asm/netlogic/interrupt.h>
  46. #include <asm/netlogic/haldefs.h>
  47. #include <asm/netlogic/xlr/msidef.h>
  48. #include <asm/netlogic/xlr/iomap.h>
  49. #include <asm/netlogic/xlr/pic.h>
  50. #include <asm/netlogic/xlr/xlr.h>
  51. static void *pci_config_base;
  52. #define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
  53. /* PCI ops */
  54. static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
  55. int where)
  56. {
  57. u32 data;
  58. u32 *cfgaddr;
  59. cfgaddr = (u32 *)(pci_config_base +
  60. pci_cfg_addr(bus->number, devfn, where & ~3));
  61. data = *cfgaddr;
  62. return cpu_to_le32(data);
  63. }
  64. static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn,
  65. int where, u32 data)
  66. {
  67. u32 *cfgaddr;
  68. cfgaddr = (u32 *)(pci_config_base +
  69. pci_cfg_addr(bus->number, devfn, where & ~3));
  70. *cfgaddr = cpu_to_le32(data);
  71. }
  72. static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  73. int where, int size, u32 *val)
  74. {
  75. u32 data;
  76. if ((size == 2) && (where & 1))
  77. return PCIBIOS_BAD_REGISTER_NUMBER;
  78. else if ((size == 4) && (where & 3))
  79. return PCIBIOS_BAD_REGISTER_NUMBER;
  80. data = pci_cfg_read_32bit(bus, devfn, where);
  81. if (size == 1)
  82. *val = (data >> ((where & 3) << 3)) & 0xff;
  83. else if (size == 2)
  84. *val = (data >> ((where & 3) << 3)) & 0xffff;
  85. else
  86. *val = data;
  87. return PCIBIOS_SUCCESSFUL;
  88. }
  89. static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn,
  90. int where, int size, u32 val)
  91. {
  92. u32 data;
  93. if ((size == 2) && (where & 1))
  94. return PCIBIOS_BAD_REGISTER_NUMBER;
  95. else if ((size == 4) && (where & 3))
  96. return PCIBIOS_BAD_REGISTER_NUMBER;
  97. data = pci_cfg_read_32bit(bus, devfn, where);
  98. if (size == 1)
  99. data = (data & ~(0xff << ((where & 3) << 3))) |
  100. (val << ((where & 3) << 3));
  101. else if (size == 2)
  102. data = (data & ~(0xffff << ((where & 3) << 3))) |
  103. (val << ((where & 3) << 3));
  104. else
  105. data = val;
  106. pci_cfg_write_32bit(bus, devfn, where, data);
  107. return PCIBIOS_SUCCESSFUL;
  108. }
  109. struct pci_ops nlm_pci_ops = {
  110. .read = nlm_pcibios_read,
  111. .write = nlm_pcibios_write
  112. };
  113. static struct resource nlm_pci_mem_resource = {
  114. .name = "XLR PCI MEM",
  115. .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
  116. .end = 0xdfffffffUL,
  117. .flags = IORESOURCE_MEM,
  118. };
  119. static struct resource nlm_pci_io_resource = {
  120. .name = "XLR IO MEM",
  121. .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
  122. .end = 0x100fffffUL,
  123. .flags = IORESOURCE_IO,
  124. };
  125. struct pci_controller nlm_pci_controller = {
  126. .index = 0,
  127. .pci_ops = &nlm_pci_ops,
  128. .mem_resource = &nlm_pci_mem_resource,
  129. .mem_offset = 0x00000000UL,
  130. .io_resource = &nlm_pci_io_resource,
  131. .io_offset = 0x00000000UL,
  132. };
  133. /*
  134. * The top level PCIe links on the XLS PCIe controller appear as
  135. * bridges. Given a device, this function finds which link it is
  136. * on.
  137. */
  138. static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev)
  139. {
  140. struct pci_bus *bus, *p;
  141. /* Find the bridge on bus 0 */
  142. bus = dev->bus;
  143. for (p = bus->parent; p && p->number != 0; p = p->parent)
  144. bus = p;
  145. return p ? bus->self : NULL;
  146. }
  147. static int get_irq_vector(const struct pci_dev *dev)
  148. {
  149. struct pci_dev *lnk;
  150. if (!nlm_chip_is_xls())
  151. return PIC_PCIX_IRQ; /* for XLR just one IRQ */
  152. /*
  153. * For XLS PCIe, there is an IRQ per Link, find out which
  154. * link the device is on to assign interrupts
  155. */
  156. lnk = xls_get_pcie_link(dev);
  157. if (lnk == NULL)
  158. return 0;
  159. switch (PCI_SLOT(lnk->devfn)) {
  160. case 0:
  161. return PIC_PCIE_LINK0_IRQ;
  162. case 1:
  163. return PIC_PCIE_LINK1_IRQ;
  164. case 2:
  165. if (nlm_chip_is_xls_b())
  166. return PIC_PCIE_XLSB0_LINK2_IRQ;
  167. else
  168. return PIC_PCIE_LINK2_IRQ;
  169. case 3:
  170. if (nlm_chip_is_xls_b())
  171. return PIC_PCIE_XLSB0_LINK3_IRQ;
  172. else
  173. return PIC_PCIE_LINK3_IRQ;
  174. }
  175. WARN(1, "Unexpected devfn %d\n", lnk->devfn);
  176. return 0;
  177. }
  178. #ifdef CONFIG_PCI_MSI
  179. void destroy_irq(unsigned int irq)
  180. {
  181. /* nothing to do yet */
  182. }
  183. void arch_teardown_msi_irq(unsigned int irq)
  184. {
  185. destroy_irq(irq);
  186. }
  187. int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
  188. {
  189. struct msi_msg msg;
  190. struct pci_dev *lnk;
  191. int irq, ret;
  192. u16 val;
  193. /* MSI not supported on XLR */
  194. if (!nlm_chip_is_xls())
  195. return 1;
  196. /*
  197. * Enable MSI on the XLS PCIe controller bridge which was disabled
  198. * at enumeration, the bridge MSI capability is at 0x50
  199. */
  200. lnk = xls_get_pcie_link(dev);
  201. if (lnk == NULL)
  202. return 1;
  203. pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val);
  204. if ((val & PCI_MSI_FLAGS_ENABLE) == 0) {
  205. val |= PCI_MSI_FLAGS_ENABLE;
  206. pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val);
  207. }
  208. irq = get_irq_vector(dev);
  209. if (irq <= 0)
  210. return 1;
  211. msg.address_hi = MSI_ADDR_BASE_HI;
  212. msg.address_lo = MSI_ADDR_BASE_LO |
  213. MSI_ADDR_DEST_MODE_PHYSICAL |
  214. MSI_ADDR_REDIRECTION_CPU;
  215. msg.data = MSI_DATA_TRIGGER_EDGE |
  216. MSI_DATA_LEVEL_ASSERT |
  217. MSI_DATA_DELIVERY_FIXED;
  218. ret = irq_set_msi_desc(irq, desc);
  219. if (ret < 0) {
  220. destroy_irq(irq);
  221. return ret;
  222. }
  223. write_msi_msg(irq, &msg);
  224. return 0;
  225. }
  226. #endif
  227. /* Extra ACK needed for XLR on chip PCI controller */
  228. static void xlr_pci_ack(struct irq_data *d)
  229. {
  230. uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET);
  231. nlm_read_reg(pcibase, (0x140 >> 2));
  232. }
  233. /* Extra ACK needed for XLS on chip PCIe controller */
  234. static void xls_pcie_ack(struct irq_data *d)
  235. {
  236. uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
  237. switch (d->irq) {
  238. case PIC_PCIE_LINK0_IRQ:
  239. nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
  240. break;
  241. case PIC_PCIE_LINK1_IRQ:
  242. nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
  243. break;
  244. case PIC_PCIE_LINK2_IRQ:
  245. nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
  246. break;
  247. case PIC_PCIE_LINK3_IRQ:
  248. nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
  249. break;
  250. }
  251. }
  252. /* For XLS B silicon, the 3,4 PCI interrupts are different */
  253. static void xls_pcie_ack_b(struct irq_data *d)
  254. {
  255. uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET);
  256. switch (d->irq) {
  257. case PIC_PCIE_LINK0_IRQ:
  258. nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff);
  259. break;
  260. case PIC_PCIE_LINK1_IRQ:
  261. nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff);
  262. break;
  263. case PIC_PCIE_XLSB0_LINK2_IRQ:
  264. nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff);
  265. break;
  266. case PIC_PCIE_XLSB0_LINK3_IRQ:
  267. nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff);
  268. break;
  269. }
  270. }
  271. int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  272. {
  273. return get_irq_vector(dev);
  274. }
  275. /* Do platform specific device initialization at pci_enable_device() time */
  276. int pcibios_plat_dev_init(struct pci_dev *dev)
  277. {
  278. return 0;
  279. }
  280. static int __init pcibios_init(void)
  281. {
  282. /* PSB assigns PCI resources */
  283. pci_set_flags(PCI_PROBE_ONLY);
  284. pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
  285. /* Extend IO port for memory mapped io */
  286. ioport_resource.start = 0;
  287. ioport_resource.end = ~0;
  288. set_io_port_base(CKSEG1);
  289. nlm_pci_controller.io_map_base = CKSEG1;
  290. pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n");
  291. register_pci_controller(&nlm_pci_controller);
  292. /*
  293. * For PCI interrupts, we need to ack the PCI controller too, overload
  294. * irq handler data to do this
  295. */
  296. if (nlm_chip_is_xls()) {
  297. if (nlm_chip_is_xls_b()) {
  298. irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
  299. xls_pcie_ack_b);
  300. irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
  301. xls_pcie_ack_b);
  302. irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
  303. xls_pcie_ack_b);
  304. irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
  305. xls_pcie_ack_b);
  306. } else {
  307. irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
  308. irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
  309. irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
  310. irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
  311. }
  312. } else {
  313. /* XLR PCI controller ACK */
  314. irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack);
  315. }
  316. return 0;
  317. }
  318. arch_initcall(pcibios_init);