pci.h 4.0 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. */
  6. #ifndef _ASM_PCI_H
  7. #define _ASM_PCI_H
  8. #include <linux/mm.h>
  9. #ifdef __KERNEL__
  10. /*
  11. * This file essentially defines the interface between board
  12. * specific PCI code and MIPS common PCI code. Should potentially put
  13. * into include/asm/pci.h file.
  14. */
  15. #include <linux/ioport.h>
  16. #include <linux/of.h>
  17. /*
  18. * Each pci channel is a top-level PCI bus seem by CPU. A machine with
  19. * multiple PCI channels may have multiple PCI host controllers or a
  20. * single controller supporting multiple channels.
  21. */
  22. struct pci_controller {
  23. struct pci_controller *next;
  24. struct pci_bus *bus;
  25. struct device_node *of_node;
  26. struct pci_ops *pci_ops;
  27. struct resource *mem_resource;
  28. unsigned long mem_offset;
  29. struct resource *io_resource;
  30. unsigned long io_offset;
  31. unsigned long io_map_base;
  32. unsigned int index;
  33. /* For compatibility with current (as of July 2003) pciutils
  34. and XFree86. Eventually will be removed. */
  35. unsigned int need_domain_info;
  36. int iommu;
  37. /* Optional access methods for reading/writing the bus number
  38. of the PCI controller */
  39. int (*get_busno)(void);
  40. void (*set_busno)(int busno);
  41. };
  42. /*
  43. * Used by boards to register their PCI busses before the actual scanning.
  44. */
  45. extern struct pci_controller * alloc_pci_controller(void);
  46. extern void register_pci_controller(struct pci_controller *hose);
  47. /*
  48. * board supplied pci irq fixup routine
  49. */
  50. extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  51. /* Can be used to override the logic in pci_scan_bus for skipping
  52. already-configured bus numbers - to be used for buggy BIOSes
  53. or architectures with incomplete PCI setup by the loader */
  54. extern unsigned int pcibios_assign_all_busses(void);
  55. extern unsigned long PCIBIOS_MIN_IO;
  56. extern unsigned long PCIBIOS_MIN_MEM;
  57. #define PCIBIOS_MIN_CARDBUS_IO 0x4000
  58. extern void pcibios_set_master(struct pci_dev *dev);
  59. static inline void pcibios_penalize_isa_irq(int irq, int active)
  60. {
  61. /* We don't do dynamic PCI IRQ allocation */
  62. }
  63. #define HAVE_PCI_MMAP
  64. extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
  65. enum pci_mmap_state mmap_state, int write_combine);
  66. /*
  67. * Dynamic DMA mapping stuff.
  68. * MIPS has everything mapped statically.
  69. */
  70. #include <linux/types.h>
  71. #include <linux/slab.h>
  72. #include <asm/scatterlist.h>
  73. #include <linux/string.h>
  74. #include <asm/io.h>
  75. #include <asm-generic/pci-bridge.h>
  76. struct pci_dev;
  77. /*
  78. * The PCI address space does equal the physical memory address space. The
  79. * networking and block device layers use this boolean for bounce buffer
  80. * decisions. This is set if any hose does not have an IOMMU.
  81. */
  82. extern unsigned int PCI_DMA_BUS_IS_PHYS;
  83. #ifdef CONFIG_PCI
  84. static inline void pci_dma_burst_advice(struct pci_dev *pdev,
  85. enum pci_dma_burst_strategy *strat,
  86. unsigned long *strategy_parameter)
  87. {
  88. *strat = PCI_DMA_BURST_INFINITY;
  89. *strategy_parameter = ~0UL;
  90. }
  91. #endif
  92. #define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
  93. static inline int pci_proc_domain(struct pci_bus *bus)
  94. {
  95. struct pci_controller *hose = bus->sysdata;
  96. return hose->need_domain_info;
  97. }
  98. #endif /* __KERNEL__ */
  99. /* implement the pci_ DMA API in terms of the generic device dma_ one */
  100. #include <asm-generic/pci-dma-compat.h>
  101. /* Do platform specific device initialization at pci_enable_device() time */
  102. extern int pcibios_plat_dev_init(struct pci_dev *dev);
  103. /* Chances are this interrupt is wired PC-style ... */
  104. static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
  105. {
  106. return channel ? 15 : 14;
  107. }
  108. #ifdef CONFIG_CPU_CAVIUM_OCTEON
  109. /* MSI arch hook for OCTEON */
  110. #define arch_setup_msi_irqs arch_setup_msi_irqs
  111. #endif
  112. extern char * (*pcibios_plat_setup)(char *str);
  113. /* this function parses memory ranges from a device node */
  114. extern void __devinit pci_load_of_ranges(struct pci_controller *hose,
  115. struct device_node *node);
  116. #endif /* _ASM_PCI_H */