mach-at2440evb.c 5.0 KB

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  1. /* linux/arch/arm/mach-s3c2440/mach-at2440evb.c
  2. *
  3. * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
  4. * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
  5. * and modifications by SBZ <sbz@spgui.org> and
  6. * Weibing <http://weibing.blogbus.com>
  7. *
  8. * For product information, visit http://www.arm.com/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/list.h>
  18. #include <linux/timer.h>
  19. #include <linux/init.h>
  20. #include <linux/io.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/dm9000.h>
  23. #include <linux/platform_device.h>
  24. #include <asm/mach/arch.h>
  25. #include <asm/mach/map.h>
  26. #include <asm/mach/irq.h>
  27. #include <mach/hardware.h>
  28. #include <mach/fb.h>
  29. #include <asm/irq.h>
  30. #include <asm/mach-types.h>
  31. #include <plat/regs-serial.h>
  32. #include <mach/regs-gpio.h>
  33. #include <mach/regs-mem.h>
  34. #include <mach/regs-lcd.h>
  35. #include <plat/nand.h>
  36. #include <plat/iic.h>
  37. #include <linux/mtd/mtd.h>
  38. #include <linux/mtd/nand.h>
  39. #include <linux/mtd/nand_ecc.h>
  40. #include <linux/mtd/partitions.h>
  41. #include <plat/clock.h>
  42. #include <plat/devs.h>
  43. #include <plat/cpu.h>
  44. #include <plat/mci.h>
  45. #include "common.h"
  46. static struct map_desc at2440evb_iodesc[] __initdata = {
  47. /* Nothing here */
  48. };
  49. #define UCON S3C2410_UCON_DEFAULT
  50. #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
  51. #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
  52. static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
  53. [0] = {
  54. .hwport = 0,
  55. .flags = 0,
  56. .ucon = UCON,
  57. .ulcon = ULCON,
  58. .ufcon = UFCON,
  59. .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
  60. },
  61. [1] = {
  62. .hwport = 1,
  63. .flags = 0,
  64. .ucon = UCON,
  65. .ulcon = ULCON,
  66. .ufcon = UFCON,
  67. .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
  68. },
  69. };
  70. /* NAND Flash on AT2440EVB board */
  71. static struct mtd_partition __initdata at2440evb_default_nand_part[] = {
  72. [0] = {
  73. .name = "Boot Agent",
  74. .size = SZ_256K,
  75. .offset = 0,
  76. },
  77. [1] = {
  78. .name = "Kernel",
  79. .size = SZ_2M,
  80. .offset = SZ_256K,
  81. },
  82. [2] = {
  83. .name = "Root",
  84. .offset = SZ_256K + SZ_2M,
  85. .size = MTDPART_SIZ_FULL,
  86. },
  87. };
  88. static struct s3c2410_nand_set __initdata at2440evb_nand_sets[] = {
  89. [0] = {
  90. .name = "nand",
  91. .nr_chips = 1,
  92. .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
  93. .partitions = at2440evb_default_nand_part,
  94. },
  95. };
  96. static struct s3c2410_platform_nand __initdata at2440evb_nand_info = {
  97. .tacls = 25,
  98. .twrph0 = 55,
  99. .twrph1 = 40,
  100. .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
  101. .sets = at2440evb_nand_sets,
  102. };
  103. /* DM9000AEP 10/100 ethernet controller */
  104. static struct resource at2440evb_dm9k_resource[] = {
  105. [0] = DEFINE_RES_MEM(S3C2410_CS3, 4),
  106. [1] = DEFINE_RES_MEM(S3C2410_CS3 + 4, 4),
  107. [2] = DEFINE_RES_NAMED(IRQ_EINT7, 1, NULL, IORESOURCE_IRQ \
  108. | IORESOURCE_IRQ_HIGHEDGE),
  109. };
  110. static struct dm9000_plat_data at2440evb_dm9k_pdata = {
  111. .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
  112. };
  113. static struct platform_device at2440evb_device_eth = {
  114. .name = "dm9000",
  115. .id = -1,
  116. .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
  117. .resource = at2440evb_dm9k_resource,
  118. .dev = {
  119. .platform_data = &at2440evb_dm9k_pdata,
  120. },
  121. };
  122. static struct s3c24xx_mci_pdata at2440evb_mci_pdata __initdata = {
  123. .gpio_detect = S3C2410_GPG(10),
  124. };
  125. /* 7" LCD panel */
  126. static struct s3c2410fb_display at2440evb_lcd_cfg __initdata = {
  127. .lcdcon5 = S3C2410_LCDCON5_FRM565 |
  128. S3C2410_LCDCON5_INVVLINE |
  129. S3C2410_LCDCON5_INVVFRAME |
  130. S3C2410_LCDCON5_PWREN |
  131. S3C2410_LCDCON5_HWSWP,
  132. .type = S3C2410_LCDCON1_TFT,
  133. .width = 800,
  134. .height = 480,
  135. .pixclock = 33333, /* HCLK 60 MHz, divisor 2 */
  136. .xres = 800,
  137. .yres = 480,
  138. .bpp = 16,
  139. .left_margin = 88,
  140. .right_margin = 40,
  141. .hsync_len = 128,
  142. .upper_margin = 32,
  143. .lower_margin = 11,
  144. .vsync_len = 2,
  145. };
  146. static struct s3c2410fb_mach_info at2440evb_fb_info __initdata = {
  147. .displays = &at2440evb_lcd_cfg,
  148. .num_displays = 1,
  149. .default_display = 0,
  150. };
  151. static struct platform_device *at2440evb_devices[] __initdata = {
  152. &s3c_device_ohci,
  153. &s3c_device_wdt,
  154. &s3c_device_adc,
  155. &s3c_device_i2c0,
  156. &s3c_device_rtc,
  157. &s3c_device_nand,
  158. &s3c_device_sdi,
  159. &s3c_device_lcd,
  160. &at2440evb_device_eth,
  161. };
  162. static void __init at2440evb_map_io(void)
  163. {
  164. s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
  165. s3c24xx_init_clocks(16934400);
  166. s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
  167. }
  168. static void __init at2440evb_init(void)
  169. {
  170. s3c24xx_fb_set_platdata(&at2440evb_fb_info);
  171. s3c24xx_mci_set_platdata(&at2440evb_mci_pdata);
  172. s3c_nand_set_platdata(&at2440evb_nand_info);
  173. s3c_i2c0_set_platdata(NULL);
  174. platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
  175. }
  176. MACHINE_START(AT2440EVB, "AT2440EVB")
  177. .atag_offset = 0x100,
  178. .map_io = at2440evb_map_io,
  179. .init_machine = at2440evb_init,
  180. .init_irq = s3c24xx_init_irq,
  181. .timer = &s3c24xx_timer,
  182. .restart = s3c244x_restart,
  183. MACHINE_END