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mach-omap2
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cm33xx.h

cm33xx.h 24 KB
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  1. /*
    2. 

  2.  * AM33XX CM offset macros
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
    5. 

  5.  * Vaibhav Hiremath <hvaibhav@ti.com>
    6. 

  6.  *
    7. 

  7.  * This program is free software; you can redistribute it and/or
    8. 

  8.  * modify it under the terms of the GNU General Public License as
    9. 

  9.  * published by the Free Software Foundation version 2.
    10. 

  10.  *
    11. 

  11.  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
    12. 

  12.  * kind, whether express or implied; without even the implied warranty
    13. 

  13.  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
    14. 

  14.  * GNU General Public License for more details.
    15. 

  15.  */
    16. 

  16. 

  17. #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
    18. 

  18. #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
    19. 

  19. 

  20. #include <linux/delay.h>
    21. 

  21. #include <linux/errno.h>
    22. 

  22. #include <linux/err.h>
    23. 

  23. #include <linux/io.h>
    24. 

  24. 

  25. #include "common.h"
    26. 

  26. 

  27. #include "cm.h"
    28. 

  28. #include "cm-regbits-33xx.h"
    29. 

  29. #include "cm33xx.h"
    30. 

  30. 

  31. /* CM base address */
    32. 

  32. #define AM33XX_CM_BASE		0x44e00000
    33. 

  33. 

  34. #define AM33XX_CM_REGADDR(inst, reg)				\
    35. 

  35. 	AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
    36. 

  36. 

  37. /* CM instances */
    38. 

  38. #define AM33XX_CM_PER_MOD		0x0000
    39. 

  39. #define AM33XX_CM_WKUP_MOD		0x0400
    40. 

  40. #define AM33XX_CM_DPLL_MOD		0x0500
    41. 

  41. #define AM33XX_CM_MPU_MOD		0x0600
    42. 

  42. #define AM33XX_CM_DEVICE_MOD		0x0700
    43. 

  43. #define AM33XX_CM_RTC_MOD		0x0800
    44. 

  44. #define AM33XX_CM_GFX_MOD		0x0900
    45. 

  45. #define AM33XX_CM_CEFUSE_MOD		0x0A00
    46. 

  46. 

  47. /* CM */
    48. 

  48. 

  49. /* CM.PER_CM register offsets */
    50. 

  50. #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET		0x0000
    51. 

  51. #define AM33XX_CM_PER_L4LS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
    52. 

  52. #define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET		0x0004
    53. 

  53. #define AM33XX_CM_PER_L3S_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
    54. 

  54. #define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET		0x0008
    55. 

  55. #define AM33XX_CM_PER_L4FW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
    56. 

  56. #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET		0x000c
    57. 

  57. #define AM33XX_CM_PER_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
    58. 

  58. #define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET		0x0014
    59. 

  59. #define AM33XX_CM_PER_CPGMAC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
    60. 

  60. #define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET		0x0018
    61. 

  61. #define AM33XX_CM_PER_LCDC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
    62. 

  62. #define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET		0x001c
    63. 

  63. #define AM33XX_CM_PER_USB0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
    64. 

  64. #define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET		0x0020
    65. 

  65. #define AM33XX_CM_PER_MLB_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
    66. 

  66. #define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET		0x0024
    67. 

  67. #define AM33XX_CM_PER_TPTC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
    68. 

  68. #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET		0x0028
    69. 

  69. #define AM33XX_CM_PER_EMIF_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
    70. 

  70. #define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET		0x002c
    71. 

  71. #define AM33XX_CM_PER_OCMCRAM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
    72. 

  72. #define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET		0x0030
    73. 

  73. #define AM33XX_CM_PER_GPMC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
    74. 

  74. #define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET		0x0034
    75. 

  75. #define AM33XX_CM_PER_MCASP0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
    76. 

  76. #define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET		0x0038
    77. 

  77. #define AM33XX_CM_PER_UART5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
    78. 

  78. #define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET		0x003c
    79. 

  79. #define AM33XX_CM_PER_MMC0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
    80. 

  80. #define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET		0x0040
    81. 

  81. #define AM33XX_CM_PER_ELM_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
    82. 

  82. #define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET		0x0044
    83. 

  83. #define AM33XX_CM_PER_I2C2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
    84. 

  84. #define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET		0x0048
    85. 

  85. #define AM33XX_CM_PER_I2C1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
    86. 

  86. #define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET		0x004c
    87. 

  87. #define AM33XX_CM_PER_SPI0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
    88. 

  88. #define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET		0x0050
    89. 

  89. #define AM33XX_CM_PER_SPI1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
    90. 

  90. #define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET		0x0054
    91. 

  91. #define AM33XX_CM_PER_SPI2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
    92. 

  92. #define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET		0x0058
    93. 

  93. #define AM33XX_CM_PER_SPI3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
    94. 

  94. #define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET		0x0060
    95. 

  95. #define AM33XX_CM_PER_L4LS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
    96. 

  96. #define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET		0x0064
    97. 

  97. #define AM33XX_CM_PER_L4FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
    98. 

  98. #define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET		0x0068
    99. 

  99. #define AM33XX_CM_PER_MCASP1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
    100. 

  100. #define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET		0x006c
    101. 

  101. #define AM33XX_CM_PER_UART1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
    102. 

  102. #define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET		0x0070
    103. 

  103. #define AM33XX_CM_PER_UART2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
    104. 

  104. #define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET		0x0074
    105. 

  105. #define AM33XX_CM_PER_UART3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
    106. 

  106. #define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET		0x0078
    107. 

  107. #define AM33XX_CM_PER_UART4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
    108. 

  108. #define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET		0x007c
    109. 

  109. #define AM33XX_CM_PER_TIMER7_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
    110. 

  110. #define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET		0x0080
    111. 

  111. #define AM33XX_CM_PER_TIMER2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
    112. 

  112. #define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET		0x0084
    113. 

  113. #define AM33XX_CM_PER_TIMER3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
    114. 

  114. #define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET		0x0088
    115. 

  115. #define AM33XX_CM_PER_TIMER4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
    116. 

  116. #define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET		0x008c
    117. 

  117. #define AM33XX_CM_PER_MCASP2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
    118. 

  118. #define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET		0x0090
    119. 

  119. #define AM33XX_CM_PER_RNG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
    120. 

  120. #define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET		0x0094
    121. 

  121. #define AM33XX_CM_PER_AES0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
    122. 

  122. #define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET		0x0098
    123. 

  123. #define AM33XX_CM_PER_AES1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
    124. 

  124. #define AM33XX_CM_PER_DES_CLKCTRL_OFFSET		0x009c
    125. 

  125. #define AM33XX_CM_PER_DES_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
    126. 

  126. #define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET		0x00a0
    127. 

  127. #define AM33XX_CM_PER_SHA0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
    128. 

  128. #define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET		0x00a4
    129. 

  129. #define AM33XX_CM_PER_PKA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
    130. 

  130. #define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET		0x00a8
    131. 

  131. #define AM33XX_CM_PER_GPIO6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
    132. 

  132. #define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET		0x00ac
    133. 

  133. #define AM33XX_CM_PER_GPIO1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
    134. 

  134. #define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET		0x00b0
    135. 

  135. #define AM33XX_CM_PER_GPIO2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
    136. 

  136. #define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET		0x00b4
    137. 

  137. #define AM33XX_CM_PER_GPIO3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
    138. 

  138. #define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET		0x00b8
    139. 

  139. #define AM33XX_CM_PER_GPIO4_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
    140. 

  140. #define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET		0x00bc
    141. 

  141. #define AM33XX_CM_PER_TPCC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
    142. 

  142. #define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET		0x00c0
    143. 

  143. #define AM33XX_CM_PER_DCAN0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
    144. 

  144. #define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET		0x00c4
    145. 

  145. #define AM33XX_CM_PER_DCAN1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
    146. 

  146. #define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET		0x00cc
    147. 

  147. #define AM33XX_CM_PER_EPWMSS1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
    148. 

  148. #define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET		0x00d0
    149. 

  149. #define AM33XX_CM_PER_EMIF_FW_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
    150. 

  150. #define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET		0x00d4
    151. 

  151. #define AM33XX_CM_PER_EPWMSS0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
    152. 

  152. #define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET		0x00d8
    153. 

  153. #define AM33XX_CM_PER_EPWMSS2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
    154. 

  154. #define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET		0x00dc
    155. 

  155. #define AM33XX_CM_PER_L3_INSTR_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
    156. 

  156. #define AM33XX_CM_PER_L3_CLKCTRL_OFFSET			0x00e0
    157. 

  157. #define AM33XX_CM_PER_L3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
    158. 

  158. #define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET		0x00e4
    159. 

  159. #define AM33XX_CM_PER_IEEE5000_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
    160. 

  160. #define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET		0x00e8
    161. 

  161. #define AM33XX_CM_PER_PRUSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
    162. 

  162. #define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET		0x00ec
    163. 

  163. #define AM33XX_CM_PER_TIMER5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
    164. 

  164. #define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET		0x00f0
    165. 

  165. #define AM33XX_CM_PER_TIMER6_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
    166. 

  166. #define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET		0x00f4
    167. 

  167. #define AM33XX_CM_PER_MMC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
    168. 

  168. #define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET		0x00f8
    169. 

  169. #define AM33XX_CM_PER_MMC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
    170. 

  170. #define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET		0x00fc
    171. 

  171. #define AM33XX_CM_PER_TPTC1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
    172. 

  172. #define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET		0x0100
    173. 

  173. #define AM33XX_CM_PER_TPTC2_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
    174. 

  174. #define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET		0x0104
    175. 

  175. #define AM33XX_CM_PER_GPIO5_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
    176. 

  176. #define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET		0x010c
    177. 

  177. #define AM33XX_CM_PER_SPINLOCK_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
    178. 

  178. #define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET		0x0110
    179. 

  179. #define AM33XX_CM_PER_MAILBOX0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
    180. 

  180. #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET		0x011c
    181. 

  181. #define AM33XX_CM_PER_L4HS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
    182. 

  182. #define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET		0x0120
    183. 

  183. #define AM33XX_CM_PER_L4HS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
    184. 

  184. #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET		0x0124
    185. 

  185. #define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
    186. 

  186. #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET		0x0128
    187. 

  187. #define AM33XX_CM_PER_SLV_EXPS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
    188. 

  188. #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET		0x012c
    189. 

  189. #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
    190. 

  190. #define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET		0x0130
    191. 

  191. #define AM33XX_CM_PER_OCPWP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
    192. 

  192. #define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET		0x0134
    193. 

  193. #define AM33XX_CM_PER_MAILBOX1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
    194. 

  194. #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET		0x0140
    195. 

  195. #define AM33XX_CM_PER_PRUSS_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
    196. 

  196. #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET		0x0144
    197. 

  197. #define AM33XX_CM_PER_CPSW_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
    198. 

  198. #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET		0x0148
    199. 

  199. #define AM33XX_CM_PER_LCDC_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
    200. 

  200. #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET		0x014c
    201. 

  201. #define AM33XX_CM_PER_CLKDIV32K_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
    202. 

  202. #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET	0x0150
    203. 

  203. #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL		AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
    204. 

  204. 

  205. /* CM.WKUP_CM register offsets */
    206. 

  206. #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET			0x0000
    207. 

  207. #define AM33XX_CM_WKUP_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
    208. 

  208. #define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET		0x0004
    209. 

  209. #define AM33XX_CM_WKUP_CONTROL_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
    210. 

  210. #define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET		0x0008
    211. 

  211. #define AM33XX_CM_WKUP_GPIO0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
    212. 

  212. #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET		0x000c
    213. 

  213. #define AM33XX_CM_WKUP_L4WKUP_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
    214. 

  214. #define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET		0x0010
    215. 

  215. #define AM33XX_CM_WKUP_TIMER0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
    216. 

  216. #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET		0x0014
    217. 

  217. #define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
    218. 

  218. #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET		0x0018
    219. 

  219. #define AM33XX_CM_L3_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
    220. 

  220. #define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x001c
    221. 

  221. #define AM33XX_CM_AUTOIDLE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
    222. 

  222. #define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET		0x0020
    223. 

  223. #define AM33XX_CM_IDLEST_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
    224. 

  224. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET	0x0024
    225. 

  225. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
    226. 

  226. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET	0x0028
    227. 

  227. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
    228. 

  228. #define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET		0x002c
    229. 

  229. #define AM33XX_CM_CLKSEL_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
    230. 

  230. #define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET		0x0030
    231. 

  231. #define AM33XX_CM_AUTOIDLE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
    232. 

  232. #define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET		0x0034
    233. 

  233. #define AM33XX_CM_IDLEST_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
    234. 

  234. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET	0x0038
    235. 

  235. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
    236. 

  236. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET	0x003c
    237. 

  237. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
    238. 

  238. #define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET		0x0040
    239. 

  239. #define AM33XX_CM_CLKSEL_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
    240. 

  240. #define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET		0x0044
    241. 

  241. #define AM33XX_CM_AUTOIDLE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
    242. 

  242. #define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET		0x0048
    243. 

  243. #define AM33XX_CM_IDLEST_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
    244. 

  244. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET	0x004c
    245. 

  245. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
    246. 

  246. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET	0x0050
    247. 

  247. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
    248. 

  248. #define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET		0x0054
    249. 

  249. #define AM33XX_CM_CLKSEL_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
    250. 

  250. #define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0058
    251. 

  251. #define AM33XX_CM_AUTOIDLE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
    252. 

  252. #define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET		0x005c
    253. 

  253. #define AM33XX_CM_IDLEST_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
    254. 

  254. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0060
    255. 

  255. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
    256. 

  256. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x0064
    257. 

  257. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
    258. 

  258. #define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET		0x0068
    259. 

  259. #define AM33XX_CM_CLKSEL_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
    260. 

  260. #define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET		0x006c
    261. 

  261. #define AM33XX_CM_AUTOIDLE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
    262. 

  262. #define AM33XX_CM_IDLEST_DPLL_PER_OFFSET		0x0070
    263. 

  263. #define AM33XX_CM_IDLEST_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
    264. 

  264. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET	0x0074
    265. 

  265. #define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
    266. 

  266. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET	0x0078
    267. 

  267. #define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
    268. 

  268. #define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET		0x007c
    269. 

  269. #define AM33XX_CM_CLKDCOLDO_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
    270. 

  270. #define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET		0x0080
    271. 

  271. #define AM33XX_CM_DIV_M4_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
    272. 

  272. #define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET		0x0084
    273. 

  273. #define AM33XX_CM_DIV_M5_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
    274. 

  274. #define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET		0x0088
    275. 

  275. #define AM33XX_CM_CLKMODE_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
    276. 

  276. #define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET		0x008c
    277. 

  277. #define AM33XX_CM_CLKMODE_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
    278. 

  278. #define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET		0x0090
    279. 

  279. #define AM33XX_CM_CLKMODE_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
    280. 

  280. #define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET		0x0094
    281. 

  281. #define AM33XX_CM_CLKMODE_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
    282. 

  282. #define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET		0x0098
    283. 

  283. #define AM33XX_CM_CLKMODE_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
    284. 

  284. #define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET		0x009c
    285. 

  285. #define AM33XX_CM_CLKSEL_DPLL_PERIPH			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
    286. 

  286. #define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET		0x00a0
    287. 

  287. #define AM33XX_CM_DIV_M2_DPLL_DDR			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
    288. 

  288. #define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET		0x00a4
    289. 

  289. #define AM33XX_CM_DIV_M2_DPLL_DISP			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
    290. 

  290. #define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET		0x00a8
    291. 

  291. #define AM33XX_CM_DIV_M2_DPLL_MPU			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
    292. 

  292. #define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET		0x00ac
    293. 

  293. #define AM33XX_CM_DIV_M2_DPLL_PER			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
    294. 

  294. #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET		0x00b0
    295. 

  295. #define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
    296. 

  296. #define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET		0x00b4
    297. 

  297. #define AM33XX_CM_WKUP_UART0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
    298. 

  298. #define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET		0x00b8
    299. 

  299. #define AM33XX_CM_WKUP_I2C0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
    300. 

  300. #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET		0x00bc
    301. 

  301. #define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
    302. 

  302. #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET	0x00c0
    303. 

  303. #define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
    304. 

  304. #define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET		0x00c4
    305. 

  305. #define AM33XX_CM_WKUP_TIMER1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
    306. 

  306. #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET	0x00c8
    307. 

  307. #define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL		AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
    308. 

  308. #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET		0x00cc
    309. 

  309. #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
    310. 

  310. #define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET		0x00d0
    311. 

  311. #define AM33XX_CM_WKUP_WDT0_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
    312. 

  312. #define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET		0x00d4
    313. 

  313. #define AM33XX_CM_WKUP_WDT1_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
    314. 

  314. #define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET		0x00d8
    315. 

  315. #define AM33XX_CM_DIV_M6_DPLL_CORE			AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
    316. 

  316. 

  317. /* CM.DPLL_CM register offsets */
    318. 

  318. #define AM33XX_CLKSEL_TIMER7_CLK_OFFSET			0x0004
    319. 

  319. #define AM33XX_CLKSEL_TIMER7_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
    320. 

  320. #define AM33XX_CLKSEL_TIMER2_CLK_OFFSET			0x0008
    321. 

  321. #define AM33XX_CLKSEL_TIMER2_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
    322. 

  322. #define AM33XX_CLKSEL_TIMER3_CLK_OFFSET			0x000c
    323. 

  323. #define AM33XX_CLKSEL_TIMER3_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
    324. 

  324. #define AM33XX_CLKSEL_TIMER4_CLK_OFFSET			0x0010
    325. 

  325. #define AM33XX_CLKSEL_TIMER4_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
    326. 

  326. #define AM33XX_CM_MAC_CLKSEL_OFFSET			0x0014
    327. 

  327. #define AM33XX_CM_MAC_CLKSEL				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
    328. 

  328. #define AM33XX_CLKSEL_TIMER5_CLK_OFFSET			0x0018
    329. 

  329. #define AM33XX_CLKSEL_TIMER5_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
    330. 

  330. #define AM33XX_CLKSEL_TIMER6_CLK_OFFSET			0x001c
    331. 

  331. #define AM33XX_CLKSEL_TIMER6_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
    332. 

  332. #define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET		0x0020
    333. 

  333. #define AM33XX_CM_CPTS_RFT_CLKSEL			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
    334. 

  334. #define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET		0x0028
    335. 

  335. #define AM33XX_CLKSEL_TIMER1MS_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
    336. 

  336. #define AM33XX_CLKSEL_GFX_FCLK_OFFSET			0x002c
    337. 

  337. #define AM33XX_CLKSEL_GFX_FCLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
    338. 

  338. #define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET		0x0030
    339. 

  339. #define AM33XX_CLKSEL_PRUSS_OCP_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
    340. 

  340. #define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET		0x0034
    341. 

  341. #define AM33XX_CLKSEL_LCDC_PIXEL_CLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
    342. 

  342. #define AM33XX_CLKSEL_WDT1_CLK_OFFSET			0x0038
    343. 

  343. #define AM33XX_CLKSEL_WDT1_CLK				AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
    344. 

  344. #define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET		0x003c
    345. 

  345. #define AM33XX_CLKSEL_GPIO0_DBCLK			AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
    346. 

  346. 

  347. /* CM.MPU_CM register offsets */
    348. 

  348. #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET			0x0000
    349. 

  349. #define AM33XX_CM_MPU_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
    350. 

  350. #define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET		0x0004
    351. 

  351. #define AM33XX_CM_MPU_MPU_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
    352. 

  352. 

  353. /* CM.DEVICE_CM register offsets */
    354. 

  354. #define AM33XX_CM_CLKOUT_CTRL_OFFSET			0x0000
    355. 

  355. #define AM33XX_CM_CLKOUT_CTRL				AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
    356. 

  356. 

  357. /* CM.RTC_CM register offsets */
    358. 

  358. #define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET		0x0000
    359. 

  359. #define AM33XX_CM_RTC_RTC_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
    360. 

  360. #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET			0x0004
    361. 

  361. #define AM33XX_CM_RTC_CLKSTCTRL				AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
    362. 

  362. 

  363. /* CM.GFX_CM register offsets */
    364. 

  364. #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET		0x0000
    365. 

  365. #define AM33XX_CM_GFX_L3_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
    366. 

  366. #define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET		0x0004
    367. 

  367. #define AM33XX_CM_GFX_GFX_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
    368. 

  368. #define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET		0x0008
    369. 

  369. #define AM33XX_CM_GFX_BITBLT_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
    370. 

  370. #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET	0x000c
    371. 

  371. #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1		AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
    372. 

  372. #define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET		0x0010
    373. 

  373. #define AM33XX_CM_GFX_MMUCFG_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
    374. 

  374. #define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET		0x0014
    375. 

  375. #define AM33XX_CM_GFX_MMUDATA_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
    376. 

  376. 

  377. /* CM.CEFUSE_CM register offsets */
    378. 

  378. #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET		0x0000
    379. 

  379. #define AM33XX_CM_CEFUSE_CLKSTCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
    380. 

  380. #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET		0x0020
    381. 

  381. #define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL			AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
    382. 

  382. 

  383. 

  384. extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
    385. 

  385. extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
    386. 

  386. extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
    387. 

  387. extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
    388. 

  388. extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
    389. 

  389. 

  390. #ifdef CONFIG_SOC_AM33XX
    391. 

  391. extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
    392. 

  392. 					u16 clkctrl_offs);
    393. 

  393. extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
    394. 

  394. 					u16 clkctrl_offs);
    395. 

  395. extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
    396. 

  396. 					u16 clkctrl_offs);
    397. 

  397. extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
    398. 

  398. 					u16 clkctrl_offs);
    399. 

  399. #else
    400. 

  400. static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
    401. 

  401. 					u16 clkctrl_offs)
    402. 

  402. {
    403. 

  403. 	return 0;
    404. 

  404. }
    405. 

  405. static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
    406. 

  406. 					u16 clkctrl_offs)
    407. 

  407. {
    408. 

  408. }
    409. 

  409. static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
    410. 

  410. 					u16 clkctrl_offs)
    411. 

  411. {
    412. 

  412. }
    413. 

  413. static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
    414. 

  414. 					u16 clkctrl_offs)
    415. 

  415. {
    416. 

  416. 	return 0;
    417. 

  417. }
    418. 

  418. #endif
    419. 

  419. 

  420. #endif
    421.