tegra20.dtsi 5.1 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. intc: interrupt-controller {
  6. compatible = "arm,cortex-a9-gic";
  7. reg = <0x50041000 0x1000
  8. 0x50040100 0x0100>;
  9. interrupt-controller;
  10. #interrupt-cells = <3>;
  11. };
  12. apbdma: dma {
  13. compatible = "nvidia,tegra20-apbdma";
  14. reg = <0x6000a000 0x1200>;
  15. interrupts = <0 104 0x04
  16. 0 105 0x04
  17. 0 106 0x04
  18. 0 107 0x04
  19. 0 108 0x04
  20. 0 109 0x04
  21. 0 110 0x04
  22. 0 111 0x04
  23. 0 112 0x04
  24. 0 113 0x04
  25. 0 114 0x04
  26. 0 115 0x04
  27. 0 116 0x04
  28. 0 117 0x04
  29. 0 118 0x04
  30. 0 119 0x04>;
  31. };
  32. ahb {
  33. compatible = "nvidia,tegra20-ahb";
  34. reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
  35. };
  36. gpio: gpio {
  37. compatible = "nvidia,tegra20-gpio";
  38. reg = <0x6000d000 0x1000>;
  39. interrupts = <0 32 0x04
  40. 0 33 0x04
  41. 0 34 0x04
  42. 0 35 0x04
  43. 0 55 0x04
  44. 0 87 0x04
  45. 0 89 0x04>;
  46. #gpio-cells = <2>;
  47. gpio-controller;
  48. #interrupt-cells = <2>;
  49. interrupt-controller;
  50. };
  51. pinmux: pinmux {
  52. compatible = "nvidia,tegra20-pinmux";
  53. reg = <0x70000014 0x10 /* Tri-state registers */
  54. 0x70000080 0x20 /* Mux registers */
  55. 0x700000a0 0x14 /* Pull-up/down registers */
  56. 0x70000868 0xa8>; /* Pad control registers */
  57. };
  58. das {
  59. compatible = "nvidia,tegra20-das";
  60. reg = <0x70000c00 0x80>;
  61. };
  62. tegra_i2s1: i2s@70002800 {
  63. compatible = "nvidia,tegra20-i2s";
  64. reg = <0x70002800 0x200>;
  65. interrupts = <0 13 0x04>;
  66. nvidia,dma-request-selector = <&apbdma 2>;
  67. status = "disabled";
  68. };
  69. tegra_i2s2: i2s@70002a00 {
  70. compatible = "nvidia,tegra20-i2s";
  71. reg = <0x70002a00 0x200>;
  72. interrupts = <0 3 0x04>;
  73. nvidia,dma-request-selector = <&apbdma 1>;
  74. status = "disabled";
  75. };
  76. serial@70006000 {
  77. compatible = "nvidia,tegra20-uart";
  78. reg = <0x70006000 0x40>;
  79. reg-shift = <2>;
  80. interrupts = <0 36 0x04>;
  81. status = "disabled";
  82. };
  83. serial@70006040 {
  84. compatible = "nvidia,tegra20-uart";
  85. reg = <0x70006040 0x40>;
  86. reg-shift = <2>;
  87. interrupts = <0 37 0x04>;
  88. status = "disabled";
  89. };
  90. serial@70006200 {
  91. compatible = "nvidia,tegra20-uart";
  92. reg = <0x70006200 0x100>;
  93. reg-shift = <2>;
  94. interrupts = <0 46 0x04>;
  95. status = "disabled";
  96. };
  97. serial@70006300 {
  98. compatible = "nvidia,tegra20-uart";
  99. reg = <0x70006300 0x100>;
  100. reg-shift = <2>;
  101. interrupts = <0 90 0x04>;
  102. status = "disabled";
  103. };
  104. serial@70006400 {
  105. compatible = "nvidia,tegra20-uart";
  106. reg = <0x70006400 0x100>;
  107. reg-shift = <2>;
  108. interrupts = <0 91 0x04>;
  109. status = "disabled";
  110. };
  111. pwm {
  112. compatible = "nvidia,tegra20-pwm";
  113. reg = <0x7000a000 0x100>;
  114. #pwm-cells = <2>;
  115. };
  116. i2c@7000c000 {
  117. compatible = "nvidia,tegra20-i2c";
  118. reg = <0x7000c000 0x100>;
  119. interrupts = <0 38 0x04>;
  120. #address-cells = <1>;
  121. #size-cells = <0>;
  122. status = "disabled";
  123. };
  124. i2c@7000c400 {
  125. compatible = "nvidia,tegra20-i2c";
  126. reg = <0x7000c400 0x100>;
  127. interrupts = <0 84 0x04>;
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. status = "disabled";
  131. };
  132. i2c@7000c500 {
  133. compatible = "nvidia,tegra20-i2c";
  134. reg = <0x7000c500 0x100>;
  135. interrupts = <0 92 0x04>;
  136. #address-cells = <1>;
  137. #size-cells = <0>;
  138. status = "disabled";
  139. };
  140. i2c@7000d000 {
  141. compatible = "nvidia,tegra20-i2c-dvc";
  142. reg = <0x7000d000 0x200>;
  143. interrupts = <0 53 0x04>;
  144. #address-cells = <1>;
  145. #size-cells = <0>;
  146. status = "disabled";
  147. };
  148. pmc {
  149. compatible = "nvidia,tegra20-pmc";
  150. reg = <0x7000e400 0x400>;
  151. };
  152. memory-controller@0x7000f000 {
  153. compatible = "nvidia,tegra20-mc";
  154. reg = <0x7000f000 0x024
  155. 0x7000f03c 0x3c4>;
  156. interrupts = <0 77 0x04>;
  157. };
  158. gart {
  159. compatible = "nvidia,tegra20-gart";
  160. reg = <0x7000f024 0x00000018 /* controller registers */
  161. 0x58000000 0x02000000>; /* GART aperture */
  162. };
  163. memory-controller@0x7000f400 {
  164. compatible = "nvidia,tegra20-emc";
  165. reg = <0x7000f400 0x200>;
  166. #address-cells = <1>;
  167. #size-cells = <0>;
  168. };
  169. usb@c5000000 {
  170. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  171. reg = <0xc5000000 0x4000>;
  172. interrupts = <0 20 0x04>;
  173. phy_type = "utmi";
  174. nvidia,has-legacy-mode;
  175. status = "disabled";
  176. };
  177. usb@c5004000 {
  178. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  179. reg = <0xc5004000 0x4000>;
  180. interrupts = <0 21 0x04>;
  181. phy_type = "ulpi";
  182. status = "disabled";
  183. };
  184. usb@c5008000 {
  185. compatible = "nvidia,tegra20-ehci", "usb-ehci";
  186. reg = <0xc5008000 0x4000>;
  187. interrupts = <0 97 0x04>;
  188. phy_type = "utmi";
  189. status = "disabled";
  190. };
  191. sdhci@c8000000 {
  192. compatible = "nvidia,tegra20-sdhci";
  193. reg = <0xc8000000 0x200>;
  194. interrupts = <0 14 0x04>;
  195. status = "disabled";
  196. };
  197. sdhci@c8000200 {
  198. compatible = "nvidia,tegra20-sdhci";
  199. reg = <0xc8000200 0x200>;
  200. interrupts = <0 15 0x04>;
  201. status = "disabled";
  202. };
  203. sdhci@c8000400 {
  204. compatible = "nvidia,tegra20-sdhci";
  205. reg = <0xc8000400 0x200>;
  206. interrupts = <0 19 0x04>;
  207. status = "disabled";
  208. };
  209. sdhci@c8000600 {
  210. compatible = "nvidia,tegra20-sdhci";
  211. reg = <0xc8000600 0x200>;
  212. interrupts = <0 31 0x04>;
  213. status = "disabled";
  214. };
  215. pmu {
  216. compatible = "arm,cortex-a9-pmu";
  217. interrupts = <0 56 0x04
  218. 0 57 0x04>;
  219. };
  220. };