tegra20-whistler.dts 6.1 KB

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  1. /dts-v1/;
  2. /include/ "tegra20.dtsi"
  3. / {
  4. model = "NVIDIA Tegra2 Whistler evaluation board";
  5. compatible = "nvidia,whistler", "nvidia,tegra20";
  6. memory {
  7. reg = <0x00000000 0x20000000>;
  8. };
  9. pinmux {
  10. pinctrl-names = "default";
  11. pinctrl-0 = <&state_default>;
  12. state_default: pinmux {
  13. ata {
  14. nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
  15. "gmc", "gmd", "gpu";
  16. nvidia,function = "gmi";
  17. };
  18. atc {
  19. nvidia,pins = "atc", "atd";
  20. nvidia,function = "sdio4";
  21. };
  22. cdev1 {
  23. nvidia,pins = "cdev1";
  24. nvidia,function = "plla_out";
  25. };
  26. cdev2 {
  27. nvidia,pins = "cdev2";
  28. nvidia,function = "osc";
  29. };
  30. crtp {
  31. nvidia,pins = "crtp";
  32. nvidia,function = "crt";
  33. };
  34. csus {
  35. nvidia,pins = "csus";
  36. nvidia,function = "vi_sensor_clk";
  37. };
  38. dap1 {
  39. nvidia,pins = "dap1";
  40. nvidia,function = "dap1";
  41. };
  42. dap2 {
  43. nvidia,pins = "dap2";
  44. nvidia,function = "dap2";
  45. };
  46. dap3 {
  47. nvidia,pins = "dap3";
  48. nvidia,function = "dap3";
  49. };
  50. dap4 {
  51. nvidia,pins = "dap4";
  52. nvidia,function = "dap4";
  53. };
  54. ddc {
  55. nvidia,pins = "ddc";
  56. nvidia,function = "i2c2";
  57. };
  58. dta {
  59. nvidia,pins = "dta", "dtb", "dtc", "dtd";
  60. nvidia,function = "vi";
  61. };
  62. dte {
  63. nvidia,pins = "dte";
  64. nvidia,function = "rsvd1";
  65. };
  66. dtf {
  67. nvidia,pins = "dtf";
  68. nvidia,function = "i2c3";
  69. };
  70. gme {
  71. nvidia,pins = "gme";
  72. nvidia,function = "dap5";
  73. };
  74. gpu7 {
  75. nvidia,pins = "gpu7";
  76. nvidia,function = "rtck";
  77. };
  78. gpv {
  79. nvidia,pins = "gpv";
  80. nvidia,function = "pcie";
  81. };
  82. hdint {
  83. nvidia,pins = "hdint", "pta";
  84. nvidia,function = "hdmi";
  85. };
  86. i2cp {
  87. nvidia,pins = "i2cp";
  88. nvidia,function = "i2cp";
  89. };
  90. irrx {
  91. nvidia,pins = "irrx", "irtx";
  92. nvidia,function = "uartb";
  93. };
  94. kbca {
  95. nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
  96. nvidia,function = "kbc";
  97. };
  98. kbcb {
  99. nvidia,pins = "kbcb", "kbcd";
  100. nvidia,function = "sdio2";
  101. };
  102. lcsn {
  103. nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
  104. "spia", "spib", "spic";
  105. nvidia,function = "spi3";
  106. };
  107. ld0 {
  108. nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
  109. "ld5", "ld6", "ld7", "ld8", "ld9",
  110. "ld10", "ld11", "ld12", "ld13", "ld14",
  111. "ld15", "ld16", "ld17", "ldc", "ldi",
  112. "lhp0", "lhp1", "lhp2", "lhs", "lm0",
  113. "lm1", "lpp", "lpw0", "lpw1", "lpw2",
  114. "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
  115. "lvs";
  116. nvidia,function = "displaya";
  117. };
  118. owc {
  119. nvidia,pins = "owc", "uac";
  120. nvidia,function = "owr";
  121. };
  122. pmc {
  123. nvidia,pins = "pmc";
  124. nvidia,function = "pwr_on";
  125. };
  126. rm {
  127. nvidia,pins = "rm";
  128. nvidia,function = "i2c1";
  129. };
  130. sdb {
  131. nvidia,pins = "sdb", "sdc", "sdd", "slxa",
  132. "slxc", "slxd", "slxk";
  133. nvidia,function = "sdio3";
  134. };
  135. sdio1 {
  136. nvidia,pins = "sdio1";
  137. nvidia,function = "sdio1";
  138. };
  139. spdi {
  140. nvidia,pins = "spdi", "spdo";
  141. nvidia,function = "rsvd2";
  142. };
  143. spid {
  144. nvidia,pins = "spid", "spie", "spig", "spih";
  145. nvidia,function = "spi2_alt";
  146. };
  147. spif {
  148. nvidia,pins = "spif";
  149. nvidia,function = "spi2";
  150. };
  151. uaa {
  152. nvidia,pins = "uaa", "uab";
  153. nvidia,function = "uarta";
  154. };
  155. uad {
  156. nvidia,pins = "uad";
  157. nvidia,function = "irda";
  158. };
  159. uca {
  160. nvidia,pins = "uca", "ucb";
  161. nvidia,function = "uartc";
  162. };
  163. uda {
  164. nvidia,pins = "uda";
  165. nvidia,function = "spi1";
  166. };
  167. conf_ata {
  168. nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
  169. "gmb", "gmc", "gmd", "irrx", "irtx",
  170. "kbca", "kbcb", "kbcc", "kbcd", "kbce",
  171. "kbcf", "sdc", "sdd", "spie", "spig",
  172. "spih", "uaa", "uab", "uad", "uca",
  173. "ucb";
  174. nvidia,pull = <2>;
  175. nvidia,tristate = <0>;
  176. };
  177. conf_atd {
  178. nvidia,pins = "atd", "ate", "cdev1", "csus",
  179. "dap1", "dap2", "dap3", "dap4", "dte",
  180. "dtf", "gpu", "gpu7", "gpv", "i2cp",
  181. "rm", "sdio1", "slxa", "slxc", "slxd",
  182. "slxk", "spdi", "spdo", "uac", "uda";
  183. nvidia,pull = <0>;
  184. nvidia,tristate = <0>;
  185. };
  186. conf_cdev2 {
  187. nvidia,pins = "cdev2", "spia", "spib";
  188. nvidia,pull = <1>;
  189. nvidia,tristate = <1>;
  190. };
  191. conf_ck32 {
  192. nvidia,pins = "ck32", "ddrc", "lc", "pmca",
  193. "pmcb", "pmcc", "pmcd", "xm2c",
  194. "xm2d";
  195. nvidia,pull = <0>;
  196. };
  197. conf_crtp {
  198. nvidia,pins = "crtp";
  199. nvidia,pull = <0>;
  200. nvidia,tristate = <1>;
  201. };
  202. conf_dta {
  203. nvidia,pins = "dta", "dtb", "dtc", "dtd",
  204. "spid", "spif";
  205. nvidia,pull = <1>;
  206. nvidia,tristate = <0>;
  207. };
  208. conf_gme {
  209. nvidia,pins = "gme", "owc", "pta", "spic";
  210. nvidia,pull = <2>;
  211. nvidia,tristate = <1>;
  212. };
  213. conf_ld17_0 {
  214. nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
  215. "ld23_22";
  216. nvidia,pull = <1>;
  217. };
  218. conf_ls {
  219. nvidia,pins = "ls", "pmce";
  220. nvidia,pull = <2>;
  221. };
  222. drive_dap1 {
  223. nvidia,pins = "drive_dap1";
  224. nvidia,high-speed-mode = <0>;
  225. nvidia,schmitt = <1>;
  226. nvidia,low-power-mode = <0>;
  227. nvidia,pull-down-strength = <0>;
  228. nvidia,pull-up-strength = <0>;
  229. nvidia,slew-rate-rising = <0>;
  230. nvidia,slew-rate-falling = <0>;
  231. };
  232. };
  233. };
  234. i2s@70002800 {
  235. status = "okay";
  236. };
  237. serial@70006000 {
  238. status = "okay";
  239. clock-frequency = <216000000>;
  240. };
  241. i2c@7000d000 {
  242. status = "okay";
  243. clock-frequency = <100000>;
  244. codec: codec@1a {
  245. compatible = "wlf,wm8753";
  246. reg = <0x1a>;
  247. };
  248. tca6416: gpio@20 {
  249. compatible = "ti,tca6416";
  250. reg = <0x20>;
  251. gpio-controller;
  252. #gpio-cells = <2>;
  253. };
  254. };
  255. usb@c5000000 {
  256. status = "okay";
  257. nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
  258. };
  259. usb@c5008000 {
  260. status = "okay";
  261. nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
  262. };
  263. sdhci@c8000400 {
  264. status = "okay";
  265. wp-gpios = <&gpio 173 0>; /* gpio PV5 */
  266. bus-width = <8>;
  267. };
  268. sdhci@c8000600 {
  269. status = "okay";
  270. bus-width = <8>;
  271. };
  272. sound {
  273. compatible = "nvidia,tegra-audio-wm8753-whistler",
  274. "nvidia,tegra-audio-wm8753";
  275. nvidia,model = "NVIDIA Tegra Whistler";
  276. nvidia,audio-routing =
  277. "Headphone Jack", "LOUT1",
  278. "Headphone Jack", "ROUT1",
  279. "MIC2", "Mic Jack",
  280. "MIC2N", "Mic Jack";
  281. nvidia,i2s-controller = <&tegra_i2s1>;
  282. nvidia,audio-codec = <&codec>;
  283. };
  284. };