imx28.dtsi 19 KB

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  1. /*
  2. * Copyright 2012 Freescale Semiconductor, Inc.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. interrupt-parent = <&icoll>;
  14. aliases {
  15. gpio0 = &gpio0;
  16. gpio1 = &gpio1;
  17. gpio2 = &gpio2;
  18. gpio3 = &gpio3;
  19. gpio4 = &gpio4;
  20. saif0 = &saif0;
  21. saif1 = &saif1;
  22. serial0 = &auart0;
  23. serial1 = &auart1;
  24. serial2 = &auart2;
  25. serial3 = &auart3;
  26. serial4 = &auart4;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. apb@80000000 {
  34. compatible = "simple-bus";
  35. #address-cells = <1>;
  36. #size-cells = <1>;
  37. reg = <0x80000000 0x80000>;
  38. ranges;
  39. apbh@80000000 {
  40. compatible = "simple-bus";
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. reg = <0x80000000 0x3c900>;
  44. ranges;
  45. icoll: interrupt-controller@80000000 {
  46. compatible = "fsl,imx28-icoll", "fsl,mxs-icoll";
  47. interrupt-controller;
  48. #interrupt-cells = <1>;
  49. reg = <0x80000000 0x2000>;
  50. };
  51. hsadc@80002000 {
  52. reg = <0x80002000 2000>;
  53. interrupts = <13 87>;
  54. status = "disabled";
  55. };
  56. dma-apbh@80004000 {
  57. compatible = "fsl,imx28-dma-apbh";
  58. reg = <0x80004000 2000>;
  59. };
  60. perfmon@80006000 {
  61. reg = <0x80006000 800>;
  62. interrupts = <27>;
  63. status = "disabled";
  64. };
  65. gpmi-nand@8000c000 {
  66. compatible = "fsl,imx28-gpmi-nand";
  67. #address-cells = <1>;
  68. #size-cells = <1>;
  69. reg = <0x8000c000 2000>, <0x8000a000 2000>;
  70. reg-names = "gpmi-nand", "bch";
  71. interrupts = <88>, <41>;
  72. interrupt-names = "gpmi-dma", "bch";
  73. fsl,gpmi-dma-channel = <4>;
  74. status = "disabled";
  75. };
  76. ssp0: ssp@80010000 {
  77. reg = <0x80010000 2000>;
  78. interrupts = <96 82>;
  79. fsl,ssp-dma-channel = <0>;
  80. status = "disabled";
  81. };
  82. ssp1: ssp@80012000 {
  83. reg = <0x80012000 2000>;
  84. interrupts = <97 83>;
  85. fsl,ssp-dma-channel = <1>;
  86. status = "disabled";
  87. };
  88. ssp2: ssp@80014000 {
  89. reg = <0x80014000 2000>;
  90. interrupts = <98 84>;
  91. fsl,ssp-dma-channel = <2>;
  92. status = "disabled";
  93. };
  94. ssp3: ssp@80016000 {
  95. reg = <0x80016000 2000>;
  96. interrupts = <99 85>;
  97. fsl,ssp-dma-channel = <3>;
  98. status = "disabled";
  99. };
  100. pinctrl@80018000 {
  101. #address-cells = <1>;
  102. #size-cells = <0>;
  103. compatible = "fsl,imx28-pinctrl", "simple-bus";
  104. reg = <0x80018000 2000>;
  105. gpio0: gpio@0 {
  106. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  107. interrupts = <127>;
  108. gpio-controller;
  109. #gpio-cells = <2>;
  110. interrupt-controller;
  111. #interrupt-cells = <2>;
  112. };
  113. gpio1: gpio@1 {
  114. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  115. interrupts = <126>;
  116. gpio-controller;
  117. #gpio-cells = <2>;
  118. interrupt-controller;
  119. #interrupt-cells = <2>;
  120. };
  121. gpio2: gpio@2 {
  122. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  123. interrupts = <125>;
  124. gpio-controller;
  125. #gpio-cells = <2>;
  126. interrupt-controller;
  127. #interrupt-cells = <2>;
  128. };
  129. gpio3: gpio@3 {
  130. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  131. interrupts = <124>;
  132. gpio-controller;
  133. #gpio-cells = <2>;
  134. interrupt-controller;
  135. #interrupt-cells = <2>;
  136. };
  137. gpio4: gpio@4 {
  138. compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
  139. interrupts = <123>;
  140. gpio-controller;
  141. #gpio-cells = <2>;
  142. interrupt-controller;
  143. #interrupt-cells = <2>;
  144. };
  145. duart_pins_a: duart@0 {
  146. reg = <0>;
  147. fsl,pinmux-ids = <
  148. 0x3102 /* MX28_PAD_PWM0__DUART_RX */
  149. 0x3112 /* MX28_PAD_PWM1__DUART_TX */
  150. >;
  151. fsl,drive-strength = <0>;
  152. fsl,voltage = <1>;
  153. fsl,pull-up = <0>;
  154. };
  155. duart_pins_b: duart@1 {
  156. reg = <1>;
  157. fsl,pinmux-ids = <
  158. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  159. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  160. >;
  161. fsl,drive-strength = <0>;
  162. fsl,voltage = <1>;
  163. fsl,pull-up = <0>;
  164. };
  165. duart_4pins_a: duart-4pins@0 {
  166. reg = <0>;
  167. fsl,pinmux-ids = <
  168. 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
  169. 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
  170. 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
  171. 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
  172. >;
  173. fsl,drive-strength = <0>;
  174. fsl,voltage = <1>;
  175. fsl,pull-up = <0>;
  176. };
  177. gpmi_pins_a: gpmi-nand@0 {
  178. reg = <0>;
  179. fsl,pinmux-ids = <
  180. 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
  181. 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
  182. 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
  183. 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
  184. 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
  185. 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
  186. 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
  187. 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
  188. 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
  189. 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
  190. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  191. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  192. 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
  193. 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
  194. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  195. >;
  196. fsl,drive-strength = <0>;
  197. fsl,voltage = <1>;
  198. fsl,pull-up = <0>;
  199. };
  200. gpmi_status_cfg: gpmi-status-cfg {
  201. fsl,pinmux-ids = <
  202. 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
  203. 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
  204. 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
  205. >;
  206. fsl,drive-strength = <2>;
  207. };
  208. auart0_pins_a: auart0@0 {
  209. reg = <0>;
  210. fsl,pinmux-ids = <
  211. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  212. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  213. 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
  214. 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
  215. >;
  216. fsl,drive-strength = <0>;
  217. fsl,voltage = <1>;
  218. fsl,pull-up = <0>;
  219. };
  220. auart0_2pins_a: auart0-2pins@0 {
  221. reg = <0>;
  222. fsl,pinmux-ids = <
  223. 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
  224. 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
  225. >;
  226. fsl,drive-strength = <0>;
  227. fsl,voltage = <1>;
  228. fsl,pull-up = <0>;
  229. };
  230. auart1_pins_a: auart1@0 {
  231. reg = <0>;
  232. fsl,pinmux-ids = <
  233. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  234. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  235. 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
  236. 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
  237. >;
  238. fsl,drive-strength = <0>;
  239. fsl,voltage = <1>;
  240. fsl,pull-up = <0>;
  241. };
  242. auart1_2pins_a: auart1-2pins@0 {
  243. reg = <0>;
  244. fsl,pinmux-ids = <
  245. 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
  246. 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
  247. >;
  248. fsl,drive-strength = <0>;
  249. fsl,voltage = <1>;
  250. fsl,pull-up = <0>;
  251. };
  252. auart2_2pins_a: auart2-2pins@0 {
  253. reg = <0>;
  254. fsl,pinmux-ids = <
  255. 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
  256. 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
  257. >;
  258. fsl,drive-strength = <0>;
  259. fsl,voltage = <1>;
  260. fsl,pull-up = <0>;
  261. };
  262. auart3_pins_a: auart3@0 {
  263. reg = <0>;
  264. fsl,pinmux-ids = <
  265. 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
  266. 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
  267. 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
  268. 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
  269. >;
  270. fsl,drive-strength = <0>;
  271. fsl,voltage = <1>;
  272. fsl,pull-up = <0>;
  273. };
  274. auart3_2pins_a: auart3-2pins@0 {
  275. reg = <0>;
  276. fsl,pinmux-ids = <
  277. 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
  278. 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
  279. >;
  280. fsl,drive-strength = <0>;
  281. fsl,voltage = <1>;
  282. fsl,pull-up = <0>;
  283. };
  284. mac0_pins_a: mac0@0 {
  285. reg = <0>;
  286. fsl,pinmux-ids = <
  287. 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
  288. 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
  289. 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
  290. 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
  291. 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
  292. 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
  293. 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
  294. 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
  295. 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
  296. >;
  297. fsl,drive-strength = <1>;
  298. fsl,voltage = <1>;
  299. fsl,pull-up = <1>;
  300. };
  301. mac1_pins_a: mac1@0 {
  302. reg = <0>;
  303. fsl,pinmux-ids = <
  304. 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
  305. 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
  306. 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
  307. 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
  308. 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
  309. 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
  310. >;
  311. fsl,drive-strength = <1>;
  312. fsl,voltage = <1>;
  313. fsl,pull-up = <1>;
  314. };
  315. mmc0_8bit_pins_a: mmc0-8bit@0 {
  316. reg = <0>;
  317. fsl,pinmux-ids = <
  318. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  319. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  320. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  321. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  322. 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
  323. 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
  324. 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
  325. 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
  326. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  327. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  328. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  329. >;
  330. fsl,drive-strength = <1>;
  331. fsl,voltage = <1>;
  332. fsl,pull-up = <1>;
  333. };
  334. mmc0_4bit_pins_a: mmc0-4bit@0 {
  335. reg = <0>;
  336. fsl,pinmux-ids = <
  337. 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
  338. 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
  339. 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
  340. 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
  341. 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
  342. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  343. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  344. >;
  345. fsl,drive-strength = <1>;
  346. fsl,voltage = <1>;
  347. fsl,pull-up = <1>;
  348. };
  349. mmc0_cd_cfg: mmc0-cd-cfg {
  350. fsl,pinmux-ids = <
  351. 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
  352. >;
  353. fsl,pull-up = <0>;
  354. };
  355. mmc0_sck_cfg: mmc0-sck-cfg {
  356. fsl,pinmux-ids = <
  357. 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
  358. >;
  359. fsl,drive-strength = <2>;
  360. fsl,pull-up = <0>;
  361. };
  362. i2c0_pins_a: i2c0@0 {
  363. reg = <0>;
  364. fsl,pinmux-ids = <
  365. 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
  366. 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
  367. >;
  368. fsl,drive-strength = <1>;
  369. fsl,voltage = <1>;
  370. fsl,pull-up = <1>;
  371. };
  372. saif0_pins_a: saif0@0 {
  373. reg = <0>;
  374. fsl,pinmux-ids = <
  375. 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
  376. 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
  377. 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
  378. 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
  379. >;
  380. fsl,drive-strength = <2>;
  381. fsl,voltage = <1>;
  382. fsl,pull-up = <1>;
  383. };
  384. saif1_pins_a: saif1@0 {
  385. reg = <0>;
  386. fsl,pinmux-ids = <
  387. 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
  388. >;
  389. fsl,drive-strength = <2>;
  390. fsl,voltage = <1>;
  391. fsl,pull-up = <1>;
  392. };
  393. pwm0_pins_a: pwm0@0 {
  394. reg = <0>;
  395. fsl,pinmux-ids = <
  396. 0x3100 /* MX28_PAD_PWM0__PWM_0 */
  397. >;
  398. fsl,drive-strength = <0>;
  399. fsl,voltage = <1>;
  400. fsl,pull-up = <0>;
  401. };
  402. pwm2_pins_a: pwm2@0 {
  403. reg = <0>;
  404. fsl,pinmux-ids = <
  405. 0x3120 /* MX28_PAD_PWM2__PWM_2 */
  406. >;
  407. fsl,drive-strength = <0>;
  408. fsl,voltage = <1>;
  409. fsl,pull-up = <0>;
  410. };
  411. lcdif_24bit_pins_a: lcdif-24bit@0 {
  412. reg = <0>;
  413. fsl,pinmux-ids = <
  414. 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
  415. 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
  416. 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
  417. 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
  418. 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
  419. 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
  420. 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
  421. 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
  422. 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
  423. 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
  424. 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
  425. 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
  426. 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
  427. 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
  428. 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
  429. 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
  430. 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
  431. 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
  432. 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
  433. 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
  434. 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
  435. 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
  436. 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
  437. 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
  438. >;
  439. fsl,drive-strength = <0>;
  440. fsl,voltage = <1>;
  441. fsl,pull-up = <0>;
  442. };
  443. can0_pins_a: can0@0 {
  444. reg = <0>;
  445. fsl,pinmux-ids = <
  446. 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
  447. 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
  448. >;
  449. fsl,drive-strength = <0>;
  450. fsl,voltage = <1>;
  451. fsl,pull-up = <0>;
  452. };
  453. can1_pins_a: can1@0 {
  454. reg = <0>;
  455. fsl,pinmux-ids = <
  456. 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
  457. 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
  458. >;
  459. fsl,drive-strength = <0>;
  460. fsl,voltage = <1>;
  461. fsl,pull-up = <0>;
  462. };
  463. };
  464. digctl@8001c000 {
  465. reg = <0x8001c000 2000>;
  466. interrupts = <89>;
  467. status = "disabled";
  468. };
  469. etm@80022000 {
  470. reg = <0x80022000 2000>;
  471. status = "disabled";
  472. };
  473. dma-apbx@80024000 {
  474. compatible = "fsl,imx28-dma-apbx";
  475. reg = <0x80024000 2000>;
  476. };
  477. dcp@80028000 {
  478. reg = <0x80028000 2000>;
  479. interrupts = <52 53 54>;
  480. status = "disabled";
  481. };
  482. pxp@8002a000 {
  483. reg = <0x8002a000 2000>;
  484. interrupts = <39>;
  485. status = "disabled";
  486. };
  487. ocotp@8002c000 {
  488. reg = <0x8002c000 2000>;
  489. status = "disabled";
  490. };
  491. axi-ahb@8002e000 {
  492. reg = <0x8002e000 2000>;
  493. status = "disabled";
  494. };
  495. lcdif@80030000 {
  496. compatible = "fsl,imx28-lcdif";
  497. reg = <0x80030000 2000>;
  498. interrupts = <38 86>;
  499. status = "disabled";
  500. };
  501. can0: can@80032000 {
  502. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  503. reg = <0x80032000 2000>;
  504. interrupts = <8>;
  505. status = "disabled";
  506. };
  507. can1: can@80034000 {
  508. compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
  509. reg = <0x80034000 2000>;
  510. interrupts = <9>;
  511. status = "disabled";
  512. };
  513. simdbg@8003c000 {
  514. reg = <0x8003c000 200>;
  515. status = "disabled";
  516. };
  517. simgpmisel@8003c200 {
  518. reg = <0x8003c200 100>;
  519. status = "disabled";
  520. };
  521. simsspsel@8003c300 {
  522. reg = <0x8003c300 100>;
  523. status = "disabled";
  524. };
  525. simmemsel@8003c400 {
  526. reg = <0x8003c400 100>;
  527. status = "disabled";
  528. };
  529. gpiomon@8003c500 {
  530. reg = <0x8003c500 100>;
  531. status = "disabled";
  532. };
  533. simenet@8003c700 {
  534. reg = <0x8003c700 100>;
  535. status = "disabled";
  536. };
  537. armjtag@8003c800 {
  538. reg = <0x8003c800 100>;
  539. status = "disabled";
  540. };
  541. };
  542. apbx@80040000 {
  543. compatible = "simple-bus";
  544. #address-cells = <1>;
  545. #size-cells = <1>;
  546. reg = <0x80040000 0x40000>;
  547. ranges;
  548. clkctl@80040000 {
  549. reg = <0x80040000 2000>;
  550. status = "disabled";
  551. };
  552. saif0: saif@80042000 {
  553. compatible = "fsl,imx28-saif";
  554. reg = <0x80042000 2000>;
  555. interrupts = <59 80>;
  556. fsl,saif-dma-channel = <4>;
  557. status = "disabled";
  558. };
  559. power@80044000 {
  560. reg = <0x80044000 2000>;
  561. status = "disabled";
  562. };
  563. saif1: saif@80046000 {
  564. compatible = "fsl,imx28-saif";
  565. reg = <0x80046000 2000>;
  566. interrupts = <58 81>;
  567. fsl,saif-dma-channel = <5>;
  568. status = "disabled";
  569. };
  570. lradc@80050000 {
  571. reg = <0x80050000 2000>;
  572. status = "disabled";
  573. };
  574. spdif@80054000 {
  575. reg = <0x80054000 2000>;
  576. interrupts = <45 66>;
  577. status = "disabled";
  578. };
  579. rtc@80056000 {
  580. compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
  581. reg = <0x80056000 2000>;
  582. interrupts = <29>;
  583. };
  584. i2c0: i2c@80058000 {
  585. #address-cells = <1>;
  586. #size-cells = <0>;
  587. compatible = "fsl,imx28-i2c";
  588. reg = <0x80058000 2000>;
  589. interrupts = <111 68>;
  590. clock-frequency = <100000>;
  591. status = "disabled";
  592. };
  593. i2c1: i2c@8005a000 {
  594. #address-cells = <1>;
  595. #size-cells = <0>;
  596. compatible = "fsl,imx28-i2c";
  597. reg = <0x8005a000 2000>;
  598. interrupts = <110 69>;
  599. clock-frequency = <100000>;
  600. status = "disabled";
  601. };
  602. pwm: pwm@80064000 {
  603. compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
  604. reg = <0x80064000 2000>;
  605. #pwm-cells = <2>;
  606. fsl,pwm-number = <8>;
  607. status = "disabled";
  608. };
  609. timrot@80068000 {
  610. reg = <0x80068000 2000>;
  611. status = "disabled";
  612. };
  613. auart0: serial@8006a000 {
  614. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  615. reg = <0x8006a000 0x2000>;
  616. interrupts = <112 70 71>;
  617. status = "disabled";
  618. };
  619. auart1: serial@8006c000 {
  620. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  621. reg = <0x8006c000 0x2000>;
  622. interrupts = <113 72 73>;
  623. status = "disabled";
  624. };
  625. auart2: serial@8006e000 {
  626. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  627. reg = <0x8006e000 0x2000>;
  628. interrupts = <114 74 75>;
  629. status = "disabled";
  630. };
  631. auart3: serial@80070000 {
  632. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  633. reg = <0x80070000 0x2000>;
  634. interrupts = <115 76 77>;
  635. status = "disabled";
  636. };
  637. auart4: serial@80072000 {
  638. compatible = "fsl,imx28-auart", "fsl,imx23-auart";
  639. reg = <0x80072000 0x2000>;
  640. interrupts = <116 78 79>;
  641. status = "disabled";
  642. };
  643. duart: serial@80074000 {
  644. compatible = "arm,pl011", "arm,primecell";
  645. reg = <0x80074000 0x1000>;
  646. interrupts = <47>;
  647. status = "disabled";
  648. };
  649. usbphy0: usbphy@8007c000 {
  650. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  651. reg = <0x8007c000 0x2000>;
  652. status = "disabled";
  653. };
  654. usbphy1: usbphy@8007e000 {
  655. compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
  656. reg = <0x8007e000 0x2000>;
  657. status = "disabled";
  658. };
  659. };
  660. };
  661. ahb@80080000 {
  662. compatible = "simple-bus";
  663. #address-cells = <1>;
  664. #size-cells = <1>;
  665. reg = <0x80080000 0x80000>;
  666. ranges;
  667. usb0: usb@80080000 {
  668. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  669. reg = <0x80080000 0x10000>;
  670. interrupts = <93>;
  671. fsl,usbphy = <&usbphy0>;
  672. status = "disabled";
  673. };
  674. usb1: usb@80090000 {
  675. compatible = "fsl,imx28-usb", "fsl,imx27-usb";
  676. reg = <0x80090000 0x10000>;
  677. interrupts = <92>;
  678. fsl,usbphy = <&usbphy1>;
  679. status = "disabled";
  680. };
  681. dflpt@800c0000 {
  682. reg = <0x800c0000 0x10000>;
  683. status = "disabled";
  684. };
  685. mac0: ethernet@800f0000 {
  686. compatible = "fsl,imx28-fec";
  687. reg = <0x800f0000 0x4000>;
  688. interrupts = <101>;
  689. status = "disabled";
  690. };
  691. mac1: ethernet@800f4000 {
  692. compatible = "fsl,imx28-fec";
  693. reg = <0x800f4000 0x4000>;
  694. interrupts = <102>;
  695. status = "disabled";
  696. };
  697. switch@800f8000 {
  698. reg = <0x800f8000 0x8000>;
  699. status = "disabled";
  700. };
  701. };
  702. };