cpsw.txt 3.3 KB

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  1. TI SoC Ethernet Switch Controller Device Tree Bindings
  2. ------------------------------------------------------
  3. Required properties:
  4. - compatible : Should be "ti,cpsw"
  5. - reg : physical base address and size of the cpsw
  6. registers map
  7. - interrupts : property with a value describing the interrupt
  8. number
  9. - interrupt-parent : The parent interrupt controller
  10. - cpdma_channels : Specifies number of channels in CPDMA
  11. - host_port_no : Specifies host port shift
  12. - cpdma_reg_ofs : Specifies CPDMA submodule register offset
  13. - cpdma_sram_ofs : Specifies CPDMA SRAM offset
  14. - ale_reg_ofs : Specifies ALE submodule register offset
  15. - ale_entries : Specifies No of entries ALE can hold
  16. - host_port_reg_ofs : Specifies host port register offset
  17. - hw_stats_reg_ofs : Specifies hardware statistics register offset
  18. - bd_ram_ofs : Specifies internal desciptor RAM offset
  19. - bd_ram_size : Specifies internal descriptor RAM size
  20. - rx_descs : Specifies number of Rx descriptors
  21. - mac_control : Specifies Default MAC control register content
  22. for the specific platform
  23. - slaves : Specifies number for slaves
  24. - slave_reg_ofs : Specifies slave register offset
  25. - sliver_reg_ofs : Specifies slave sliver register offset
  26. - phy_id : Specifies slave phy id
  27. - mac-address : Specifies slave MAC address
  28. Optional properties:
  29. - ti,hwmods : Must be "cpgmac0"
  30. - no_bd_ram : Must be 0 or 1
  31. Note: "ti,hwmods" field is used to fetch the base address and irq
  32. resources from TI, omap hwmod data base during device registration.
  33. Future plan is to migrate hwmod data base contents into device tree
  34. blob so that, all the required data will be used from device tree dts
  35. file.
  36. Examples:
  37. mac: ethernet@4A100000 {
  38. compatible = "ti,cpsw";
  39. reg = <0x4A100000 0x1000>;
  40. interrupts = <55 0x4>;
  41. interrupt-parent = <&intc>;
  42. cpdma_channels = <8>;
  43. host_port_no = <0>;
  44. cpdma_reg_ofs = <0x800>;
  45. cpdma_sram_ofs = <0xa00>;
  46. ale_reg_ofs = <0xd00>;
  47. ale_entries = <1024>;
  48. host_port_reg_ofs = <0x108>;
  49. hw_stats_reg_ofs = <0x900>;
  50. bd_ram_ofs = <0x2000>;
  51. bd_ram_size = <0x2000>;
  52. no_bd_ram = <0>;
  53. rx_descs = <64>;
  54. mac_control = <0x20>;
  55. slaves = <2>;
  56. cpsw_emac0: slave@0 {
  57. slave_reg_ofs = <0x208>;
  58. sliver_reg_ofs = <0xd80>;
  59. phy_id = "davinci_mdio.16:00";
  60. /* Filled in by U-Boot */
  61. mac-address = [ 00 00 00 00 00 00 ];
  62. };
  63. cpsw_emac1: slave@1 {
  64. slave_reg_ofs = <0x308>;
  65. sliver_reg_ofs = <0xdc0>;
  66. phy_id = "davinci_mdio.16:01";
  67. /* Filled in by U-Boot */
  68. mac-address = [ 00 00 00 00 00 00 ];
  69. };
  70. };
  71. (or)
  72. mac: ethernet@4A100000 {
  73. compatible = "ti,cpsw";
  74. ti,hwmods = "cpgmac0";
  75. cpdma_channels = <8>;
  76. host_port_no = <0>;
  77. cpdma_reg_ofs = <0x800>;
  78. cpdma_sram_ofs = <0xa00>;
  79. ale_reg_ofs = <0xd00>;
  80. ale_entries = <1024>;
  81. host_port_reg_ofs = <0x108>;
  82. hw_stats_reg_ofs = <0x900>;
  83. bd_ram_ofs = <0x2000>;
  84. bd_ram_size = <0x2000>;
  85. no_bd_ram = <0>;
  86. rx_descs = <64>;
  87. mac_control = <0x20>;
  88. slaves = <2>;
  89. cpsw_emac0: slave@0 {
  90. slave_reg_ofs = <0x208>;
  91. sliver_reg_ofs = <0xd80>;
  92. phy_id = "davinci_mdio.16:00";
  93. /* Filled in by U-Boot */
  94. mac-address = [ 00 00 00 00 00 00 ];
  95. };
  96. cpsw_emac1: slave@1 {
  97. slave_reg_ofs = <0x308>;
  98. sliver_reg_ofs = <0xdc0>;
  99. phy_id = "davinci_mdio.16:01";
  100. /* Filled in by U-Boot */
  101. mac-address = [ 00 00 00 00 00 00 ];
  102. };
  103. };