p54common.c 28 KB

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  1. /*
  2. * Common code for mac80211 Prism54 drivers
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2007, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jbnote@gmail.com>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/firmware.h>
  16. #include <linux/etherdevice.h>
  17. #include <net/mac80211.h>
  18. #include "p54.h"
  19. #include "p54common.h"
  20. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  21. MODULE_DESCRIPTION("Softmac Prism54 common code");
  22. MODULE_LICENSE("GPL");
  23. MODULE_ALIAS("prism54common");
  24. void p54_parse_firmware(struct ieee80211_hw *dev, const struct firmware *fw)
  25. {
  26. struct p54_common *priv = dev->priv;
  27. struct bootrec_exp_if *exp_if;
  28. struct bootrec *bootrec;
  29. u32 *data = (u32 *)fw->data;
  30. u32 *end_data = (u32 *)fw->data + (fw->size >> 2);
  31. u8 *fw_version = NULL;
  32. size_t len;
  33. int i;
  34. if (priv->rx_start)
  35. return;
  36. while (data < end_data && *data)
  37. data++;
  38. while (data < end_data && !*data)
  39. data++;
  40. bootrec = (struct bootrec *) data;
  41. while (bootrec->data <= end_data &&
  42. (bootrec->data + (len = le32_to_cpu(bootrec->len))) <= end_data) {
  43. u32 code = le32_to_cpu(bootrec->code);
  44. switch (code) {
  45. case BR_CODE_COMPONENT_ID:
  46. switch (be32_to_cpu(*bootrec->data)) {
  47. case FW_FMAC:
  48. printk(KERN_INFO "p54: FreeMAC firmware\n");
  49. break;
  50. case FW_LM20:
  51. printk(KERN_INFO "p54: LM20 firmware\n");
  52. break;
  53. case FW_LM86:
  54. printk(KERN_INFO "p54: LM86 firmware\n");
  55. break;
  56. case FW_LM87:
  57. printk(KERN_INFO "p54: LM87 firmware - not supported yet!\n");
  58. break;
  59. default:
  60. printk(KERN_INFO "p54: unknown firmware\n");
  61. break;
  62. }
  63. break;
  64. case BR_CODE_COMPONENT_VERSION:
  65. /* 24 bytes should be enough for all firmwares */
  66. if (strnlen((unsigned char*)bootrec->data, 24) < 24)
  67. fw_version = (unsigned char*)bootrec->data;
  68. break;
  69. case BR_CODE_DESCR:
  70. priv->rx_start = le32_to_cpu(bootrec->data[1]);
  71. /* FIXME add sanity checking */
  72. priv->rx_end = le32_to_cpu(bootrec->data[2]) - 0x3500;
  73. break;
  74. case BR_CODE_EXPOSED_IF:
  75. exp_if = (struct bootrec_exp_if *) bootrec->data;
  76. for (i = 0; i < (len * sizeof(*exp_if) / 4); i++)
  77. if (exp_if[i].if_id == 0x1a)
  78. priv->fw_var = le16_to_cpu(exp_if[i].variant);
  79. break;
  80. case BR_CODE_DEPENDENT_IF:
  81. break;
  82. case BR_CODE_END_OF_BRA:
  83. case LEGACY_BR_CODE_END_OF_BRA:
  84. end_data = NULL;
  85. break;
  86. default:
  87. break;
  88. }
  89. bootrec = (struct bootrec *)&bootrec->data[len];
  90. }
  91. if (fw_version)
  92. printk(KERN_INFO "p54: FW rev %s - Softmac protocol %x.%x\n",
  93. fw_version, priv->fw_var >> 8, priv->fw_var & 0xff);
  94. if (priv->fw_var >= 0x300) {
  95. /* Firmware supports QoS, use it! */
  96. priv->tx_stats.data[0].limit = 3;
  97. priv->tx_stats.data[1].limit = 4;
  98. priv->tx_stats.data[2].limit = 3;
  99. priv->tx_stats.data[3].limit = 1;
  100. dev->queues = 4;
  101. }
  102. }
  103. EXPORT_SYMBOL_GPL(p54_parse_firmware);
  104. static int p54_convert_rev0_to_rev1(struct ieee80211_hw *dev,
  105. struct pda_pa_curve_data *curve_data)
  106. {
  107. struct p54_common *priv = dev->priv;
  108. struct pda_pa_curve_data_sample_rev1 *rev1;
  109. struct pda_pa_curve_data_sample_rev0 *rev0;
  110. size_t cd_len = sizeof(*curve_data) +
  111. (curve_data->points_per_channel*sizeof(*rev1) + 2) *
  112. curve_data->channels;
  113. unsigned int i, j;
  114. void *source, *target;
  115. priv->curve_data = kmalloc(cd_len, GFP_KERNEL);
  116. if (!priv->curve_data)
  117. return -ENOMEM;
  118. memcpy(priv->curve_data, curve_data, sizeof(*curve_data));
  119. source = curve_data->data;
  120. target = priv->curve_data->data;
  121. for (i = 0; i < curve_data->channels; i++) {
  122. __le16 *freq = source;
  123. source += sizeof(__le16);
  124. *((__le16 *)target) = *freq;
  125. target += sizeof(__le16);
  126. for (j = 0; j < curve_data->points_per_channel; j++) {
  127. rev1 = target;
  128. rev0 = source;
  129. rev1->rf_power = rev0->rf_power;
  130. rev1->pa_detector = rev0->pa_detector;
  131. rev1->data_64qam = rev0->pcv;
  132. /* "invent" the points for the other modulations */
  133. #define SUB(x,y) (u8)((x) - (y)) > (x) ? 0 : (x) - (y)
  134. rev1->data_16qam = SUB(rev0->pcv, 12);
  135. rev1->data_qpsk = SUB(rev1->data_16qam, 12);
  136. rev1->data_bpsk = SUB(rev1->data_qpsk, 12);
  137. rev1->data_barker= SUB(rev1->data_bpsk, 14);
  138. #undef SUB
  139. target += sizeof(*rev1);
  140. source += sizeof(*rev0);
  141. }
  142. }
  143. return 0;
  144. }
  145. int p54_parse_eeprom(struct ieee80211_hw *dev, void *eeprom, int len)
  146. {
  147. struct p54_common *priv = dev->priv;
  148. struct eeprom_pda_wrap *wrap = NULL;
  149. struct pda_entry *entry;
  150. int i = 0;
  151. unsigned int data_len, entry_len;
  152. void *tmp;
  153. int err;
  154. wrap = (struct eeprom_pda_wrap *) eeprom;
  155. entry = (void *)wrap->data + wrap->len;
  156. i += 2;
  157. i += le16_to_cpu(entry->len)*2;
  158. while (i < len) {
  159. entry_len = le16_to_cpu(entry->len);
  160. data_len = ((entry_len - 1) << 1);
  161. switch (le16_to_cpu(entry->code)) {
  162. case PDR_MAC_ADDRESS:
  163. SET_IEEE80211_PERM_ADDR(dev, entry->data);
  164. break;
  165. case PDR_PRISM_PA_CAL_OUTPUT_POWER_LIMITS:
  166. if (data_len < 2) {
  167. err = -EINVAL;
  168. goto err;
  169. }
  170. if (2 + entry->data[1]*sizeof(*priv->output_limit) > data_len) {
  171. err = -EINVAL;
  172. goto err;
  173. }
  174. priv->output_limit = kmalloc(entry->data[1] *
  175. sizeof(*priv->output_limit), GFP_KERNEL);
  176. if (!priv->output_limit) {
  177. err = -ENOMEM;
  178. goto err;
  179. }
  180. memcpy(priv->output_limit, &entry->data[2],
  181. entry->data[1]*sizeof(*priv->output_limit));
  182. priv->output_limit_len = entry->data[1];
  183. break;
  184. case PDR_PRISM_PA_CAL_CURVE_DATA:
  185. if (data_len < sizeof(struct pda_pa_curve_data)) {
  186. err = -EINVAL;
  187. goto err;
  188. }
  189. if (((struct pda_pa_curve_data *)entry->data)->cal_method_rev) {
  190. priv->curve_data = kmalloc(data_len, GFP_KERNEL);
  191. if (!priv->curve_data) {
  192. err = -ENOMEM;
  193. goto err;
  194. }
  195. memcpy(priv->curve_data, entry->data, data_len);
  196. } else {
  197. err = p54_convert_rev0_to_rev1(dev, (struct pda_pa_curve_data *)entry->data);
  198. if (err)
  199. goto err;
  200. }
  201. break;
  202. case PDR_PRISM_ZIF_TX_IQ_CALIBRATION:
  203. priv->iq_autocal = kmalloc(data_len, GFP_KERNEL);
  204. if (!priv->iq_autocal) {
  205. err = -ENOMEM;
  206. goto err;
  207. }
  208. memcpy(priv->iq_autocal, entry->data, data_len);
  209. priv->iq_autocal_len = data_len / sizeof(struct pda_iq_autocal_entry);
  210. break;
  211. case PDR_INTERFACE_LIST:
  212. tmp = entry->data;
  213. while ((u8 *)tmp < entry->data + data_len) {
  214. struct bootrec_exp_if *exp_if = tmp;
  215. if (le16_to_cpu(exp_if->if_id) == 0xF)
  216. priv->rxhw = exp_if->variant & cpu_to_le16(0x07);
  217. tmp += sizeof(struct bootrec_exp_if);
  218. }
  219. break;
  220. case PDR_HARDWARE_PLATFORM_COMPONENT_ID:
  221. priv->version = *(u8 *)(entry->data + 1);
  222. break;
  223. case PDR_END:
  224. i = len;
  225. break;
  226. }
  227. entry = (void *)entry + (entry_len + 1)*2;
  228. i += 2;
  229. i += entry_len*2;
  230. }
  231. if (!priv->iq_autocal || !priv->output_limit || !priv->curve_data) {
  232. printk(KERN_ERR "p54: not all required entries found in eeprom!\n");
  233. err = -EINVAL;
  234. goto err;
  235. }
  236. return 0;
  237. err:
  238. if (priv->iq_autocal) {
  239. kfree(priv->iq_autocal);
  240. priv->iq_autocal = NULL;
  241. }
  242. if (priv->output_limit) {
  243. kfree(priv->output_limit);
  244. priv->output_limit = NULL;
  245. }
  246. if (priv->curve_data) {
  247. kfree(priv->curve_data);
  248. priv->curve_data = NULL;
  249. }
  250. printk(KERN_ERR "p54: eeprom parse failed!\n");
  251. return err;
  252. }
  253. EXPORT_SYMBOL_GPL(p54_parse_eeprom);
  254. void p54_fill_eeprom_readback(struct p54_control_hdr *hdr)
  255. {
  256. struct p54_eeprom_lm86 *eeprom_hdr;
  257. hdr->magic1 = cpu_to_le16(0x8000);
  258. hdr->len = cpu_to_le16(sizeof(*eeprom_hdr) + 0x2000);
  259. hdr->type = cpu_to_le16(P54_CONTROL_TYPE_EEPROM_READBACK);
  260. hdr->retry1 = hdr->retry2 = 0;
  261. eeprom_hdr = (struct p54_eeprom_lm86 *) hdr->data;
  262. eeprom_hdr->offset = 0x0;
  263. eeprom_hdr->len = cpu_to_le16(0x2000);
  264. }
  265. EXPORT_SYMBOL_GPL(p54_fill_eeprom_readback);
  266. static void p54_rx_data(struct ieee80211_hw *dev, struct sk_buff *skb)
  267. {
  268. struct p54_rx_hdr *hdr = (struct p54_rx_hdr *) skb->data;
  269. struct ieee80211_rx_status rx_status = {0};
  270. u16 freq = le16_to_cpu(hdr->freq);
  271. rx_status.ssi = hdr->rssi;
  272. rx_status.rate = hdr->rate & 0x1f; /* report short preambles & CCK too */
  273. rx_status.channel = freq == 2484 ? 14 : (freq - 2407)/5;
  274. rx_status.freq = freq;
  275. rx_status.phymode = MODE_IEEE80211G;
  276. rx_status.antenna = hdr->antenna;
  277. rx_status.mactime = le64_to_cpu(hdr->timestamp);
  278. rx_status.flag |= RX_FLAG_TSFT;
  279. skb_pull(skb, sizeof(*hdr));
  280. skb_trim(skb, le16_to_cpu(hdr->len));
  281. ieee80211_rx_irqsafe(dev, skb, &rx_status);
  282. }
  283. static void inline p54_wake_free_queues(struct ieee80211_hw *dev)
  284. {
  285. struct p54_common *priv = dev->priv;
  286. int i;
  287. /* ieee80211_start_queues is great if all queues are really empty.
  288. * But, what if some are full? */
  289. for (i = 0; i < dev->queues; i++)
  290. if (priv->tx_stats.data[i].len < priv->tx_stats.data[i].limit)
  291. ieee80211_wake_queue(dev, i);
  292. }
  293. static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb)
  294. {
  295. struct p54_common *priv = dev->priv;
  296. struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
  297. struct p54_frame_sent_hdr *payload = (struct p54_frame_sent_hdr *) hdr->data;
  298. struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next;
  299. u32 addr = le32_to_cpu(hdr->req_id) - 0x70;
  300. struct memrecord *range = NULL;
  301. u32 freed = 0;
  302. u32 last_addr = priv->rx_start;
  303. while (entry != (struct sk_buff *)&priv->tx_queue) {
  304. range = (struct memrecord *)&entry->cb;
  305. if (range->start_addr == addr) {
  306. struct ieee80211_tx_status status = {{0}};
  307. struct p54_control_hdr *entry_hdr;
  308. struct p54_tx_control_allocdata *entry_data;
  309. int pad = 0;
  310. if (entry->next != (struct sk_buff *)&priv->tx_queue)
  311. freed = ((struct memrecord *)&entry->next->cb)->start_addr - last_addr;
  312. else
  313. freed = priv->rx_end - last_addr;
  314. last_addr = range->end_addr;
  315. __skb_unlink(entry, &priv->tx_queue);
  316. if (!range->control) {
  317. kfree_skb(entry);
  318. break;
  319. }
  320. memcpy(&status.control, range->control,
  321. sizeof(status.control));
  322. kfree(range->control);
  323. priv->tx_stats.data[status.control.queue].len--;
  324. entry_hdr = (struct p54_control_hdr *) entry->data;
  325. entry_data = (struct p54_tx_control_allocdata *) entry_hdr->data;
  326. if ((entry_hdr->magic1 & cpu_to_le16(0x4000)) != 0)
  327. pad = entry_data->align[0];
  328. if (!status.control.flags & IEEE80211_TXCTL_NO_ACK) {
  329. if (!(payload->status & 0x01))
  330. status.flags |= IEEE80211_TX_STATUS_ACK;
  331. else
  332. status.excessive_retries = 1;
  333. }
  334. status.retry_count = payload->retries - 1;
  335. status.ack_signal = le16_to_cpu(payload->ack_rssi);
  336. skb_pull(entry, sizeof(*hdr) + pad + sizeof(*entry_data));
  337. ieee80211_tx_status_irqsafe(dev, entry, &status);
  338. break;
  339. } else
  340. last_addr = range->end_addr;
  341. entry = entry->next;
  342. }
  343. if (freed >= IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
  344. sizeof(struct p54_control_hdr))
  345. p54_wake_free_queues(dev);
  346. }
  347. static void p54_rx_control(struct ieee80211_hw *dev, struct sk_buff *skb)
  348. {
  349. struct p54_control_hdr *hdr = (struct p54_control_hdr *) skb->data;
  350. switch (le16_to_cpu(hdr->type)) {
  351. case P54_CONTROL_TYPE_TXDONE:
  352. p54_rx_frame_sent(dev, skb);
  353. break;
  354. case P54_CONTROL_TYPE_BBP:
  355. break;
  356. default:
  357. printk(KERN_DEBUG "%s: not handling 0x%02x type control frame\n",
  358. wiphy_name(dev->wiphy), le16_to_cpu(hdr->type));
  359. break;
  360. }
  361. }
  362. /* returns zero if skb can be reused */
  363. int p54_rx(struct ieee80211_hw *dev, struct sk_buff *skb)
  364. {
  365. u8 type = le16_to_cpu(*((__le16 *)skb->data)) >> 8;
  366. switch (type) {
  367. case 0x00:
  368. case 0x01:
  369. p54_rx_data(dev, skb);
  370. return -1;
  371. case 0x4d:
  372. /* TODO: do something better... but then again, I've never seen this happen */
  373. printk(KERN_ERR "%s: Received fault. Probably need to restart hardware now..\n",
  374. wiphy_name(dev->wiphy));
  375. break;
  376. case 0x80:
  377. p54_rx_control(dev, skb);
  378. break;
  379. default:
  380. printk(KERN_ERR "%s: unknown frame RXed (0x%02x)\n",
  381. wiphy_name(dev->wiphy), type);
  382. break;
  383. }
  384. return 0;
  385. }
  386. EXPORT_SYMBOL_GPL(p54_rx);
  387. /*
  388. * So, the firmware is somewhat stupid and doesn't know what places in its
  389. * memory incoming data should go to. By poking around in the firmware, we
  390. * can find some unused memory to upload our packets to. However, data that we
  391. * want the card to TX needs to stay intact until the card has told us that
  392. * it is done with it. This function finds empty places we can upload to and
  393. * marks allocated areas as reserved if necessary. p54_rx_frame_sent frees
  394. * allocated areas.
  395. */
  396. static void p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb,
  397. struct p54_control_hdr *data, u32 len,
  398. struct ieee80211_tx_control *control)
  399. {
  400. struct p54_common *priv = dev->priv;
  401. struct sk_buff *entry = priv->tx_queue.next;
  402. struct sk_buff *target_skb = NULL;
  403. struct memrecord *range;
  404. u32 last_addr = priv->rx_start;
  405. u32 largest_hole = 0;
  406. u32 target_addr = priv->rx_start;
  407. unsigned long flags;
  408. unsigned int left;
  409. len = (len + 0x170 + 3) & ~0x3; /* 0x70 headroom, 0x100 tailroom */
  410. spin_lock_irqsave(&priv->tx_queue.lock, flags);
  411. left = skb_queue_len(&priv->tx_queue);
  412. while (left--) {
  413. u32 hole_size;
  414. range = (struct memrecord *)&entry->cb;
  415. hole_size = range->start_addr - last_addr;
  416. if (!target_skb && hole_size >= len) {
  417. target_skb = entry->prev;
  418. hole_size -= len;
  419. target_addr = last_addr;
  420. }
  421. largest_hole = max(largest_hole, hole_size);
  422. last_addr = range->end_addr;
  423. entry = entry->next;
  424. }
  425. if (!target_skb && priv->rx_end - last_addr >= len) {
  426. target_skb = priv->tx_queue.prev;
  427. largest_hole = max(largest_hole, priv->rx_end - last_addr - len);
  428. if (!skb_queue_empty(&priv->tx_queue)) {
  429. range = (struct memrecord *)&target_skb->cb;
  430. target_addr = range->end_addr;
  431. }
  432. } else
  433. largest_hole = max(largest_hole, priv->rx_end - last_addr);
  434. if (skb) {
  435. range = (struct memrecord *)&skb->cb;
  436. range->start_addr = target_addr;
  437. range->end_addr = target_addr + len;
  438. range->control = control;
  439. __skb_queue_after(&priv->tx_queue, target_skb, skb);
  440. if (largest_hole < IEEE80211_MAX_RTS_THRESHOLD + 0x170 +
  441. sizeof(struct p54_control_hdr))
  442. ieee80211_stop_queues(dev);
  443. }
  444. spin_unlock_irqrestore(&priv->tx_queue.lock, flags);
  445. data->req_id = cpu_to_le32(target_addr + 0x70);
  446. }
  447. static int p54_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
  448. struct ieee80211_tx_control *control)
  449. {
  450. struct ieee80211_tx_queue_stats_data *current_queue;
  451. struct p54_common *priv = dev->priv;
  452. struct p54_control_hdr *hdr;
  453. struct p54_tx_control_allocdata *txhdr;
  454. struct ieee80211_tx_control *control_copy;
  455. size_t padding, len;
  456. u8 rate;
  457. current_queue = &priv->tx_stats.data[control->queue];
  458. if (unlikely(current_queue->len > current_queue->limit))
  459. return NETDEV_TX_BUSY;
  460. current_queue->len++;
  461. current_queue->count++;
  462. if (current_queue->len == current_queue->limit)
  463. ieee80211_stop_queue(dev, control->queue);
  464. padding = (unsigned long)(skb->data - (sizeof(*hdr) + sizeof(*txhdr))) & 3;
  465. len = skb->len;
  466. control_copy = kmalloc(sizeof(*control), GFP_ATOMIC);
  467. if (control_copy)
  468. memcpy(control_copy, control, sizeof(*control));
  469. txhdr = (struct p54_tx_control_allocdata *)
  470. skb_push(skb, sizeof(*txhdr) + padding);
  471. hdr = (struct p54_control_hdr *) skb_push(skb, sizeof(*hdr));
  472. if (padding)
  473. hdr->magic1 = cpu_to_le16(0x4010);
  474. else
  475. hdr->magic1 = cpu_to_le16(0x0010);
  476. hdr->len = cpu_to_le16(len);
  477. hdr->type = (control->flags & IEEE80211_TXCTL_NO_ACK) ? 0 : cpu_to_le16(1);
  478. hdr->retry1 = hdr->retry2 = control->retry_limit;
  479. p54_assign_address(dev, skb, hdr, skb->len, control_copy);
  480. memset(txhdr->wep_key, 0x0, 16);
  481. txhdr->padding = 0;
  482. txhdr->padding2 = 0;
  483. /* TODO: add support for alternate retry TX rates */
  484. rate = control->tx_rate;
  485. if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
  486. rate |= 0x40;
  487. else if (control->flags & IEEE80211_TXCTL_USE_CTS_PROTECT)
  488. rate |= 0x20;
  489. memset(txhdr->rateset, rate, 8);
  490. txhdr->wep_key_present = 0;
  491. txhdr->wep_key_len = 0;
  492. txhdr->frame_type = cpu_to_le32(control->queue + 4);
  493. txhdr->magic4 = 0;
  494. txhdr->antenna = (control->antenna_sel_tx == 0) ?
  495. 2 : control->antenna_sel_tx - 1;
  496. txhdr->output_power = 0x7f; // HW Maximum
  497. txhdr->magic5 = (control->flags & IEEE80211_TXCTL_NO_ACK) ?
  498. 0 : ((rate > 0x3) ? cpu_to_le32(0x33) : cpu_to_le32(0x23));
  499. if (padding)
  500. txhdr->align[0] = padding;
  501. priv->tx(dev, hdr, skb->len, 0);
  502. return 0;
  503. }
  504. static int p54_set_filter(struct ieee80211_hw *dev, u16 filter_type,
  505. const u8 *dst, const u8 *src, u8 antenna,
  506. u32 magic3, u32 magic8, u32 magic9)
  507. {
  508. struct p54_common *priv = dev->priv;
  509. struct p54_control_hdr *hdr;
  510. struct p54_tx_control_filter *filter;
  511. hdr = kzalloc(sizeof(*hdr) + sizeof(*filter) +
  512. priv->tx_hdr_len, GFP_ATOMIC);
  513. if (!hdr)
  514. return -ENOMEM;
  515. hdr = (void *)hdr + priv->tx_hdr_len;
  516. filter = (struct p54_tx_control_filter *) hdr->data;
  517. hdr->magic1 = cpu_to_le16(0x8001);
  518. hdr->len = cpu_to_le16(sizeof(*filter));
  519. p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*filter), NULL);
  520. hdr->type = cpu_to_le16(P54_CONTROL_TYPE_FILTER_SET);
  521. filter->filter_type = cpu_to_le16(filter_type);
  522. memcpy(filter->dst, dst, ETH_ALEN);
  523. if (!src)
  524. memset(filter->src, ~0, ETH_ALEN);
  525. else
  526. memcpy(filter->src, src, ETH_ALEN);
  527. filter->antenna = antenna;
  528. filter->magic3 = cpu_to_le32(magic3);
  529. filter->rx_addr = cpu_to_le32(priv->rx_end);
  530. filter->max_rx = cpu_to_le16(0x0620); /* FIXME: for usb ver 1.. maybe */
  531. filter->rxhw = priv->rxhw;
  532. filter->magic8 = cpu_to_le16(magic8);
  533. filter->magic9 = cpu_to_le16(magic9);
  534. priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*filter), 1);
  535. return 0;
  536. }
  537. static int p54_set_freq(struct ieee80211_hw *dev, __le16 freq)
  538. {
  539. struct p54_common *priv = dev->priv;
  540. struct p54_control_hdr *hdr;
  541. struct p54_tx_control_channel *chan;
  542. unsigned int i;
  543. size_t payload_len = sizeof(*chan) + sizeof(u32)*2 +
  544. sizeof(*chan->curve_data) *
  545. priv->curve_data->points_per_channel;
  546. void *entry;
  547. hdr = kzalloc(sizeof(*hdr) + payload_len +
  548. priv->tx_hdr_len, GFP_KERNEL);
  549. if (!hdr)
  550. return -ENOMEM;
  551. hdr = (void *)hdr + priv->tx_hdr_len;
  552. chan = (struct p54_tx_control_channel *) hdr->data;
  553. hdr->magic1 = cpu_to_le16(0x8001);
  554. hdr->len = cpu_to_le16(sizeof(*chan));
  555. hdr->type = cpu_to_le16(P54_CONTROL_TYPE_CHANNEL_CHANGE);
  556. p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + payload_len, NULL);
  557. chan->magic1 = cpu_to_le16(0x1);
  558. chan->magic2 = cpu_to_le16(0x0);
  559. for (i = 0; i < priv->iq_autocal_len; i++) {
  560. if (priv->iq_autocal[i].freq != freq)
  561. continue;
  562. memcpy(&chan->iq_autocal, &priv->iq_autocal[i],
  563. sizeof(*priv->iq_autocal));
  564. break;
  565. }
  566. if (i == priv->iq_autocal_len)
  567. goto err;
  568. for (i = 0; i < priv->output_limit_len; i++) {
  569. if (priv->output_limit[i].freq != freq)
  570. continue;
  571. chan->val_barker = 0x38;
  572. chan->val_bpsk = priv->output_limit[i].val_bpsk;
  573. chan->val_qpsk = priv->output_limit[i].val_qpsk;
  574. chan->val_16qam = priv->output_limit[i].val_16qam;
  575. chan->val_64qam = priv->output_limit[i].val_64qam;
  576. break;
  577. }
  578. if (i == priv->output_limit_len)
  579. goto err;
  580. chan->pa_points_per_curve = priv->curve_data->points_per_channel;
  581. entry = priv->curve_data->data;
  582. for (i = 0; i < priv->curve_data->channels; i++) {
  583. if (*((__le16 *)entry) != freq) {
  584. entry += sizeof(__le16);
  585. entry += sizeof(struct pda_pa_curve_data_sample_rev1) *
  586. chan->pa_points_per_curve;
  587. continue;
  588. }
  589. entry += sizeof(__le16);
  590. memcpy(chan->curve_data, entry, sizeof(*chan->curve_data) *
  591. chan->pa_points_per_curve);
  592. break;
  593. }
  594. memcpy(hdr->data + payload_len - 4, &chan->val_bpsk, 4);
  595. priv->tx(dev, hdr, sizeof(*hdr) + payload_len, 1);
  596. return 0;
  597. err:
  598. printk(KERN_ERR "%s: frequency change failed\n", wiphy_name(dev->wiphy));
  599. kfree(hdr);
  600. return -EINVAL;
  601. }
  602. static int p54_set_leds(struct ieee80211_hw *dev, int mode, int link, int act)
  603. {
  604. struct p54_common *priv = dev->priv;
  605. struct p54_control_hdr *hdr;
  606. struct p54_tx_control_led *led;
  607. hdr = kzalloc(sizeof(*hdr) + sizeof(*led) +
  608. priv->tx_hdr_len, GFP_KERNEL);
  609. if (!hdr)
  610. return -ENOMEM;
  611. hdr = (void *)hdr + priv->tx_hdr_len;
  612. hdr->magic1 = cpu_to_le16(0x8001);
  613. hdr->len = cpu_to_le16(sizeof(*led));
  614. hdr->type = cpu_to_le16(P54_CONTROL_TYPE_LED);
  615. p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*led), NULL);
  616. led = (struct p54_tx_control_led *) hdr->data;
  617. led->mode = cpu_to_le16(mode);
  618. led->led_permanent = cpu_to_le16(link);
  619. led->led_temporary = cpu_to_le16(act);
  620. led->duration = cpu_to_le16(1000);
  621. priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*led), 1);
  622. return 0;
  623. }
  624. #define P54_SET_QUEUE(queue, ai_fs, cw_min, cw_max, burst) \
  625. do { \
  626. queue.aifs = cpu_to_le16(ai_fs); \
  627. queue.cwmin = cpu_to_le16(cw_min); \
  628. queue.cwmax = cpu_to_le16(cw_max); \
  629. queue.txop = (burst == 0) ? \
  630. 0 : cpu_to_le16((burst * 100) / 32 + 1); \
  631. } while(0)
  632. static void p54_init_vdcf(struct ieee80211_hw *dev)
  633. {
  634. struct p54_common *priv = dev->priv;
  635. struct p54_control_hdr *hdr;
  636. struct p54_tx_control_vdcf *vdcf;
  637. /* all USB V1 adapters need a extra headroom */
  638. hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
  639. hdr->magic1 = cpu_to_le16(0x8001);
  640. hdr->len = cpu_to_le16(sizeof(*vdcf));
  641. hdr->type = cpu_to_le16(P54_CONTROL_TYPE_DCFINIT);
  642. hdr->req_id = cpu_to_le32(priv->rx_start);
  643. vdcf = (struct p54_tx_control_vdcf *) hdr->data;
  644. P54_SET_QUEUE(vdcf->queue[0], 0x0002, 0x0003, 0x0007, 0x000f);
  645. P54_SET_QUEUE(vdcf->queue[1], 0x0002, 0x0007, 0x000f, 0x001e);
  646. P54_SET_QUEUE(vdcf->queue[2], 0x0002, 0x000f, 0x03ff, 0x0014);
  647. P54_SET_QUEUE(vdcf->queue[3], 0x0007, 0x000f, 0x03ff, 0x0000);
  648. }
  649. static void p54_set_vdcf(struct ieee80211_hw *dev)
  650. {
  651. struct p54_common *priv = dev->priv;
  652. struct p54_control_hdr *hdr;
  653. struct p54_tx_control_vdcf *vdcf;
  654. hdr = (void *)priv->cached_vdcf + priv->tx_hdr_len;
  655. p54_assign_address(dev, NULL, hdr, sizeof(*hdr) + sizeof(*vdcf), NULL);
  656. vdcf = (struct p54_tx_control_vdcf *) hdr->data;
  657. if (dev->conf.flags & IEEE80211_CONF_SHORT_SLOT_TIME) {
  658. vdcf->slottime = 9;
  659. vdcf->magic1 = 0x00;
  660. vdcf->magic2 = 0x10;
  661. } else {
  662. vdcf->slottime = 20;
  663. vdcf->magic1 = 0x0a;
  664. vdcf->magic2 = 0x06;
  665. }
  666. /* (see prism54/isl_oid.h for further details) */
  667. vdcf->frameburst = cpu_to_le16(0);
  668. priv->tx(dev, hdr, sizeof(*hdr) + sizeof(*vdcf), 0);
  669. }
  670. static int p54_start(struct ieee80211_hw *dev)
  671. {
  672. struct p54_common *priv = dev->priv;
  673. int err;
  674. err = priv->open(dev);
  675. if (!err)
  676. priv->mode = IEEE80211_IF_TYPE_MNTR;
  677. return err;
  678. }
  679. static void p54_stop(struct ieee80211_hw *dev)
  680. {
  681. struct p54_common *priv = dev->priv;
  682. struct sk_buff *skb;
  683. while ((skb = skb_dequeue(&priv->tx_queue))) {
  684. struct memrecord *range = (struct memrecord *)&skb->cb;
  685. if (range->control)
  686. kfree(range->control);
  687. kfree_skb(skb);
  688. }
  689. priv->stop(dev);
  690. priv->mode = IEEE80211_IF_TYPE_INVALID;
  691. }
  692. static int p54_add_interface(struct ieee80211_hw *dev,
  693. struct ieee80211_if_init_conf *conf)
  694. {
  695. struct p54_common *priv = dev->priv;
  696. if (priv->mode != IEEE80211_IF_TYPE_MNTR)
  697. return -EOPNOTSUPP;
  698. switch (conf->type) {
  699. case IEEE80211_IF_TYPE_STA:
  700. priv->mode = conf->type;
  701. break;
  702. default:
  703. return -EOPNOTSUPP;
  704. }
  705. memcpy(priv->mac_addr, conf->mac_addr, ETH_ALEN);
  706. p54_set_filter(dev, 0, priv->mac_addr, NULL, 0, 1, 0, 0xF642);
  707. p54_set_filter(dev, 0, priv->mac_addr, NULL, 1, 0, 0, 0xF642);
  708. switch (conf->type) {
  709. case IEEE80211_IF_TYPE_STA:
  710. p54_set_filter(dev, 1, priv->mac_addr, NULL, 0, 0x15F, 0x1F4, 0);
  711. break;
  712. default:
  713. BUG(); /* impossible */
  714. break;
  715. }
  716. p54_set_leds(dev, 1, 0, 0);
  717. return 0;
  718. }
  719. static void p54_remove_interface(struct ieee80211_hw *dev,
  720. struct ieee80211_if_init_conf *conf)
  721. {
  722. struct p54_common *priv = dev->priv;
  723. priv->mode = IEEE80211_IF_TYPE_MNTR;
  724. memset(priv->mac_addr, 0, ETH_ALEN);
  725. p54_set_filter(dev, 0, priv->mac_addr, NULL, 2, 0, 0, 0);
  726. }
  727. static int p54_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
  728. {
  729. int ret;
  730. ret = p54_set_freq(dev, cpu_to_le16(conf->freq));
  731. p54_set_vdcf(dev);
  732. return ret;
  733. }
  734. static int p54_config_interface(struct ieee80211_hw *dev, int if_id,
  735. struct ieee80211_if_conf *conf)
  736. {
  737. struct p54_common *priv = dev->priv;
  738. p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 0, 1, 0, 0xF642);
  739. p54_set_filter(dev, 0, priv->mac_addr, conf->bssid, 2, 0, 0, 0);
  740. p54_set_leds(dev, 1, !is_multicast_ether_addr(conf->bssid), 0);
  741. memcpy(priv->bssid, conf->bssid, ETH_ALEN);
  742. return 0;
  743. }
  744. static void p54_configure_filter(struct ieee80211_hw *dev,
  745. unsigned int changed_flags,
  746. unsigned int *total_flags,
  747. int mc_count, struct dev_mc_list *mclist)
  748. {
  749. struct p54_common *priv = dev->priv;
  750. *total_flags &= FIF_BCN_PRBRESP_PROMISC;
  751. if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
  752. if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
  753. p54_set_filter(dev, 0, priv->mac_addr,
  754. NULL, 2, 0, 0, 0);
  755. else
  756. p54_set_filter(dev, 0, priv->mac_addr,
  757. priv->bssid, 2, 0, 0, 0);
  758. }
  759. }
  760. static int p54_conf_tx(struct ieee80211_hw *dev, int queue,
  761. const struct ieee80211_tx_queue_params *params)
  762. {
  763. struct p54_common *priv = dev->priv;
  764. struct p54_tx_control_vdcf *vdcf;
  765. vdcf = (struct p54_tx_control_vdcf *)(((struct p54_control_hdr *)
  766. ((void *)priv->cached_vdcf + priv->tx_hdr_len))->data);
  767. if ((params) && !((queue < 0) || (queue > 4))) {
  768. P54_SET_QUEUE(vdcf->queue[queue], params->aifs,
  769. params->cw_min, params->cw_max, params->burst_time);
  770. } else
  771. return -EINVAL;
  772. p54_set_vdcf(dev);
  773. return 0;
  774. }
  775. static int p54_get_stats(struct ieee80211_hw *dev,
  776. struct ieee80211_low_level_stats *stats)
  777. {
  778. /* TODO */
  779. return 0;
  780. }
  781. static int p54_get_tx_stats(struct ieee80211_hw *dev,
  782. struct ieee80211_tx_queue_stats *stats)
  783. {
  784. struct p54_common *priv = dev->priv;
  785. unsigned int i;
  786. for (i = 0; i < dev->queues; i++)
  787. memcpy(&stats->data[i], &priv->tx_stats.data[i],
  788. sizeof(stats->data[i]));
  789. return 0;
  790. }
  791. static const struct ieee80211_ops p54_ops = {
  792. .tx = p54_tx,
  793. .start = p54_start,
  794. .stop = p54_stop,
  795. .add_interface = p54_add_interface,
  796. .remove_interface = p54_remove_interface,
  797. .config = p54_config,
  798. .config_interface = p54_config_interface,
  799. .configure_filter = p54_configure_filter,
  800. .conf_tx = p54_conf_tx,
  801. .get_stats = p54_get_stats,
  802. .get_tx_stats = p54_get_tx_stats
  803. };
  804. struct ieee80211_hw *p54_init_common(size_t priv_data_len)
  805. {
  806. struct ieee80211_hw *dev;
  807. struct p54_common *priv;
  808. int i;
  809. dev = ieee80211_alloc_hw(priv_data_len, &p54_ops);
  810. if (!dev)
  811. return NULL;
  812. priv = dev->priv;
  813. priv->mode = IEEE80211_IF_TYPE_INVALID;
  814. skb_queue_head_init(&priv->tx_queue);
  815. memcpy(priv->channels, p54_channels, sizeof(p54_channels));
  816. memcpy(priv->rates, p54_rates, sizeof(p54_rates));
  817. priv->modes[1].mode = MODE_IEEE80211B;
  818. priv->modes[1].num_rates = 4;
  819. priv->modes[1].rates = priv->rates;
  820. priv->modes[1].num_channels = ARRAY_SIZE(p54_channels);
  821. priv->modes[1].channels = priv->channels;
  822. priv->modes[0].mode = MODE_IEEE80211G;
  823. priv->modes[0].num_rates = ARRAY_SIZE(p54_rates);
  824. priv->modes[0].rates = priv->rates;
  825. priv->modes[0].num_channels = ARRAY_SIZE(p54_channels);
  826. priv->modes[0].channels = priv->channels;
  827. dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | /* not sure */
  828. IEEE80211_HW_RX_INCLUDES_FCS;
  829. dev->channel_change_time = 1000; /* TODO: find actual value */
  830. dev->max_rssi = 127;
  831. priv->tx_stats.data[0].limit = 5;
  832. dev->queues = 1;
  833. dev->extra_tx_headroom = sizeof(struct p54_control_hdr) + 4 +
  834. sizeof(struct p54_tx_control_allocdata);
  835. priv->cached_vdcf = kzalloc(sizeof(struct p54_tx_control_vdcf) +
  836. priv->tx_hdr_len + sizeof(struct p54_control_hdr), GFP_KERNEL);
  837. if (!priv->cached_vdcf) {
  838. ieee80211_free_hw(dev);
  839. return NULL;
  840. }
  841. p54_init_vdcf(dev);
  842. for (i = 0; i < 2; i++) {
  843. if (ieee80211_register_hwmode(dev, &priv->modes[i])) {
  844. kfree(priv->cached_vdcf);
  845. ieee80211_free_hw(dev);
  846. return NULL;
  847. }
  848. }
  849. return dev;
  850. }
  851. EXPORT_SYMBOL_GPL(p54_init_common);
  852. void p54_free_common(struct ieee80211_hw *dev)
  853. {
  854. struct p54_common *priv = dev->priv;
  855. kfree(priv->iq_autocal);
  856. kfree(priv->output_limit);
  857. kfree(priv->curve_data);
  858. kfree(priv->cached_vdcf);
  859. }
  860. EXPORT_SYMBOL_GPL(p54_free_common);
  861. static int __init p54_init(void)
  862. {
  863. return 0;
  864. }
  865. static void __exit p54_exit(void)
  866. {
  867. }
  868. module_init(p54_init);
  869. module_exit(p54_exit);