mpc8313erdb.dts 6.1 KB

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  1. /*
  2. * MPC8313E RDB Device Tree Source
  3. *
  4. * Copyright 2005, 2006, 2007 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8313ERDB";
  14. compatible = "MPC8313ERDB", "MPC831xRDB", "MPC83xxRDB";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. };
  24. cpus {
  25. #address-cells = <1>;
  26. #size-cells = <0>;
  27. PowerPC,8313@0 {
  28. device_type = "cpu";
  29. reg = <0x0>;
  30. d-cache-line-size = <32>;
  31. i-cache-line-size = <32>;
  32. d-cache-size = <16384>;
  33. i-cache-size = <16384>;
  34. timebase-frequency = <0>; // from bootloader
  35. bus-frequency = <0>; // from bootloader
  36. clock-frequency = <0>; // from bootloader
  37. };
  38. };
  39. memory {
  40. device_type = "memory";
  41. reg = <0x00000000 0x08000000>; // 128MB at 0
  42. };
  43. localbus@e0005000 {
  44. #address-cells = <2>;
  45. #size-cells = <1>;
  46. compatible = "fsl,mpc8313-elbc", "fsl,elbc", "simple-bus";
  47. reg = <0xe0005000 0x1000>;
  48. interrupts = <77 0x8>;
  49. interrupt-parent = <&ipic>;
  50. // CS0 and CS1 are swapped when
  51. // booting from nand, but the
  52. // addresses are the same.
  53. ranges = <0x0 0x0 0xfe000000 0x00800000
  54. 0x1 0x0 0xe2800000 0x00008000
  55. 0x2 0x0 0xf0000000 0x00020000
  56. 0x3 0x0 0xfa000000 0x00008000>;
  57. flash@0,0 {
  58. #address-cells = <1>;
  59. #size-cells = <1>;
  60. compatible = "cfi-flash";
  61. reg = <0x0 0x0 0x800000>;
  62. bank-width = <2>;
  63. device-width = <1>;
  64. };
  65. nand@1,0 {
  66. #address-cells = <1>;
  67. #size-cells = <1>;
  68. compatible = "fsl,mpc8313-fcm-nand",
  69. "fsl,elbc-fcm-nand";
  70. reg = <0x1 0x0 0x2000>;
  71. u-boot@0 {
  72. reg = <0x0 0x100000>;
  73. read-only;
  74. };
  75. kernel@100000 {
  76. reg = <0x100000 0x300000>;
  77. };
  78. fs@400000 {
  79. reg = <0x400000 0x1c00000>;
  80. };
  81. };
  82. };
  83. soc8313@e0000000 {
  84. #address-cells = <1>;
  85. #size-cells = <1>;
  86. device_type = "soc";
  87. compatible = "simple-bus";
  88. ranges = <0x0 0xe0000000 0x00100000>;
  89. reg = <0xe0000000 0x00000200>;
  90. bus-frequency = <0>;
  91. wdt@200 {
  92. device_type = "watchdog";
  93. compatible = "mpc83xx_wdt";
  94. reg = <0x200 0x100>;
  95. };
  96. i2c@3000 {
  97. #address-cells = <1>;
  98. #size-cells = <0>;
  99. cell-index = <0>;
  100. compatible = "fsl-i2c";
  101. reg = <0x3000 0x100>;
  102. interrupts = <14 0x8>;
  103. interrupt-parent = <&ipic>;
  104. dfsrr;
  105. };
  106. i2c@3100 {
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. cell-index = <1>;
  110. compatible = "fsl-i2c";
  111. reg = <0x3100 0x100>;
  112. interrupts = <15 0x8>;
  113. interrupt-parent = <&ipic>;
  114. dfsrr;
  115. };
  116. spi@7000 {
  117. cell-index = <0>;
  118. compatible = "fsl,spi";
  119. reg = <0x7000 0x1000>;
  120. interrupts = <16 0x8>;
  121. interrupt-parent = <&ipic>;
  122. mode = "cpu";
  123. };
  124. /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
  125. usb@23000 {
  126. compatible = "fsl-usb2-dr";
  127. reg = <0x23000 0x1000>;
  128. #address-cells = <1>;
  129. #size-cells = <0>;
  130. interrupt-parent = <&ipic>;
  131. interrupts = <38 0x8>;
  132. phy_type = "utmi_wide";
  133. };
  134. mdio@24520 {
  135. #address-cells = <1>;
  136. #size-cells = <0>;
  137. compatible = "fsl,gianfar-mdio";
  138. reg = <0x24520 0x20>;
  139. phy1: ethernet-phy@1 {
  140. interrupt-parent = <&ipic>;
  141. interrupts = <19 0x8>;
  142. reg = <0x1>;
  143. device_type = "ethernet-phy";
  144. };
  145. phy4: ethernet-phy@4 {
  146. interrupt-parent = <&ipic>;
  147. interrupts = <20 0x8>;
  148. reg = <0x4>;
  149. device_type = "ethernet-phy";
  150. };
  151. };
  152. enet0: ethernet@24000 {
  153. cell-index = <0>;
  154. device_type = "network";
  155. model = "eTSEC";
  156. compatible = "gianfar";
  157. reg = <0x24000 0x1000>;
  158. local-mac-address = [ 00 00 00 00 00 00 ];
  159. interrupts = <37 0x8 36 0x8 35 0x8>;
  160. interrupt-parent = <&ipic>;
  161. phy-handle = < &phy1 >;
  162. };
  163. enet1: ethernet@25000 {
  164. cell-index = <1>;
  165. device_type = "network";
  166. model = "eTSEC";
  167. compatible = "gianfar";
  168. reg = <0x25000 0x1000>;
  169. local-mac-address = [ 00 00 00 00 00 00 ];
  170. interrupts = <34 0x8 33 0x8 32 0x8>;
  171. interrupt-parent = <&ipic>;
  172. phy-handle = < &phy4 >;
  173. };
  174. serial0: serial@4500 {
  175. cell-index = <0>;
  176. device_type = "serial";
  177. compatible = "ns16550";
  178. reg = <0x4500 0x100>;
  179. clock-frequency = <0>;
  180. interrupts = <9 0x8>;
  181. interrupt-parent = <&ipic>;
  182. };
  183. serial1: serial@4600 {
  184. cell-index = <1>;
  185. device_type = "serial";
  186. compatible = "ns16550";
  187. reg = <0x4600 0x100>;
  188. clock-frequency = <0>;
  189. interrupts = <10 0x8>;
  190. interrupt-parent = <&ipic>;
  191. };
  192. crypto@30000 {
  193. device_type = "crypto";
  194. model = "SEC2";
  195. compatible = "talitos";
  196. reg = <0x30000 0x7000>;
  197. interrupts = <11 0x8>;
  198. interrupt-parent = <&ipic>;
  199. /* Rev. 2.2 */
  200. num-channels = <1>;
  201. channel-fifo-len = <24>;
  202. exec-units-mask = <0x0000004c>;
  203. descriptor-types-mask = <0x0122003f>;
  204. };
  205. /* IPIC
  206. * interrupts cell = <intr #, sense>
  207. * sense values match linux IORESOURCE_IRQ_* defines:
  208. * sense == 8: Level, low assertion
  209. * sense == 2: Edge, high-to-low change
  210. */
  211. ipic: pic@700 {
  212. interrupt-controller;
  213. #address-cells = <0>;
  214. #interrupt-cells = <2>;
  215. reg = <0x700 0x100>;
  216. device_type = "ipic";
  217. };
  218. };
  219. pci0: pci@e0008500 {
  220. cell-index = <1>;
  221. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  222. interrupt-map = <
  223. /* IDSEL 0x0E -mini PCI */
  224. 0x7000 0x0 0x0 0x1 &ipic 18 0x8
  225. 0x7000 0x0 0x0 0x2 &ipic 18 0x8
  226. 0x7000 0x0 0x0 0x3 &ipic 18 0x8
  227. 0x7000 0x0 0x0 0x4 &ipic 18 0x8
  228. /* IDSEL 0x0F - PCI slot */
  229. 0x7800 0x0 0x0 0x1 &ipic 17 0x8
  230. 0x7800 0x0 0x0 0x2 &ipic 18 0x8
  231. 0x7800 0x0 0x0 0x3 &ipic 17 0x8
  232. 0x7800 0x0 0x0 0x4 &ipic 18 0x8>;
  233. interrupt-parent = <&ipic>;
  234. interrupts = <66 0x8>;
  235. bus-range = <0x0 0x0>;
  236. ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
  237. 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
  238. 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
  239. clock-frequency = <66666666>;
  240. #interrupt-cells = <1>;
  241. #size-cells = <2>;
  242. #address-cells = <3>;
  243. reg = <0xe0008500 0x100>;
  244. compatible = "fsl,mpc8349-pci";
  245. device_type = "pci";
  246. };
  247. };