main.c 50 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. u32 txpow;
  52. if (sc->curtxpow != sc->config.txpowlimit) {
  53. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  54. /* read back in case value is clamped */
  55. ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
  56. sc->curtxpow = txpow;
  57. }
  58. }
  59. static u8 parse_mpdudensity(u8 mpdudensity)
  60. {
  61. /*
  62. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  63. * 0 for no restriction
  64. * 1 for 1/4 us
  65. * 2 for 1/2 us
  66. * 3 for 1 us
  67. * 4 for 2 us
  68. * 5 for 4 us
  69. * 6 for 8 us
  70. * 7 for 16 us
  71. */
  72. switch (mpdudensity) {
  73. case 0:
  74. return 0;
  75. case 1:
  76. case 2:
  77. case 3:
  78. /* Our lower layer calculations limit our precision to
  79. 1 microsecond */
  80. return 1;
  81. case 4:
  82. return 2;
  83. case 5:
  84. return 4;
  85. case 6:
  86. return 8;
  87. case 7:
  88. return 16;
  89. default:
  90. return 0;
  91. }
  92. }
  93. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  94. struct ieee80211_hw *hw)
  95. {
  96. struct ieee80211_channel *curchan = hw->conf.channel;
  97. struct ath9k_channel *channel;
  98. u8 chan_idx;
  99. chan_idx = curchan->hw_value;
  100. channel = &sc->sc_ah->channels[chan_idx];
  101. ath9k_update_ichannel(sc, hw, channel);
  102. return channel;
  103. }
  104. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  105. {
  106. unsigned long flags;
  107. bool ret;
  108. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  109. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  110. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  111. return ret;
  112. }
  113. void ath9k_ps_wakeup(struct ath_softc *sc)
  114. {
  115. unsigned long flags;
  116. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  117. if (++sc->ps_usecount != 1)
  118. goto unlock;
  119. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  120. unlock:
  121. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  122. }
  123. void ath9k_ps_restore(struct ath_softc *sc)
  124. {
  125. unsigned long flags;
  126. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  127. if (--sc->ps_usecount != 0)
  128. goto unlock;
  129. if (sc->ps_enabled &&
  130. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  131. PS_WAIT_FOR_CAB |
  132. PS_WAIT_FOR_PSPOLL_DATA |
  133. PS_WAIT_FOR_TX_ACK)))
  134. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  135. unlock:
  136. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  137. }
  138. /*
  139. * Set/change channels. If the channel is really being changed, it's done
  140. * by reseting the chip. To accomplish this we must first cleanup any pending
  141. * DMA, then restart stuff.
  142. */
  143. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  144. struct ath9k_channel *hchan)
  145. {
  146. struct ath_hw *ah = sc->sc_ah;
  147. struct ath_common *common = ath9k_hw_common(ah);
  148. struct ieee80211_conf *conf = &common->hw->conf;
  149. bool fastcc = true, stopped;
  150. struct ieee80211_channel *channel = hw->conf.channel;
  151. int r;
  152. if (sc->sc_flags & SC_OP_INVALID)
  153. return -EIO;
  154. ath9k_ps_wakeup(sc);
  155. /*
  156. * This is only performed if the channel settings have
  157. * actually changed.
  158. *
  159. * To switch channels clear any pending DMA operations;
  160. * wait long enough for the RX fifo to drain, reset the
  161. * hardware at the new frequency, and then re-enable
  162. * the relevant bits of the h/w.
  163. */
  164. ath9k_hw_set_interrupts(ah, 0);
  165. ath_drain_all_txq(sc, false);
  166. stopped = ath_stoprecv(sc);
  167. /* XXX: do not flush receive queue here. We don't want
  168. * to flush data frames already in queue because of
  169. * changing channel. */
  170. if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
  171. fastcc = false;
  172. ath_print(common, ATH_DBG_CONFIG,
  173. "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
  174. sc->sc_ah->curchan->channel,
  175. channel->center_freq, conf_is_ht40(conf));
  176. spin_lock_bh(&sc->sc_resetlock);
  177. r = ath9k_hw_reset(ah, hchan, fastcc);
  178. if (r) {
  179. ath_print(common, ATH_DBG_FATAL,
  180. "Unable to reset channel (%u Mhz) "
  181. "reset status %d\n",
  182. channel->center_freq, r);
  183. spin_unlock_bh(&sc->sc_resetlock);
  184. goto ps_restore;
  185. }
  186. spin_unlock_bh(&sc->sc_resetlock);
  187. sc->sc_flags &= ~SC_OP_FULL_RESET;
  188. if (ath_startrecv(sc) != 0) {
  189. ath_print(common, ATH_DBG_FATAL,
  190. "Unable to restart recv logic\n");
  191. r = -EIO;
  192. goto ps_restore;
  193. }
  194. ath_cache_conf_rate(sc, &hw->conf);
  195. ath_update_txpow(sc);
  196. ath9k_hw_set_interrupts(ah, sc->imask);
  197. ps_restore:
  198. ath9k_ps_restore(sc);
  199. return r;
  200. }
  201. /*
  202. * This routine performs the periodic noise floor calibration function
  203. * that is used to adjust and optimize the chip performance. This
  204. * takes environmental changes (location, temperature) into account.
  205. * When the task is complete, it reschedules itself depending on the
  206. * appropriate interval that was calculated.
  207. */
  208. void ath_ani_calibrate(unsigned long data)
  209. {
  210. struct ath_softc *sc = (struct ath_softc *)data;
  211. struct ath_hw *ah = sc->sc_ah;
  212. struct ath_common *common = ath9k_hw_common(ah);
  213. bool longcal = false;
  214. bool shortcal = false;
  215. bool aniflag = false;
  216. unsigned int timestamp = jiffies_to_msecs(jiffies);
  217. u32 cal_interval, short_cal_interval;
  218. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  219. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  220. /* Only calibrate if awake */
  221. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  222. goto set_timer;
  223. ath9k_ps_wakeup(sc);
  224. /* Long calibration runs independently of short calibration. */
  225. if ((timestamp - common->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
  226. longcal = true;
  227. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  228. common->ani.longcal_timer = timestamp;
  229. }
  230. /* Short calibration applies only while caldone is false */
  231. if (!common->ani.caldone) {
  232. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  233. shortcal = true;
  234. ath_print(common, ATH_DBG_ANI,
  235. "shortcal @%lu\n", jiffies);
  236. common->ani.shortcal_timer = timestamp;
  237. common->ani.resetcal_timer = timestamp;
  238. }
  239. } else {
  240. if ((timestamp - common->ani.resetcal_timer) >=
  241. ATH_RESTART_CALINTERVAL) {
  242. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  243. if (common->ani.caldone)
  244. common->ani.resetcal_timer = timestamp;
  245. }
  246. }
  247. /* Verify whether we must check ANI */
  248. if ((timestamp - common->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
  249. aniflag = true;
  250. common->ani.checkani_timer = timestamp;
  251. }
  252. /* Skip all processing if there's nothing to do. */
  253. if (longcal || shortcal || aniflag) {
  254. /* Call ANI routine if necessary */
  255. if (aniflag)
  256. ath9k_hw_ani_monitor(ah, ah->curchan);
  257. /* Perform calibration if necessary */
  258. if (longcal || shortcal) {
  259. common->ani.caldone =
  260. ath9k_hw_calibrate(ah,
  261. ah->curchan,
  262. common->rx_chainmask,
  263. longcal);
  264. if (longcal)
  265. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  266. ah->curchan);
  267. ath_print(common, ATH_DBG_ANI,
  268. " calibrate chan %u/%x nf: %d\n",
  269. ah->curchan->channel,
  270. ah->curchan->channelFlags,
  271. common->ani.noise_floor);
  272. }
  273. }
  274. ath9k_ps_restore(sc);
  275. set_timer:
  276. /*
  277. * Set timer interval based on previous results.
  278. * The interval must be the shortest necessary to satisfy ANI,
  279. * short calibration and long calibration.
  280. */
  281. cal_interval = ATH_LONG_CALINTERVAL;
  282. if (sc->sc_ah->config.enable_ani)
  283. cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
  284. if (!common->ani.caldone)
  285. cal_interval = min(cal_interval, (u32)short_cal_interval);
  286. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  287. }
  288. static void ath_start_ani(struct ath_common *common)
  289. {
  290. unsigned long timestamp = jiffies_to_msecs(jiffies);
  291. common->ani.longcal_timer = timestamp;
  292. common->ani.shortcal_timer = timestamp;
  293. common->ani.checkani_timer = timestamp;
  294. mod_timer(&common->ani.timer,
  295. jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
  296. }
  297. /*
  298. * Update tx/rx chainmask. For legacy association,
  299. * hard code chainmask to 1x1, for 11n association, use
  300. * the chainmask configuration, for bt coexistence, use
  301. * the chainmask configuration even in legacy mode.
  302. */
  303. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  304. {
  305. struct ath_hw *ah = sc->sc_ah;
  306. struct ath_common *common = ath9k_hw_common(ah);
  307. if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
  308. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  309. common->tx_chainmask = ah->caps.tx_chainmask;
  310. common->rx_chainmask = ah->caps.rx_chainmask;
  311. } else {
  312. common->tx_chainmask = 1;
  313. common->rx_chainmask = 1;
  314. }
  315. ath_print(common, ATH_DBG_CONFIG,
  316. "tx chmask: %d, rx chmask: %d\n",
  317. common->tx_chainmask,
  318. common->rx_chainmask);
  319. }
  320. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  321. {
  322. struct ath_node *an;
  323. an = (struct ath_node *)sta->drv_priv;
  324. if (sc->sc_flags & SC_OP_TXAGGR) {
  325. ath_tx_node_init(sc, an);
  326. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  327. sta->ht_cap.ampdu_factor);
  328. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  329. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  330. }
  331. }
  332. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  333. {
  334. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  335. if (sc->sc_flags & SC_OP_TXAGGR)
  336. ath_tx_node_cleanup(sc, an);
  337. }
  338. void ath9k_tasklet(unsigned long data)
  339. {
  340. struct ath_softc *sc = (struct ath_softc *)data;
  341. struct ath_hw *ah = sc->sc_ah;
  342. struct ath_common *common = ath9k_hw_common(ah);
  343. u32 status = sc->intrstatus;
  344. ath9k_ps_wakeup(sc);
  345. if (status & ATH9K_INT_FATAL) {
  346. ath_reset(sc, false);
  347. ath9k_ps_restore(sc);
  348. return;
  349. }
  350. if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
  351. spin_lock_bh(&sc->rx.rxflushlock);
  352. ath_rx_tasklet(sc, 0);
  353. spin_unlock_bh(&sc->rx.rxflushlock);
  354. }
  355. if (status & ATH9K_INT_TX)
  356. ath_tx_tasklet(sc);
  357. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  358. /*
  359. * TSF sync does not look correct; remain awake to sync with
  360. * the next Beacon.
  361. */
  362. ath_print(common, ATH_DBG_PS,
  363. "TSFOOR - Sync with next Beacon\n");
  364. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  365. }
  366. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  367. if (status & ATH9K_INT_GENTIMER)
  368. ath_gen_timer_isr(sc->sc_ah);
  369. /* re-enable hardware interrupt */
  370. ath9k_hw_set_interrupts(ah, sc->imask);
  371. ath9k_ps_restore(sc);
  372. }
  373. irqreturn_t ath_isr(int irq, void *dev)
  374. {
  375. #define SCHED_INTR ( \
  376. ATH9K_INT_FATAL | \
  377. ATH9K_INT_RXORN | \
  378. ATH9K_INT_RXEOL | \
  379. ATH9K_INT_RX | \
  380. ATH9K_INT_TX | \
  381. ATH9K_INT_BMISS | \
  382. ATH9K_INT_CST | \
  383. ATH9K_INT_TSFOOR | \
  384. ATH9K_INT_GENTIMER)
  385. struct ath_softc *sc = dev;
  386. struct ath_hw *ah = sc->sc_ah;
  387. enum ath9k_int status;
  388. bool sched = false;
  389. /*
  390. * The hardware is not ready/present, don't
  391. * touch anything. Note this can happen early
  392. * on if the IRQ is shared.
  393. */
  394. if (sc->sc_flags & SC_OP_INVALID)
  395. return IRQ_NONE;
  396. /* shared irq, not for us */
  397. if (!ath9k_hw_intrpend(ah))
  398. return IRQ_NONE;
  399. /*
  400. * Figure out the reason(s) for the interrupt. Note
  401. * that the hal returns a pseudo-ISR that may include
  402. * bits we haven't explicitly enabled so we mask the
  403. * value to insure we only process bits we requested.
  404. */
  405. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  406. status &= sc->imask; /* discard unasked-for bits */
  407. /*
  408. * If there are no status bits set, then this interrupt was not
  409. * for me (should have been caught above).
  410. */
  411. if (!status)
  412. return IRQ_NONE;
  413. /* Cache the status */
  414. sc->intrstatus = status;
  415. if (status & SCHED_INTR)
  416. sched = true;
  417. /*
  418. * If a FATAL or RXORN interrupt is received, we have to reset the
  419. * chip immediately.
  420. */
  421. if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
  422. goto chip_reset;
  423. if (status & ATH9K_INT_SWBA)
  424. tasklet_schedule(&sc->bcon_tasklet);
  425. if (status & ATH9K_INT_TXURN)
  426. ath9k_hw_updatetxtriglevel(ah, true);
  427. if (status & ATH9K_INT_MIB) {
  428. /*
  429. * Disable interrupts until we service the MIB
  430. * interrupt; otherwise it will continue to
  431. * fire.
  432. */
  433. ath9k_hw_set_interrupts(ah, 0);
  434. /*
  435. * Let the hal handle the event. We assume
  436. * it will clear whatever condition caused
  437. * the interrupt.
  438. */
  439. ath9k_hw_procmibevent(ah);
  440. ath9k_hw_set_interrupts(ah, sc->imask);
  441. }
  442. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  443. if (status & ATH9K_INT_TIM_TIMER) {
  444. /* Clear RxAbort bit so that we can
  445. * receive frames */
  446. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  447. ath9k_hw_setrxabort(sc->sc_ah, 0);
  448. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  449. }
  450. chip_reset:
  451. ath_debug_stat_interrupt(sc, status);
  452. if (sched) {
  453. /* turn off every interrupt except SWBA */
  454. ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
  455. tasklet_schedule(&sc->intr_tq);
  456. }
  457. return IRQ_HANDLED;
  458. #undef SCHED_INTR
  459. }
  460. static u32 ath_get_extchanmode(struct ath_softc *sc,
  461. struct ieee80211_channel *chan,
  462. enum nl80211_channel_type channel_type)
  463. {
  464. u32 chanmode = 0;
  465. switch (chan->band) {
  466. case IEEE80211_BAND_2GHZ:
  467. switch(channel_type) {
  468. case NL80211_CHAN_NO_HT:
  469. case NL80211_CHAN_HT20:
  470. chanmode = CHANNEL_G_HT20;
  471. break;
  472. case NL80211_CHAN_HT40PLUS:
  473. chanmode = CHANNEL_G_HT40PLUS;
  474. break;
  475. case NL80211_CHAN_HT40MINUS:
  476. chanmode = CHANNEL_G_HT40MINUS;
  477. break;
  478. }
  479. break;
  480. case IEEE80211_BAND_5GHZ:
  481. switch(channel_type) {
  482. case NL80211_CHAN_NO_HT:
  483. case NL80211_CHAN_HT20:
  484. chanmode = CHANNEL_A_HT20;
  485. break;
  486. case NL80211_CHAN_HT40PLUS:
  487. chanmode = CHANNEL_A_HT40PLUS;
  488. break;
  489. case NL80211_CHAN_HT40MINUS:
  490. chanmode = CHANNEL_A_HT40MINUS;
  491. break;
  492. }
  493. break;
  494. default:
  495. break;
  496. }
  497. return chanmode;
  498. }
  499. static int ath_setkey_tkip(struct ath_common *common, u16 keyix, const u8 *key,
  500. struct ath9k_keyval *hk, const u8 *addr,
  501. bool authenticator)
  502. {
  503. struct ath_hw *ah = common->ah;
  504. const u8 *key_rxmic;
  505. const u8 *key_txmic;
  506. key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
  507. key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
  508. if (addr == NULL) {
  509. /*
  510. * Group key installation - only two key cache entries are used
  511. * regardless of splitmic capability since group key is only
  512. * used either for TX or RX.
  513. */
  514. if (authenticator) {
  515. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  516. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
  517. } else {
  518. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  519. memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
  520. }
  521. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  522. }
  523. if (!common->splitmic) {
  524. /* TX and RX keys share the same key cache entry. */
  525. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  526. memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
  527. return ath9k_hw_set_keycache_entry(ah, keyix, hk, addr);
  528. }
  529. /* Separate key cache entries for TX and RX */
  530. /* TX key goes at first index, RX key at +32. */
  531. memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
  532. if (!ath9k_hw_set_keycache_entry(ah, keyix, hk, NULL)) {
  533. /* TX MIC entry failed. No need to proceed further */
  534. ath_print(common, ATH_DBG_FATAL,
  535. "Setting TX MIC Key Failed\n");
  536. return 0;
  537. }
  538. memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
  539. /* XXX delete tx key on failure? */
  540. return ath9k_hw_set_keycache_entry(ah, keyix + 32, hk, addr);
  541. }
  542. static int ath_reserve_key_cache_slot_tkip(struct ath_common *common)
  543. {
  544. int i;
  545. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  546. if (test_bit(i, common->keymap) ||
  547. test_bit(i + 64, common->keymap))
  548. continue; /* At least one part of TKIP key allocated */
  549. if (common->splitmic &&
  550. (test_bit(i + 32, common->keymap) ||
  551. test_bit(i + 64 + 32, common->keymap)))
  552. continue; /* At least one part of TKIP key allocated */
  553. /* Found a free slot for a TKIP key */
  554. return i;
  555. }
  556. return -1;
  557. }
  558. static int ath_reserve_key_cache_slot(struct ath_common *common)
  559. {
  560. int i;
  561. /* First, try to find slots that would not be available for TKIP. */
  562. if (common->splitmic) {
  563. for (i = IEEE80211_WEP_NKID; i < common->keymax / 4; i++) {
  564. if (!test_bit(i, common->keymap) &&
  565. (test_bit(i + 32, common->keymap) ||
  566. test_bit(i + 64, common->keymap) ||
  567. test_bit(i + 64 + 32, common->keymap)))
  568. return i;
  569. if (!test_bit(i + 32, common->keymap) &&
  570. (test_bit(i, common->keymap) ||
  571. test_bit(i + 64, common->keymap) ||
  572. test_bit(i + 64 + 32, common->keymap)))
  573. return i + 32;
  574. if (!test_bit(i + 64, common->keymap) &&
  575. (test_bit(i , common->keymap) ||
  576. test_bit(i + 32, common->keymap) ||
  577. test_bit(i + 64 + 32, common->keymap)))
  578. return i + 64;
  579. if (!test_bit(i + 64 + 32, common->keymap) &&
  580. (test_bit(i, common->keymap) ||
  581. test_bit(i + 32, common->keymap) ||
  582. test_bit(i + 64, common->keymap)))
  583. return i + 64 + 32;
  584. }
  585. } else {
  586. for (i = IEEE80211_WEP_NKID; i < common->keymax / 2; i++) {
  587. if (!test_bit(i, common->keymap) &&
  588. test_bit(i + 64, common->keymap))
  589. return i;
  590. if (test_bit(i, common->keymap) &&
  591. !test_bit(i + 64, common->keymap))
  592. return i + 64;
  593. }
  594. }
  595. /* No partially used TKIP slots, pick any available slot */
  596. for (i = IEEE80211_WEP_NKID; i < common->keymax; i++) {
  597. /* Do not allow slots that could be needed for TKIP group keys
  598. * to be used. This limitation could be removed if we know that
  599. * TKIP will not be used. */
  600. if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
  601. continue;
  602. if (common->splitmic) {
  603. if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
  604. continue;
  605. if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
  606. continue;
  607. }
  608. if (!test_bit(i, common->keymap))
  609. return i; /* Found a free slot for a key */
  610. }
  611. /* No free slot found */
  612. return -1;
  613. }
  614. static int ath_key_config(struct ath_common *common,
  615. struct ieee80211_vif *vif,
  616. struct ieee80211_sta *sta,
  617. struct ieee80211_key_conf *key)
  618. {
  619. struct ath_hw *ah = common->ah;
  620. struct ath9k_keyval hk;
  621. const u8 *mac = NULL;
  622. int ret = 0;
  623. int idx;
  624. memset(&hk, 0, sizeof(hk));
  625. switch (key->alg) {
  626. case ALG_WEP:
  627. hk.kv_type = ATH9K_CIPHER_WEP;
  628. break;
  629. case ALG_TKIP:
  630. hk.kv_type = ATH9K_CIPHER_TKIP;
  631. break;
  632. case ALG_CCMP:
  633. hk.kv_type = ATH9K_CIPHER_AES_CCM;
  634. break;
  635. default:
  636. return -EOPNOTSUPP;
  637. }
  638. hk.kv_len = key->keylen;
  639. memcpy(hk.kv_val, key->key, key->keylen);
  640. if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  641. /* For now, use the default keys for broadcast keys. This may
  642. * need to change with virtual interfaces. */
  643. idx = key->keyidx;
  644. } else if (key->keyidx) {
  645. if (WARN_ON(!sta))
  646. return -EOPNOTSUPP;
  647. mac = sta->addr;
  648. if (vif->type != NL80211_IFTYPE_AP) {
  649. /* Only keyidx 0 should be used with unicast key, but
  650. * allow this for client mode for now. */
  651. idx = key->keyidx;
  652. } else
  653. return -EIO;
  654. } else {
  655. if (WARN_ON(!sta))
  656. return -EOPNOTSUPP;
  657. mac = sta->addr;
  658. if (key->alg == ALG_TKIP)
  659. idx = ath_reserve_key_cache_slot_tkip(common);
  660. else
  661. idx = ath_reserve_key_cache_slot(common);
  662. if (idx < 0)
  663. return -ENOSPC; /* no free key cache entries */
  664. }
  665. if (key->alg == ALG_TKIP)
  666. ret = ath_setkey_tkip(common, idx, key->key, &hk, mac,
  667. vif->type == NL80211_IFTYPE_AP);
  668. else
  669. ret = ath9k_hw_set_keycache_entry(ah, idx, &hk, mac);
  670. if (!ret)
  671. return -EIO;
  672. set_bit(idx, common->keymap);
  673. if (key->alg == ALG_TKIP) {
  674. set_bit(idx + 64, common->keymap);
  675. if (common->splitmic) {
  676. set_bit(idx + 32, common->keymap);
  677. set_bit(idx + 64 + 32, common->keymap);
  678. }
  679. }
  680. return idx;
  681. }
  682. static void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key)
  683. {
  684. struct ath_hw *ah = common->ah;
  685. ath9k_hw_keyreset(ah, key->hw_key_idx);
  686. if (key->hw_key_idx < IEEE80211_WEP_NKID)
  687. return;
  688. clear_bit(key->hw_key_idx, common->keymap);
  689. if (key->alg != ALG_TKIP)
  690. return;
  691. clear_bit(key->hw_key_idx + 64, common->keymap);
  692. if (common->splitmic) {
  693. clear_bit(key->hw_key_idx + 32, common->keymap);
  694. clear_bit(key->hw_key_idx + 64 + 32, common->keymap);
  695. }
  696. }
  697. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  698. struct ieee80211_vif *vif,
  699. struct ieee80211_bss_conf *bss_conf)
  700. {
  701. struct ath_hw *ah = sc->sc_ah;
  702. struct ath_common *common = ath9k_hw_common(ah);
  703. if (bss_conf->assoc) {
  704. ath_print(common, ATH_DBG_CONFIG,
  705. "Bss Info ASSOC %d, bssid: %pM\n",
  706. bss_conf->aid, common->curbssid);
  707. /* New association, store aid */
  708. common->curaid = bss_conf->aid;
  709. ath9k_hw_write_associd(ah);
  710. /*
  711. * Request a re-configuration of Beacon related timers
  712. * on the receipt of the first Beacon frame (i.e.,
  713. * after time sync with the AP).
  714. */
  715. sc->ps_flags |= PS_BEACON_SYNC;
  716. /* Configure the beacon */
  717. ath_beacon_config(sc, vif);
  718. /* Reset rssi stats */
  719. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  720. ath_start_ani(common);
  721. } else {
  722. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  723. common->curaid = 0;
  724. /* Stop ANI */
  725. del_timer_sync(&common->ani.timer);
  726. }
  727. }
  728. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  729. {
  730. struct ath_hw *ah = sc->sc_ah;
  731. struct ath_common *common = ath9k_hw_common(ah);
  732. struct ieee80211_channel *channel = hw->conf.channel;
  733. int r;
  734. ath9k_ps_wakeup(sc);
  735. ath9k_hw_configpcipowersave(ah, 0, 0);
  736. if (!ah->curchan)
  737. ah->curchan = ath_get_curchannel(sc, sc->hw);
  738. spin_lock_bh(&sc->sc_resetlock);
  739. r = ath9k_hw_reset(ah, ah->curchan, false);
  740. if (r) {
  741. ath_print(common, ATH_DBG_FATAL,
  742. "Unable to reset channel %u (%uMhz) ",
  743. "reset status %d\n",
  744. channel->center_freq, r);
  745. }
  746. spin_unlock_bh(&sc->sc_resetlock);
  747. ath_update_txpow(sc);
  748. if (ath_startrecv(sc) != 0) {
  749. ath_print(common, ATH_DBG_FATAL,
  750. "Unable to restart recv logic\n");
  751. return;
  752. }
  753. if (sc->sc_flags & SC_OP_BEACONS)
  754. ath_beacon_config(sc, NULL); /* restart beacons */
  755. /* Re-Enable interrupts */
  756. ath9k_hw_set_interrupts(ah, sc->imask);
  757. /* Enable LED */
  758. ath9k_hw_cfg_output(ah, ah->led_pin,
  759. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  760. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  761. ieee80211_wake_queues(hw);
  762. ath9k_ps_restore(sc);
  763. }
  764. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  765. {
  766. struct ath_hw *ah = sc->sc_ah;
  767. struct ieee80211_channel *channel = hw->conf.channel;
  768. int r;
  769. ath9k_ps_wakeup(sc);
  770. ieee80211_stop_queues(hw);
  771. /* Disable LED */
  772. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  773. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  774. /* Disable interrupts */
  775. ath9k_hw_set_interrupts(ah, 0);
  776. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  777. ath_stoprecv(sc); /* turn off frame recv */
  778. ath_flushrecv(sc); /* flush recv queue */
  779. if (!ah->curchan)
  780. ah->curchan = ath_get_curchannel(sc, hw);
  781. spin_lock_bh(&sc->sc_resetlock);
  782. r = ath9k_hw_reset(ah, ah->curchan, false);
  783. if (r) {
  784. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  785. "Unable to reset channel %u (%uMhz) "
  786. "reset status %d\n",
  787. channel->center_freq, r);
  788. }
  789. spin_unlock_bh(&sc->sc_resetlock);
  790. ath9k_hw_phy_disable(ah);
  791. ath9k_hw_configpcipowersave(ah, 1, 1);
  792. ath9k_ps_restore(sc);
  793. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  794. }
  795. int ath_reset(struct ath_softc *sc, bool retry_tx)
  796. {
  797. struct ath_hw *ah = sc->sc_ah;
  798. struct ath_common *common = ath9k_hw_common(ah);
  799. struct ieee80211_hw *hw = sc->hw;
  800. int r;
  801. /* Stop ANI */
  802. del_timer_sync(&common->ani.timer);
  803. ath9k_hw_set_interrupts(ah, 0);
  804. ath_drain_all_txq(sc, retry_tx);
  805. ath_stoprecv(sc);
  806. ath_flushrecv(sc);
  807. spin_lock_bh(&sc->sc_resetlock);
  808. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
  809. if (r)
  810. ath_print(common, ATH_DBG_FATAL,
  811. "Unable to reset hardware; reset status %d\n", r);
  812. spin_unlock_bh(&sc->sc_resetlock);
  813. if (ath_startrecv(sc) != 0)
  814. ath_print(common, ATH_DBG_FATAL,
  815. "Unable to start recv logic\n");
  816. /*
  817. * We may be doing a reset in response to a request
  818. * that changes the channel so update any state that
  819. * might change as a result.
  820. */
  821. ath_cache_conf_rate(sc, &hw->conf);
  822. ath_update_txpow(sc);
  823. if (sc->sc_flags & SC_OP_BEACONS)
  824. ath_beacon_config(sc, NULL); /* restart beacons */
  825. ath9k_hw_set_interrupts(ah, sc->imask);
  826. if (retry_tx) {
  827. int i;
  828. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  829. if (ATH_TXQ_SETUP(sc, i)) {
  830. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  831. ath_txq_schedule(sc, &sc->tx.txq[i]);
  832. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  833. }
  834. }
  835. }
  836. /* Start ANI */
  837. ath_start_ani(common);
  838. return r;
  839. }
  840. int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  841. {
  842. int qnum;
  843. switch (queue) {
  844. case 0:
  845. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
  846. break;
  847. case 1:
  848. qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
  849. break;
  850. case 2:
  851. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  852. break;
  853. case 3:
  854. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
  855. break;
  856. default:
  857. qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
  858. break;
  859. }
  860. return qnum;
  861. }
  862. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  863. {
  864. int qnum;
  865. switch (queue) {
  866. case ATH9K_WME_AC_VO:
  867. qnum = 0;
  868. break;
  869. case ATH9K_WME_AC_VI:
  870. qnum = 1;
  871. break;
  872. case ATH9K_WME_AC_BE:
  873. qnum = 2;
  874. break;
  875. case ATH9K_WME_AC_BK:
  876. qnum = 3;
  877. break;
  878. default:
  879. qnum = -1;
  880. break;
  881. }
  882. return qnum;
  883. }
  884. /* XXX: Remove me once we don't depend on ath9k_channel for all
  885. * this redundant data */
  886. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  887. struct ath9k_channel *ichan)
  888. {
  889. struct ieee80211_channel *chan = hw->conf.channel;
  890. struct ieee80211_conf *conf = &hw->conf;
  891. ichan->channel = chan->center_freq;
  892. ichan->chan = chan;
  893. if (chan->band == IEEE80211_BAND_2GHZ) {
  894. ichan->chanmode = CHANNEL_G;
  895. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  896. } else {
  897. ichan->chanmode = CHANNEL_A;
  898. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  899. }
  900. if (conf_is_ht(conf))
  901. ichan->chanmode = ath_get_extchanmode(sc, chan,
  902. conf->channel_type);
  903. }
  904. /**********************/
  905. /* mac80211 callbacks */
  906. /**********************/
  907. static int ath9k_start(struct ieee80211_hw *hw)
  908. {
  909. struct ath_wiphy *aphy = hw->priv;
  910. struct ath_softc *sc = aphy->sc;
  911. struct ath_hw *ah = sc->sc_ah;
  912. struct ath_common *common = ath9k_hw_common(ah);
  913. struct ieee80211_channel *curchan = hw->conf.channel;
  914. struct ath9k_channel *init_channel;
  915. int r;
  916. ath_print(common, ATH_DBG_CONFIG,
  917. "Starting driver with initial channel: %d MHz\n",
  918. curchan->center_freq);
  919. mutex_lock(&sc->mutex);
  920. if (ath9k_wiphy_started(sc)) {
  921. if (sc->chan_idx == curchan->hw_value) {
  922. /*
  923. * Already on the operational channel, the new wiphy
  924. * can be marked active.
  925. */
  926. aphy->state = ATH_WIPHY_ACTIVE;
  927. ieee80211_wake_queues(hw);
  928. } else {
  929. /*
  930. * Another wiphy is on another channel, start the new
  931. * wiphy in paused state.
  932. */
  933. aphy->state = ATH_WIPHY_PAUSED;
  934. ieee80211_stop_queues(hw);
  935. }
  936. mutex_unlock(&sc->mutex);
  937. return 0;
  938. }
  939. aphy->state = ATH_WIPHY_ACTIVE;
  940. /* setup initial channel */
  941. sc->chan_idx = curchan->hw_value;
  942. init_channel = ath_get_curchannel(sc, hw);
  943. /* Reset SERDES registers */
  944. ath9k_hw_configpcipowersave(ah, 0, 0);
  945. /*
  946. * The basic interface to setting the hardware in a good
  947. * state is ``reset''. On return the hardware is known to
  948. * be powered up and with interrupts disabled. This must
  949. * be followed by initialization of the appropriate bits
  950. * and then setup of the interrupt mask.
  951. */
  952. spin_lock_bh(&sc->sc_resetlock);
  953. r = ath9k_hw_reset(ah, init_channel, false);
  954. if (r) {
  955. ath_print(common, ATH_DBG_FATAL,
  956. "Unable to reset hardware; reset status %d "
  957. "(freq %u MHz)\n", r,
  958. curchan->center_freq);
  959. spin_unlock_bh(&sc->sc_resetlock);
  960. goto mutex_unlock;
  961. }
  962. spin_unlock_bh(&sc->sc_resetlock);
  963. /*
  964. * This is needed only to setup initial state
  965. * but it's best done after a reset.
  966. */
  967. ath_update_txpow(sc);
  968. /*
  969. * Setup the hardware after reset:
  970. * The receive engine is set going.
  971. * Frame transmit is handled entirely
  972. * in the frame output path; there's nothing to do
  973. * here except setup the interrupt mask.
  974. */
  975. if (ath_startrecv(sc) != 0) {
  976. ath_print(common, ATH_DBG_FATAL,
  977. "Unable to start recv logic\n");
  978. r = -EIO;
  979. goto mutex_unlock;
  980. }
  981. /* Setup our intr mask. */
  982. sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
  983. | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
  984. | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
  985. if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
  986. sc->imask |= ATH9K_INT_GTT;
  987. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  988. sc->imask |= ATH9K_INT_CST;
  989. ath_cache_conf_rate(sc, &hw->conf);
  990. sc->sc_flags &= ~SC_OP_INVALID;
  991. /* Disable BMISS interrupt when we're not associated */
  992. sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  993. ath9k_hw_set_interrupts(ah, sc->imask);
  994. ieee80211_wake_queues(hw);
  995. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  996. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  997. !ah->btcoex_hw.enabled) {
  998. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  999. AR_STOMP_LOW_WLAN_WGHT);
  1000. ath9k_hw_btcoex_enable(ah);
  1001. if (common->bus_ops->bt_coex_prep)
  1002. common->bus_ops->bt_coex_prep(common);
  1003. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1004. ath9k_btcoex_timer_resume(sc);
  1005. }
  1006. mutex_unlock:
  1007. mutex_unlock(&sc->mutex);
  1008. return r;
  1009. }
  1010. static int ath9k_tx(struct ieee80211_hw *hw,
  1011. struct sk_buff *skb)
  1012. {
  1013. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1014. struct ath_wiphy *aphy = hw->priv;
  1015. struct ath_softc *sc = aphy->sc;
  1016. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1017. struct ath_tx_control txctl;
  1018. int padpos, padsize;
  1019. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1020. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  1021. ath_print(common, ATH_DBG_XMIT,
  1022. "ath9k: %s: TX in unexpected wiphy state "
  1023. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  1024. goto exit;
  1025. }
  1026. if (sc->ps_enabled) {
  1027. /*
  1028. * mac80211 does not set PM field for normal data frames, so we
  1029. * need to update that based on the current PS mode.
  1030. */
  1031. if (ieee80211_is_data(hdr->frame_control) &&
  1032. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1033. !ieee80211_has_pm(hdr->frame_control)) {
  1034. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1035. "while in PS mode\n");
  1036. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1037. }
  1038. }
  1039. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1040. /*
  1041. * We are using PS-Poll and mac80211 can request TX while in
  1042. * power save mode. Need to wake up hardware for the TX to be
  1043. * completed and if needed, also for RX of buffered frames.
  1044. */
  1045. ath9k_ps_wakeup(sc);
  1046. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1047. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1048. ath_print(common, ATH_DBG_PS,
  1049. "Sending PS-Poll to pick a buffered frame\n");
  1050. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1051. } else {
  1052. ath_print(common, ATH_DBG_PS,
  1053. "Wake up to complete TX\n");
  1054. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1055. }
  1056. /*
  1057. * The actual restore operation will happen only after
  1058. * the sc_flags bit is cleared. We are just dropping
  1059. * the ps_usecount here.
  1060. */
  1061. ath9k_ps_restore(sc);
  1062. }
  1063. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1064. /*
  1065. * As a temporary workaround, assign seq# here; this will likely need
  1066. * to be cleaned up to work better with Beacon transmission and virtual
  1067. * BSSes.
  1068. */
  1069. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1070. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1071. sc->tx.seq_no += 0x10;
  1072. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1073. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1074. }
  1075. /* Add the padding after the header if this is not already done */
  1076. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1077. padsize = padpos & 3;
  1078. if (padsize && skb->len>padpos) {
  1079. if (skb_headroom(skb) < padsize)
  1080. return -1;
  1081. skb_push(skb, padsize);
  1082. memmove(skb->data, skb->data + padsize, padpos);
  1083. }
  1084. /* Check if a tx queue is available */
  1085. txctl.txq = ath_test_get_txq(sc, skb);
  1086. if (!txctl.txq)
  1087. goto exit;
  1088. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1089. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1090. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1091. goto exit;
  1092. }
  1093. return 0;
  1094. exit:
  1095. dev_kfree_skb_any(skb);
  1096. return 0;
  1097. }
  1098. static void ath9k_stop(struct ieee80211_hw *hw)
  1099. {
  1100. struct ath_wiphy *aphy = hw->priv;
  1101. struct ath_softc *sc = aphy->sc;
  1102. struct ath_hw *ah = sc->sc_ah;
  1103. struct ath_common *common = ath9k_hw_common(ah);
  1104. mutex_lock(&sc->mutex);
  1105. aphy->state = ATH_WIPHY_INACTIVE;
  1106. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1107. cancel_delayed_work_sync(&sc->tx_complete_work);
  1108. if (!sc->num_sec_wiphy) {
  1109. cancel_delayed_work_sync(&sc->wiphy_work);
  1110. cancel_work_sync(&sc->chan_work);
  1111. }
  1112. if (sc->sc_flags & SC_OP_INVALID) {
  1113. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1114. mutex_unlock(&sc->mutex);
  1115. return;
  1116. }
  1117. if (ath9k_wiphy_started(sc)) {
  1118. mutex_unlock(&sc->mutex);
  1119. return; /* another wiphy still in use */
  1120. }
  1121. /* Ensure HW is awake when we try to shut it down. */
  1122. ath9k_ps_wakeup(sc);
  1123. if (ah->btcoex_hw.enabled) {
  1124. ath9k_hw_btcoex_disable(ah);
  1125. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1126. ath9k_btcoex_timer_pause(sc);
  1127. }
  1128. /* make sure h/w will not generate any interrupt
  1129. * before setting the invalid flag. */
  1130. ath9k_hw_set_interrupts(ah, 0);
  1131. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1132. ath_drain_all_txq(sc, false);
  1133. ath_stoprecv(sc);
  1134. ath9k_hw_phy_disable(ah);
  1135. } else
  1136. sc->rx.rxlink = NULL;
  1137. /* disable HAL and put h/w to sleep */
  1138. ath9k_hw_disable(ah);
  1139. ath9k_hw_configpcipowersave(ah, 1, 1);
  1140. ath9k_ps_restore(sc);
  1141. /* Finally, put the chip in FULL SLEEP mode */
  1142. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1143. sc->sc_flags |= SC_OP_INVALID;
  1144. mutex_unlock(&sc->mutex);
  1145. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1146. }
  1147. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1148. struct ieee80211_vif *vif)
  1149. {
  1150. struct ath_wiphy *aphy = hw->priv;
  1151. struct ath_softc *sc = aphy->sc;
  1152. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1153. struct ath_vif *avp = (void *)vif->drv_priv;
  1154. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1155. int ret = 0;
  1156. mutex_lock(&sc->mutex);
  1157. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
  1158. sc->nvifs > 0) {
  1159. ret = -ENOBUFS;
  1160. goto out;
  1161. }
  1162. switch (vif->type) {
  1163. case NL80211_IFTYPE_STATION:
  1164. ic_opmode = NL80211_IFTYPE_STATION;
  1165. break;
  1166. case NL80211_IFTYPE_ADHOC:
  1167. case NL80211_IFTYPE_AP:
  1168. case NL80211_IFTYPE_MESH_POINT:
  1169. if (sc->nbcnvifs >= ATH_BCBUF) {
  1170. ret = -ENOBUFS;
  1171. goto out;
  1172. }
  1173. ic_opmode = vif->type;
  1174. break;
  1175. default:
  1176. ath_print(common, ATH_DBG_FATAL,
  1177. "Interface type %d not yet supported\n", vif->type);
  1178. ret = -EOPNOTSUPP;
  1179. goto out;
  1180. }
  1181. ath_print(common, ATH_DBG_CONFIG,
  1182. "Attach a VIF of type: %d\n", ic_opmode);
  1183. /* Set the VIF opmode */
  1184. avp->av_opmode = ic_opmode;
  1185. avp->av_bslot = -1;
  1186. sc->nvifs++;
  1187. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
  1188. ath9k_set_bssid_mask(hw);
  1189. if (sc->nvifs > 1)
  1190. goto out; /* skip global settings for secondary vif */
  1191. if (ic_opmode == NL80211_IFTYPE_AP) {
  1192. ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
  1193. sc->sc_flags |= SC_OP_TSF_RESET;
  1194. }
  1195. /* Set the device opmode */
  1196. sc->sc_ah->opmode = ic_opmode;
  1197. /*
  1198. * Enable MIB interrupts when there are hardware phy counters.
  1199. * Note we only do this (at the moment) for station mode.
  1200. */
  1201. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1202. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1203. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1204. sc->imask |= ATH9K_INT_MIB;
  1205. sc->imask |= ATH9K_INT_TSFOOR;
  1206. }
  1207. ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
  1208. if (vif->type == NL80211_IFTYPE_AP ||
  1209. vif->type == NL80211_IFTYPE_ADHOC ||
  1210. vif->type == NL80211_IFTYPE_MONITOR)
  1211. ath_start_ani(common);
  1212. out:
  1213. mutex_unlock(&sc->mutex);
  1214. return ret;
  1215. }
  1216. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1217. struct ieee80211_vif *vif)
  1218. {
  1219. struct ath_wiphy *aphy = hw->priv;
  1220. struct ath_softc *sc = aphy->sc;
  1221. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1222. struct ath_vif *avp = (void *)vif->drv_priv;
  1223. int i;
  1224. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1225. mutex_lock(&sc->mutex);
  1226. /* Stop ANI */
  1227. del_timer_sync(&common->ani.timer);
  1228. /* Reclaim beacon resources */
  1229. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1230. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1231. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1232. ath9k_ps_wakeup(sc);
  1233. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1234. ath_beacon_return(sc, avp);
  1235. ath9k_ps_restore(sc);
  1236. }
  1237. sc->sc_flags &= ~SC_OP_BEACONS;
  1238. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1239. if (sc->beacon.bslot[i] == vif) {
  1240. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1241. "slot\n", __func__);
  1242. sc->beacon.bslot[i] = NULL;
  1243. sc->beacon.bslot_aphy[i] = NULL;
  1244. }
  1245. }
  1246. sc->nvifs--;
  1247. mutex_unlock(&sc->mutex);
  1248. }
  1249. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1250. {
  1251. struct ath_wiphy *aphy = hw->priv;
  1252. struct ath_softc *sc = aphy->sc;
  1253. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1254. struct ieee80211_conf *conf = &hw->conf;
  1255. struct ath_hw *ah = sc->sc_ah;
  1256. bool disable_radio;
  1257. mutex_lock(&sc->mutex);
  1258. /*
  1259. * Leave this as the first check because we need to turn on the
  1260. * radio if it was disabled before prior to processing the rest
  1261. * of the changes. Likewise we must only disable the radio towards
  1262. * the end.
  1263. */
  1264. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1265. bool enable_radio;
  1266. bool all_wiphys_idle;
  1267. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1268. spin_lock_bh(&sc->wiphy_lock);
  1269. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1270. ath9k_set_wiphy_idle(aphy, idle);
  1271. if (!idle && all_wiphys_idle)
  1272. enable_radio = true;
  1273. /*
  1274. * After we unlock here its possible another wiphy
  1275. * can be re-renabled so to account for that we will
  1276. * only disable the radio toward the end of this routine
  1277. * if by then all wiphys are still idle.
  1278. */
  1279. spin_unlock_bh(&sc->wiphy_lock);
  1280. if (enable_radio) {
  1281. ath_radio_enable(sc, hw);
  1282. ath_print(common, ATH_DBG_CONFIG,
  1283. "not-idle: enabling radio\n");
  1284. }
  1285. }
  1286. /*
  1287. * We just prepare to enable PS. We have to wait until our AP has
  1288. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1289. * those ACKs and end up retransmitting the same null data frames.
  1290. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1291. */
  1292. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1293. if (conf->flags & IEEE80211_CONF_PS) {
  1294. sc->ps_flags |= PS_ENABLED;
  1295. if (!(ah->caps.hw_caps &
  1296. ATH9K_HW_CAP_AUTOSLEEP)) {
  1297. if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1298. sc->imask |= ATH9K_INT_TIM_TIMER;
  1299. ath9k_hw_set_interrupts(sc->sc_ah,
  1300. sc->imask);
  1301. }
  1302. }
  1303. /*
  1304. * At this point we know hardware has received an ACK
  1305. * of a previously sent null data frame.
  1306. */
  1307. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1308. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1309. sc->ps_enabled = true;
  1310. ath9k_hw_setrxabort(sc->sc_ah, 1);
  1311. }
  1312. } else {
  1313. sc->ps_enabled = false;
  1314. sc->ps_flags &= ~(PS_ENABLED |
  1315. PS_NULLFUNC_COMPLETED);
  1316. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  1317. if (!(ah->caps.hw_caps &
  1318. ATH9K_HW_CAP_AUTOSLEEP)) {
  1319. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1320. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1321. PS_WAIT_FOR_CAB |
  1322. PS_WAIT_FOR_PSPOLL_DATA |
  1323. PS_WAIT_FOR_TX_ACK);
  1324. if (sc->imask & ATH9K_INT_TIM_TIMER) {
  1325. sc->imask &= ~ATH9K_INT_TIM_TIMER;
  1326. ath9k_hw_set_interrupts(sc->sc_ah,
  1327. sc->imask);
  1328. }
  1329. }
  1330. }
  1331. }
  1332. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1333. struct ieee80211_channel *curchan = hw->conf.channel;
  1334. int pos = curchan->hw_value;
  1335. aphy->chan_idx = pos;
  1336. aphy->chan_is_ht = conf_is_ht(conf);
  1337. if (aphy->state == ATH_WIPHY_SCAN ||
  1338. aphy->state == ATH_WIPHY_ACTIVE)
  1339. ath9k_wiphy_pause_all_forced(sc, aphy);
  1340. else {
  1341. /*
  1342. * Do not change operational channel based on a paused
  1343. * wiphy changes.
  1344. */
  1345. goto skip_chan_change;
  1346. }
  1347. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1348. curchan->center_freq);
  1349. /* XXX: remove me eventualy */
  1350. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1351. ath_update_chainmask(sc, conf_is_ht(conf));
  1352. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1353. ath_print(common, ATH_DBG_FATAL,
  1354. "Unable to set channel\n");
  1355. mutex_unlock(&sc->mutex);
  1356. return -EINVAL;
  1357. }
  1358. }
  1359. skip_chan_change:
  1360. if (changed & IEEE80211_CONF_CHANGE_POWER)
  1361. sc->config.txpowlimit = 2 * conf->power_level;
  1362. spin_lock_bh(&sc->wiphy_lock);
  1363. disable_radio = ath9k_all_wiphys_idle(sc);
  1364. spin_unlock_bh(&sc->wiphy_lock);
  1365. if (disable_radio) {
  1366. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1367. ath_radio_disable(sc, hw);
  1368. }
  1369. mutex_unlock(&sc->mutex);
  1370. return 0;
  1371. }
  1372. #define SUPPORTED_FILTERS \
  1373. (FIF_PROMISC_IN_BSS | \
  1374. FIF_ALLMULTI | \
  1375. FIF_CONTROL | \
  1376. FIF_PSPOLL | \
  1377. FIF_OTHER_BSS | \
  1378. FIF_BCN_PRBRESP_PROMISC | \
  1379. FIF_FCSFAIL)
  1380. /* FIXME: sc->sc_full_reset ? */
  1381. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1382. unsigned int changed_flags,
  1383. unsigned int *total_flags,
  1384. u64 multicast)
  1385. {
  1386. struct ath_wiphy *aphy = hw->priv;
  1387. struct ath_softc *sc = aphy->sc;
  1388. u32 rfilt;
  1389. changed_flags &= SUPPORTED_FILTERS;
  1390. *total_flags &= SUPPORTED_FILTERS;
  1391. sc->rx.rxfilter = *total_flags;
  1392. ath9k_ps_wakeup(sc);
  1393. rfilt = ath_calcrxfilter(sc);
  1394. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1395. ath9k_ps_restore(sc);
  1396. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1397. "Set HW RX filter: 0x%x\n", rfilt);
  1398. }
  1399. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1400. struct ieee80211_vif *vif,
  1401. enum sta_notify_cmd cmd,
  1402. struct ieee80211_sta *sta)
  1403. {
  1404. struct ath_wiphy *aphy = hw->priv;
  1405. struct ath_softc *sc = aphy->sc;
  1406. switch (cmd) {
  1407. case STA_NOTIFY_ADD:
  1408. ath_node_attach(sc, sta);
  1409. break;
  1410. case STA_NOTIFY_REMOVE:
  1411. ath_node_detach(sc, sta);
  1412. break;
  1413. default:
  1414. break;
  1415. }
  1416. }
  1417. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1418. const struct ieee80211_tx_queue_params *params)
  1419. {
  1420. struct ath_wiphy *aphy = hw->priv;
  1421. struct ath_softc *sc = aphy->sc;
  1422. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1423. struct ath9k_tx_queue_info qi;
  1424. int ret = 0, qnum;
  1425. if (queue >= WME_NUM_AC)
  1426. return 0;
  1427. mutex_lock(&sc->mutex);
  1428. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1429. qi.tqi_aifs = params->aifs;
  1430. qi.tqi_cwmin = params->cw_min;
  1431. qi.tqi_cwmax = params->cw_max;
  1432. qi.tqi_burstTime = params->txop;
  1433. qnum = ath_get_hal_qnum(queue, sc);
  1434. ath_print(common, ATH_DBG_CONFIG,
  1435. "Configure tx [queue/halq] [%d/%d], "
  1436. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1437. queue, qnum, params->aifs, params->cw_min,
  1438. params->cw_max, params->txop);
  1439. ret = ath_txq_update(sc, qnum, &qi);
  1440. if (ret)
  1441. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1442. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1443. if ((qnum == sc->tx.hwq_map[ATH9K_WME_AC_BE]) && !ret)
  1444. ath_beaconq_config(sc);
  1445. mutex_unlock(&sc->mutex);
  1446. return ret;
  1447. }
  1448. static int ath9k_set_key(struct ieee80211_hw *hw,
  1449. enum set_key_cmd cmd,
  1450. struct ieee80211_vif *vif,
  1451. struct ieee80211_sta *sta,
  1452. struct ieee80211_key_conf *key)
  1453. {
  1454. struct ath_wiphy *aphy = hw->priv;
  1455. struct ath_softc *sc = aphy->sc;
  1456. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1457. int ret = 0;
  1458. if (modparam_nohwcrypt)
  1459. return -ENOSPC;
  1460. mutex_lock(&sc->mutex);
  1461. ath9k_ps_wakeup(sc);
  1462. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1463. switch (cmd) {
  1464. case SET_KEY:
  1465. ret = ath_key_config(common, vif, sta, key);
  1466. if (ret >= 0) {
  1467. key->hw_key_idx = ret;
  1468. /* push IV and Michael MIC generation to stack */
  1469. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1470. if (key->alg == ALG_TKIP)
  1471. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1472. if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
  1473. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1474. ret = 0;
  1475. }
  1476. break;
  1477. case DISABLE_KEY:
  1478. ath_key_delete(common, key);
  1479. break;
  1480. default:
  1481. ret = -EINVAL;
  1482. }
  1483. ath9k_ps_restore(sc);
  1484. mutex_unlock(&sc->mutex);
  1485. return ret;
  1486. }
  1487. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1488. struct ieee80211_vif *vif,
  1489. struct ieee80211_bss_conf *bss_conf,
  1490. u32 changed)
  1491. {
  1492. struct ath_wiphy *aphy = hw->priv;
  1493. struct ath_softc *sc = aphy->sc;
  1494. struct ath_hw *ah = sc->sc_ah;
  1495. struct ath_common *common = ath9k_hw_common(ah);
  1496. struct ath_vif *avp = (void *)vif->drv_priv;
  1497. int error;
  1498. mutex_lock(&sc->mutex);
  1499. if (changed & BSS_CHANGED_BSSID) {
  1500. /* Set BSSID */
  1501. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1502. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1503. common->curaid = 0;
  1504. ath9k_hw_write_associd(ah);
  1505. /* Set aggregation protection mode parameters */
  1506. sc->config.ath_aggr_prot = 0;
  1507. /* Only legacy IBSS for now */
  1508. if (vif->type == NL80211_IFTYPE_ADHOC)
  1509. ath_update_chainmask(sc, 0);
  1510. ath_print(common, ATH_DBG_CONFIG,
  1511. "BSSID: %pM aid: 0x%x\n",
  1512. common->curbssid, common->curaid);
  1513. /* need to reconfigure the beacon */
  1514. sc->sc_flags &= ~SC_OP_BEACONS ;
  1515. }
  1516. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1517. if ((changed & BSS_CHANGED_BEACON) ||
  1518. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1519. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1520. error = ath_beacon_alloc(aphy, vif);
  1521. if (!error)
  1522. ath_beacon_config(sc, vif);
  1523. }
  1524. /* Disable transmission of beacons */
  1525. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1526. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1527. if (changed & BSS_CHANGED_BEACON_INT) {
  1528. sc->beacon_interval = bss_conf->beacon_int;
  1529. /*
  1530. * In case of AP mode, the HW TSF has to be reset
  1531. * when the beacon interval changes.
  1532. */
  1533. if (vif->type == NL80211_IFTYPE_AP) {
  1534. sc->sc_flags |= SC_OP_TSF_RESET;
  1535. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1536. error = ath_beacon_alloc(aphy, vif);
  1537. if (!error)
  1538. ath_beacon_config(sc, vif);
  1539. } else {
  1540. ath_beacon_config(sc, vif);
  1541. }
  1542. }
  1543. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1544. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1545. bss_conf->use_short_preamble);
  1546. if (bss_conf->use_short_preamble)
  1547. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1548. else
  1549. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1550. }
  1551. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1552. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1553. bss_conf->use_cts_prot);
  1554. if (bss_conf->use_cts_prot &&
  1555. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1556. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1557. else
  1558. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1559. }
  1560. if (changed & BSS_CHANGED_ASSOC) {
  1561. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1562. bss_conf->assoc);
  1563. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1564. }
  1565. mutex_unlock(&sc->mutex);
  1566. }
  1567. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1568. {
  1569. u64 tsf;
  1570. struct ath_wiphy *aphy = hw->priv;
  1571. struct ath_softc *sc = aphy->sc;
  1572. mutex_lock(&sc->mutex);
  1573. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1574. mutex_unlock(&sc->mutex);
  1575. return tsf;
  1576. }
  1577. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1578. {
  1579. struct ath_wiphy *aphy = hw->priv;
  1580. struct ath_softc *sc = aphy->sc;
  1581. mutex_lock(&sc->mutex);
  1582. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1583. mutex_unlock(&sc->mutex);
  1584. }
  1585. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1586. {
  1587. struct ath_wiphy *aphy = hw->priv;
  1588. struct ath_softc *sc = aphy->sc;
  1589. mutex_lock(&sc->mutex);
  1590. ath9k_ps_wakeup(sc);
  1591. ath9k_hw_reset_tsf(sc->sc_ah);
  1592. ath9k_ps_restore(sc);
  1593. mutex_unlock(&sc->mutex);
  1594. }
  1595. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1596. struct ieee80211_vif *vif,
  1597. enum ieee80211_ampdu_mlme_action action,
  1598. struct ieee80211_sta *sta,
  1599. u16 tid, u16 *ssn)
  1600. {
  1601. struct ath_wiphy *aphy = hw->priv;
  1602. struct ath_softc *sc = aphy->sc;
  1603. int ret = 0;
  1604. switch (action) {
  1605. case IEEE80211_AMPDU_RX_START:
  1606. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1607. ret = -ENOTSUPP;
  1608. break;
  1609. case IEEE80211_AMPDU_RX_STOP:
  1610. break;
  1611. case IEEE80211_AMPDU_TX_START:
  1612. ath9k_ps_wakeup(sc);
  1613. ath_tx_aggr_start(sc, sta, tid, ssn);
  1614. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1615. ath9k_ps_restore(sc);
  1616. break;
  1617. case IEEE80211_AMPDU_TX_STOP:
  1618. ath9k_ps_wakeup(sc);
  1619. ath_tx_aggr_stop(sc, sta, tid);
  1620. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1621. ath9k_ps_restore(sc);
  1622. break;
  1623. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1624. ath9k_ps_wakeup(sc);
  1625. ath_tx_aggr_resume(sc, sta, tid);
  1626. ath9k_ps_restore(sc);
  1627. break;
  1628. default:
  1629. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1630. "Unknown AMPDU action\n");
  1631. }
  1632. return ret;
  1633. }
  1634. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1635. {
  1636. struct ath_wiphy *aphy = hw->priv;
  1637. struct ath_softc *sc = aphy->sc;
  1638. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1639. mutex_lock(&sc->mutex);
  1640. if (ath9k_wiphy_scanning(sc)) {
  1641. printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
  1642. "same time\n");
  1643. /*
  1644. * Do not allow the concurrent scanning state for now. This
  1645. * could be improved with scanning control moved into ath9k.
  1646. */
  1647. mutex_unlock(&sc->mutex);
  1648. return;
  1649. }
  1650. aphy->state = ATH_WIPHY_SCAN;
  1651. ath9k_wiphy_pause_all_forced(sc, aphy);
  1652. sc->sc_flags |= SC_OP_SCANNING;
  1653. del_timer_sync(&common->ani.timer);
  1654. cancel_delayed_work_sync(&sc->tx_complete_work);
  1655. mutex_unlock(&sc->mutex);
  1656. }
  1657. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1658. {
  1659. struct ath_wiphy *aphy = hw->priv;
  1660. struct ath_softc *sc = aphy->sc;
  1661. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1662. mutex_lock(&sc->mutex);
  1663. aphy->state = ATH_WIPHY_ACTIVE;
  1664. sc->sc_flags &= ~SC_OP_SCANNING;
  1665. sc->sc_flags |= SC_OP_FULL_RESET;
  1666. ath_start_ani(common);
  1667. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  1668. ath_beacon_config(sc, NULL);
  1669. mutex_unlock(&sc->mutex);
  1670. }
  1671. struct ieee80211_ops ath9k_ops = {
  1672. .tx = ath9k_tx,
  1673. .start = ath9k_start,
  1674. .stop = ath9k_stop,
  1675. .add_interface = ath9k_add_interface,
  1676. .remove_interface = ath9k_remove_interface,
  1677. .config = ath9k_config,
  1678. .configure_filter = ath9k_configure_filter,
  1679. .sta_notify = ath9k_sta_notify,
  1680. .conf_tx = ath9k_conf_tx,
  1681. .bss_info_changed = ath9k_bss_info_changed,
  1682. .set_key = ath9k_set_key,
  1683. .get_tsf = ath9k_get_tsf,
  1684. .set_tsf = ath9k_set_tsf,
  1685. .reset_tsf = ath9k_reset_tsf,
  1686. .ampdu_action = ath9k_ampdu_action,
  1687. .sw_scan_start = ath9k_sw_scan_start,
  1688. .sw_scan_complete = ath9k_sw_scan_complete,
  1689. .rfkill_poll = ath9k_rfkill_poll_state,
  1690. };