qla_mr.c 91 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <linux/pci.h>
  10. #include <linux/ratelimit.h>
  11. #include <linux/vmalloc.h>
  12. #include <scsi/scsi_tcq.h>
  13. #include <linux/utsname.h>
  14. /* QLAFX00 specific Mailbox implementation functions */
  15. /*
  16. * qlafx00_mailbox_command
  17. * Issue mailbox command and waits for completion.
  18. *
  19. * Input:
  20. * ha = adapter block pointer.
  21. * mcp = driver internal mbx struct pointer.
  22. *
  23. * Output:
  24. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  25. *
  26. * Returns:
  27. * 0 : QLA_SUCCESS = cmd performed success
  28. * 1 : QLA_FUNCTION_FAILED (error encountered)
  29. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  30. *
  31. * Context:
  32. * Kernel context.
  33. */
  34. static int
  35. qlafx00_mailbox_command(scsi_qla_host_t *vha, struct mbx_cmd_32 *mcp)
  36. {
  37. int rval;
  38. unsigned long flags = 0;
  39. device_reg_t __iomem *reg;
  40. uint8_t abort_active;
  41. uint8_t io_lock_on;
  42. uint16_t command = 0;
  43. uint32_t *iptr;
  44. uint32_t __iomem *optr;
  45. uint32_t cnt;
  46. uint32_t mboxes;
  47. unsigned long wait_time;
  48. struct qla_hw_data *ha = vha->hw;
  49. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  50. if (ha->pdev->error_state > pci_channel_io_frozen) {
  51. ql_log(ql_log_warn, vha, 0x115c,
  52. "error_state is greater than pci_channel_io_frozen, "
  53. "exiting.\n");
  54. return QLA_FUNCTION_TIMEOUT;
  55. }
  56. if (vha->device_flags & DFLG_DEV_FAILED) {
  57. ql_log(ql_log_warn, vha, 0x115f,
  58. "Device in failed state, exiting.\n");
  59. return QLA_FUNCTION_TIMEOUT;
  60. }
  61. reg = ha->iobase;
  62. io_lock_on = base_vha->flags.init_done;
  63. rval = QLA_SUCCESS;
  64. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  65. if (ha->flags.pci_channel_io_perm_failure) {
  66. ql_log(ql_log_warn, vha, 0x1175,
  67. "Perm failure on EEH timeout MBX, exiting.\n");
  68. return QLA_FUNCTION_TIMEOUT;
  69. }
  70. if (ha->flags.isp82xx_fw_hung) {
  71. /* Setting Link-Down error */
  72. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  73. ql_log(ql_log_warn, vha, 0x1176,
  74. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  75. rval = QLA_FUNCTION_FAILED;
  76. goto premature_exit;
  77. }
  78. /*
  79. * Wait for active mailbox commands to finish by waiting at most tov
  80. * seconds. This is to serialize actual issuing of mailbox cmds during
  81. * non ISP abort time.
  82. */
  83. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  84. /* Timeout occurred. Return error. */
  85. ql_log(ql_log_warn, vha, 0x1177,
  86. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  87. mcp->mb[0]);
  88. return QLA_FUNCTION_TIMEOUT;
  89. }
  90. ha->flags.mbox_busy = 1;
  91. /* Save mailbox command for debug */
  92. ha->mcp32 = mcp;
  93. ql_dbg(ql_dbg_mbx, vha, 0x1178,
  94. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  95. spin_lock_irqsave(&ha->hardware_lock, flags);
  96. /* Load mailbox registers. */
  97. optr = (uint32_t __iomem *)&reg->ispfx00.mailbox0;
  98. iptr = mcp->mb;
  99. command = mcp->mb[0];
  100. mboxes = mcp->out_mb;
  101. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  102. if (mboxes & BIT_0)
  103. WRT_REG_DWORD(optr, *iptr);
  104. mboxes >>= 1;
  105. optr++;
  106. iptr++;
  107. }
  108. /* Issue set host interrupt command to send cmd out. */
  109. ha->flags.mbox_int = 0;
  110. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  111. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1172,
  112. (uint8_t *)mcp->mb, 16);
  113. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1173,
  114. ((uint8_t *)mcp->mb + 0x10), 16);
  115. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1174,
  116. ((uint8_t *)mcp->mb + 0x20), 8);
  117. /* Unlock mbx registers and wait for interrupt */
  118. ql_dbg(ql_dbg_mbx, vha, 0x1179,
  119. "Going to unlock irq & waiting for interrupts. "
  120. "jiffies=%lx.\n", jiffies);
  121. /* Wait for mbx cmd completion until timeout */
  122. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  123. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  124. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  125. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  126. wait_for_completion_timeout(&ha->mbx_intr_comp, mcp->tov * HZ);
  127. } else {
  128. ql_dbg(ql_dbg_mbx, vha, 0x112c,
  129. "Cmd=%x Polling Mode.\n", command);
  130. QLAFX00_SET_HST_INTR(ha, ha->mbx_intr_code);
  131. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  132. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  133. while (!ha->flags.mbox_int) {
  134. if (time_after(jiffies, wait_time))
  135. break;
  136. /* Check for pending interrupts. */
  137. qla2x00_poll(ha->rsp_q_map[0]);
  138. if (!ha->flags.mbox_int &&
  139. !(IS_QLA2200(ha) &&
  140. command == MBC_LOAD_RISC_RAM_EXTENDED))
  141. usleep_range(10000, 11000);
  142. } /* while */
  143. ql_dbg(ql_dbg_mbx, vha, 0x112d,
  144. "Waited %d sec.\n",
  145. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  146. }
  147. /* Check whether we timed out */
  148. if (ha->flags.mbox_int) {
  149. uint32_t *iptr2;
  150. ql_dbg(ql_dbg_mbx, vha, 0x112e,
  151. "Cmd=%x completed.\n", command);
  152. /* Got interrupt. Clear the flag. */
  153. ha->flags.mbox_int = 0;
  154. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  155. if (ha->mailbox_out32[0] != MBS_COMMAND_COMPLETE)
  156. rval = QLA_FUNCTION_FAILED;
  157. /* Load return mailbox registers. */
  158. iptr2 = mcp->mb;
  159. iptr = (uint32_t *)&ha->mailbox_out32[0];
  160. mboxes = mcp->in_mb;
  161. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  162. if (mboxes & BIT_0)
  163. *iptr2 = *iptr;
  164. mboxes >>= 1;
  165. iptr2++;
  166. iptr++;
  167. }
  168. } else {
  169. rval = QLA_FUNCTION_TIMEOUT;
  170. }
  171. ha->flags.mbox_busy = 0;
  172. /* Clean up */
  173. ha->mcp32 = NULL;
  174. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  175. ql_dbg(ql_dbg_mbx, vha, 0x113a,
  176. "checking for additional resp interrupt.\n");
  177. /* polling mode for non isp_abort commands. */
  178. qla2x00_poll(ha->rsp_q_map[0]);
  179. }
  180. if (rval == QLA_FUNCTION_TIMEOUT &&
  181. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  182. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  183. ha->flags.eeh_busy) {
  184. /* not in dpc. schedule it for dpc to take over. */
  185. ql_dbg(ql_dbg_mbx, vha, 0x115d,
  186. "Timeout, schedule isp_abort_needed.\n");
  187. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  188. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  189. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  190. ql_log(ql_log_info, base_vha, 0x115e,
  191. "Mailbox cmd timeout occurred, cmd=0x%x, "
  192. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  193. "abort.\n", command, mcp->mb[0],
  194. ha->flags.eeh_busy);
  195. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  196. qla2xxx_wake_dpc(vha);
  197. }
  198. } else if (!abort_active) {
  199. /* call abort directly since we are in the DPC thread */
  200. ql_dbg(ql_dbg_mbx, vha, 0x1160,
  201. "Timeout, calling abort_isp.\n");
  202. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  203. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  204. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  205. ql_log(ql_log_info, base_vha, 0x1161,
  206. "Mailbox cmd timeout occurred, cmd=0x%x, "
  207. "mb[0]=0x%x. Scheduling ISP abort ",
  208. command, mcp->mb[0]);
  209. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  210. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  211. if (ha->isp_ops->abort_isp(vha)) {
  212. /* Failed. retry later. */
  213. set_bit(ISP_ABORT_NEEDED,
  214. &vha->dpc_flags);
  215. }
  216. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  217. ql_dbg(ql_dbg_mbx, vha, 0x1162,
  218. "Finished abort_isp.\n");
  219. }
  220. }
  221. }
  222. premature_exit:
  223. /* Allow next mbx cmd to come in. */
  224. complete(&ha->mbx_cmd_comp);
  225. if (rval) {
  226. ql_log(ql_log_warn, base_vha, 0x1163,
  227. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, "
  228. "mb[3]=%x, cmd=%x ****.\n",
  229. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  230. } else {
  231. ql_dbg(ql_dbg_mbx, base_vha, 0x1164, "Done %s.\n", __func__);
  232. }
  233. return rval;
  234. }
  235. /*
  236. * qlafx00_driver_shutdown
  237. * Indicate a driver shutdown to firmware.
  238. *
  239. * Input:
  240. * ha = adapter block pointer.
  241. *
  242. * Returns:
  243. * local function return status code.
  244. *
  245. * Context:
  246. * Kernel context.
  247. */
  248. static int
  249. qlafx00_driver_shutdown(scsi_qla_host_t *vha, int tmo)
  250. {
  251. int rval;
  252. struct mbx_cmd_32 mc;
  253. struct mbx_cmd_32 *mcp = &mc;
  254. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1166,
  255. "Entered %s.\n", __func__);
  256. mcp->mb[0] = MBC_MR_DRV_SHUTDOWN;
  257. mcp->out_mb = MBX_0;
  258. mcp->in_mb = MBX_0;
  259. if (tmo)
  260. mcp->tov = tmo;
  261. else
  262. mcp->tov = MBX_TOV_SECONDS;
  263. mcp->flags = 0;
  264. rval = qlafx00_mailbox_command(vha, mcp);
  265. if (rval != QLA_SUCCESS) {
  266. ql_dbg(ql_dbg_mbx, vha, 0x1167,
  267. "Failed=%x.\n", rval);
  268. } else {
  269. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1168,
  270. "Done %s.\n", __func__);
  271. }
  272. return rval;
  273. }
  274. /*
  275. * qlafx00_get_firmware_state
  276. * Get adapter firmware state.
  277. *
  278. * Input:
  279. * ha = adapter block pointer.
  280. * TARGET_QUEUE_LOCK must be released.
  281. * ADAPTER_STATE_LOCK must be released.
  282. *
  283. * Returns:
  284. * qla7xxx local function return status code.
  285. *
  286. * Context:
  287. * Kernel context.
  288. */
  289. static int
  290. qlafx00_get_firmware_state(scsi_qla_host_t *vha, uint32_t *states)
  291. {
  292. int rval;
  293. struct mbx_cmd_32 mc;
  294. struct mbx_cmd_32 *mcp = &mc;
  295. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1169,
  296. "Entered %s.\n", __func__);
  297. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  298. mcp->out_mb = MBX_0;
  299. mcp->in_mb = MBX_1|MBX_0;
  300. mcp->tov = MBX_TOV_SECONDS;
  301. mcp->flags = 0;
  302. rval = qlafx00_mailbox_command(vha, mcp);
  303. /* Return firmware states. */
  304. states[0] = mcp->mb[1];
  305. if (rval != QLA_SUCCESS) {
  306. ql_dbg(ql_dbg_mbx, vha, 0x116a,
  307. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  308. } else {
  309. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116b,
  310. "Done %s.\n", __func__);
  311. }
  312. return rval;
  313. }
  314. /*
  315. * qlafx00_init_firmware
  316. * Initialize adapter firmware.
  317. *
  318. * Input:
  319. * ha = adapter block pointer.
  320. * dptr = Initialization control block pointer.
  321. * size = size of initialization control block.
  322. * TARGET_QUEUE_LOCK must be released.
  323. * ADAPTER_STATE_LOCK must be released.
  324. *
  325. * Returns:
  326. * qlafx00 local function return status code.
  327. *
  328. * Context:
  329. * Kernel context.
  330. */
  331. int
  332. qlafx00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  333. {
  334. int rval;
  335. struct mbx_cmd_32 mc;
  336. struct mbx_cmd_32 *mcp = &mc;
  337. struct qla_hw_data *ha = vha->hw;
  338. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116c,
  339. "Entered %s.\n", __func__);
  340. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  341. mcp->mb[1] = 0;
  342. mcp->mb[2] = MSD(ha->init_cb_dma);
  343. mcp->mb[3] = LSD(ha->init_cb_dma);
  344. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  345. mcp->in_mb = MBX_0;
  346. mcp->buf_size = size;
  347. mcp->flags = MBX_DMA_OUT;
  348. mcp->tov = MBX_TOV_SECONDS;
  349. rval = qlafx00_mailbox_command(vha, mcp);
  350. if (rval != QLA_SUCCESS) {
  351. ql_dbg(ql_dbg_mbx, vha, 0x116d,
  352. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  353. } else {
  354. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116e,
  355. "Done %s.\n", __func__);
  356. }
  357. return rval;
  358. }
  359. /*
  360. * qlafx00_mbx_reg_test
  361. */
  362. static int
  363. qlafx00_mbx_reg_test(scsi_qla_host_t *vha)
  364. {
  365. int rval;
  366. struct mbx_cmd_32 mc;
  367. struct mbx_cmd_32 *mcp = &mc;
  368. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x116f,
  369. "Entered %s.\n", __func__);
  370. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  371. mcp->mb[1] = 0xAAAA;
  372. mcp->mb[2] = 0x5555;
  373. mcp->mb[3] = 0xAA55;
  374. mcp->mb[4] = 0x55AA;
  375. mcp->mb[5] = 0xA5A5;
  376. mcp->mb[6] = 0x5A5A;
  377. mcp->mb[7] = 0x2525;
  378. mcp->mb[8] = 0xBBBB;
  379. mcp->mb[9] = 0x6666;
  380. mcp->mb[10] = 0xBB66;
  381. mcp->mb[11] = 0x66BB;
  382. mcp->mb[12] = 0xB6B6;
  383. mcp->mb[13] = 0x6B6B;
  384. mcp->mb[14] = 0x3636;
  385. mcp->mb[15] = 0xCCCC;
  386. mcp->out_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  387. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  388. mcp->in_mb = MBX_15|MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  389. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  390. mcp->buf_size = 0;
  391. mcp->flags = MBX_DMA_OUT;
  392. mcp->tov = MBX_TOV_SECONDS;
  393. rval = qlafx00_mailbox_command(vha, mcp);
  394. if (rval == QLA_SUCCESS) {
  395. if (mcp->mb[17] != 0xAAAA || mcp->mb[18] != 0x5555 ||
  396. mcp->mb[19] != 0xAA55 || mcp->mb[20] != 0x55AA)
  397. rval = QLA_FUNCTION_FAILED;
  398. if (mcp->mb[21] != 0xA5A5 || mcp->mb[22] != 0x5A5A ||
  399. mcp->mb[23] != 0x2525 || mcp->mb[24] != 0xBBBB)
  400. rval = QLA_FUNCTION_FAILED;
  401. if (mcp->mb[25] != 0x6666 || mcp->mb[26] != 0xBB66 ||
  402. mcp->mb[27] != 0x66BB || mcp->mb[28] != 0xB6B6)
  403. rval = QLA_FUNCTION_FAILED;
  404. if (mcp->mb[29] != 0x6B6B || mcp->mb[30] != 0x3636 ||
  405. mcp->mb[31] != 0xCCCC)
  406. rval = QLA_FUNCTION_FAILED;
  407. }
  408. if (rval != QLA_SUCCESS) {
  409. ql_dbg(ql_dbg_mbx, vha, 0x1170,
  410. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  411. } else {
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1171,
  413. "Done %s.\n", __func__);
  414. }
  415. return rval;
  416. }
  417. /**
  418. * qlafx00_pci_config() - Setup ISPFx00 PCI configuration registers.
  419. * @ha: HA context
  420. *
  421. * Returns 0 on success.
  422. */
  423. int
  424. qlafx00_pci_config(scsi_qla_host_t *vha)
  425. {
  426. uint16_t w;
  427. struct qla_hw_data *ha = vha->hw;
  428. pci_set_master(ha->pdev);
  429. pci_try_set_mwi(ha->pdev);
  430. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  431. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  432. w &= ~PCI_COMMAND_INTX_DISABLE;
  433. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  434. /* PCIe -- adjust Maximum Read Request Size (2048). */
  435. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  436. pcie_set_readrq(ha->pdev, 2048);
  437. ha->chip_revision = ha->pdev->revision;
  438. return QLA_SUCCESS;
  439. }
  440. /**
  441. * qlafx00_warm_reset() - Perform warm reset of iSA(CPUs being reset on SOC).
  442. * @ha: HA context
  443. *
  444. */
  445. static inline void
  446. qlafx00_soc_cpu_reset(scsi_qla_host_t *vha)
  447. {
  448. unsigned long flags = 0;
  449. struct qla_hw_data *ha = vha->hw;
  450. int i, core;
  451. uint32_t cnt;
  452. /* Set all 4 cores in reset */
  453. for (i = 0; i < 4; i++) {
  454. QLAFX00_SET_HBA_SOC_REG(ha,
  455. (SOC_SW_RST_CONTROL_REG_CORE0 + 8*i), (0xF01));
  456. }
  457. /* Set all 4 core Clock gating control */
  458. for (i = 0; i < 4; i++) {
  459. QLAFX00_SET_HBA_SOC_REG(ha,
  460. (SOC_SW_RST_CONTROL_REG_CORE0 + 4 + 8*i), (0x01010101));
  461. }
  462. /* Reset all units in Fabric */
  463. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x11F0101));
  464. /* Reset all interrupt control registers */
  465. for (i = 0; i < 115; i++) {
  466. QLAFX00_SET_HBA_SOC_REG(ha,
  467. (SOC_INTERRUPT_SOURCE_I_CONTROL_REG + 4*i), (0x0));
  468. }
  469. /* Reset Timers control registers. per core */
  470. for (core = 0; core < 4; core++)
  471. for (i = 0; i < 8; i++)
  472. QLAFX00_SET_HBA_SOC_REG(ha,
  473. (SOC_CORE_TIMER_REG + 0x100*core + 4*i), (0x0));
  474. /* Reset per core IRQ ack register */
  475. for (core = 0; core < 4; core++)
  476. QLAFX00_SET_HBA_SOC_REG(ha,
  477. (SOC_IRQ_ACK_REG + 0x100*core), (0x3FF));
  478. /* Set Fabric control and config to defaults */
  479. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONTROL_REG, (0x2));
  480. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_CONFIG_REG, (0x3));
  481. spin_lock_irqsave(&ha->hardware_lock, flags);
  482. /* Kick in Fabric units */
  483. QLAFX00_SET_HBA_SOC_REG(ha, SOC_FABRIC_RST_CONTROL_REG, (0x0));
  484. /* Kick in Core0 to start boot process */
  485. QLAFX00_SET_HBA_SOC_REG(ha, SOC_SW_RST_CONTROL_REG_CORE0, (0xF00));
  486. /* Wait 10secs for soft-reset to complete. */
  487. for (cnt = 10; cnt; cnt--) {
  488. msleep(1000);
  489. barrier();
  490. }
  491. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  492. }
  493. /**
  494. * qlafx00_soft_reset() - Soft Reset ISPFx00.
  495. * @ha: HA context
  496. *
  497. * Returns 0 on success.
  498. */
  499. void
  500. qlafx00_soft_reset(scsi_qla_host_t *vha)
  501. {
  502. struct qla_hw_data *ha = vha->hw;
  503. if (unlikely(pci_channel_offline(ha->pdev) &&
  504. ha->flags.pci_channel_io_perm_failure))
  505. return;
  506. ha->isp_ops->disable_intrs(ha);
  507. qlafx00_soc_cpu_reset(vha);
  508. ha->isp_ops->enable_intrs(ha);
  509. }
  510. /**
  511. * qlafx00_chip_diag() - Test ISPFx00 for proper operation.
  512. * @ha: HA context
  513. *
  514. * Returns 0 on success.
  515. */
  516. int
  517. qlafx00_chip_diag(scsi_qla_host_t *vha)
  518. {
  519. int rval = 0;
  520. struct qla_hw_data *ha = vha->hw;
  521. struct req_que *req = ha->req_q_map[0];
  522. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  523. rval = qlafx00_mbx_reg_test(vha);
  524. if (rval) {
  525. ql_log(ql_log_warn, vha, 0x1165,
  526. "Failed mailbox send register test\n");
  527. } else {
  528. /* Flag a successful rval */
  529. rval = QLA_SUCCESS;
  530. }
  531. return rval;
  532. }
  533. void
  534. qlafx00_config_rings(struct scsi_qla_host *vha)
  535. {
  536. struct qla_hw_data *ha = vha->hw;
  537. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  538. struct init_cb_fx *icb;
  539. struct req_que *req = ha->req_q_map[0];
  540. struct rsp_que *rsp = ha->rsp_q_map[0];
  541. /* Setup ring parameters in initialization control block. */
  542. icb = (struct init_cb_fx *)ha->init_cb;
  543. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  544. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  545. icb->request_q_length = cpu_to_le16(req->length);
  546. icb->response_q_length = cpu_to_le16(rsp->length);
  547. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  548. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  549. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  550. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  551. WRT_REG_DWORD(&reg->req_q_in, 0);
  552. WRT_REG_DWORD(&reg->req_q_out, 0);
  553. WRT_REG_DWORD(&reg->rsp_q_in, 0);
  554. WRT_REG_DWORD(&reg->rsp_q_out, 0);
  555. /* PCI posting */
  556. RD_REG_DWORD(&reg->rsp_q_out);
  557. }
  558. char *
  559. qlafx00_pci_info_str(struct scsi_qla_host *vha, char *str)
  560. {
  561. struct qla_hw_data *ha = vha->hw;
  562. int pcie_reg;
  563. pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP);
  564. if (pcie_reg) {
  565. strcpy(str, "PCIe iSA");
  566. return str;
  567. }
  568. return str;
  569. }
  570. char *
  571. qlafx00_fw_version_str(struct scsi_qla_host *vha, char *str)
  572. {
  573. struct qla_hw_data *ha = vha->hw;
  574. sprintf(str, "%s", ha->mr.fw_version);
  575. return str;
  576. }
  577. void
  578. qlafx00_enable_intrs(struct qla_hw_data *ha)
  579. {
  580. unsigned long flags = 0;
  581. spin_lock_irqsave(&ha->hardware_lock, flags);
  582. ha->interrupts_on = 1;
  583. QLAFX00_ENABLE_ICNTRL_REG(ha);
  584. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  585. }
  586. void
  587. qlafx00_disable_intrs(struct qla_hw_data *ha)
  588. {
  589. unsigned long flags = 0;
  590. spin_lock_irqsave(&ha->hardware_lock, flags);
  591. ha->interrupts_on = 0;
  592. QLAFX00_DISABLE_ICNTRL_REG(ha);
  593. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  594. }
  595. static void
  596. qlafx00_tmf_iocb_timeout(void *data)
  597. {
  598. srb_t *sp = (srb_t *)data;
  599. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  600. tmf->u.tmf.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  601. complete(&tmf->u.tmf.comp);
  602. }
  603. static void
  604. qlafx00_tmf_sp_done(void *data, void *ptr, int res)
  605. {
  606. srb_t *sp = (srb_t *)ptr;
  607. struct srb_iocb *tmf = &sp->u.iocb_cmd;
  608. complete(&tmf->u.tmf.comp);
  609. }
  610. static int
  611. qlafx00_async_tm_cmd(fc_port_t *fcport, uint32_t flags,
  612. uint32_t lun, uint32_t tag)
  613. {
  614. scsi_qla_host_t *vha = fcport->vha;
  615. struct srb_iocb *tm_iocb;
  616. srb_t *sp;
  617. int rval = QLA_FUNCTION_FAILED;
  618. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  619. if (!sp)
  620. goto done;
  621. tm_iocb = &sp->u.iocb_cmd;
  622. sp->type = SRB_TM_CMD;
  623. sp->name = "tmf";
  624. qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
  625. tm_iocb->u.tmf.flags = flags;
  626. tm_iocb->u.tmf.lun = lun;
  627. tm_iocb->u.tmf.data = tag;
  628. sp->done = qlafx00_tmf_sp_done;
  629. tm_iocb->timeout = qlafx00_tmf_iocb_timeout;
  630. init_completion(&tm_iocb->u.tmf.comp);
  631. rval = qla2x00_start_sp(sp);
  632. if (rval != QLA_SUCCESS)
  633. goto done_free_sp;
  634. ql_dbg(ql_dbg_async, vha, 0x507b,
  635. "Task management command issued target_id=%x\n",
  636. fcport->tgt_id);
  637. wait_for_completion(&tm_iocb->u.tmf.comp);
  638. rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
  639. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  640. done_free_sp:
  641. sp->free(vha, sp);
  642. done:
  643. return rval;
  644. }
  645. int
  646. qlafx00_abort_target(fc_port_t *fcport, unsigned int l, int tag)
  647. {
  648. return qlafx00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  649. }
  650. int
  651. qlafx00_lun_reset(fc_port_t *fcport, unsigned int l, int tag)
  652. {
  653. return qlafx00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  654. }
  655. int
  656. qlafx00_loop_reset(scsi_qla_host_t *vha)
  657. {
  658. int ret;
  659. struct fc_port *fcport;
  660. struct qla_hw_data *ha = vha->hw;
  661. if (ql2xtargetreset) {
  662. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  663. if (fcport->port_type != FCT_TARGET)
  664. continue;
  665. ret = ha->isp_ops->target_reset(fcport, 0, 0);
  666. if (ret != QLA_SUCCESS) {
  667. ql_dbg(ql_dbg_taskm, vha, 0x803d,
  668. "Bus Reset failed: Reset=%d "
  669. "d_id=%x.\n", ret, fcport->d_id.b24);
  670. }
  671. }
  672. }
  673. return QLA_SUCCESS;
  674. }
  675. int
  676. qlafx00_iospace_config(struct qla_hw_data *ha)
  677. {
  678. if (pci_request_selected_regions(ha->pdev, ha->bars,
  679. QLA2XXX_DRIVER_NAME)) {
  680. ql_log_pci(ql_log_fatal, ha->pdev, 0x014e,
  681. "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
  682. pci_name(ha->pdev));
  683. goto iospace_error_exit;
  684. }
  685. /* Use MMIO operations for all accesses. */
  686. if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
  687. ql_log_pci(ql_log_warn, ha->pdev, 0x014f,
  688. "Invalid pci I/O region size (%s).\n",
  689. pci_name(ha->pdev));
  690. goto iospace_error_exit;
  691. }
  692. if (pci_resource_len(ha->pdev, 0) < BAR0_LEN_FX00) {
  693. ql_log_pci(ql_log_warn, ha->pdev, 0x0127,
  694. "Invalid PCI mem BAR0 region size (%s), aborting\n",
  695. pci_name(ha->pdev));
  696. goto iospace_error_exit;
  697. }
  698. ha->cregbase =
  699. ioremap_nocache(pci_resource_start(ha->pdev, 0), BAR0_LEN_FX00);
  700. if (!ha->cregbase) {
  701. ql_log_pci(ql_log_fatal, ha->pdev, 0x0128,
  702. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  703. goto iospace_error_exit;
  704. }
  705. if (!(pci_resource_flags(ha->pdev, 2) & IORESOURCE_MEM)) {
  706. ql_log_pci(ql_log_warn, ha->pdev, 0x0129,
  707. "region #2 not an MMIO resource (%s), aborting\n",
  708. pci_name(ha->pdev));
  709. goto iospace_error_exit;
  710. }
  711. if (pci_resource_len(ha->pdev, 2) < BAR2_LEN_FX00) {
  712. ql_log_pci(ql_log_warn, ha->pdev, 0x012a,
  713. "Invalid PCI mem BAR2 region size (%s), aborting\n",
  714. pci_name(ha->pdev));
  715. goto iospace_error_exit;
  716. }
  717. ha->iobase =
  718. ioremap_nocache(pci_resource_start(ha->pdev, 2), BAR2_LEN_FX00);
  719. if (!ha->iobase) {
  720. ql_log_pci(ql_log_fatal, ha->pdev, 0x012b,
  721. "cannot remap MMIO (%s), aborting\n", pci_name(ha->pdev));
  722. goto iospace_error_exit;
  723. }
  724. /* Determine queue resources */
  725. ha->max_req_queues = ha->max_rsp_queues = 1;
  726. ql_log_pci(ql_log_info, ha->pdev, 0x012c,
  727. "Bars 0x%x, iobase0 0x%p, iobase2 0x%p\n",
  728. ha->bars, ha->cregbase, ha->iobase);
  729. return 0;
  730. iospace_error_exit:
  731. return -ENOMEM;
  732. }
  733. static void
  734. qlafx00_save_queue_ptrs(struct scsi_qla_host *vha)
  735. {
  736. struct qla_hw_data *ha = vha->hw;
  737. struct req_que *req = ha->req_q_map[0];
  738. struct rsp_que *rsp = ha->rsp_q_map[0];
  739. req->length_fx00 = req->length;
  740. req->ring_fx00 = req->ring;
  741. req->dma_fx00 = req->dma;
  742. rsp->length_fx00 = rsp->length;
  743. rsp->ring_fx00 = rsp->ring;
  744. rsp->dma_fx00 = rsp->dma;
  745. ql_dbg(ql_dbg_init, vha, 0x012d,
  746. "req: %p, ring_fx00: %p, length_fx00: 0x%x,"
  747. "req->dma_fx00: 0x%llx\n", req, req->ring_fx00,
  748. req->length_fx00, (u64)req->dma_fx00);
  749. ql_dbg(ql_dbg_init, vha, 0x012e,
  750. "rsp: %p, ring_fx00: %p, length_fx00: 0x%x,"
  751. "rsp->dma_fx00: 0x%llx\n", rsp, rsp->ring_fx00,
  752. rsp->length_fx00, (u64)rsp->dma_fx00);
  753. }
  754. static int
  755. qlafx00_config_queues(struct scsi_qla_host *vha)
  756. {
  757. struct qla_hw_data *ha = vha->hw;
  758. struct req_que *req = ha->req_q_map[0];
  759. struct rsp_que *rsp = ha->rsp_q_map[0];
  760. dma_addr_t bar2_hdl = pci_resource_start(ha->pdev, 2);
  761. req->length = ha->req_que_len;
  762. req->ring = (void *)ha->iobase + ha->req_que_off;
  763. req->dma = bar2_hdl + ha->req_que_off;
  764. if ((!req->ring) || (req->length == 0)) {
  765. ql_log_pci(ql_log_info, ha->pdev, 0x012f,
  766. "Unable to allocate memory for req_ring\n");
  767. return QLA_FUNCTION_FAILED;
  768. }
  769. ql_dbg(ql_dbg_init, vha, 0x0130,
  770. "req: %p req_ring pointer %p req len 0x%x "
  771. "req off 0x%x\n, req->dma: 0x%llx",
  772. req, req->ring, req->length,
  773. ha->req_que_off, (u64)req->dma);
  774. rsp->length = ha->rsp_que_len;
  775. rsp->ring = (void *)ha->iobase + ha->rsp_que_off;
  776. rsp->dma = bar2_hdl + ha->rsp_que_off;
  777. if ((!rsp->ring) || (rsp->length == 0)) {
  778. ql_log_pci(ql_log_info, ha->pdev, 0x0131,
  779. "Unable to allocate memory for rsp_ring\n");
  780. return QLA_FUNCTION_FAILED;
  781. }
  782. ql_dbg(ql_dbg_init, vha, 0x0132,
  783. "rsp: %p rsp_ring pointer %p rsp len 0x%x "
  784. "rsp off 0x%x, rsp->dma: 0x%llx\n",
  785. rsp, rsp->ring, rsp->length,
  786. ha->rsp_que_off, (u64)rsp->dma);
  787. return QLA_SUCCESS;
  788. }
  789. static int
  790. qlafx00_init_fw_ready(scsi_qla_host_t *vha)
  791. {
  792. int rval = 0;
  793. unsigned long wtime;
  794. uint16_t wait_time; /* Wait time */
  795. struct qla_hw_data *ha = vha->hw;
  796. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  797. uint32_t aenmbx, aenmbx7 = 0;
  798. uint32_t state[5];
  799. bool done = false;
  800. /* 30 seconds wait - Adjust if required */
  801. wait_time = 30;
  802. /* wait time before firmware ready */
  803. wtime = jiffies + (wait_time * HZ);
  804. do {
  805. aenmbx = RD_REG_DWORD(&reg->aenmailbox0);
  806. barrier();
  807. ql_dbg(ql_dbg_mbx, vha, 0x0133,
  808. "aenmbx: 0x%x\n", aenmbx);
  809. switch (aenmbx) {
  810. case MBA_FW_NOT_STARTED:
  811. case MBA_FW_STARTING:
  812. break;
  813. case MBA_SYSTEM_ERR:
  814. case MBA_REQ_TRANSFER_ERR:
  815. case MBA_RSP_TRANSFER_ERR:
  816. case MBA_FW_INIT_FAILURE:
  817. qlafx00_soft_reset(vha);
  818. break;
  819. case MBA_FW_RESTART_CMPLT:
  820. /* Set the mbx and rqstq intr code */
  821. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  822. ha->mbx_intr_code = MSW(aenmbx7);
  823. ha->rqstq_intr_code = LSW(aenmbx7);
  824. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  825. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  826. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  827. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  828. WRT_REG_DWORD(&reg->aenmailbox0, 0);
  829. RD_REG_DWORD_RELAXED(&reg->aenmailbox0);
  830. ql_dbg(ql_dbg_init, vha, 0x0134,
  831. "f/w returned mbx_intr_code: 0x%x, "
  832. "rqstq_intr_code: 0x%x\n",
  833. ha->mbx_intr_code, ha->rqstq_intr_code);
  834. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  835. rval = QLA_SUCCESS;
  836. done = true;
  837. break;
  838. default:
  839. /* If fw is apparently not ready. In order to continue,
  840. * we might need to issue Mbox cmd, but the problem is
  841. * that the DoorBell vector values that come with the
  842. * 8060 AEN are most likely gone by now (and thus no
  843. * bell would be rung on the fw side when mbox cmd is
  844. * issued). We have to therefore grab the 8060 AEN
  845. * shadow regs (filled in by FW when the last 8060
  846. * AEN was being posted).
  847. * Do the following to determine what is needed in
  848. * order to get the FW ready:
  849. * 1. reload the 8060 AEN values from the shadow regs
  850. * 2. clear int status to get rid of possible pending
  851. * interrupts
  852. * 3. issue Get FW State Mbox cmd to determine fw state
  853. * Set the mbx and rqstq intr code from Shadow Regs
  854. */
  855. aenmbx7 = RD_REG_DWORD(&reg->initval7);
  856. ha->mbx_intr_code = MSW(aenmbx7);
  857. ha->rqstq_intr_code = LSW(aenmbx7);
  858. ha->req_que_off = RD_REG_DWORD(&reg->initval1);
  859. ha->rsp_que_off = RD_REG_DWORD(&reg->initval3);
  860. ha->req_que_len = RD_REG_DWORD(&reg->initval5);
  861. ha->rsp_que_len = RD_REG_DWORD(&reg->initval6);
  862. ql_dbg(ql_dbg_init, vha, 0x0135,
  863. "f/w returned mbx_intr_code: 0x%x, "
  864. "rqstq_intr_code: 0x%x\n",
  865. ha->mbx_intr_code, ha->rqstq_intr_code);
  866. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  867. /* Get the FW state */
  868. rval = qlafx00_get_firmware_state(vha, state);
  869. if (rval != QLA_SUCCESS) {
  870. /* Retry if timer has not expired */
  871. break;
  872. }
  873. if (state[0] == FSTATE_FX00_CONFIG_WAIT) {
  874. /* Firmware is waiting to be
  875. * initialized by driver
  876. */
  877. rval = QLA_SUCCESS;
  878. done = true;
  879. break;
  880. }
  881. /* Issue driver shutdown and wait until f/w recovers.
  882. * Driver should continue to poll until 8060 AEN is
  883. * received indicating firmware recovery.
  884. */
  885. ql_dbg(ql_dbg_init, vha, 0x0136,
  886. "Sending Driver shutdown fw_state 0x%x\n",
  887. state[0]);
  888. rval = qlafx00_driver_shutdown(vha, 10);
  889. if (rval != QLA_SUCCESS) {
  890. rval = QLA_FUNCTION_FAILED;
  891. break;
  892. }
  893. msleep(500);
  894. wtime = jiffies + (wait_time * HZ);
  895. break;
  896. }
  897. if (!done) {
  898. if (time_after_eq(jiffies, wtime)) {
  899. ql_dbg(ql_dbg_init, vha, 0x0137,
  900. "Init f/w failed: aen[7]: 0x%x\n",
  901. RD_REG_DWORD(&reg->aenmailbox7));
  902. rval = QLA_FUNCTION_FAILED;
  903. done = true;
  904. break;
  905. }
  906. /* Delay for a while */
  907. msleep(500);
  908. }
  909. } while (!done);
  910. if (rval)
  911. ql_dbg(ql_dbg_init, vha, 0x0138,
  912. "%s **** FAILED ****.\n", __func__);
  913. else
  914. ql_dbg(ql_dbg_init, vha, 0x0139,
  915. "%s **** SUCCESS ****.\n", __func__);
  916. return rval;
  917. }
  918. /*
  919. * qlafx00_fw_ready() - Waits for firmware ready.
  920. * @ha: HA context
  921. *
  922. * Returns 0 on success.
  923. */
  924. int
  925. qlafx00_fw_ready(scsi_qla_host_t *vha)
  926. {
  927. int rval;
  928. unsigned long wtime;
  929. uint16_t wait_time; /* Wait time if loop is coming ready */
  930. uint32_t state[5];
  931. rval = QLA_SUCCESS;
  932. wait_time = 10;
  933. /* wait time before firmware ready */
  934. wtime = jiffies + (wait_time * HZ);
  935. /* Wait for ISP to finish init */
  936. if (!vha->flags.init_done)
  937. ql_dbg(ql_dbg_init, vha, 0x013a,
  938. "Waiting for init to complete...\n");
  939. do {
  940. rval = qlafx00_get_firmware_state(vha, state);
  941. if (rval == QLA_SUCCESS) {
  942. if (state[0] == FSTATE_FX00_INITIALIZED) {
  943. ql_dbg(ql_dbg_init, vha, 0x013b,
  944. "fw_state=%x\n", state[0]);
  945. rval = QLA_SUCCESS;
  946. break;
  947. }
  948. }
  949. rval = QLA_FUNCTION_FAILED;
  950. if (time_after_eq(jiffies, wtime))
  951. break;
  952. /* Delay for a while */
  953. msleep(500);
  954. ql_dbg(ql_dbg_init, vha, 0x013c,
  955. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  956. } while (1);
  957. if (rval)
  958. ql_dbg(ql_dbg_init, vha, 0x013d,
  959. "Firmware ready **** FAILED ****.\n");
  960. else
  961. ql_dbg(ql_dbg_init, vha, 0x013e,
  962. "Firmware ready **** SUCCESS ****.\n");
  963. return rval;
  964. }
  965. static int
  966. qlafx00_find_all_targets(scsi_qla_host_t *vha,
  967. struct list_head *new_fcports)
  968. {
  969. int rval;
  970. uint16_t tgt_id;
  971. fc_port_t *fcport, *new_fcport;
  972. int found;
  973. struct qla_hw_data *ha = vha->hw;
  974. rval = QLA_SUCCESS;
  975. if (!test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
  976. return QLA_FUNCTION_FAILED;
  977. if ((atomic_read(&vha->loop_down_timer) ||
  978. STATE_TRANSITION(vha))) {
  979. atomic_set(&vha->loop_down_timer, 0);
  980. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  981. return QLA_FUNCTION_FAILED;
  982. }
  983. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x2088,
  984. "Listing Target bit map...\n");
  985. ql_dump_buffer(ql_dbg_disc + ql_dbg_init, vha,
  986. 0x2089, (uint8_t *)ha->gid_list, 32);
  987. /* Allocate temporary rmtport for any new rmtports discovered. */
  988. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  989. if (new_fcport == NULL)
  990. return QLA_MEMORY_ALLOC_FAILED;
  991. for_each_set_bit(tgt_id, (void *)ha->gid_list,
  992. QLAFX00_TGT_NODE_LIST_SIZE) {
  993. /* Send get target node info */
  994. new_fcport->tgt_id = tgt_id;
  995. rval = qlafx00_fx_disc(vha, new_fcport,
  996. FXDISC_GET_TGT_NODE_INFO);
  997. if (rval != QLA_SUCCESS) {
  998. ql_log(ql_log_warn, vha, 0x208a,
  999. "Target info scan failed -- assuming zero-entry "
  1000. "result...\n");
  1001. continue;
  1002. }
  1003. /* Locate matching device in database. */
  1004. found = 0;
  1005. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1006. if (memcmp(new_fcport->port_name,
  1007. fcport->port_name, WWN_SIZE))
  1008. continue;
  1009. found++;
  1010. /*
  1011. * If tgt_id is same and state FCS_ONLINE, nothing
  1012. * changed.
  1013. */
  1014. if (fcport->tgt_id == new_fcport->tgt_id &&
  1015. atomic_read(&fcport->state) == FCS_ONLINE)
  1016. break;
  1017. /*
  1018. * Tgt ID changed or device was marked to be updated.
  1019. */
  1020. ql_dbg(ql_dbg_disc + ql_dbg_init, vha, 0x208b,
  1021. "TGT-ID Change(%s): Present tgt id: "
  1022. "0x%x state: 0x%x "
  1023. "wwnn = %llx wwpn = %llx.\n",
  1024. __func__, fcport->tgt_id,
  1025. atomic_read(&fcport->state),
  1026. (unsigned long long)wwn_to_u64(fcport->node_name),
  1027. (unsigned long long)wwn_to_u64(fcport->port_name));
  1028. ql_log(ql_log_info, vha, 0x208c,
  1029. "TGT-ID Announce(%s): Discovered tgt "
  1030. "id 0x%x wwnn = %llx "
  1031. "wwpn = %llx.\n", __func__, new_fcport->tgt_id,
  1032. (unsigned long long)
  1033. wwn_to_u64(new_fcport->node_name),
  1034. (unsigned long long)
  1035. wwn_to_u64(new_fcport->port_name));
  1036. if (atomic_read(&fcport->state) != FCS_ONLINE) {
  1037. fcport->old_tgt_id = fcport->tgt_id;
  1038. fcport->tgt_id = new_fcport->tgt_id;
  1039. ql_log(ql_log_info, vha, 0x208d,
  1040. "TGT-ID: New fcport Added: %p\n", fcport);
  1041. qla2x00_update_fcport(vha, fcport);
  1042. } else {
  1043. ql_log(ql_log_info, vha, 0x208e,
  1044. " Existing TGT-ID %x did not get "
  1045. " offline event from firmware.\n",
  1046. fcport->old_tgt_id);
  1047. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1048. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1049. kfree(new_fcport);
  1050. return rval;
  1051. }
  1052. break;
  1053. }
  1054. if (found)
  1055. continue;
  1056. /* If device was not in our fcports list, then add it. */
  1057. list_add_tail(&new_fcport->list, new_fcports);
  1058. /* Allocate a new replacement fcport. */
  1059. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  1060. if (new_fcport == NULL)
  1061. return QLA_MEMORY_ALLOC_FAILED;
  1062. }
  1063. kfree(new_fcport);
  1064. return rval;
  1065. }
  1066. /*
  1067. * qlafx00_configure_all_targets
  1068. * Setup target devices with node ID's.
  1069. *
  1070. * Input:
  1071. * ha = adapter block pointer.
  1072. *
  1073. * Returns:
  1074. * 0 = success.
  1075. * BIT_0 = error
  1076. */
  1077. static int
  1078. qlafx00_configure_all_targets(scsi_qla_host_t *vha)
  1079. {
  1080. int rval;
  1081. fc_port_t *fcport, *rmptemp;
  1082. LIST_HEAD(new_fcports);
  1083. rval = qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
  1084. FXDISC_GET_TGT_NODE_LIST);
  1085. if (rval != QLA_SUCCESS) {
  1086. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1087. return rval;
  1088. }
  1089. rval = qlafx00_find_all_targets(vha, &new_fcports);
  1090. if (rval != QLA_SUCCESS) {
  1091. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1092. return rval;
  1093. }
  1094. /*
  1095. * Delete all previous devices marked lost.
  1096. */
  1097. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1098. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1099. break;
  1100. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  1101. if (fcport->port_type != FCT_INITIATOR)
  1102. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1103. }
  1104. }
  1105. /*
  1106. * Add the new devices to our devices list.
  1107. */
  1108. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1109. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  1110. break;
  1111. qla2x00_update_fcport(vha, fcport);
  1112. list_move_tail(&fcport->list, &vha->vp_fcports);
  1113. ql_log(ql_log_info, vha, 0x208f,
  1114. "Attach new target id 0x%x wwnn = %llx "
  1115. "wwpn = %llx.\n",
  1116. fcport->tgt_id,
  1117. (unsigned long long)wwn_to_u64(fcport->node_name),
  1118. (unsigned long long)wwn_to_u64(fcport->port_name));
  1119. }
  1120. /* Free all new device structures not processed. */
  1121. list_for_each_entry_safe(fcport, rmptemp, &new_fcports, list) {
  1122. list_del(&fcport->list);
  1123. kfree(fcport);
  1124. }
  1125. return rval;
  1126. }
  1127. /*
  1128. * qlafx00_configure_devices
  1129. * Updates Fibre Channel Device Database with what is actually on loop.
  1130. *
  1131. * Input:
  1132. * ha = adapter block pointer.
  1133. *
  1134. * Returns:
  1135. * 0 = success.
  1136. * 1 = error.
  1137. * 2 = database was full and device was not configured.
  1138. */
  1139. int
  1140. qlafx00_configure_devices(scsi_qla_host_t *vha)
  1141. {
  1142. int rval;
  1143. unsigned long flags, save_flags;
  1144. rval = QLA_SUCCESS;
  1145. save_flags = flags = vha->dpc_flags;
  1146. ql_dbg(ql_dbg_disc, vha, 0x2090,
  1147. "Configure devices -- dpc flags =0x%lx\n", flags);
  1148. rval = qlafx00_configure_all_targets(vha);
  1149. if (rval == QLA_SUCCESS) {
  1150. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  1151. rval = QLA_FUNCTION_FAILED;
  1152. } else {
  1153. atomic_set(&vha->loop_state, LOOP_READY);
  1154. ql_log(ql_log_info, vha, 0x2091,
  1155. "Device Ready\n");
  1156. }
  1157. }
  1158. if (rval) {
  1159. ql_dbg(ql_dbg_disc, vha, 0x2092,
  1160. "%s *** FAILED ***.\n", __func__);
  1161. } else {
  1162. ql_dbg(ql_dbg_disc, vha, 0x2093,
  1163. "%s: exiting normally.\n", __func__);
  1164. }
  1165. return rval;
  1166. }
  1167. static void
  1168. qlafx00_abort_isp_cleanup(scsi_qla_host_t *vha)
  1169. {
  1170. struct qla_hw_data *ha = vha->hw;
  1171. fc_port_t *fcport;
  1172. vha->flags.online = 0;
  1173. ha->flags.chip_reset_done = 0;
  1174. ha->mr.fw_hbt_en = 0;
  1175. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1176. vha->qla_stats.total_isp_aborts++;
  1177. ql_log(ql_log_info, vha, 0x013f,
  1178. "Performing ISP error recovery - ha = %p.\n", ha);
  1179. ha->isp_ops->reset_chip(vha);
  1180. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  1181. atomic_set(&vha->loop_state, LOOP_DOWN);
  1182. atomic_set(&vha->loop_down_timer,
  1183. QLAFX00_LOOP_DOWN_TIME);
  1184. } else {
  1185. if (!atomic_read(&vha->loop_down_timer))
  1186. atomic_set(&vha->loop_down_timer,
  1187. QLAFX00_LOOP_DOWN_TIME);
  1188. }
  1189. /* Clear all async request states across all VPs. */
  1190. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1191. fcport->flags = 0;
  1192. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1193. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  1194. }
  1195. if (!ha->flags.eeh_busy) {
  1196. /* Requeue all commands in outstanding command list. */
  1197. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  1198. }
  1199. qla2x00_free_irqs(vha);
  1200. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1201. /* Clear the Interrupts */
  1202. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1203. ql_log(ql_log_info, vha, 0x0140,
  1204. "%s Done done - ha=%p.\n", __func__, ha);
  1205. }
  1206. /**
  1207. * qlafx00_init_response_q_entries() - Initializes response queue entries.
  1208. * @ha: HA context
  1209. *
  1210. * Beginning of request ring has initialization control block already built
  1211. * by nvram config routine.
  1212. *
  1213. * Returns 0 on success.
  1214. */
  1215. void
  1216. qlafx00_init_response_q_entries(struct rsp_que *rsp)
  1217. {
  1218. uint16_t cnt;
  1219. response_t *pkt;
  1220. rsp->ring_ptr = rsp->ring;
  1221. rsp->ring_index = 0;
  1222. rsp->status_srb = NULL;
  1223. pkt = rsp->ring_ptr;
  1224. for (cnt = 0; cnt < rsp->length; cnt++) {
  1225. pkt->signature = RESPONSE_PROCESSED;
  1226. WRT_REG_DWORD((void __iomem *)&pkt->signature,
  1227. RESPONSE_PROCESSED);
  1228. pkt++;
  1229. }
  1230. }
  1231. int
  1232. qlafx00_rescan_isp(scsi_qla_host_t *vha)
  1233. {
  1234. uint32_t status = QLA_FUNCTION_FAILED;
  1235. struct qla_hw_data *ha = vha->hw;
  1236. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1237. uint32_t aenmbx7;
  1238. qla2x00_request_irqs(ha, ha->rsp_q_map[0]);
  1239. aenmbx7 = RD_REG_DWORD(&reg->aenmailbox7);
  1240. ha->mbx_intr_code = MSW(aenmbx7);
  1241. ha->rqstq_intr_code = LSW(aenmbx7);
  1242. ha->req_que_off = RD_REG_DWORD(&reg->aenmailbox1);
  1243. ha->rsp_que_off = RD_REG_DWORD(&reg->aenmailbox3);
  1244. ha->req_que_len = RD_REG_DWORD(&reg->aenmailbox5);
  1245. ha->rsp_que_len = RD_REG_DWORD(&reg->aenmailbox6);
  1246. ql_dbg(ql_dbg_disc, vha, 0x2094,
  1247. "fw returned mbx_intr_code: 0x%x, rqstq_intr_code: 0x%x "
  1248. " Req que offset 0x%x Rsp que offset 0x%x\n",
  1249. ha->mbx_intr_code, ha->rqstq_intr_code,
  1250. ha->req_que_off, ha->rsp_que_len);
  1251. /* Clear the Interrupts */
  1252. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1253. status = qla2x00_init_rings(vha);
  1254. if (!status) {
  1255. vha->flags.online = 1;
  1256. /* if no cable then assume it's good */
  1257. if ((vha->device_flags & DFLG_NO_CABLE))
  1258. status = 0;
  1259. /* Register system information */
  1260. if (qlafx00_fx_disc(vha,
  1261. &vha->hw->mr.fcport, FXDISC_REG_HOST_INFO))
  1262. ql_dbg(ql_dbg_disc, vha, 0x2095,
  1263. "failed to register host info\n");
  1264. }
  1265. scsi_unblock_requests(vha->host);
  1266. return status;
  1267. }
  1268. void
  1269. qlafx00_timer_routine(scsi_qla_host_t *vha)
  1270. {
  1271. struct qla_hw_data *ha = vha->hw;
  1272. uint32_t fw_heart_beat;
  1273. uint32_t aenmbx0;
  1274. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  1275. /* Check firmware health */
  1276. if (ha->mr.fw_hbt_cnt)
  1277. ha->mr.fw_hbt_cnt--;
  1278. else {
  1279. if ((!ha->flags.mr_reset_hdlr_active) &&
  1280. (!test_bit(UNLOADING, &vha->dpc_flags)) &&
  1281. (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
  1282. (ha->mr.fw_hbt_en)) {
  1283. fw_heart_beat = RD_REG_DWORD(&reg->fwheartbeat);
  1284. if (fw_heart_beat != ha->mr.old_fw_hbt_cnt) {
  1285. ha->mr.old_fw_hbt_cnt = fw_heart_beat;
  1286. ha->mr.fw_hbt_miss_cnt = 0;
  1287. } else {
  1288. ha->mr.fw_hbt_miss_cnt++;
  1289. if (ha->mr.fw_hbt_miss_cnt ==
  1290. QLAFX00_HEARTBEAT_MISS_CNT) {
  1291. set_bit(ISP_ABORT_NEEDED,
  1292. &vha->dpc_flags);
  1293. qla2xxx_wake_dpc(vha);
  1294. ha->mr.fw_hbt_miss_cnt = 0;
  1295. }
  1296. }
  1297. }
  1298. ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
  1299. }
  1300. if (test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags)) {
  1301. /* Reset recovery to be performed in timer routine */
  1302. aenmbx0 = RD_REG_DWORD(&reg->aenmailbox0);
  1303. if (ha->mr.fw_reset_timer_exp) {
  1304. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1305. qla2xxx_wake_dpc(vha);
  1306. ha->mr.fw_reset_timer_exp = 0;
  1307. } else if (aenmbx0 == MBA_FW_RESTART_CMPLT) {
  1308. /* Wake up DPC to rescan the targets */
  1309. set_bit(FX00_TARGET_SCAN, &vha->dpc_flags);
  1310. clear_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1311. qla2xxx_wake_dpc(vha);
  1312. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1313. } else if ((aenmbx0 == MBA_FW_STARTING) &&
  1314. (!ha->mr.fw_hbt_en)) {
  1315. ha->mr.fw_hbt_en = 1;
  1316. } else if (!ha->mr.fw_reset_timer_tick) {
  1317. if (aenmbx0 == ha->mr.old_aenmbx0_state)
  1318. ha->mr.fw_reset_timer_exp = 1;
  1319. ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
  1320. } else if (aenmbx0 == 0xFFFFFFFF) {
  1321. uint32_t data0, data1;
  1322. data0 = QLAFX00_RD_REG(ha,
  1323. QLAFX00_BAR1_BASE_ADDR_REG);
  1324. data1 = QLAFX00_RD_REG(ha,
  1325. QLAFX00_PEX0_WIN0_BASE_ADDR_REG);
  1326. data0 &= 0xffff0000;
  1327. data1 &= 0x0000ffff;
  1328. QLAFX00_WR_REG(ha,
  1329. QLAFX00_PEX0_WIN0_BASE_ADDR_REG,
  1330. (data0 | data1));
  1331. } else if ((aenmbx0 & 0xFF00) == MBA_FW_POLL_STATE) {
  1332. ha->mr.fw_reset_timer_tick =
  1333. QLAFX00_MAX_RESET_INTERVAL;
  1334. } else if (aenmbx0 == MBA_FW_RESET_FCT) {
  1335. ha->mr.fw_reset_timer_tick =
  1336. QLAFX00_MAX_RESET_INTERVAL;
  1337. }
  1338. ha->mr.old_aenmbx0_state = aenmbx0;
  1339. ha->mr.fw_reset_timer_tick--;
  1340. }
  1341. }
  1342. /*
  1343. * qlfx00a_reset_initialize
  1344. * Re-initialize after a iSA device reset.
  1345. *
  1346. * Input:
  1347. * ha = adapter block pointer.
  1348. *
  1349. * Returns:
  1350. * 0 = success
  1351. */
  1352. int
  1353. qlafx00_reset_initialize(scsi_qla_host_t *vha)
  1354. {
  1355. struct qla_hw_data *ha = vha->hw;
  1356. if (vha->device_flags & DFLG_DEV_FAILED) {
  1357. ql_dbg(ql_dbg_init, vha, 0x0142,
  1358. "Device in failed state\n");
  1359. return QLA_SUCCESS;
  1360. }
  1361. ha->flags.mr_reset_hdlr_active = 1;
  1362. if (vha->flags.online) {
  1363. scsi_block_requests(vha->host);
  1364. qlafx00_abort_isp_cleanup(vha);
  1365. }
  1366. ql_log(ql_log_info, vha, 0x0143,
  1367. "(%s): succeeded.\n", __func__);
  1368. ha->flags.mr_reset_hdlr_active = 0;
  1369. return QLA_SUCCESS;
  1370. }
  1371. /*
  1372. * qlafx00_abort_isp
  1373. * Resets ISP and aborts all outstanding commands.
  1374. *
  1375. * Input:
  1376. * ha = adapter block pointer.
  1377. *
  1378. * Returns:
  1379. * 0 = success
  1380. */
  1381. int
  1382. qlafx00_abort_isp(scsi_qla_host_t *vha)
  1383. {
  1384. struct qla_hw_data *ha = vha->hw;
  1385. if (vha->flags.online) {
  1386. if (unlikely(pci_channel_offline(ha->pdev) &&
  1387. ha->flags.pci_channel_io_perm_failure)) {
  1388. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  1389. return QLA_SUCCESS;
  1390. }
  1391. scsi_block_requests(vha->host);
  1392. qlafx00_abort_isp_cleanup(vha);
  1393. } else {
  1394. scsi_block_requests(vha->host);
  1395. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1396. vha->qla_stats.total_isp_aborts++;
  1397. ha->isp_ops->reset_chip(vha);
  1398. set_bit(FX00_RESET_RECOVERY, &vha->dpc_flags);
  1399. /* Clear the Interrupts */
  1400. QLAFX00_CLR_INTR_REG(ha, QLAFX00_HST_INT_STS_BITS);
  1401. }
  1402. ql_log(ql_log_info, vha, 0x0145,
  1403. "(%s): succeeded.\n", __func__);
  1404. return QLA_SUCCESS;
  1405. }
  1406. static inline fc_port_t*
  1407. qlafx00_get_fcport(struct scsi_qla_host *vha, int tgt_id)
  1408. {
  1409. fc_port_t *fcport;
  1410. /* Check for matching device in remote port list. */
  1411. fcport = NULL;
  1412. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  1413. if (fcport->tgt_id == tgt_id) {
  1414. ql_dbg(ql_dbg_async, vha, 0x5072,
  1415. "Matching fcport(%p) found with TGT-ID: 0x%x "
  1416. "and Remote TGT_ID: 0x%x\n",
  1417. fcport, fcport->tgt_id, tgt_id);
  1418. break;
  1419. }
  1420. }
  1421. return fcport;
  1422. }
  1423. static void
  1424. qlafx00_tgt_detach(struct scsi_qla_host *vha, int tgt_id)
  1425. {
  1426. fc_port_t *fcport;
  1427. ql_log(ql_log_info, vha, 0x5073,
  1428. "Detach TGT-ID: 0x%x\n", tgt_id);
  1429. fcport = qlafx00_get_fcport(vha, tgt_id);
  1430. if (!fcport)
  1431. return;
  1432. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  1433. return;
  1434. }
  1435. int
  1436. qlafx00_process_aen(struct scsi_qla_host *vha, struct qla_work_evt *evt)
  1437. {
  1438. int rval = 0;
  1439. uint32_t aen_code, aen_data;
  1440. aen_code = FCH_EVT_VENDOR_UNIQUE;
  1441. aen_data = evt->u.aenfx.evtcode;
  1442. switch (evt->u.aenfx.evtcode) {
  1443. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  1444. if (evt->u.aenfx.mbx[1] == 0) {
  1445. if (evt->u.aenfx.mbx[2] == 1) {
  1446. if (!vha->flags.fw_tgt_reported)
  1447. vha->flags.fw_tgt_reported = 1;
  1448. atomic_set(&vha->loop_down_timer, 0);
  1449. atomic_set(&vha->loop_state, LOOP_UP);
  1450. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1451. qla2xxx_wake_dpc(vha);
  1452. } else if (evt->u.aenfx.mbx[2] == 2) {
  1453. qlafx00_tgt_detach(vha, evt->u.aenfx.mbx[3]);
  1454. }
  1455. } else if (evt->u.aenfx.mbx[1] == 0xffff) {
  1456. if (evt->u.aenfx.mbx[2] == 1) {
  1457. if (!vha->flags.fw_tgt_reported)
  1458. vha->flags.fw_tgt_reported = 1;
  1459. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  1460. } else if (evt->u.aenfx.mbx[2] == 2) {
  1461. vha->device_flags |= DFLG_NO_CABLE;
  1462. qla2x00_mark_all_devices_lost(vha, 1);
  1463. }
  1464. }
  1465. break;
  1466. case QLAFX00_MBA_LINK_UP:
  1467. aen_code = FCH_EVT_LINKUP;
  1468. aen_data = 0;
  1469. break;
  1470. case QLAFX00_MBA_LINK_DOWN:
  1471. aen_code = FCH_EVT_LINKDOWN;
  1472. aen_data = 0;
  1473. break;
  1474. }
  1475. fc_host_post_event(vha->host, fc_get_event_number(),
  1476. aen_code, aen_data);
  1477. return rval;
  1478. }
  1479. static void
  1480. qlafx00_update_host_attr(scsi_qla_host_t *vha, struct port_info_data *pinfo)
  1481. {
  1482. u64 port_name = 0, node_name = 0;
  1483. port_name = (unsigned long long)wwn_to_u64(pinfo->port_name);
  1484. node_name = (unsigned long long)wwn_to_u64(pinfo->node_name);
  1485. fc_host_node_name(vha->host) = node_name;
  1486. fc_host_port_name(vha->host) = port_name;
  1487. if (!pinfo->port_type)
  1488. vha->hw->current_topology = ISP_CFG_F;
  1489. if (pinfo->link_status == QLAFX00_LINK_STATUS_UP)
  1490. atomic_set(&vha->loop_state, LOOP_READY);
  1491. else if (pinfo->link_status == QLAFX00_LINK_STATUS_DOWN)
  1492. atomic_set(&vha->loop_state, LOOP_DOWN);
  1493. vha->hw->link_data_rate = (uint16_t)pinfo->link_config;
  1494. }
  1495. static void
  1496. qla2x00_fxdisc_iocb_timeout(void *data)
  1497. {
  1498. srb_t *sp = (srb_t *)data;
  1499. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1500. complete(&lio->u.fxiocb.fxiocb_comp);
  1501. }
  1502. static void
  1503. qla2x00_fxdisc_sp_done(void *data, void *ptr, int res)
  1504. {
  1505. srb_t *sp = (srb_t *)ptr;
  1506. struct srb_iocb *lio = &sp->u.iocb_cmd;
  1507. complete(&lio->u.fxiocb.fxiocb_comp);
  1508. }
  1509. int
  1510. qlafx00_fx_disc(scsi_qla_host_t *vha, fc_port_t *fcport, uint16_t fx_type)
  1511. {
  1512. srb_t *sp;
  1513. struct srb_iocb *fdisc;
  1514. int rval = QLA_FUNCTION_FAILED;
  1515. struct qla_hw_data *ha = vha->hw;
  1516. struct host_system_info *phost_info;
  1517. struct register_host_info *preg_hsi;
  1518. struct new_utsname *p_sysid = NULL;
  1519. struct timeval tv;
  1520. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1521. if (!sp)
  1522. goto done;
  1523. fdisc = &sp->u.iocb_cmd;
  1524. switch (fx_type) {
  1525. case FXDISC_GET_CONFIG_INFO:
  1526. fdisc->u.fxiocb.flags =
  1527. SRB_FXDISC_RESP_DMA_VALID;
  1528. fdisc->u.fxiocb.rsp_len = sizeof(struct config_info_data);
  1529. break;
  1530. case FXDISC_GET_PORT_INFO:
  1531. fdisc->u.fxiocb.flags =
  1532. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1533. fdisc->u.fxiocb.rsp_len = QLAFX00_PORT_DATA_INFO;
  1534. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->port_id);
  1535. break;
  1536. case FXDISC_GET_TGT_NODE_INFO:
  1537. fdisc->u.fxiocb.flags =
  1538. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1539. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_INFO;
  1540. fdisc->u.fxiocb.req_data = cpu_to_le32(fcport->tgt_id);
  1541. break;
  1542. case FXDISC_GET_TGT_NODE_LIST:
  1543. fdisc->u.fxiocb.flags =
  1544. SRB_FXDISC_RESP_DMA_VALID | SRB_FXDISC_REQ_DWRD_VALID;
  1545. fdisc->u.fxiocb.rsp_len = QLAFX00_TGT_NODE_LIST_SIZE;
  1546. break;
  1547. case FXDISC_REG_HOST_INFO:
  1548. fdisc->u.fxiocb.flags = SRB_FXDISC_REQ_DMA_VALID;
  1549. fdisc->u.fxiocb.req_len = sizeof(struct register_host_info);
  1550. p_sysid = utsname();
  1551. if (!p_sysid) {
  1552. ql_log(ql_log_warn, vha, 0x303c,
  1553. "Not able to get the system informtion\n");
  1554. goto done_free_sp;
  1555. }
  1556. break;
  1557. default:
  1558. break;
  1559. }
  1560. if (fdisc->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  1561. fdisc->u.fxiocb.req_addr = dma_alloc_coherent(&ha->pdev->dev,
  1562. fdisc->u.fxiocb.req_len,
  1563. &fdisc->u.fxiocb.req_dma_handle, GFP_KERNEL);
  1564. if (!fdisc->u.fxiocb.req_addr)
  1565. goto done_free_sp;
  1566. if (fx_type == FXDISC_REG_HOST_INFO) {
  1567. preg_hsi = (struct register_host_info *)
  1568. fdisc->u.fxiocb.req_addr;
  1569. phost_info = &preg_hsi->hsi;
  1570. memset(preg_hsi, 0, sizeof(struct register_host_info));
  1571. phost_info->os_type = OS_TYPE_LINUX;
  1572. strncpy(phost_info->sysname,
  1573. p_sysid->sysname, SYSNAME_LENGTH);
  1574. strncpy(phost_info->nodename,
  1575. p_sysid->nodename, NODENAME_LENGTH);
  1576. strncpy(phost_info->release,
  1577. p_sysid->release, RELEASE_LENGTH);
  1578. strncpy(phost_info->version,
  1579. p_sysid->version, VERSION_LENGTH);
  1580. strncpy(phost_info->machine,
  1581. p_sysid->machine, MACHINE_LENGTH);
  1582. strncpy(phost_info->domainname,
  1583. p_sysid->domainname, DOMNAME_LENGTH);
  1584. strncpy(phost_info->hostdriver,
  1585. QLA2XXX_VERSION, VERSION_LENGTH);
  1586. do_gettimeofday(&tv);
  1587. preg_hsi->utc = (uint64_t)tv.tv_sec;
  1588. ql_dbg(ql_dbg_init, vha, 0x0149,
  1589. "ISP%04X: Host registration with firmware\n",
  1590. ha->pdev->device);
  1591. ql_dbg(ql_dbg_init, vha, 0x014a,
  1592. "os_type = '%d', sysname = '%s', nodname = '%s'\n",
  1593. phost_info->os_type,
  1594. phost_info->sysname,
  1595. phost_info->nodename);
  1596. ql_dbg(ql_dbg_init, vha, 0x014b,
  1597. "release = '%s', version = '%s'\n",
  1598. phost_info->release,
  1599. phost_info->version);
  1600. ql_dbg(ql_dbg_init, vha, 0x014c,
  1601. "machine = '%s' "
  1602. "domainname = '%s', hostdriver = '%s'\n",
  1603. phost_info->machine,
  1604. phost_info->domainname,
  1605. phost_info->hostdriver);
  1606. ql_dump_buffer(ql_dbg_init + ql_dbg_disc, vha, 0x014d,
  1607. (uint8_t *)phost_info,
  1608. sizeof(struct host_system_info));
  1609. }
  1610. }
  1611. if (fdisc->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  1612. fdisc->u.fxiocb.rsp_addr = dma_alloc_coherent(&ha->pdev->dev,
  1613. fdisc->u.fxiocb.rsp_len,
  1614. &fdisc->u.fxiocb.rsp_dma_handle, GFP_KERNEL);
  1615. if (!fdisc->u.fxiocb.rsp_addr)
  1616. goto done_unmap_req;
  1617. }
  1618. sp->type = SRB_FXIOCB_DCMD;
  1619. sp->name = "fxdisc";
  1620. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1621. fdisc->timeout = qla2x00_fxdisc_iocb_timeout;
  1622. fdisc->u.fxiocb.req_func_type = cpu_to_le16(fx_type);
  1623. sp->done = qla2x00_fxdisc_sp_done;
  1624. rval = qla2x00_start_sp(sp);
  1625. if (rval != QLA_SUCCESS)
  1626. goto done_unmap_dma;
  1627. wait_for_completion(&fdisc->u.fxiocb.fxiocb_comp);
  1628. if (fx_type == FXDISC_GET_CONFIG_INFO) {
  1629. struct config_info_data *pinfo =
  1630. (struct config_info_data *) fdisc->u.fxiocb.rsp_addr;
  1631. memcpy(&vha->hw->mr.product_name, pinfo->product_name,
  1632. sizeof(vha->hw->mr.product_name));
  1633. memcpy(&vha->hw->mr.symbolic_name, pinfo->symbolic_name,
  1634. sizeof(vha->hw->mr.symbolic_name));
  1635. memcpy(&vha->hw->mr.serial_num, pinfo->serial_num,
  1636. sizeof(vha->hw->mr.serial_num));
  1637. memcpy(&vha->hw->mr.hw_version, pinfo->hw_version,
  1638. sizeof(vha->hw->mr.hw_version));
  1639. memcpy(&vha->hw->mr.fw_version, pinfo->fw_version,
  1640. sizeof(vha->hw->mr.fw_version));
  1641. strim(vha->hw->mr.fw_version);
  1642. memcpy(&vha->hw->mr.uboot_version, pinfo->uboot_version,
  1643. sizeof(vha->hw->mr.uboot_version));
  1644. memcpy(&vha->hw->mr.fru_serial_num, pinfo->fru_serial_num,
  1645. sizeof(vha->hw->mr.fru_serial_num));
  1646. } else if (fx_type == FXDISC_GET_PORT_INFO) {
  1647. struct port_info_data *pinfo =
  1648. (struct port_info_data *) fdisc->u.fxiocb.rsp_addr;
  1649. memcpy(vha->node_name, pinfo->node_name, WWN_SIZE);
  1650. memcpy(vha->port_name, pinfo->port_name, WWN_SIZE);
  1651. vha->d_id.b.domain = pinfo->port_id[0];
  1652. vha->d_id.b.area = pinfo->port_id[1];
  1653. vha->d_id.b.al_pa = pinfo->port_id[2];
  1654. qlafx00_update_host_attr(vha, pinfo);
  1655. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0141,
  1656. (uint8_t *)pinfo, 16);
  1657. } else if (fx_type == FXDISC_GET_TGT_NODE_INFO) {
  1658. struct qlafx00_tgt_node_info *pinfo =
  1659. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1660. memcpy(fcport->node_name, pinfo->tgt_node_wwnn, WWN_SIZE);
  1661. memcpy(fcport->port_name, pinfo->tgt_node_wwpn, WWN_SIZE);
  1662. fcport->port_type = FCT_TARGET;
  1663. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0144,
  1664. (uint8_t *)pinfo, 16);
  1665. } else if (fx_type == FXDISC_GET_TGT_NODE_LIST) {
  1666. struct qlafx00_tgt_node_info *pinfo =
  1667. (struct qlafx00_tgt_node_info *) fdisc->u.fxiocb.rsp_addr;
  1668. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0146,
  1669. (uint8_t *)pinfo, 16);
  1670. memcpy(vha->hw->gid_list, pinfo, QLAFX00_TGT_NODE_LIST_SIZE);
  1671. }
  1672. rval = le32_to_cpu(fdisc->u.fxiocb.result);
  1673. done_unmap_dma:
  1674. if (fdisc->u.fxiocb.rsp_addr)
  1675. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.rsp_len,
  1676. fdisc->u.fxiocb.rsp_addr, fdisc->u.fxiocb.rsp_dma_handle);
  1677. done_unmap_req:
  1678. if (fdisc->u.fxiocb.req_addr)
  1679. dma_free_coherent(&ha->pdev->dev, fdisc->u.fxiocb.req_len,
  1680. fdisc->u.fxiocb.req_addr, fdisc->u.fxiocb.req_dma_handle);
  1681. done_free_sp:
  1682. sp->free(vha, sp);
  1683. done:
  1684. return rval;
  1685. }
  1686. static void
  1687. qlafx00_abort_iocb_timeout(void *data)
  1688. {
  1689. srb_t *sp = (srb_t *)data;
  1690. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1691. abt->u.abt.comp_status = cpu_to_le16((uint16_t)CS_TIMEOUT);
  1692. complete(&abt->u.abt.comp);
  1693. }
  1694. static void
  1695. qlafx00_abort_sp_done(void *data, void *ptr, int res)
  1696. {
  1697. srb_t *sp = (srb_t *)ptr;
  1698. struct srb_iocb *abt = &sp->u.iocb_cmd;
  1699. complete(&abt->u.abt.comp);
  1700. }
  1701. static int
  1702. qlafx00_async_abt_cmd(srb_t *cmd_sp)
  1703. {
  1704. scsi_qla_host_t *vha = cmd_sp->fcport->vha;
  1705. fc_port_t *fcport = cmd_sp->fcport;
  1706. struct srb_iocb *abt_iocb;
  1707. srb_t *sp;
  1708. int rval = QLA_FUNCTION_FAILED;
  1709. sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
  1710. if (!sp)
  1711. goto done;
  1712. abt_iocb = &sp->u.iocb_cmd;
  1713. sp->type = SRB_ABT_CMD;
  1714. sp->name = "abort";
  1715. qla2x00_init_timer(sp, FXDISC_TIMEOUT);
  1716. abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
  1717. sp->done = qlafx00_abort_sp_done;
  1718. abt_iocb->timeout = qlafx00_abort_iocb_timeout;
  1719. init_completion(&abt_iocb->u.abt.comp);
  1720. rval = qla2x00_start_sp(sp);
  1721. if (rval != QLA_SUCCESS)
  1722. goto done_free_sp;
  1723. ql_dbg(ql_dbg_async, vha, 0x507c,
  1724. "Abort command issued - hdl=%x, target_id=%x\n",
  1725. cmd_sp->handle, fcport->tgt_id);
  1726. wait_for_completion(&abt_iocb->u.abt.comp);
  1727. rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
  1728. QLA_SUCCESS : QLA_FUNCTION_FAILED;
  1729. done_free_sp:
  1730. sp->free(vha, sp);
  1731. done:
  1732. return rval;
  1733. }
  1734. int
  1735. qlafx00_abort_command(srb_t *sp)
  1736. {
  1737. unsigned long flags = 0;
  1738. uint32_t handle;
  1739. fc_port_t *fcport = sp->fcport;
  1740. struct scsi_qla_host *vha = fcport->vha;
  1741. struct qla_hw_data *ha = vha->hw;
  1742. struct req_que *req = vha->req;
  1743. spin_lock_irqsave(&ha->hardware_lock, flags);
  1744. for (handle = 1; handle < DEFAULT_OUTSTANDING_COMMANDS; handle++) {
  1745. if (req->outstanding_cmds[handle] == sp)
  1746. break;
  1747. }
  1748. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1749. if (handle == DEFAULT_OUTSTANDING_COMMANDS) {
  1750. /* Command not found. */
  1751. return QLA_FUNCTION_FAILED;
  1752. }
  1753. return qlafx00_async_abt_cmd(sp);
  1754. }
  1755. /*
  1756. * qlafx00_initialize_adapter
  1757. * Initialize board.
  1758. *
  1759. * Input:
  1760. * ha = adapter block pointer.
  1761. *
  1762. * Returns:
  1763. * 0 = success
  1764. */
  1765. int
  1766. qlafx00_initialize_adapter(scsi_qla_host_t *vha)
  1767. {
  1768. int rval;
  1769. struct qla_hw_data *ha = vha->hw;
  1770. /* Clear adapter flags. */
  1771. vha->flags.online = 0;
  1772. ha->flags.chip_reset_done = 0;
  1773. vha->flags.reset_active = 0;
  1774. ha->flags.pci_channel_io_perm_failure = 0;
  1775. ha->flags.eeh_busy = 0;
  1776. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  1777. atomic_set(&vha->loop_state, LOOP_DOWN);
  1778. vha->device_flags = DFLG_NO_CABLE;
  1779. vha->dpc_flags = 0;
  1780. vha->flags.management_server_logged_in = 0;
  1781. vha->marker_needed = 0;
  1782. ha->isp_abort_cnt = 0;
  1783. ha->beacon_blink_led = 0;
  1784. set_bit(0, ha->req_qid_map);
  1785. set_bit(0, ha->rsp_qid_map);
  1786. ql_dbg(ql_dbg_init, vha, 0x0147,
  1787. "Configuring PCI space...\n");
  1788. rval = ha->isp_ops->pci_config(vha);
  1789. if (rval) {
  1790. ql_log(ql_log_warn, vha, 0x0148,
  1791. "Unable to configure PCI space.\n");
  1792. return rval;
  1793. }
  1794. rval = qlafx00_init_fw_ready(vha);
  1795. if (rval != QLA_SUCCESS)
  1796. return rval;
  1797. qlafx00_save_queue_ptrs(vha);
  1798. rval = qlafx00_config_queues(vha);
  1799. if (rval != QLA_SUCCESS)
  1800. return rval;
  1801. /*
  1802. * Allocate the array of outstanding commands
  1803. * now that we know the firmware resources.
  1804. */
  1805. rval = qla2x00_alloc_outstanding_cmds(ha, vha->req);
  1806. if (rval != QLA_SUCCESS)
  1807. return rval;
  1808. rval = qla2x00_init_rings(vha);
  1809. ha->flags.chip_reset_done = 1;
  1810. return rval;
  1811. }
  1812. uint32_t
  1813. qlafx00_fw_state_show(struct device *dev, struct device_attribute *attr,
  1814. char *buf)
  1815. {
  1816. scsi_qla_host_t *vha = shost_priv(class_to_shost(dev));
  1817. int rval = QLA_FUNCTION_FAILED;
  1818. uint32_t state[1];
  1819. if (qla2x00_reset_active(vha))
  1820. ql_log(ql_log_warn, vha, 0x70ce,
  1821. "ISP reset active.\n");
  1822. else if (!vha->hw->flags.eeh_busy) {
  1823. rval = qlafx00_get_firmware_state(vha, state);
  1824. }
  1825. if (rval != QLA_SUCCESS)
  1826. memset(state, -1, sizeof(state));
  1827. return state[0];
  1828. }
  1829. void
  1830. qlafx00_get_host_speed(struct Scsi_Host *shost)
  1831. {
  1832. struct qla_hw_data *ha = ((struct scsi_qla_host *)
  1833. (shost_priv(shost)))->hw;
  1834. u32 speed = FC_PORTSPEED_UNKNOWN;
  1835. switch (ha->link_data_rate) {
  1836. case QLAFX00_PORT_SPEED_2G:
  1837. speed = FC_PORTSPEED_2GBIT;
  1838. break;
  1839. case QLAFX00_PORT_SPEED_4G:
  1840. speed = FC_PORTSPEED_4GBIT;
  1841. break;
  1842. case QLAFX00_PORT_SPEED_8G:
  1843. speed = FC_PORTSPEED_8GBIT;
  1844. break;
  1845. case QLAFX00_PORT_SPEED_10G:
  1846. speed = FC_PORTSPEED_10GBIT;
  1847. break;
  1848. }
  1849. fc_host_speed(shost) = speed;
  1850. }
  1851. /** QLAFX00 specific ISR implementation functions */
  1852. static inline void
  1853. qlafx00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1854. uint32_t sense_len, struct rsp_que *rsp, int res)
  1855. {
  1856. struct scsi_qla_host *vha = sp->fcport->vha;
  1857. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1858. uint32_t track_sense_len;
  1859. SET_FW_SENSE_LEN(sp, sense_len);
  1860. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1861. sense_len = SCSI_SENSE_BUFFERSIZE;
  1862. SET_CMD_SENSE_LEN(sp, sense_len);
  1863. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1864. track_sense_len = sense_len;
  1865. if (sense_len > par_sense_len)
  1866. sense_len = par_sense_len;
  1867. memcpy(cp->sense_buffer, sense_data, sense_len);
  1868. SET_FW_SENSE_LEN(sp, GET_FW_SENSE_LEN(sp) - sense_len);
  1869. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1870. track_sense_len -= sense_len;
  1871. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1872. ql_dbg(ql_dbg_io, vha, 0x304d,
  1873. "sense_len=0x%x par_sense_len=0x%x track_sense_len=0x%x.\n",
  1874. sense_len, par_sense_len, track_sense_len);
  1875. if (GET_FW_SENSE_LEN(sp) > 0) {
  1876. rsp->status_srb = sp;
  1877. cp->result = res;
  1878. }
  1879. if (sense_len) {
  1880. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x3039,
  1881. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1882. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1883. cp);
  1884. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3049,
  1885. cp->sense_buffer, sense_len);
  1886. }
  1887. }
  1888. static void
  1889. qlafx00_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1890. struct tsk_mgmt_entry_fx00 *pkt, srb_t *sp,
  1891. __le16 sstatus, __le16 cpstatus)
  1892. {
  1893. struct srb_iocb *tmf;
  1894. tmf = &sp->u.iocb_cmd;
  1895. if (cpstatus != cpu_to_le16((uint16_t)CS_COMPLETE) ||
  1896. (sstatus & cpu_to_le16((uint16_t)SS_RESPONSE_INFO_LEN_VALID)))
  1897. cpstatus = cpu_to_le16((uint16_t)CS_INCOMPLETE);
  1898. tmf->u.tmf.comp_status = cpstatus;
  1899. sp->done(vha, sp, 0);
  1900. }
  1901. static void
  1902. qlafx00_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1903. struct abort_iocb_entry_fx00 *pkt)
  1904. {
  1905. const char func[] = "ABT_IOCB";
  1906. srb_t *sp;
  1907. struct srb_iocb *abt;
  1908. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1909. if (!sp)
  1910. return;
  1911. abt = &sp->u.iocb_cmd;
  1912. abt->u.abt.comp_status = pkt->tgt_id_sts;
  1913. sp->done(vha, sp, 0);
  1914. }
  1915. static void
  1916. qlafx00_ioctl_iosb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1917. struct ioctl_iocb_entry_fx00 *pkt)
  1918. {
  1919. const char func[] = "IOSB_IOCB";
  1920. srb_t *sp;
  1921. struct fc_bsg_job *bsg_job;
  1922. struct srb_iocb *iocb_job;
  1923. int res;
  1924. struct qla_mt_iocb_rsp_fx00 fstatus;
  1925. uint8_t *fw_sts_ptr;
  1926. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1927. if (!sp)
  1928. return;
  1929. if (sp->type == SRB_FXIOCB_DCMD) {
  1930. iocb_job = &sp->u.iocb_cmd;
  1931. iocb_job->u.fxiocb.seq_number = pkt->seq_no;
  1932. iocb_job->u.fxiocb.fw_flags = pkt->fw_iotcl_flags;
  1933. iocb_job->u.fxiocb.result = pkt->status;
  1934. if (iocb_job->u.fxiocb.flags & SRB_FXDISC_RSP_DWRD_VALID)
  1935. iocb_job->u.fxiocb.req_data =
  1936. pkt->dataword_r;
  1937. } else {
  1938. bsg_job = sp->u.bsg_job;
  1939. memset(&fstatus, 0, sizeof(struct qla_mt_iocb_rsp_fx00));
  1940. fstatus.reserved_1 = pkt->reserved_0;
  1941. fstatus.func_type = pkt->comp_func_num;
  1942. fstatus.ioctl_flags = pkt->fw_iotcl_flags;
  1943. fstatus.ioctl_data = pkt->dataword_r;
  1944. fstatus.adapid = pkt->adapid;
  1945. fstatus.adapid_hi = pkt->adapid_hi;
  1946. fstatus.reserved_2 = pkt->reserved_1;
  1947. fstatus.res_count = pkt->residuallen;
  1948. fstatus.status = pkt->status;
  1949. fstatus.seq_number = pkt->seq_no;
  1950. memcpy(fstatus.reserved_3,
  1951. pkt->reserved_2, 20 * sizeof(uint8_t));
  1952. fw_sts_ptr = ((uint8_t *)bsg_job->req->sense) +
  1953. sizeof(struct fc_bsg_reply);
  1954. memcpy(fw_sts_ptr, (uint8_t *)&fstatus,
  1955. sizeof(struct qla_mt_iocb_rsp_fx00));
  1956. bsg_job->reply_len = sizeof(struct fc_bsg_reply) +
  1957. sizeof(struct qla_mt_iocb_rsp_fx00) + sizeof(uint8_t);
  1958. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1959. sp->fcport->vha, 0x5080,
  1960. (uint8_t *)pkt, sizeof(struct ioctl_iocb_entry_fx00));
  1961. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  1962. sp->fcport->vha, 0x5074,
  1963. (uint8_t *)fw_sts_ptr, sizeof(struct qla_mt_iocb_rsp_fx00));
  1964. res = bsg_job->reply->result = DID_OK << 16;
  1965. bsg_job->reply->reply_payload_rcv_len =
  1966. bsg_job->reply_payload.payload_len;
  1967. }
  1968. sp->done(vha, sp, res);
  1969. }
  1970. /**
  1971. * qlafx00_status_entry() - Process a Status IOCB entry.
  1972. * @ha: SCSI driver HA context
  1973. * @pkt: Entry pointer
  1974. */
  1975. static void
  1976. qlafx00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1977. {
  1978. srb_t *sp;
  1979. fc_port_t *fcport;
  1980. struct scsi_cmnd *cp;
  1981. struct sts_entry_fx00 *sts;
  1982. __le16 comp_status;
  1983. __le16 scsi_status;
  1984. uint16_t ox_id;
  1985. __le16 lscsi_status;
  1986. int32_t resid;
  1987. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1988. fw_resid_len;
  1989. uint8_t *rsp_info = NULL, *sense_data = NULL;
  1990. struct qla_hw_data *ha = vha->hw;
  1991. uint32_t hindex, handle;
  1992. uint16_t que;
  1993. struct req_que *req;
  1994. int logit = 1;
  1995. int res = 0;
  1996. sts = (struct sts_entry_fx00 *) pkt;
  1997. comp_status = sts->comp_status;
  1998. scsi_status = sts->scsi_status & cpu_to_le16((uint16_t)SS_MASK);
  1999. hindex = sts->handle;
  2000. handle = LSW(hindex);
  2001. que = MSW(hindex);
  2002. req = ha->req_q_map[que];
  2003. /* Validate handle. */
  2004. if (handle < req->num_outstanding_cmds)
  2005. sp = req->outstanding_cmds[handle];
  2006. else
  2007. sp = NULL;
  2008. if (sp == NULL) {
  2009. ql_dbg(ql_dbg_io, vha, 0x3034,
  2010. "Invalid status handle (0x%x).\n", handle);
  2011. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2012. qla2xxx_wake_dpc(vha);
  2013. return;
  2014. }
  2015. if (sp->type == SRB_TM_CMD) {
  2016. req->outstanding_cmds[handle] = NULL;
  2017. qlafx00_tm_iocb_entry(vha, req, pkt, sp,
  2018. scsi_status, comp_status);
  2019. return;
  2020. }
  2021. /* Fast path completion. */
  2022. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  2023. qla2x00_do_host_ramp_up(vha);
  2024. qla2x00_process_completed_request(vha, req, handle);
  2025. return;
  2026. }
  2027. req->outstanding_cmds[handle] = NULL;
  2028. cp = GET_CMD_SP(sp);
  2029. if (cp == NULL) {
  2030. ql_dbg(ql_dbg_io, vha, 0x3048,
  2031. "Command already returned (0x%x/%p).\n",
  2032. handle, sp);
  2033. return;
  2034. }
  2035. lscsi_status = scsi_status & cpu_to_le16((uint16_t)STATUS_MASK);
  2036. fcport = sp->fcport;
  2037. ox_id = 0;
  2038. sense_len = par_sense_len = rsp_info_len = resid_len =
  2039. fw_resid_len = 0;
  2040. if (scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID))
  2041. sense_len = sts->sense_len;
  2042. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2043. | (uint16_t)SS_RESIDUAL_OVER)))
  2044. resid_len = le32_to_cpu(sts->residual_len);
  2045. if (comp_status == cpu_to_le16((uint16_t)CS_DATA_UNDERRUN))
  2046. fw_resid_len = le32_to_cpu(sts->residual_len);
  2047. rsp_info = sense_data = sts->data;
  2048. par_sense_len = sizeof(sts->data);
  2049. /* Check for overrun. */
  2050. if (comp_status == CS_COMPLETE &&
  2051. scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_OVER))
  2052. comp_status = cpu_to_le16((uint16_t)CS_DATA_OVERRUN);
  2053. /*
  2054. * Based on Host and scsi status generate status code for Linux
  2055. */
  2056. switch (le16_to_cpu(comp_status)) {
  2057. case CS_COMPLETE:
  2058. case CS_QUEUE_FULL:
  2059. if (scsi_status == 0) {
  2060. res = DID_OK << 16;
  2061. break;
  2062. }
  2063. if (scsi_status & cpu_to_le16(((uint16_t)SS_RESIDUAL_UNDER
  2064. | (uint16_t)SS_RESIDUAL_OVER))) {
  2065. resid = resid_len;
  2066. scsi_set_resid(cp, resid);
  2067. if (!lscsi_status &&
  2068. ((unsigned)(scsi_bufflen(cp) - resid) <
  2069. cp->underflow)) {
  2070. ql_dbg(ql_dbg_io, fcport->vha, 0x3050,
  2071. "Mid-layer underflow "
  2072. "detected (0x%x of 0x%x bytes).\n",
  2073. resid, scsi_bufflen(cp));
  2074. res = DID_ERROR << 16;
  2075. break;
  2076. }
  2077. }
  2078. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2079. if (lscsi_status ==
  2080. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2081. ql_dbg(ql_dbg_io, fcport->vha, 0x3051,
  2082. "QUEUE FULL detected.\n");
  2083. break;
  2084. }
  2085. logit = 0;
  2086. if (lscsi_status != cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2087. break;
  2088. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2089. if (!(scsi_status & cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2090. break;
  2091. qlafx00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  2092. rsp, res);
  2093. break;
  2094. case CS_DATA_UNDERRUN:
  2095. /* Use F/W calculated residual length. */
  2096. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2097. resid = fw_resid_len;
  2098. else
  2099. resid = resid_len;
  2100. scsi_set_resid(cp, resid);
  2101. if (scsi_status & cpu_to_le16((uint16_t)SS_RESIDUAL_UNDER)) {
  2102. if ((IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2103. && fw_resid_len != resid_len) {
  2104. ql_dbg(ql_dbg_io, fcport->vha, 0x3052,
  2105. "Dropped frame(s) detected "
  2106. "(0x%x of 0x%x bytes).\n",
  2107. resid, scsi_bufflen(cp));
  2108. res = DID_ERROR << 16 |
  2109. le16_to_cpu(lscsi_status);
  2110. goto check_scsi_status;
  2111. }
  2112. if (!lscsi_status &&
  2113. ((unsigned)(scsi_bufflen(cp) - resid) <
  2114. cp->underflow)) {
  2115. ql_dbg(ql_dbg_io, fcport->vha, 0x3053,
  2116. "Mid-layer underflow "
  2117. "detected (0x%x of 0x%x bytes, "
  2118. "cp->underflow: 0x%x).\n",
  2119. resid, scsi_bufflen(cp), cp->underflow);
  2120. res = DID_ERROR << 16;
  2121. break;
  2122. }
  2123. } else if (lscsi_status !=
  2124. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL) &&
  2125. lscsi_status != cpu_to_le16((uint16_t)SAM_STAT_BUSY)) {
  2126. /*
  2127. * scsi status of task set and busy are considered
  2128. * to be task not completed.
  2129. */
  2130. ql_dbg(ql_dbg_io, fcport->vha, 0x3054,
  2131. "Dropped frame(s) detected (0x%x "
  2132. "of 0x%x bytes).\n", resid,
  2133. scsi_bufflen(cp));
  2134. res = DID_ERROR << 16 | le16_to_cpu(lscsi_status);
  2135. goto check_scsi_status;
  2136. } else {
  2137. ql_dbg(ql_dbg_io, fcport->vha, 0x3055,
  2138. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2139. scsi_status, lscsi_status);
  2140. }
  2141. res = DID_OK << 16 | le16_to_cpu(lscsi_status);
  2142. logit = 0;
  2143. check_scsi_status:
  2144. /*
  2145. * Check to see if SCSI Status is non zero. If so report SCSI
  2146. * Status.
  2147. */
  2148. if (lscsi_status != 0) {
  2149. if (lscsi_status ==
  2150. cpu_to_le16((uint16_t)SAM_STAT_TASK_SET_FULL)) {
  2151. ql_dbg(ql_dbg_io, fcport->vha, 0x3056,
  2152. "QUEUE FULL detected.\n");
  2153. logit = 1;
  2154. break;
  2155. }
  2156. if (lscsi_status !=
  2157. cpu_to_le16((uint16_t)SS_CHECK_CONDITION))
  2158. break;
  2159. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2160. if (!(scsi_status &
  2161. cpu_to_le16((uint16_t)SS_SENSE_LEN_VALID)))
  2162. break;
  2163. qlafx00_handle_sense(sp, sense_data, par_sense_len,
  2164. sense_len, rsp, res);
  2165. }
  2166. break;
  2167. case CS_PORT_LOGGED_OUT:
  2168. case CS_PORT_CONFIG_CHG:
  2169. case CS_PORT_BUSY:
  2170. case CS_INCOMPLETE:
  2171. case CS_PORT_UNAVAILABLE:
  2172. case CS_TIMEOUT:
  2173. case CS_RESET:
  2174. /*
  2175. * We are going to have the fc class block the rport
  2176. * while we try to recover so instruct the mid layer
  2177. * to requeue until the class decides how to handle this.
  2178. */
  2179. res = DID_TRANSPORT_DISRUPTED << 16;
  2180. ql_dbg(ql_dbg_io, fcport->vha, 0x3057,
  2181. "Port down status: port-state=0x%x.\n",
  2182. atomic_read(&fcport->state));
  2183. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2184. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2185. break;
  2186. case CS_ABORTED:
  2187. res = DID_RESET << 16;
  2188. break;
  2189. default:
  2190. res = DID_ERROR << 16;
  2191. break;
  2192. }
  2193. if (logit)
  2194. ql_dbg(ql_dbg_io, fcport->vha, 0x3058,
  2195. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%d "
  2196. "tgt_id: 0x%x lscsi_status: 0x%x cdb=%10phN len=0x%x "
  2197. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sense_len=0x%x, "
  2198. "par_sense_len=0x%x, rsp_info_len=0x%x\n",
  2199. comp_status, scsi_status, res, vha->host_no,
  2200. cp->device->id, cp->device->lun, fcport->tgt_id,
  2201. lscsi_status, cp->cmnd, scsi_bufflen(cp),
  2202. rsp_info_len, resid_len, fw_resid_len, sense_len,
  2203. par_sense_len, rsp_info_len);
  2204. if (!res)
  2205. qla2x00_do_host_ramp_up(vha);
  2206. if (rsp->status_srb == NULL)
  2207. sp->done(ha, sp, res);
  2208. }
  2209. /**
  2210. * qlafx00_status_cont_entry() - Process a Status Continuations entry.
  2211. * @ha: SCSI driver HA context
  2212. * @pkt: Entry pointer
  2213. *
  2214. * Extended sense data.
  2215. */
  2216. static void
  2217. qlafx00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2218. {
  2219. uint8_t sense_sz = 0;
  2220. struct qla_hw_data *ha = rsp->hw;
  2221. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2222. srb_t *sp = rsp->status_srb;
  2223. struct scsi_cmnd *cp;
  2224. uint32_t sense_len;
  2225. uint8_t *sense_ptr;
  2226. if (!sp) {
  2227. ql_dbg(ql_dbg_io, vha, 0x3037,
  2228. "no SP, sp = %p\n", sp);
  2229. return;
  2230. }
  2231. if (!GET_FW_SENSE_LEN(sp)) {
  2232. ql_dbg(ql_dbg_io, vha, 0x304b,
  2233. "no fw sense data, sp = %p\n", sp);
  2234. return;
  2235. }
  2236. cp = GET_CMD_SP(sp);
  2237. if (cp == NULL) {
  2238. ql_log(ql_log_warn, vha, 0x303b,
  2239. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2240. rsp->status_srb = NULL;
  2241. return;
  2242. }
  2243. if (!GET_CMD_SENSE_LEN(sp)) {
  2244. ql_dbg(ql_dbg_io, vha, 0x304c,
  2245. "no sense data, sp = %p\n", sp);
  2246. } else {
  2247. sense_len = GET_CMD_SENSE_LEN(sp);
  2248. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2249. ql_dbg(ql_dbg_io, vha, 0x304f,
  2250. "sp=%p sense_len=0x%x sense_ptr=%p.\n",
  2251. sp, sense_len, sense_ptr);
  2252. if (sense_len > sizeof(pkt->data))
  2253. sense_sz = sizeof(pkt->data);
  2254. else
  2255. sense_sz = sense_len;
  2256. /* Move sense data. */
  2257. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304e,
  2258. (uint8_t *)pkt, sizeof(sts_cont_entry_t));
  2259. memcpy(sense_ptr, pkt->data, sense_sz);
  2260. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x304a,
  2261. sense_ptr, sense_sz);
  2262. sense_len -= sense_sz;
  2263. sense_ptr += sense_sz;
  2264. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2265. SET_CMD_SENSE_LEN(sp, sense_len);
  2266. }
  2267. sense_len = GET_FW_SENSE_LEN(sp);
  2268. sense_len = (sense_len > sizeof(pkt->data)) ?
  2269. (sense_len - sizeof(pkt->data)) : 0;
  2270. SET_FW_SENSE_LEN(sp, sense_len);
  2271. /* Place command on done queue. */
  2272. if (sense_len == 0) {
  2273. rsp->status_srb = NULL;
  2274. sp->done(ha, sp, cp->result);
  2275. }
  2276. }
  2277. /**
  2278. * qlafx00_multistatus_entry() - Process Multi response queue entries.
  2279. * @ha: SCSI driver HA context
  2280. */
  2281. static void
  2282. qlafx00_multistatus_entry(struct scsi_qla_host *vha,
  2283. struct rsp_que *rsp, void *pkt)
  2284. {
  2285. srb_t *sp;
  2286. struct multi_sts_entry_fx00 *stsmfx;
  2287. struct qla_hw_data *ha = vha->hw;
  2288. uint32_t handle, hindex, handle_count, i;
  2289. uint16_t que;
  2290. struct req_que *req;
  2291. __le32 *handle_ptr;
  2292. stsmfx = (struct multi_sts_entry_fx00 *) pkt;
  2293. handle_count = stsmfx->handle_count;
  2294. if (handle_count > MAX_HANDLE_COUNT) {
  2295. ql_dbg(ql_dbg_io, vha, 0x3035,
  2296. "Invalid handle count (0x%x).\n", handle_count);
  2297. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2298. qla2xxx_wake_dpc(vha);
  2299. return;
  2300. }
  2301. handle_ptr = &stsmfx->handles[0];
  2302. for (i = 0; i < handle_count; i++) {
  2303. hindex = le32_to_cpu(*handle_ptr);
  2304. handle = LSW(hindex);
  2305. que = MSW(hindex);
  2306. req = ha->req_q_map[que];
  2307. /* Validate handle. */
  2308. if (handle < req->num_outstanding_cmds)
  2309. sp = req->outstanding_cmds[handle];
  2310. else
  2311. sp = NULL;
  2312. if (sp == NULL) {
  2313. ql_dbg(ql_dbg_io, vha, 0x3044,
  2314. "Invalid status handle (0x%x).\n", handle);
  2315. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2316. qla2xxx_wake_dpc(vha);
  2317. return;
  2318. }
  2319. qla2x00_process_completed_request(vha, req, handle);
  2320. handle_ptr++;
  2321. }
  2322. }
  2323. /**
  2324. * qlafx00_error_entry() - Process an error entry.
  2325. * @ha: SCSI driver HA context
  2326. * @pkt: Entry pointer
  2327. */
  2328. static void
  2329. qlafx00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp,
  2330. struct sts_entry_fx00 *pkt, uint8_t estatus, uint8_t etype)
  2331. {
  2332. srb_t *sp;
  2333. struct qla_hw_data *ha = vha->hw;
  2334. const char func[] = "ERROR-IOCB";
  2335. uint16_t que = MSW(pkt->handle);
  2336. struct req_que *req = NULL;
  2337. int res = DID_ERROR << 16;
  2338. ql_dbg(ql_dbg_async, vha, 0x507f,
  2339. "type of error status in response: 0x%x\n", estatus);
  2340. req = ha->req_q_map[que];
  2341. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2342. if (sp) {
  2343. sp->done(ha, sp, res);
  2344. return;
  2345. }
  2346. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2347. qla2xxx_wake_dpc(vha);
  2348. }
  2349. /**
  2350. * qlafx00_process_response_queue() - Process response queue entries.
  2351. * @ha: SCSI driver HA context
  2352. */
  2353. static void
  2354. qlafx00_process_response_queue(struct scsi_qla_host *vha,
  2355. struct rsp_que *rsp)
  2356. {
  2357. struct sts_entry_fx00 *pkt;
  2358. response_t *lptr;
  2359. if (!vha->flags.online)
  2360. return;
  2361. while (RD_REG_DWORD((void __iomem *)&(rsp->ring_ptr->signature)) !=
  2362. RESPONSE_PROCESSED) {
  2363. lptr = rsp->ring_ptr;
  2364. memcpy_fromio(rsp->rsp_pkt, (void __iomem *)lptr,
  2365. sizeof(rsp->rsp_pkt));
  2366. pkt = (struct sts_entry_fx00 *)rsp->rsp_pkt;
  2367. rsp->ring_index++;
  2368. if (rsp->ring_index == rsp->length) {
  2369. rsp->ring_index = 0;
  2370. rsp->ring_ptr = rsp->ring;
  2371. } else {
  2372. rsp->ring_ptr++;
  2373. }
  2374. if (pkt->entry_status != 0 &&
  2375. pkt->entry_type != IOCTL_IOSB_TYPE_FX00) {
  2376. qlafx00_error_entry(vha, rsp,
  2377. (struct sts_entry_fx00 *)pkt, pkt->entry_status,
  2378. pkt->entry_type);
  2379. goto next_iter;
  2380. continue;
  2381. }
  2382. switch (pkt->entry_type) {
  2383. case STATUS_TYPE_FX00:
  2384. qlafx00_status_entry(vha, rsp, pkt);
  2385. break;
  2386. case STATUS_CONT_TYPE_FX00:
  2387. qlafx00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2388. break;
  2389. case MULTI_STATUS_TYPE_FX00:
  2390. qlafx00_multistatus_entry(vha, rsp, pkt);
  2391. break;
  2392. case ABORT_IOCB_TYPE_FX00:
  2393. qlafx00_abort_iocb_entry(vha, rsp->req,
  2394. (struct abort_iocb_entry_fx00 *)pkt);
  2395. break;
  2396. case IOCTL_IOSB_TYPE_FX00:
  2397. qlafx00_ioctl_iosb_entry(vha, rsp->req,
  2398. (struct ioctl_iocb_entry_fx00 *)pkt);
  2399. break;
  2400. default:
  2401. /* Type Not Supported. */
  2402. ql_dbg(ql_dbg_async, vha, 0x5081,
  2403. "Received unknown response pkt type %x "
  2404. "entry status=%x.\n",
  2405. pkt->entry_type, pkt->entry_status);
  2406. break;
  2407. }
  2408. next_iter:
  2409. WRT_REG_DWORD((void __iomem *)&lptr->signature,
  2410. RESPONSE_PROCESSED);
  2411. wmb();
  2412. }
  2413. /* Adjust ring index */
  2414. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2415. }
  2416. /**
  2417. * qlafx00_async_event() - Process aynchronous events.
  2418. * @ha: SCSI driver HA context
  2419. */
  2420. static void
  2421. qlafx00_async_event(scsi_qla_host_t *vha)
  2422. {
  2423. struct qla_hw_data *ha = vha->hw;
  2424. struct device_reg_fx00 __iomem *reg;
  2425. int data_size = 1;
  2426. reg = &ha->iobase->ispfx00;
  2427. /* Setup to process RIO completion. */
  2428. switch (ha->aenmb[0]) {
  2429. case QLAFX00_MBA_SYSTEM_ERR: /* System Error */
  2430. ql_log(ql_log_warn, vha, 0x5079,
  2431. "ISP System Error - mbx1=%x\n", ha->aenmb[0]);
  2432. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2433. break;
  2434. case QLAFX00_MBA_SHUTDOWN_RQSTD: /* Shutdown requested */
  2435. ql_dbg(ql_dbg_async, vha, 0x5076,
  2436. "Asynchronous FW shutdown requested.\n");
  2437. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2438. qla2xxx_wake_dpc(vha);
  2439. break;
  2440. case QLAFX00_MBA_PORT_UPDATE: /* Port database update */
  2441. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2442. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2443. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2444. ql_dbg(ql_dbg_async, vha, 0x5077,
  2445. "Asynchronous port Update received "
  2446. "aenmb[0]: %x, aenmb[1]: %x, aenmb[2]: %x, aenmb[3]: %x\n",
  2447. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3]);
  2448. data_size = 4;
  2449. break;
  2450. default:
  2451. ha->aenmb[1] = RD_REG_WORD(&reg->aenmailbox1);
  2452. ha->aenmb[2] = RD_REG_WORD(&reg->aenmailbox2);
  2453. ha->aenmb[3] = RD_REG_WORD(&reg->aenmailbox3);
  2454. ha->aenmb[4] = RD_REG_WORD(&reg->aenmailbox4);
  2455. ha->aenmb[5] = RD_REG_WORD(&reg->aenmailbox5);
  2456. ha->aenmb[6] = RD_REG_WORD(&reg->aenmailbox6);
  2457. ha->aenmb[7] = RD_REG_WORD(&reg->aenmailbox7);
  2458. ql_dbg(ql_dbg_async, vha, 0x5078,
  2459. "AEN:%04x %04x %04x %04x :%04x %04x %04x %04x\n",
  2460. ha->aenmb[0], ha->aenmb[1], ha->aenmb[2], ha->aenmb[3],
  2461. ha->aenmb[4], ha->aenmb[5], ha->aenmb[6], ha->aenmb[7]);
  2462. break;
  2463. }
  2464. qlafx00_post_aenfx_work(vha, ha->aenmb[0],
  2465. (uint32_t *)ha->aenmb, data_size);
  2466. }
  2467. /**
  2468. *
  2469. * qlafx00x_mbx_completion() - Process mailbox command completions.
  2470. * @ha: SCSI driver HA context
  2471. * @mb16: Mailbox16 register
  2472. */
  2473. static void
  2474. qlafx00_mbx_completion(scsi_qla_host_t *vha, uint32_t mb0)
  2475. {
  2476. uint16_t cnt;
  2477. uint16_t __iomem *wptr;
  2478. struct qla_hw_data *ha = vha->hw;
  2479. struct device_reg_fx00 __iomem *reg = &ha->iobase->ispfx00;
  2480. if (!ha->mcp32)
  2481. ql_dbg(ql_dbg_async, vha, 0x507e, "MBX pointer ERROR.\n");
  2482. /* Load return mailbox registers. */
  2483. ha->flags.mbox_int = 1;
  2484. ha->mailbox_out32[0] = mb0;
  2485. wptr = (uint16_t __iomem *)&reg->mailbox17;
  2486. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2487. ha->mailbox_out32[cnt] = RD_REG_WORD(wptr);
  2488. wptr++;
  2489. }
  2490. }
  2491. /**
  2492. * qlafx00_intr_handler() - Process interrupts for the ISPFX00.
  2493. * @irq:
  2494. * @dev_id: SCSI driver HA context
  2495. *
  2496. * Called by system whenever the host adapter generates an interrupt.
  2497. *
  2498. * Returns handled flag.
  2499. */
  2500. irqreturn_t
  2501. qlafx00_intr_handler(int irq, void *dev_id)
  2502. {
  2503. scsi_qla_host_t *vha;
  2504. struct qla_hw_data *ha;
  2505. struct device_reg_fx00 __iomem *reg;
  2506. int status;
  2507. unsigned long iter;
  2508. uint32_t stat;
  2509. uint32_t mb[8];
  2510. struct rsp_que *rsp;
  2511. unsigned long flags;
  2512. uint32_t clr_intr = 0;
  2513. rsp = (struct rsp_que *) dev_id;
  2514. if (!rsp) {
  2515. ql_log(ql_log_info, NULL, 0x507d,
  2516. "%s: NULL response queue pointer.\n", __func__);
  2517. return IRQ_NONE;
  2518. }
  2519. ha = rsp->hw;
  2520. reg = &ha->iobase->ispfx00;
  2521. status = 0;
  2522. if (unlikely(pci_channel_offline(ha->pdev)))
  2523. return IRQ_HANDLED;
  2524. spin_lock_irqsave(&ha->hardware_lock, flags);
  2525. vha = pci_get_drvdata(ha->pdev);
  2526. for (iter = 50; iter--; clr_intr = 0) {
  2527. stat = QLAFX00_RD_INTR_REG(ha);
  2528. if ((stat & QLAFX00_HST_INT_STS_BITS) == 0)
  2529. break;
  2530. switch (stat & QLAFX00_HST_INT_STS_BITS) {
  2531. case QLAFX00_INTR_MB_CMPLT:
  2532. case QLAFX00_INTR_MB_RSP_CMPLT:
  2533. case QLAFX00_INTR_MB_ASYNC_CMPLT:
  2534. case QLAFX00_INTR_ALL_CMPLT:
  2535. mb[0] = RD_REG_WORD(&reg->mailbox16);
  2536. qlafx00_mbx_completion(vha, mb[0]);
  2537. status |= MBX_INTERRUPT;
  2538. clr_intr |= QLAFX00_INTR_MB_CMPLT;
  2539. break;
  2540. case QLAFX00_INTR_ASYNC_CMPLT:
  2541. case QLAFX00_INTR_RSP_ASYNC_CMPLT:
  2542. ha->aenmb[0] = RD_REG_WORD(&reg->aenmailbox0);
  2543. qlafx00_async_event(vha);
  2544. clr_intr |= QLAFX00_INTR_ASYNC_CMPLT;
  2545. break;
  2546. case QLAFX00_INTR_RSP_CMPLT:
  2547. qlafx00_process_response_queue(vha, rsp);
  2548. clr_intr |= QLAFX00_INTR_RSP_CMPLT;
  2549. break;
  2550. default:
  2551. ql_dbg(ql_dbg_async, vha, 0x507a,
  2552. "Unrecognized interrupt type (%d).\n", stat);
  2553. break;
  2554. }
  2555. QLAFX00_CLR_INTR_REG(ha, clr_intr);
  2556. QLAFX00_RD_INTR_REG(ha);
  2557. }
  2558. qla2x00_handle_mbx_completion(ha, status);
  2559. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2560. return IRQ_HANDLED;
  2561. }
  2562. /** QLAFX00 specific IOCB implementation functions */
  2563. static inline cont_a64_entry_t *
  2564. qlafx00_prep_cont_type1_iocb(struct req_que *req,
  2565. cont_a64_entry_t *lcont_pkt)
  2566. {
  2567. cont_a64_entry_t *cont_pkt;
  2568. /* Adjust ring index. */
  2569. req->ring_index++;
  2570. if (req->ring_index == req->length) {
  2571. req->ring_index = 0;
  2572. req->ring_ptr = req->ring;
  2573. } else {
  2574. req->ring_ptr++;
  2575. }
  2576. cont_pkt = (cont_a64_entry_t *)req->ring_ptr;
  2577. /* Load packet defaults. */
  2578. lcont_pkt->entry_type = CONTINUE_A64_TYPE_FX00;
  2579. return cont_pkt;
  2580. }
  2581. static inline void
  2582. qlafx00_build_scsi_iocbs(srb_t *sp, struct cmd_type_7_fx00 *cmd_pkt,
  2583. uint16_t tot_dsds, struct cmd_type_7_fx00 *lcmd_pkt)
  2584. {
  2585. uint16_t avail_dsds;
  2586. __le32 *cur_dsd;
  2587. scsi_qla_host_t *vha;
  2588. struct scsi_cmnd *cmd;
  2589. struct scatterlist *sg;
  2590. int i, cont;
  2591. struct req_que *req;
  2592. cont_a64_entry_t lcont_pkt;
  2593. cont_a64_entry_t *cont_pkt;
  2594. vha = sp->fcport->vha;
  2595. req = vha->req;
  2596. cmd = GET_CMD_SP(sp);
  2597. cont = 0;
  2598. cont_pkt = NULL;
  2599. /* Update entry type to indicate Command Type 3 IOCB */
  2600. lcmd_pkt->entry_type = FX00_COMMAND_TYPE_7;
  2601. /* No data transfer */
  2602. if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) {
  2603. lcmd_pkt->byte_count = __constant_cpu_to_le32(0);
  2604. return;
  2605. }
  2606. /* Set transfer direction */
  2607. if (cmd->sc_data_direction == DMA_TO_DEVICE) {
  2608. lcmd_pkt->cntrl_flags = TMF_WRITE_DATA;
  2609. vha->qla_stats.output_bytes += scsi_bufflen(cmd);
  2610. } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) {
  2611. lcmd_pkt->cntrl_flags = TMF_READ_DATA;
  2612. vha->qla_stats.input_bytes += scsi_bufflen(cmd);
  2613. }
  2614. /* One DSD is available in the Command Type 3 IOCB */
  2615. avail_dsds = 1;
  2616. cur_dsd = (__le32 *)&lcmd_pkt->dseg_0_address;
  2617. /* Load data segments */
  2618. scsi_for_each_sg(cmd, sg, tot_dsds, i) {
  2619. dma_addr_t sle_dma;
  2620. /* Allocate additional continuation packets? */
  2621. if (avail_dsds == 0) {
  2622. /*
  2623. * Five DSDs are available in the Continuation
  2624. * Type 1 IOCB.
  2625. */
  2626. memset(&lcont_pkt, 0, REQUEST_ENTRY_SIZE);
  2627. cont_pkt =
  2628. qlafx00_prep_cont_type1_iocb(req, &lcont_pkt);
  2629. cur_dsd = (__le32 *)lcont_pkt.dseg_0_address;
  2630. avail_dsds = 5;
  2631. cont = 1;
  2632. }
  2633. sle_dma = sg_dma_address(sg);
  2634. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2635. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2636. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2637. avail_dsds--;
  2638. if (avail_dsds == 0 && cont == 1) {
  2639. cont = 0;
  2640. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2641. REQUEST_ENTRY_SIZE);
  2642. }
  2643. }
  2644. if (avail_dsds != 0 && cont == 1) {
  2645. memcpy_toio((void __iomem *)cont_pkt, &lcont_pkt,
  2646. REQUEST_ENTRY_SIZE);
  2647. }
  2648. }
  2649. /**
  2650. * qlafx00_start_scsi() - Send a SCSI command to the ISP
  2651. * @sp: command to send to the ISP
  2652. *
  2653. * Returns non-zero if a failure occurred, else zero.
  2654. */
  2655. int
  2656. qlafx00_start_scsi(srb_t *sp)
  2657. {
  2658. int ret, nseg;
  2659. unsigned long flags;
  2660. uint32_t index;
  2661. uint32_t handle;
  2662. uint16_t cnt;
  2663. uint16_t req_cnt;
  2664. uint16_t tot_dsds;
  2665. struct req_que *req = NULL;
  2666. struct rsp_que *rsp = NULL;
  2667. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  2668. struct scsi_qla_host *vha = sp->fcport->vha;
  2669. struct qla_hw_data *ha = vha->hw;
  2670. struct cmd_type_7_fx00 *cmd_pkt;
  2671. struct cmd_type_7_fx00 lcmd_pkt;
  2672. struct scsi_lun llun;
  2673. char tag[2];
  2674. /* Setup device pointers. */
  2675. ret = 0;
  2676. rsp = ha->rsp_q_map[0];
  2677. req = vha->req;
  2678. /* So we know we haven't pci_map'ed anything yet */
  2679. tot_dsds = 0;
  2680. /* Forcing marker needed for now */
  2681. vha->marker_needed = 0;
  2682. /* Send marker if required */
  2683. if (vha->marker_needed != 0) {
  2684. if (qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL) !=
  2685. QLA_SUCCESS)
  2686. return QLA_FUNCTION_FAILED;
  2687. vha->marker_needed = 0;
  2688. }
  2689. /* Acquire ring specific lock */
  2690. spin_lock_irqsave(&ha->hardware_lock, flags);
  2691. /* Check for room in outstanding command list. */
  2692. handle = req->current_outstanding_cmd;
  2693. for (index = 1; index < req->num_outstanding_cmds; index++) {
  2694. handle++;
  2695. if (handle == req->num_outstanding_cmds)
  2696. handle = 1;
  2697. if (!req->outstanding_cmds[handle])
  2698. break;
  2699. }
  2700. if (index == req->num_outstanding_cmds)
  2701. goto queuing_error;
  2702. /* Map the sg table so we have an accurate count of sg entries needed */
  2703. if (scsi_sg_count(cmd)) {
  2704. nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd),
  2705. scsi_sg_count(cmd), cmd->sc_data_direction);
  2706. if (unlikely(!nseg))
  2707. goto queuing_error;
  2708. } else
  2709. nseg = 0;
  2710. tot_dsds = nseg;
  2711. req_cnt = qla24xx_calc_iocbs(vha, tot_dsds);
  2712. if (req->cnt < (req_cnt + 2)) {
  2713. cnt = RD_REG_DWORD_RELAXED(req->req_q_out);
  2714. if (req->ring_index < cnt)
  2715. req->cnt = cnt - req->ring_index;
  2716. else
  2717. req->cnt = req->length -
  2718. (req->ring_index - cnt);
  2719. if (req->cnt < (req_cnt + 2))
  2720. goto queuing_error;
  2721. }
  2722. /* Build command packet. */
  2723. req->current_outstanding_cmd = handle;
  2724. req->outstanding_cmds[handle] = sp;
  2725. sp->handle = handle;
  2726. cmd->host_scribble = (unsigned char *)(unsigned long)handle;
  2727. req->cnt -= req_cnt;
  2728. cmd_pkt = (struct cmd_type_7_fx00 *)req->ring_ptr;
  2729. memset(&lcmd_pkt, 0, REQUEST_ENTRY_SIZE);
  2730. lcmd_pkt.handle = MAKE_HANDLE(req->id, sp->handle);
  2731. lcmd_pkt.handle_hi = 0;
  2732. lcmd_pkt.dseg_count = cpu_to_le16(tot_dsds);
  2733. lcmd_pkt.tgt_idx = cpu_to_le16(sp->fcport->tgt_id);
  2734. int_to_scsilun(cmd->device->lun, &llun);
  2735. host_to_adap((uint8_t *)&llun, (uint8_t *)&lcmd_pkt.lun,
  2736. sizeof(lcmd_pkt.lun));
  2737. /* Update tagged queuing modifier -- default is TSK_SIMPLE (0). */
  2738. if (scsi_populate_tag_msg(cmd, tag)) {
  2739. switch (tag[0]) {
  2740. case HEAD_OF_QUEUE_TAG:
  2741. lcmd_pkt.task = TSK_HEAD_OF_QUEUE;
  2742. break;
  2743. case ORDERED_QUEUE_TAG:
  2744. lcmd_pkt.task = TSK_ORDERED;
  2745. break;
  2746. }
  2747. }
  2748. /* Load SCSI command packet. */
  2749. host_to_adap(cmd->cmnd, lcmd_pkt.fcp_cdb, sizeof(lcmd_pkt.fcp_cdb));
  2750. lcmd_pkt.byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd));
  2751. /* Build IOCB segments */
  2752. qlafx00_build_scsi_iocbs(sp, cmd_pkt, tot_dsds, &lcmd_pkt);
  2753. /* Set total data segment count. */
  2754. lcmd_pkt.entry_count = (uint8_t)req_cnt;
  2755. /* Specify response queue number where completion should happen */
  2756. lcmd_pkt.entry_status = (uint8_t) rsp->id;
  2757. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302e,
  2758. (uint8_t *)cmd->cmnd, cmd->cmd_len);
  2759. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x3032,
  2760. (uint8_t *)&lcmd_pkt, REQUEST_ENTRY_SIZE);
  2761. memcpy_toio((void __iomem *)cmd_pkt, &lcmd_pkt, REQUEST_ENTRY_SIZE);
  2762. wmb();
  2763. /* Adjust ring index. */
  2764. req->ring_index++;
  2765. if (req->ring_index == req->length) {
  2766. req->ring_index = 0;
  2767. req->ring_ptr = req->ring;
  2768. } else
  2769. req->ring_ptr++;
  2770. sp->flags |= SRB_DMA_VALID;
  2771. /* Set chip new ring index. */
  2772. WRT_REG_DWORD(req->req_q_in, req->ring_index);
  2773. QLAFX00_SET_HST_INTR(ha, ha->rqstq_intr_code);
  2774. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2775. return QLA_SUCCESS;
  2776. queuing_error:
  2777. if (tot_dsds)
  2778. scsi_dma_unmap(cmd);
  2779. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2780. return QLA_FUNCTION_FAILED;
  2781. }
  2782. void
  2783. qlafx00_tm_iocb(srb_t *sp, struct tsk_mgmt_entry_fx00 *ptm_iocb)
  2784. {
  2785. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2786. scsi_qla_host_t *vha = sp->fcport->vha;
  2787. struct req_que *req = vha->req;
  2788. struct tsk_mgmt_entry_fx00 tm_iocb;
  2789. struct scsi_lun llun;
  2790. memset(&tm_iocb, 0, sizeof(struct tsk_mgmt_entry_fx00));
  2791. tm_iocb.entry_type = TSK_MGMT_IOCB_TYPE_FX00;
  2792. tm_iocb.entry_count = 1;
  2793. tm_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2794. tm_iocb.handle_hi = 0;
  2795. tm_iocb.timeout = cpu_to_le16(qla2x00_get_async_timeout(vha) + 2);
  2796. tm_iocb.tgt_id = cpu_to_le16(sp->fcport->tgt_id);
  2797. tm_iocb.control_flags = cpu_to_le32(fxio->u.tmf.flags);
  2798. if (tm_iocb.control_flags == cpu_to_le32((uint32_t)TCF_LUN_RESET)) {
  2799. int_to_scsilun(fxio->u.tmf.lun, &llun);
  2800. host_to_adap((uint8_t *)&llun, (uint8_t *)&tm_iocb.lun,
  2801. sizeof(struct scsi_lun));
  2802. }
  2803. memcpy((void *)ptm_iocb, &tm_iocb,
  2804. sizeof(struct tsk_mgmt_entry_fx00));
  2805. wmb();
  2806. }
  2807. void
  2808. qlafx00_abort_iocb(srb_t *sp, struct abort_iocb_entry_fx00 *pabt_iocb)
  2809. {
  2810. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2811. scsi_qla_host_t *vha = sp->fcport->vha;
  2812. struct req_que *req = vha->req;
  2813. struct abort_iocb_entry_fx00 abt_iocb;
  2814. memset(&abt_iocb, 0, sizeof(struct abort_iocb_entry_fx00));
  2815. abt_iocb.entry_type = ABORT_IOCB_TYPE_FX00;
  2816. abt_iocb.entry_count = 1;
  2817. abt_iocb.handle = cpu_to_le32(MAKE_HANDLE(req->id, sp->handle));
  2818. abt_iocb.abort_handle =
  2819. cpu_to_le32(MAKE_HANDLE(req->id, fxio->u.abt.cmd_hndl));
  2820. abt_iocb.tgt_id_sts = cpu_to_le16(sp->fcport->tgt_id);
  2821. abt_iocb.req_que_no = cpu_to_le16(req->id);
  2822. memcpy((void *)pabt_iocb, &abt_iocb,
  2823. sizeof(struct abort_iocb_entry_fx00));
  2824. wmb();
  2825. }
  2826. void
  2827. qlafx00_fxdisc_iocb(srb_t *sp, struct fxdisc_entry_fx00 *pfxiocb)
  2828. {
  2829. struct srb_iocb *fxio = &sp->u.iocb_cmd;
  2830. struct qla_mt_iocb_rqst_fx00 *piocb_rqst;
  2831. struct fc_bsg_job *bsg_job;
  2832. struct fxdisc_entry_fx00 fx_iocb;
  2833. uint8_t entry_cnt = 1;
  2834. memset(&fx_iocb, 0, sizeof(struct fxdisc_entry_fx00));
  2835. fx_iocb.entry_type = FX00_IOCB_TYPE;
  2836. fx_iocb.handle = cpu_to_le32(sp->handle);
  2837. fx_iocb.entry_count = entry_cnt;
  2838. if (sp->type == SRB_FXIOCB_DCMD) {
  2839. fx_iocb.func_num =
  2840. sp->u.iocb_cmd.u.fxiocb.req_func_type;
  2841. fx_iocb.adapid = fxio->u.fxiocb.adapter_id;
  2842. fx_iocb.adapid_hi = fxio->u.fxiocb.adapter_id_hi;
  2843. fx_iocb.reserved_0 = fxio->u.fxiocb.reserved_0;
  2844. fx_iocb.reserved_1 = fxio->u.fxiocb.reserved_1;
  2845. fx_iocb.dataword_extra = fxio->u.fxiocb.req_data_extra;
  2846. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DMA_VALID) {
  2847. fx_iocb.req_dsdcnt = cpu_to_le16(1);
  2848. fx_iocb.req_xfrcnt =
  2849. cpu_to_le16(fxio->u.fxiocb.req_len);
  2850. fx_iocb.dseg_rq_address[0] =
  2851. cpu_to_le32(LSD(fxio->u.fxiocb.req_dma_handle));
  2852. fx_iocb.dseg_rq_address[1] =
  2853. cpu_to_le32(MSD(fxio->u.fxiocb.req_dma_handle));
  2854. fx_iocb.dseg_rq_len =
  2855. cpu_to_le32(fxio->u.fxiocb.req_len);
  2856. }
  2857. if (fxio->u.fxiocb.flags & SRB_FXDISC_RESP_DMA_VALID) {
  2858. fx_iocb.rsp_dsdcnt = cpu_to_le16(1);
  2859. fx_iocb.rsp_xfrcnt =
  2860. cpu_to_le16(fxio->u.fxiocb.rsp_len);
  2861. fx_iocb.dseg_rsp_address[0] =
  2862. cpu_to_le32(LSD(fxio->u.fxiocb.rsp_dma_handle));
  2863. fx_iocb.dseg_rsp_address[1] =
  2864. cpu_to_le32(MSD(fxio->u.fxiocb.rsp_dma_handle));
  2865. fx_iocb.dseg_rsp_len =
  2866. cpu_to_le32(fxio->u.fxiocb.rsp_len);
  2867. }
  2868. if (fxio->u.fxiocb.flags & SRB_FXDISC_REQ_DWRD_VALID) {
  2869. fx_iocb.dataword = fxio->u.fxiocb.req_data;
  2870. }
  2871. fx_iocb.flags = fxio->u.fxiocb.flags;
  2872. } else {
  2873. struct scatterlist *sg;
  2874. bsg_job = sp->u.bsg_job;
  2875. piocb_rqst = (struct qla_mt_iocb_rqst_fx00 *)
  2876. &bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  2877. fx_iocb.func_num = piocb_rqst->func_type;
  2878. fx_iocb.adapid = piocb_rqst->adapid;
  2879. fx_iocb.adapid_hi = piocb_rqst->adapid_hi;
  2880. fx_iocb.reserved_0 = piocb_rqst->reserved_0;
  2881. fx_iocb.reserved_1 = piocb_rqst->reserved_1;
  2882. fx_iocb.dataword_extra = piocb_rqst->dataword_extra;
  2883. fx_iocb.dataword = piocb_rqst->dataword;
  2884. fx_iocb.req_xfrcnt = piocb_rqst->req_len;
  2885. fx_iocb.rsp_xfrcnt = piocb_rqst->rsp_len;
  2886. if (piocb_rqst->flags & SRB_FXDISC_REQ_DMA_VALID) {
  2887. int avail_dsds, tot_dsds;
  2888. cont_a64_entry_t lcont_pkt;
  2889. cont_a64_entry_t *cont_pkt = NULL;
  2890. __le32 *cur_dsd;
  2891. int index = 0, cont = 0;
  2892. fx_iocb.req_dsdcnt =
  2893. cpu_to_le16(bsg_job->request_payload.sg_cnt);
  2894. tot_dsds =
  2895. bsg_job->request_payload.sg_cnt;
  2896. cur_dsd = (__le32 *)&fx_iocb.dseg_rq_address[0];
  2897. avail_dsds = 1;
  2898. for_each_sg(bsg_job->request_payload.sg_list, sg,
  2899. tot_dsds, index) {
  2900. dma_addr_t sle_dma;
  2901. /* Allocate additional continuation packets? */
  2902. if (avail_dsds == 0) {
  2903. /*
  2904. * Five DSDs are available in the Cont.
  2905. * Type 1 IOCB.
  2906. */
  2907. memset(&lcont_pkt, 0,
  2908. REQUEST_ENTRY_SIZE);
  2909. cont_pkt =
  2910. qlafx00_prep_cont_type1_iocb(
  2911. sp->fcport->vha->req,
  2912. &lcont_pkt);
  2913. cur_dsd = (__le32 *)
  2914. lcont_pkt.dseg_0_address;
  2915. avail_dsds = 5;
  2916. cont = 1;
  2917. entry_cnt++;
  2918. }
  2919. sle_dma = sg_dma_address(sg);
  2920. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2921. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2922. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2923. avail_dsds--;
  2924. if (avail_dsds == 0 && cont == 1) {
  2925. cont = 0;
  2926. memcpy_toio(
  2927. (void __iomem *)cont_pkt,
  2928. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2929. ql_dump_buffer(
  2930. ql_dbg_user + ql_dbg_verbose,
  2931. sp->fcport->vha, 0x3042,
  2932. (uint8_t *)&lcont_pkt,
  2933. REQUEST_ENTRY_SIZE);
  2934. }
  2935. }
  2936. if (avail_dsds != 0 && cont == 1) {
  2937. memcpy_toio((void __iomem *)cont_pkt,
  2938. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2939. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2940. sp->fcport->vha, 0x3043,
  2941. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2942. }
  2943. }
  2944. if (piocb_rqst->flags & SRB_FXDISC_RESP_DMA_VALID) {
  2945. int avail_dsds, tot_dsds;
  2946. cont_a64_entry_t lcont_pkt;
  2947. cont_a64_entry_t *cont_pkt = NULL;
  2948. __le32 *cur_dsd;
  2949. int index = 0, cont = 0;
  2950. fx_iocb.rsp_dsdcnt =
  2951. cpu_to_le16(bsg_job->reply_payload.sg_cnt);
  2952. tot_dsds = bsg_job->reply_payload.sg_cnt;
  2953. cur_dsd = (__le32 *)&fx_iocb.dseg_rsp_address[0];
  2954. avail_dsds = 1;
  2955. for_each_sg(bsg_job->reply_payload.sg_list, sg,
  2956. tot_dsds, index) {
  2957. dma_addr_t sle_dma;
  2958. /* Allocate additional continuation packets? */
  2959. if (avail_dsds == 0) {
  2960. /*
  2961. * Five DSDs are available in the Cont.
  2962. * Type 1 IOCB.
  2963. */
  2964. memset(&lcont_pkt, 0,
  2965. REQUEST_ENTRY_SIZE);
  2966. cont_pkt =
  2967. qlafx00_prep_cont_type1_iocb(
  2968. sp->fcport->vha->req,
  2969. &lcont_pkt);
  2970. cur_dsd = (__le32 *)
  2971. lcont_pkt.dseg_0_address;
  2972. avail_dsds = 5;
  2973. cont = 1;
  2974. entry_cnt++;
  2975. }
  2976. sle_dma = sg_dma_address(sg);
  2977. *cur_dsd++ = cpu_to_le32(LSD(sle_dma));
  2978. *cur_dsd++ = cpu_to_le32(MSD(sle_dma));
  2979. *cur_dsd++ = cpu_to_le32(sg_dma_len(sg));
  2980. avail_dsds--;
  2981. if (avail_dsds == 0 && cont == 1) {
  2982. cont = 0;
  2983. memcpy_toio((void __iomem *)cont_pkt,
  2984. &lcont_pkt,
  2985. REQUEST_ENTRY_SIZE);
  2986. ql_dump_buffer(
  2987. ql_dbg_user + ql_dbg_verbose,
  2988. sp->fcport->vha, 0x3045,
  2989. (uint8_t *)&lcont_pkt,
  2990. REQUEST_ENTRY_SIZE);
  2991. }
  2992. }
  2993. if (avail_dsds != 0 && cont == 1) {
  2994. memcpy_toio((void __iomem *)cont_pkt,
  2995. &lcont_pkt, REQUEST_ENTRY_SIZE);
  2996. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  2997. sp->fcport->vha, 0x3046,
  2998. (uint8_t *)&lcont_pkt, REQUEST_ENTRY_SIZE);
  2999. }
  3000. }
  3001. if (piocb_rqst->flags & SRB_FXDISC_REQ_DWRD_VALID)
  3002. fx_iocb.dataword = piocb_rqst->dataword;
  3003. fx_iocb.flags = piocb_rqst->flags;
  3004. fx_iocb.entry_count = entry_cnt;
  3005. }
  3006. ql_dump_buffer(ql_dbg_user + ql_dbg_verbose,
  3007. sp->fcport->vha, 0x3047,
  3008. (uint8_t *)&fx_iocb, sizeof(struct fxdisc_entry_fx00));
  3009. memcpy((void *)pfxiocb, &fx_iocb,
  3010. sizeof(struct fxdisc_entry_fx00));
  3011. wmb();
  3012. }