mii-bitbang.c 8.1 KB

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  1. /*
  2. * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
  3. *
  4. * Copyright (c) 2003 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * 2005 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public License
  11. * version 2. This program is licensed "as is" without any warranty of any
  12. * kind, whether express or implied.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/string.h>
  18. #include <linux/ptrace.h>
  19. #include <linux/errno.h>
  20. #include <linux/ioport.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/pci.h>
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/netdevice.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/skbuff.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/mii.h>
  31. #include <linux/ethtool.h>
  32. #include <linux/bitops.h>
  33. #include <linux/platform_device.h>
  34. #include <asm/pgtable.h>
  35. #include <asm/irq.h>
  36. #include <asm/uaccess.h>
  37. #include "fs_enet.h"
  38. static int bitbang_prep_bit(u8 **datp, u8 *mskp,
  39. struct fs_mii_bit *mii_bit)
  40. {
  41. void *dat;
  42. int adv;
  43. u8 msk;
  44. dat = (void*) mii_bit->offset;
  45. adv = mii_bit->bit >> 3;
  46. dat = (char *)dat + adv;
  47. msk = 1 << (7 - (mii_bit->bit & 7));
  48. *datp = dat;
  49. *mskp = msk;
  50. return 0;
  51. }
  52. static inline void bb_set(u8 *p, u8 m)
  53. {
  54. out_8(p, in_8(p) | m);
  55. }
  56. static inline void bb_clr(u8 *p, u8 m)
  57. {
  58. out_8(p, in_8(p) & ~m);
  59. }
  60. static inline int bb_read(u8 *p, u8 m)
  61. {
  62. return (in_8(p) & m) != 0;
  63. }
  64. static inline void mdio_active(struct bb_info *bitbang)
  65. {
  66. bb_set(bitbang->mdio_dir, bitbang->mdio_dir_msk);
  67. }
  68. static inline void mdio_tristate(struct bb_info *bitbang )
  69. {
  70. bb_clr(bitbang->mdio_dir, bitbang->mdio_dir_msk);
  71. }
  72. static inline int mdio_read(struct bb_info *bitbang )
  73. {
  74. return bb_read(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  75. }
  76. static inline void mdio(struct bb_info *bitbang , int what)
  77. {
  78. if (what)
  79. bb_set(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  80. else
  81. bb_clr(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  82. }
  83. static inline void mdc(struct bb_info *bitbang , int what)
  84. {
  85. if (what)
  86. bb_set(bitbang->mdc_dat, bitbang->mdc_msk);
  87. else
  88. bb_clr(bitbang->mdc_dat, bitbang->mdc_msk);
  89. }
  90. static inline void mii_delay(struct bb_info *bitbang )
  91. {
  92. udelay(bitbang->delay);
  93. }
  94. /* Utility to send the preamble, address, and register (common to read and write). */
  95. static void bitbang_pre(struct bb_info *bitbang , int read, u8 addr, u8 reg)
  96. {
  97. int j;
  98. /*
  99. * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
  100. * The IEEE spec says this is a PHY optional requirement. The AMD
  101. * 79C874 requires one after power up and one after a MII communications
  102. * error. This means that we are doing more preambles than we need,
  103. * but it is safer and will be much more robust.
  104. */
  105. mdio_active(bitbang);
  106. mdio(bitbang, 1);
  107. for (j = 0; j < 32; j++) {
  108. mdc(bitbang, 0);
  109. mii_delay(bitbang);
  110. mdc(bitbang, 1);
  111. mii_delay(bitbang);
  112. }
  113. /* send the start bit (01) and the read opcode (10) or write (10) */
  114. mdc(bitbang, 0);
  115. mdio(bitbang, 0);
  116. mii_delay(bitbang);
  117. mdc(bitbang, 1);
  118. mii_delay(bitbang);
  119. mdc(bitbang, 0);
  120. mdio(bitbang, 1);
  121. mii_delay(bitbang);
  122. mdc(bitbang, 1);
  123. mii_delay(bitbang);
  124. mdc(bitbang, 0);
  125. mdio(bitbang, read);
  126. mii_delay(bitbang);
  127. mdc(bitbang, 1);
  128. mii_delay(bitbang);
  129. mdc(bitbang, 0);
  130. mdio(bitbang, !read);
  131. mii_delay(bitbang);
  132. mdc(bitbang, 1);
  133. mii_delay(bitbang);
  134. /* send the PHY address */
  135. for (j = 0; j < 5; j++) {
  136. mdc(bitbang, 0);
  137. mdio(bitbang, (addr & 0x10) != 0);
  138. mii_delay(bitbang);
  139. mdc(bitbang, 1);
  140. mii_delay(bitbang);
  141. addr <<= 1;
  142. }
  143. /* send the register address */
  144. for (j = 0; j < 5; j++) {
  145. mdc(bitbang, 0);
  146. mdio(bitbang, (reg & 0x10) != 0);
  147. mii_delay(bitbang);
  148. mdc(bitbang, 1);
  149. mii_delay(bitbang);
  150. reg <<= 1;
  151. }
  152. }
  153. static int fs_enet_mii_bb_read(struct mii_bus *bus , int phy_id, int location)
  154. {
  155. u16 rdreg;
  156. int ret, j;
  157. u8 addr = phy_id & 0xff;
  158. u8 reg = location & 0xff;
  159. struct bb_info* bitbang = bus->priv;
  160. bitbang_pre(bitbang, 1, addr, reg);
  161. /* tri-state our MDIO I/O pin so we can read */
  162. mdc(bitbang, 0);
  163. mdio_tristate(bitbang);
  164. mii_delay(bitbang);
  165. mdc(bitbang, 1);
  166. mii_delay(bitbang);
  167. /* check the turnaround bit: the PHY should be driving it to zero */
  168. if (mdio_read(bitbang) != 0) {
  169. /* PHY didn't drive TA low */
  170. for (j = 0; j < 32; j++) {
  171. mdc(bitbang, 0);
  172. mii_delay(bitbang);
  173. mdc(bitbang, 1);
  174. mii_delay(bitbang);
  175. }
  176. ret = -1;
  177. goto out;
  178. }
  179. mdc(bitbang, 0);
  180. mii_delay(bitbang);
  181. /* read 16 bits of register data, MSB first */
  182. rdreg = 0;
  183. for (j = 0; j < 16; j++) {
  184. mdc(bitbang, 1);
  185. mii_delay(bitbang);
  186. rdreg <<= 1;
  187. rdreg |= mdio_read(bitbang);
  188. mdc(bitbang, 0);
  189. mii_delay(bitbang);
  190. }
  191. mdc(bitbang, 1);
  192. mii_delay(bitbang);
  193. mdc(bitbang, 0);
  194. mii_delay(bitbang);
  195. mdc(bitbang, 1);
  196. mii_delay(bitbang);
  197. ret = rdreg;
  198. out:
  199. return ret;
  200. }
  201. static int fs_enet_mii_bb_write(struct mii_bus *bus, int phy_id, int location, u16 val)
  202. {
  203. int j;
  204. struct bb_info* bitbang = bus->priv;
  205. u8 addr = phy_id & 0xff;
  206. u8 reg = location & 0xff;
  207. u16 value = val & 0xffff;
  208. bitbang_pre(bitbang, 0, addr, reg);
  209. /* send the turnaround (10) */
  210. mdc(bitbang, 0);
  211. mdio(bitbang, 1);
  212. mii_delay(bitbang);
  213. mdc(bitbang, 1);
  214. mii_delay(bitbang);
  215. mdc(bitbang, 0);
  216. mdio(bitbang, 0);
  217. mii_delay(bitbang);
  218. mdc(bitbang, 1);
  219. mii_delay(bitbang);
  220. /* write 16 bits of register data, MSB first */
  221. for (j = 0; j < 16; j++) {
  222. mdc(bitbang, 0);
  223. mdio(bitbang, (value & 0x8000) != 0);
  224. mii_delay(bitbang);
  225. mdc(bitbang, 1);
  226. mii_delay(bitbang);
  227. value <<= 1;
  228. }
  229. /*
  230. * Tri-state the MDIO line.
  231. */
  232. mdio_tristate(bitbang);
  233. mdc(bitbang, 0);
  234. mii_delay(bitbang);
  235. mdc(bitbang, 1);
  236. mii_delay(bitbang);
  237. return 0;
  238. }
  239. static int fs_enet_mii_bb_reset(struct mii_bus *bus)
  240. {
  241. /*nothing here - dunno how to reset it*/
  242. return 0;
  243. }
  244. static int fs_mii_bitbang_init(struct bb_info *bitbang, struct fs_mii_bb_platform_info* fmpi)
  245. {
  246. int r;
  247. bitbang->delay = fmpi->delay;
  248. r = bitbang_prep_bit(&bitbang->mdio_dir,
  249. &bitbang->mdio_dir_msk,
  250. &fmpi->mdio_dir);
  251. if (r != 0)
  252. return r;
  253. r = bitbang_prep_bit(&bitbang->mdio_dat,
  254. &bitbang->mdio_dat_msk,
  255. &fmpi->mdio_dat);
  256. if (r != 0)
  257. return r;
  258. r = bitbang_prep_bit(&bitbang->mdc_dat,
  259. &bitbang->mdc_msk,
  260. &fmpi->mdc_dat);
  261. if (r != 0)
  262. return r;
  263. return 0;
  264. }
  265. static int __devinit fs_enet_mdio_probe(struct device *dev)
  266. {
  267. struct platform_device *pdev = to_platform_device(dev);
  268. struct fs_mii_bb_platform_info *pdata;
  269. struct mii_bus *new_bus;
  270. struct bb_info *bitbang;
  271. int err = 0;
  272. if (NULL == dev)
  273. return -EINVAL;
  274. new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
  275. if (NULL == new_bus)
  276. return -ENOMEM;
  277. bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
  278. if (NULL == bitbang)
  279. return -ENOMEM;
  280. new_bus->name = "BB MII Bus",
  281. new_bus->read = &fs_enet_mii_bb_read,
  282. new_bus->write = &fs_enet_mii_bb_write,
  283. new_bus->reset = &fs_enet_mii_bb_reset,
  284. new_bus->id = pdev->id;
  285. new_bus->phy_mask = ~0x9;
  286. pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
  287. if (NULL == pdata) {
  288. printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
  289. return -ENODEV;
  290. }
  291. /*set up workspace*/
  292. fs_mii_bitbang_init(bitbang, pdata);
  293. new_bus->priv = bitbang;
  294. new_bus->irq = pdata->irq;
  295. new_bus->dev = dev;
  296. dev_set_drvdata(dev, new_bus);
  297. err = mdiobus_register(new_bus);
  298. if (0 != err) {
  299. printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
  300. new_bus->name);
  301. goto bus_register_fail;
  302. }
  303. return 0;
  304. bus_register_fail:
  305. kfree(bitbang);
  306. kfree(new_bus);
  307. return err;
  308. }
  309. static int fs_enet_mdio_remove(struct device *dev)
  310. {
  311. struct mii_bus *bus = dev_get_drvdata(dev);
  312. mdiobus_unregister(bus);
  313. dev_set_drvdata(dev, NULL);
  314. iounmap((void *) (&bus->priv));
  315. bus->priv = NULL;
  316. kfree(bus);
  317. return 0;
  318. }
  319. static struct device_driver fs_enet_bb_mdio_driver = {
  320. .name = "fsl-bb-mdio",
  321. .bus = &platform_bus_type,
  322. .probe = fs_enet_mdio_probe,
  323. .remove = fs_enet_mdio_remove,
  324. };
  325. int fs_enet_mdio_bb_init(void)
  326. {
  327. return driver_register(&fs_enet_bb_mdio_driver);
  328. }
  329. void fs_enet_mdio_bb_exit(void)
  330. {
  331. driver_unregister(&fs_enet_bb_mdio_driver);
  332. }