ab8500-core.c 18 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com>
  7. * Changes: Mattias Wallin <mattias.wallin@stericsson.com>
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/init.h>
  12. #include <linux/irq.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/mfd/core.h>
  18. #include <linux/mfd/abx500.h>
  19. #include <linux/mfd/ab8500.h>
  20. #include <linux/regulator/ab8500.h>
  21. /*
  22. * Interrupt register offsets
  23. * Bank : 0x0E
  24. */
  25. #define AB8500_IT_SOURCE1_REG 0x00
  26. #define AB8500_IT_SOURCE2_REG 0x01
  27. #define AB8500_IT_SOURCE3_REG 0x02
  28. #define AB8500_IT_SOURCE4_REG 0x03
  29. #define AB8500_IT_SOURCE5_REG 0x04
  30. #define AB8500_IT_SOURCE6_REG 0x05
  31. #define AB8500_IT_SOURCE7_REG 0x06
  32. #define AB8500_IT_SOURCE8_REG 0x07
  33. #define AB8500_IT_SOURCE19_REG 0x12
  34. #define AB8500_IT_SOURCE20_REG 0x13
  35. #define AB8500_IT_SOURCE21_REG 0x14
  36. #define AB8500_IT_SOURCE22_REG 0x15
  37. #define AB8500_IT_SOURCE23_REG 0x16
  38. #define AB8500_IT_SOURCE24_REG 0x17
  39. /*
  40. * latch registers
  41. */
  42. #define AB8500_IT_LATCH1_REG 0x20
  43. #define AB8500_IT_LATCH2_REG 0x21
  44. #define AB8500_IT_LATCH3_REG 0x22
  45. #define AB8500_IT_LATCH4_REG 0x23
  46. #define AB8500_IT_LATCH5_REG 0x24
  47. #define AB8500_IT_LATCH6_REG 0x25
  48. #define AB8500_IT_LATCH7_REG 0x26
  49. #define AB8500_IT_LATCH8_REG 0x27
  50. #define AB8500_IT_LATCH9_REG 0x28
  51. #define AB8500_IT_LATCH10_REG 0x29
  52. #define AB8500_IT_LATCH12_REG 0x2B
  53. #define AB8500_IT_LATCH19_REG 0x32
  54. #define AB8500_IT_LATCH20_REG 0x33
  55. #define AB8500_IT_LATCH21_REG 0x34
  56. #define AB8500_IT_LATCH22_REG 0x35
  57. #define AB8500_IT_LATCH23_REG 0x36
  58. #define AB8500_IT_LATCH24_REG 0x37
  59. /*
  60. * mask registers
  61. */
  62. #define AB8500_IT_MASK1_REG 0x40
  63. #define AB8500_IT_MASK2_REG 0x41
  64. #define AB8500_IT_MASK3_REG 0x42
  65. #define AB8500_IT_MASK4_REG 0x43
  66. #define AB8500_IT_MASK5_REG 0x44
  67. #define AB8500_IT_MASK6_REG 0x45
  68. #define AB8500_IT_MASK7_REG 0x46
  69. #define AB8500_IT_MASK8_REG 0x47
  70. #define AB8500_IT_MASK9_REG 0x48
  71. #define AB8500_IT_MASK10_REG 0x49
  72. #define AB8500_IT_MASK11_REG 0x4A
  73. #define AB8500_IT_MASK12_REG 0x4B
  74. #define AB8500_IT_MASK13_REG 0x4C
  75. #define AB8500_IT_MASK14_REG 0x4D
  76. #define AB8500_IT_MASK15_REG 0x4E
  77. #define AB8500_IT_MASK16_REG 0x4F
  78. #define AB8500_IT_MASK17_REG 0x50
  79. #define AB8500_IT_MASK18_REG 0x51
  80. #define AB8500_IT_MASK19_REG 0x52
  81. #define AB8500_IT_MASK20_REG 0x53
  82. #define AB8500_IT_MASK21_REG 0x54
  83. #define AB8500_IT_MASK22_REG 0x55
  84. #define AB8500_IT_MASK23_REG 0x56
  85. #define AB8500_IT_MASK24_REG 0x57
  86. #define AB8500_REV_REG 0x80
  87. /*
  88. * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt
  89. * numbers are indexed into this array with (num / 8).
  90. *
  91. * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at
  92. * offset 0.
  93. */
  94. static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = {
  95. 0, 1, 2, 3, 4, 6, 7, 8, 9, 11, 18, 19, 20, 21,
  96. };
  97. static int ab8500_get_chip_id(struct device *dev)
  98. {
  99. struct ab8500 *ab8500;
  100. if (!dev)
  101. return -EINVAL;
  102. ab8500 = dev_get_drvdata(dev->parent);
  103. return ab8500 ? (int)ab8500->chip_id : -EINVAL;
  104. }
  105. static int set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  106. u8 reg, u8 data)
  107. {
  108. int ret;
  109. /*
  110. * Put the u8 bank and u8 register together into a an u16.
  111. * The bank on higher 8 bits and register in lower 8 bits.
  112. * */
  113. u16 addr = ((u16)bank) << 8 | reg;
  114. dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data);
  115. ret = mutex_lock_interruptible(&ab8500->lock);
  116. if (ret)
  117. return ret;
  118. ret = ab8500->write(ab8500, addr, data);
  119. if (ret < 0)
  120. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  121. addr, ret);
  122. mutex_unlock(&ab8500->lock);
  123. return ret;
  124. }
  125. static int ab8500_set_register(struct device *dev, u8 bank,
  126. u8 reg, u8 value)
  127. {
  128. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  129. return set_register_interruptible(ab8500, bank, reg, value);
  130. }
  131. static int get_register_interruptible(struct ab8500 *ab8500, u8 bank,
  132. u8 reg, u8 *value)
  133. {
  134. int ret;
  135. /* put the u8 bank and u8 reg together into a an u16.
  136. * bank on higher 8 bits and reg in lower */
  137. u16 addr = ((u16)bank) << 8 | reg;
  138. ret = mutex_lock_interruptible(&ab8500->lock);
  139. if (ret)
  140. return ret;
  141. ret = ab8500->read(ab8500, addr);
  142. if (ret < 0)
  143. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  144. addr, ret);
  145. else
  146. *value = ret;
  147. mutex_unlock(&ab8500->lock);
  148. dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret);
  149. return ret;
  150. }
  151. static int ab8500_get_register(struct device *dev, u8 bank,
  152. u8 reg, u8 *value)
  153. {
  154. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  155. return get_register_interruptible(ab8500, bank, reg, value);
  156. }
  157. static int mask_and_set_register_interruptible(struct ab8500 *ab8500, u8 bank,
  158. u8 reg, u8 bitmask, u8 bitvalues)
  159. {
  160. int ret;
  161. u8 data;
  162. /* put the u8 bank and u8 reg together into a an u16.
  163. * bank on higher 8 bits and reg in lower */
  164. u16 addr = ((u16)bank) << 8 | reg;
  165. ret = mutex_lock_interruptible(&ab8500->lock);
  166. if (ret)
  167. return ret;
  168. ret = ab8500->read(ab8500, addr);
  169. if (ret < 0) {
  170. dev_err(ab8500->dev, "failed to read reg %#x: %d\n",
  171. addr, ret);
  172. goto out;
  173. }
  174. data = (u8)ret;
  175. data = (~bitmask & data) | (bitmask & bitvalues);
  176. ret = ab8500->write(ab8500, addr, data);
  177. if (ret < 0)
  178. dev_err(ab8500->dev, "failed to write reg %#x: %d\n",
  179. addr, ret);
  180. dev_vdbg(ab8500->dev, "mask: addr %#x => data %#x\n", addr, data);
  181. out:
  182. mutex_unlock(&ab8500->lock);
  183. return ret;
  184. }
  185. static int ab8500_mask_and_set_register(struct device *dev,
  186. u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
  187. {
  188. struct ab8500 *ab8500 = dev_get_drvdata(dev->parent);
  189. return mask_and_set_register_interruptible(ab8500, bank, reg,
  190. bitmask, bitvalues);
  191. }
  192. static struct abx500_ops ab8500_ops = {
  193. .get_chip_id = ab8500_get_chip_id,
  194. .get_register = ab8500_get_register,
  195. .set_register = ab8500_set_register,
  196. .get_register_page = NULL,
  197. .set_register_page = NULL,
  198. .mask_and_set_register = ab8500_mask_and_set_register,
  199. .event_registers_startup_state_get = NULL,
  200. .startup_irq_enabled = NULL,
  201. };
  202. static void ab8500_irq_lock(struct irq_data *data)
  203. {
  204. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  205. mutex_lock(&ab8500->irq_lock);
  206. }
  207. static void ab8500_irq_sync_unlock(struct irq_data *data)
  208. {
  209. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  210. int i;
  211. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  212. u8 old = ab8500->oldmask[i];
  213. u8 new = ab8500->mask[i];
  214. int reg;
  215. if (new == old)
  216. continue;
  217. /* Interrupt register 12 does'nt exist prior to version 0x20 */
  218. if (ab8500_irq_regoffset[i] == 11 && ab8500->chip_id < 0x20)
  219. continue;
  220. ab8500->oldmask[i] = new;
  221. reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i];
  222. set_register_interruptible(ab8500, AB8500_INTERRUPT, reg, new);
  223. }
  224. mutex_unlock(&ab8500->irq_lock);
  225. }
  226. static void ab8500_irq_mask(struct irq_data *data)
  227. {
  228. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  229. int offset = data->irq - ab8500->irq_base;
  230. int index = offset / 8;
  231. int mask = 1 << (offset % 8);
  232. ab8500->mask[index] |= mask;
  233. }
  234. static void ab8500_irq_unmask(struct irq_data *data)
  235. {
  236. struct ab8500 *ab8500 = irq_data_get_irq_chip_data(data);
  237. int offset = data->irq - ab8500->irq_base;
  238. int index = offset / 8;
  239. int mask = 1 << (offset % 8);
  240. ab8500->mask[index] &= ~mask;
  241. }
  242. static struct irq_chip ab8500_irq_chip = {
  243. .name = "ab8500",
  244. .irq_bus_lock = ab8500_irq_lock,
  245. .irq_bus_sync_unlock = ab8500_irq_sync_unlock,
  246. .irq_mask = ab8500_irq_mask,
  247. .irq_unmask = ab8500_irq_unmask,
  248. };
  249. static irqreturn_t ab8500_irq(int irq, void *dev)
  250. {
  251. struct ab8500 *ab8500 = dev;
  252. int i;
  253. dev_vdbg(ab8500->dev, "interrupt\n");
  254. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  255. int regoffset = ab8500_irq_regoffset[i];
  256. int status;
  257. u8 value;
  258. /* Interrupt register 12 does'nt exist prior to version 0x20 */
  259. if (regoffset == 11 && ab8500->chip_id < 0x20)
  260. continue;
  261. status = get_register_interruptible(ab8500, AB8500_INTERRUPT,
  262. AB8500_IT_LATCH1_REG + regoffset, &value);
  263. if (status < 0 || value == 0)
  264. continue;
  265. do {
  266. int bit = __ffs(value);
  267. int line = i * 8 + bit;
  268. handle_nested_irq(ab8500->irq_base + line);
  269. value &= ~(1 << bit);
  270. } while (value);
  271. }
  272. return IRQ_HANDLED;
  273. }
  274. static int ab8500_irq_init(struct ab8500 *ab8500)
  275. {
  276. int base = ab8500->irq_base;
  277. int irq;
  278. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  279. set_irq_chip_data(irq, ab8500);
  280. set_irq_chip_and_handler(irq, &ab8500_irq_chip,
  281. handle_simple_irq);
  282. set_irq_nested_thread(irq, 1);
  283. #ifdef CONFIG_ARM
  284. set_irq_flags(irq, IRQF_VALID);
  285. #else
  286. set_irq_noprobe(irq);
  287. #endif
  288. }
  289. return 0;
  290. }
  291. static void ab8500_irq_remove(struct ab8500 *ab8500)
  292. {
  293. int base = ab8500->irq_base;
  294. int irq;
  295. for (irq = base; irq < base + AB8500_NR_IRQS; irq++) {
  296. #ifdef CONFIG_ARM
  297. set_irq_flags(irq, 0);
  298. #endif
  299. set_irq_chip_and_handler(irq, NULL, NULL);
  300. set_irq_chip_data(irq, NULL);
  301. }
  302. }
  303. static struct resource ab8500_gpadc_resources[] = {
  304. {
  305. .name = "HW_CONV_END",
  306. .start = AB8500_INT_GP_HW_ADC_CONV_END,
  307. .end = AB8500_INT_GP_HW_ADC_CONV_END,
  308. .flags = IORESOURCE_IRQ,
  309. },
  310. {
  311. .name = "SW_CONV_END",
  312. .start = AB8500_INT_GP_SW_ADC_CONV_END,
  313. .end = AB8500_INT_GP_SW_ADC_CONV_END,
  314. .flags = IORESOURCE_IRQ,
  315. },
  316. };
  317. static struct resource ab8500_rtc_resources[] = {
  318. {
  319. .name = "60S",
  320. .start = AB8500_INT_RTC_60S,
  321. .end = AB8500_INT_RTC_60S,
  322. .flags = IORESOURCE_IRQ,
  323. },
  324. {
  325. .name = "ALARM",
  326. .start = AB8500_INT_RTC_ALARM,
  327. .end = AB8500_INT_RTC_ALARM,
  328. .flags = IORESOURCE_IRQ,
  329. },
  330. };
  331. static struct resource ab8500_poweronkey_db_resources[] = {
  332. {
  333. .name = "ONKEY_DBF",
  334. .start = AB8500_INT_PON_KEY1DB_F,
  335. .end = AB8500_INT_PON_KEY1DB_F,
  336. .flags = IORESOURCE_IRQ,
  337. },
  338. {
  339. .name = "ONKEY_DBR",
  340. .start = AB8500_INT_PON_KEY1DB_R,
  341. .end = AB8500_INT_PON_KEY1DB_R,
  342. .flags = IORESOURCE_IRQ,
  343. },
  344. };
  345. static struct resource ab8500_bm_resources[] = {
  346. {
  347. .name = "MAIN_EXT_CH_NOT_OK",
  348. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  349. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  350. .flags = IORESOURCE_IRQ,
  351. },
  352. {
  353. .name = "BATT_OVV",
  354. .start = AB8500_INT_BATT_OVV,
  355. .end = AB8500_INT_BATT_OVV,
  356. .flags = IORESOURCE_IRQ,
  357. },
  358. {
  359. .name = "MAIN_CH_UNPLUG_DET",
  360. .start = AB8500_INT_MAIN_CH_UNPLUG_DET,
  361. .end = AB8500_INT_MAIN_CH_UNPLUG_DET,
  362. .flags = IORESOURCE_IRQ,
  363. },
  364. {
  365. .name = "MAIN_CHARGE_PLUG_DET",
  366. .start = AB8500_INT_MAIN_CH_PLUG_DET,
  367. .end = AB8500_INT_MAIN_CH_PLUG_DET,
  368. .flags = IORESOURCE_IRQ,
  369. },
  370. {
  371. .name = "VBUS_DET_F",
  372. .start = AB8500_INT_VBUS_DET_F,
  373. .end = AB8500_INT_VBUS_DET_F,
  374. .flags = IORESOURCE_IRQ,
  375. },
  376. {
  377. .name = "VBUS_DET_R",
  378. .start = AB8500_INT_VBUS_DET_R,
  379. .end = AB8500_INT_VBUS_DET_R,
  380. .flags = IORESOURCE_IRQ,
  381. },
  382. {
  383. .name = "BAT_CTRL_INDB",
  384. .start = AB8500_INT_BAT_CTRL_INDB,
  385. .end = AB8500_INT_BAT_CTRL_INDB,
  386. .flags = IORESOURCE_IRQ,
  387. },
  388. {
  389. .name = "CH_WD_EXP",
  390. .start = AB8500_INT_CH_WD_EXP,
  391. .end = AB8500_INT_CH_WD_EXP,
  392. .flags = IORESOURCE_IRQ,
  393. },
  394. {
  395. .name = "VBUS_OVV",
  396. .start = AB8500_INT_VBUS_OVV,
  397. .end = AB8500_INT_VBUS_OVV,
  398. .flags = IORESOURCE_IRQ,
  399. },
  400. {
  401. .name = "NCONV_ACCU",
  402. .start = AB8500_INT_CCN_CONV_ACC,
  403. .end = AB8500_INT_CCN_CONV_ACC,
  404. .flags = IORESOURCE_IRQ,
  405. },
  406. {
  407. .name = "LOW_BAT_F",
  408. .start = AB8500_INT_LOW_BAT_F,
  409. .end = AB8500_INT_LOW_BAT_F,
  410. .flags = IORESOURCE_IRQ,
  411. },
  412. {
  413. .name = "LOW_BAT_R",
  414. .start = AB8500_INT_LOW_BAT_R,
  415. .end = AB8500_INT_LOW_BAT_R,
  416. .flags = IORESOURCE_IRQ,
  417. },
  418. {
  419. .name = "BTEMP_LOW",
  420. .start = AB8500_INT_BTEMP_LOW,
  421. .end = AB8500_INT_BTEMP_LOW,
  422. .flags = IORESOURCE_IRQ,
  423. },
  424. {
  425. .name = "BTEMP_HIGH",
  426. .start = AB8500_INT_BTEMP_HIGH,
  427. .end = AB8500_INT_BTEMP_HIGH,
  428. .flags = IORESOURCE_IRQ,
  429. },
  430. {
  431. .name = "USB_CHARGER_NOT_OKR",
  432. .start = AB8500_INT_USB_CHARGER_NOT_OK,
  433. .end = AB8500_INT_USB_CHARGER_NOT_OK,
  434. .flags = IORESOURCE_IRQ,
  435. },
  436. {
  437. .name = "USB_CHARGE_DET_DONE",
  438. .start = AB8500_INT_USB_CHG_DET_DONE,
  439. .end = AB8500_INT_USB_CHG_DET_DONE,
  440. .flags = IORESOURCE_IRQ,
  441. },
  442. {
  443. .name = "USB_CH_TH_PROT_R",
  444. .start = AB8500_INT_USB_CH_TH_PROT_R,
  445. .end = AB8500_INT_USB_CH_TH_PROT_R,
  446. .flags = IORESOURCE_IRQ,
  447. },
  448. {
  449. .name = "MAIN_CH_TH_PROT_R",
  450. .start = AB8500_INT_MAIN_CH_TH_PROT_R,
  451. .end = AB8500_INT_MAIN_CH_TH_PROT_R,
  452. .flags = IORESOURCE_IRQ,
  453. },
  454. {
  455. .name = "USB_CHARGER_NOT_OKF",
  456. .start = AB8500_INT_USB_CHARGER_NOT_OKF,
  457. .end = AB8500_INT_USB_CHARGER_NOT_OKF,
  458. .flags = IORESOURCE_IRQ,
  459. },
  460. };
  461. static struct resource ab8500_debug_resources[] = {
  462. {
  463. .name = "IRQ_FIRST",
  464. .start = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  465. .end = AB8500_INT_MAIN_EXT_CH_NOT_OK,
  466. .flags = IORESOURCE_IRQ,
  467. },
  468. {
  469. .name = "IRQ_LAST",
  470. .start = AB8500_INT_USB_CHARGER_NOT_OKF,
  471. .end = AB8500_INT_USB_CHARGER_NOT_OKF,
  472. .flags = IORESOURCE_IRQ,
  473. },
  474. };
  475. static struct resource ab8500_usb_resources[] = {
  476. {
  477. .name = "ID_WAKEUP_R",
  478. .start = AB8500_INT_ID_WAKEUP_R,
  479. .end = AB8500_INT_ID_WAKEUP_R,
  480. .flags = IORESOURCE_IRQ,
  481. },
  482. {
  483. .name = "ID_WAKEUP_F",
  484. .start = AB8500_INT_ID_WAKEUP_F,
  485. .end = AB8500_INT_ID_WAKEUP_F,
  486. .flags = IORESOURCE_IRQ,
  487. },
  488. {
  489. .name = "VBUS_DET_F",
  490. .start = AB8500_INT_VBUS_DET_F,
  491. .end = AB8500_INT_VBUS_DET_F,
  492. .flags = IORESOURCE_IRQ,
  493. },
  494. {
  495. .name = "VBUS_DET_R",
  496. .start = AB8500_INT_VBUS_DET_R,
  497. .end = AB8500_INT_VBUS_DET_R,
  498. .flags = IORESOURCE_IRQ,
  499. },
  500. {
  501. .name = "USB_LINK_STATUS",
  502. .start = AB8500_INT_USB_LINK_STATUS,
  503. .end = AB8500_INT_USB_LINK_STATUS,
  504. .flags = IORESOURCE_IRQ,
  505. },
  506. };
  507. static struct resource ab8500_temp_resources[] = {
  508. {
  509. .name = "AB8500_TEMP_WARM",
  510. .start = AB8500_INT_TEMP_WARM,
  511. .end = AB8500_INT_TEMP_WARM,
  512. .flags = IORESOURCE_IRQ,
  513. },
  514. };
  515. static struct mfd_cell ab8500_devs[] = {
  516. #ifdef CONFIG_DEBUG_FS
  517. {
  518. .name = "ab8500-debug",
  519. .num_resources = ARRAY_SIZE(ab8500_debug_resources),
  520. .resources = ab8500_debug_resources,
  521. },
  522. #endif
  523. {
  524. .name = "ab8500-sysctrl",
  525. },
  526. {
  527. .name = "ab8500-regulator",
  528. },
  529. {
  530. .name = "ab8500-gpadc",
  531. .num_resources = ARRAY_SIZE(ab8500_gpadc_resources),
  532. .resources = ab8500_gpadc_resources,
  533. },
  534. {
  535. .name = "ab8500-rtc",
  536. .num_resources = ARRAY_SIZE(ab8500_rtc_resources),
  537. .resources = ab8500_rtc_resources,
  538. },
  539. {
  540. .name = "ab8500-bm",
  541. .num_resources = ARRAY_SIZE(ab8500_bm_resources),
  542. .resources = ab8500_bm_resources,
  543. },
  544. { .name = "ab8500-codec", },
  545. {
  546. .name = "ab8500-usb",
  547. .num_resources = ARRAY_SIZE(ab8500_usb_resources),
  548. .resources = ab8500_usb_resources,
  549. },
  550. {
  551. .name = "ab8500-poweron-key",
  552. .num_resources = ARRAY_SIZE(ab8500_poweronkey_db_resources),
  553. .resources = ab8500_poweronkey_db_resources,
  554. },
  555. {
  556. .name = "ab8500-pwm",
  557. .id = 1,
  558. },
  559. {
  560. .name = "ab8500-pwm",
  561. .id = 2,
  562. },
  563. {
  564. .name = "ab8500-pwm",
  565. .id = 3,
  566. },
  567. { .name = "ab8500-leds", },
  568. {
  569. .name = "ab8500-denc",
  570. },
  571. {
  572. .name = "ab8500-temp",
  573. .num_resources = ARRAY_SIZE(ab8500_temp_resources),
  574. .resources = ab8500_temp_resources,
  575. },
  576. };
  577. static ssize_t show_chip_id(struct device *dev,
  578. struct device_attribute *attr, char *buf)
  579. {
  580. struct ab8500 *ab8500;
  581. ab8500 = dev_get_drvdata(dev);
  582. return sprintf(buf, "%#x\n", ab8500 ? ab8500->chip_id : -EINVAL);
  583. }
  584. static DEVICE_ATTR(chip_id, S_IRUGO, show_chip_id, NULL);
  585. static struct attribute *ab8500_sysfs_entries[] = {
  586. &dev_attr_chip_id.attr,
  587. NULL,
  588. };
  589. static struct attribute_group ab8500_attr_group = {
  590. .attrs = ab8500_sysfs_entries,
  591. };
  592. int __devinit ab8500_init(struct ab8500 *ab8500)
  593. {
  594. struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev);
  595. int ret;
  596. int i;
  597. u8 value;
  598. if (plat)
  599. ab8500->irq_base = plat->irq_base;
  600. mutex_init(&ab8500->lock);
  601. mutex_init(&ab8500->irq_lock);
  602. ret = get_register_interruptible(ab8500, AB8500_MISC,
  603. AB8500_REV_REG, &value);
  604. if (ret < 0)
  605. return ret;
  606. /*
  607. * 0x0 - Early Drop
  608. * 0x10 - Cut 1.0
  609. * 0x11 - Cut 1.1
  610. * 0x20 - Cut 2.0
  611. */
  612. if (value == 0x0 || value == 0x10 || value == 0x11 || value == 0x20) {
  613. ab8500->revision = value;
  614. dev_info(ab8500->dev, "detected chip, revision: %#x\n", value);
  615. } else {
  616. dev_err(ab8500->dev, "unknown chip, revision: %#x\n", value);
  617. return -EINVAL;
  618. }
  619. ab8500->chip_id = value;
  620. if (plat && plat->init)
  621. plat->init(ab8500);
  622. /* Clear and mask all interrupts */
  623. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) {
  624. /* Interrupt register 12 does'nt exist prior to version 0x20 */
  625. if (ab8500_irq_regoffset[i] == 11 && ab8500->chip_id < 0x20)
  626. continue;
  627. get_register_interruptible(ab8500, AB8500_INTERRUPT,
  628. AB8500_IT_LATCH1_REG + ab8500_irq_regoffset[i],
  629. &value);
  630. set_register_interruptible(ab8500, AB8500_INTERRUPT,
  631. AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i], 0xff);
  632. }
  633. ret = abx500_register_ops(ab8500->dev, &ab8500_ops);
  634. if (ret)
  635. return ret;
  636. for (i = 0; i < AB8500_NUM_IRQ_REGS; i++)
  637. ab8500->mask[i] = ab8500->oldmask[i] = 0xff;
  638. if (ab8500->irq_base) {
  639. ret = ab8500_irq_init(ab8500);
  640. if (ret)
  641. return ret;
  642. ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq,
  643. IRQF_ONESHOT | IRQF_NO_SUSPEND,
  644. "ab8500", ab8500);
  645. if (ret)
  646. goto out_removeirq;
  647. }
  648. ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs,
  649. ARRAY_SIZE(ab8500_devs), NULL,
  650. ab8500->irq_base);
  651. if (ret)
  652. goto out_freeirq;
  653. ret = sysfs_create_group(&ab8500->dev->kobj, &ab8500_attr_group);
  654. if (ret)
  655. dev_err(ab8500->dev, "error creating sysfs entries\n");
  656. return ret;
  657. out_freeirq:
  658. if (ab8500->irq_base) {
  659. free_irq(ab8500->irq, ab8500);
  660. out_removeirq:
  661. ab8500_irq_remove(ab8500);
  662. }
  663. return ret;
  664. }
  665. int __devexit ab8500_exit(struct ab8500 *ab8500)
  666. {
  667. sysfs_remove_group(&ab8500->dev->kobj, &ab8500_attr_group);
  668. mfd_remove_devices(ab8500->dev);
  669. if (ab8500->irq_base) {
  670. free_irq(ab8500->irq, ab8500);
  671. ab8500_irq_remove(ab8500);
  672. }
  673. return 0;
  674. }
  675. MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent");
  676. MODULE_DESCRIPTION("AB8500 MFD core");
  677. MODULE_LICENSE("GPL v2");