bfin_5xx.c 32 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327
  1. /*
  2. * Blackfin On-Chip Serial Driver
  3. *
  4. * Copyright 2006-2007 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  11. #define SUPPORT_SYSRQ
  12. #endif
  13. #include <linux/module.h>
  14. #include <linux/ioport.h>
  15. #include <linux/init.h>
  16. #include <linux/console.h>
  17. #include <linux/sysrq.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/tty.h>
  20. #include <linux/tty_flip.h>
  21. #include <linux/serial_core.h>
  22. #ifdef CONFIG_KGDB_UART
  23. #include <linux/kgdb.h>
  24. #include <asm/irq_regs.h>
  25. #endif
  26. #include <asm/gpio.h>
  27. #include <asm/mach/bfin_serial_5xx.h>
  28. #ifdef CONFIG_SERIAL_BFIN_DMA
  29. #include <linux/dma-mapping.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <asm/cacheflush.h>
  33. #endif
  34. /* UART name and device definitions */
  35. #define BFIN_SERIAL_NAME "ttyBF"
  36. #define BFIN_SERIAL_MAJOR 204
  37. #define BFIN_SERIAL_MINOR 64
  38. /*
  39. * Setup for console. Argument comes from the menuconfig
  40. */
  41. #define DMA_RX_XCOUNT 512
  42. #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
  43. #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
  44. #ifdef CONFIG_SERIAL_BFIN_DMA
  45. static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
  46. #else
  47. static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
  48. #endif
  49. static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
  50. /*
  51. * interrupts are disabled on entry
  52. */
  53. static void bfin_serial_stop_tx(struct uart_port *port)
  54. {
  55. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  56. struct circ_buf *xmit = &uart->port.info->xmit;
  57. #if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA)
  58. unsigned short ier;
  59. #endif
  60. while (!(UART_GET_LSR(uart) & TEMT))
  61. cpu_relax();
  62. #ifdef CONFIG_SERIAL_BFIN_DMA
  63. disable_dma(uart->tx_dma_channel);
  64. xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
  65. uart->port.icount.tx += uart->tx_count;
  66. uart->tx_count = 0;
  67. uart->tx_done = 1;
  68. #else
  69. #ifdef CONFIG_BF54x
  70. /* Clear TFI bit */
  71. UART_PUT_LSR(uart, TFI);
  72. UART_CLEAR_IER(uart, ETBEI);
  73. #else
  74. ier = UART_GET_IER(uart);
  75. ier &= ~ETBEI;
  76. UART_PUT_IER(uart, ier);
  77. #endif
  78. #endif
  79. }
  80. /*
  81. * port is locked and interrupts are disabled
  82. */
  83. static void bfin_serial_start_tx(struct uart_port *port)
  84. {
  85. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  86. #ifdef CONFIG_SERIAL_BFIN_DMA
  87. if (uart->tx_done)
  88. bfin_serial_dma_tx_chars(uart);
  89. #else
  90. #ifdef CONFIG_BF54x
  91. UART_SET_IER(uart, ETBEI);
  92. #else
  93. unsigned short ier;
  94. ier = UART_GET_IER(uart);
  95. ier |= ETBEI;
  96. UART_PUT_IER(uart, ier);
  97. #endif
  98. bfin_serial_tx_chars(uart);
  99. #endif
  100. }
  101. /*
  102. * Interrupts are enabled
  103. */
  104. static void bfin_serial_stop_rx(struct uart_port *port)
  105. {
  106. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  107. #ifdef CONFIG_KGDB_UART
  108. if (uart->port.line != CONFIG_KGDB_UART_PORT) {
  109. #endif
  110. #ifdef CONFIG_BF54x
  111. UART_CLEAR_IER(uart, ERBFI);
  112. #else
  113. unsigned short ier;
  114. ier = UART_GET_IER(uart);
  115. ier &= ~ERBFI;
  116. UART_PUT_IER(uart, ier);
  117. #endif
  118. #ifdef CONFIG_KGDB_UART
  119. }
  120. #endif
  121. }
  122. /*
  123. * Set the modem control timer to fire immediately.
  124. */
  125. static void bfin_serial_enable_ms(struct uart_port *port)
  126. {
  127. }
  128. #ifdef CONFIG_KGDB_UART
  129. static int kgdb_entry_state;
  130. void kgdb_put_debug_char(int chr)
  131. {
  132. struct bfin_serial_port *uart;
  133. if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
  134. uart = &bfin_serial_ports[0];
  135. else
  136. uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
  137. while (!(UART_GET_LSR(uart) & THRE)) {
  138. SSYNC();
  139. }
  140. #ifndef CONFIG_BF54x
  141. UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
  142. SSYNC();
  143. #endif
  144. UART_PUT_CHAR(uart, (unsigned char)chr);
  145. SSYNC();
  146. }
  147. int kgdb_get_debug_char(void)
  148. {
  149. struct bfin_serial_port *uart;
  150. unsigned char chr;
  151. if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
  152. uart = &bfin_serial_ports[0];
  153. else
  154. uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
  155. while(!(UART_GET_LSR(uart) & DR)) {
  156. SSYNC();
  157. }
  158. #ifndef CONFIG_BF54x
  159. UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
  160. SSYNC();
  161. #endif
  162. chr = UART_GET_CHAR(uart);
  163. SSYNC();
  164. return chr;
  165. }
  166. #endif
  167. #if ANOMALY_05000230 && defined(CONFIG_SERIAL_BFIN_PIO)
  168. # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
  169. # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
  170. #else
  171. # define UART_GET_ANOMALY_THRESHOLD(uart) 0
  172. # define UART_SET_ANOMALY_THRESHOLD(uart, v)
  173. #endif
  174. #ifdef CONFIG_SERIAL_BFIN_PIO
  175. static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
  176. {
  177. struct tty_struct *tty = uart->port.info->tty;
  178. unsigned int status, ch, flg;
  179. static struct timeval anomaly_start = { .tv_sec = 0 };
  180. #ifdef CONFIG_KGDB_UART
  181. struct pt_regs *regs = get_irq_regs();
  182. #endif
  183. status = UART_GET_LSR(uart);
  184. UART_CLEAR_LSR(uart);
  185. ch = UART_GET_CHAR(uart);
  186. uart->port.icount.rx++;
  187. #ifdef CONFIG_KGDB_UART
  188. if (uart->port.line == CONFIG_KGDB_UART_PORT) {
  189. if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
  190. kgdb_breakkey_pressed(regs);
  191. return;
  192. } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
  193. kgdb_entry_state = 1;
  194. } else if (kgdb_entry_state == 1 && ch == 'q') {
  195. kgdb_entry_state = 0;
  196. kgdb_breakkey_pressed(regs);
  197. return;
  198. } else if (ch == 0x3) {/* Ctrl + C */
  199. kgdb_entry_state = 0;
  200. kgdb_breakkey_pressed(regs);
  201. return;
  202. } else {
  203. kgdb_entry_state = 0;
  204. }
  205. }
  206. #endif
  207. if (ANOMALY_05000230) {
  208. /* The BF533 (and BF561) family of processors have a nice anomaly
  209. * where they continuously generate characters for a "single" break.
  210. * We have to basically ignore this flood until the "next" valid
  211. * character comes across. Due to the nature of the flood, it is
  212. * not possible to reliably catch bytes that are sent too quickly
  213. * after this break. So application code talking to the Blackfin
  214. * which sends a break signal must allow at least 1.5 character
  215. * times after the end of the break for things to stabilize. This
  216. * timeout was picked as it must absolutely be larger than 1
  217. * character time +/- some percent. So 1.5 sounds good. All other
  218. * Blackfin families operate properly. Woo.
  219. * Note: While Anomaly 05000230 does not directly address this,
  220. * the changes that went in for it also fixed this issue.
  221. * That anomaly was fixed in 0.5+ silicon. I like bunnies.
  222. */
  223. if (anomaly_start.tv_sec) {
  224. struct timeval curr;
  225. suseconds_t usecs;
  226. if ((~ch & (~ch + 1)) & 0xff)
  227. goto known_good_char;
  228. do_gettimeofday(&curr);
  229. if (curr.tv_sec - anomaly_start.tv_sec > 1)
  230. goto known_good_char;
  231. usecs = 0;
  232. if (curr.tv_sec != anomaly_start.tv_sec)
  233. usecs += USEC_PER_SEC;
  234. usecs += curr.tv_usec - anomaly_start.tv_usec;
  235. if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
  236. goto known_good_char;
  237. if (ch)
  238. anomaly_start.tv_sec = 0;
  239. else
  240. anomaly_start = curr;
  241. return;
  242. known_good_char:
  243. anomaly_start.tv_sec = 0;
  244. }
  245. }
  246. if (status & BI) {
  247. if (ANOMALY_05000230)
  248. if (bfin_revid() < 5)
  249. do_gettimeofday(&anomaly_start);
  250. uart->port.icount.brk++;
  251. if (uart_handle_break(&uart->port))
  252. goto ignore_char;
  253. status &= ~(PE | FE);
  254. }
  255. if (status & PE)
  256. uart->port.icount.parity++;
  257. if (status & OE)
  258. uart->port.icount.overrun++;
  259. if (status & FE)
  260. uart->port.icount.frame++;
  261. status &= uart->port.read_status_mask;
  262. if (status & BI)
  263. flg = TTY_BREAK;
  264. else if (status & PE)
  265. flg = TTY_PARITY;
  266. else if (status & FE)
  267. flg = TTY_FRAME;
  268. else
  269. flg = TTY_NORMAL;
  270. if (uart_handle_sysrq_char(&uart->port, ch))
  271. goto ignore_char;
  272. uart_insert_char(&uart->port, status, OE, ch, flg);
  273. ignore_char:
  274. tty_flip_buffer_push(tty);
  275. }
  276. static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
  277. {
  278. struct circ_buf *xmit = &uart->port.info->xmit;
  279. if (uart->port.x_char) {
  280. UART_PUT_CHAR(uart, uart->port.x_char);
  281. uart->port.icount.tx++;
  282. uart->port.x_char = 0;
  283. }
  284. /*
  285. * Check the modem control lines before
  286. * transmitting anything.
  287. */
  288. bfin_serial_mctrl_check(uart);
  289. if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
  290. bfin_serial_stop_tx(&uart->port);
  291. return;
  292. }
  293. while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
  294. UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
  295. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  296. uart->port.icount.tx++;
  297. SSYNC();
  298. }
  299. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  300. uart_write_wakeup(&uart->port);
  301. if (uart_circ_empty(xmit))
  302. bfin_serial_stop_tx(&uart->port);
  303. }
  304. static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
  305. {
  306. struct bfin_serial_port *uart = dev_id;
  307. spin_lock(&uart->port.lock);
  308. while (UART_GET_LSR(uart) & DR)
  309. bfin_serial_rx_chars(uart);
  310. spin_unlock(&uart->port.lock);
  311. return IRQ_HANDLED;
  312. }
  313. static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
  314. {
  315. struct bfin_serial_port *uart = dev_id;
  316. spin_lock(&uart->port.lock);
  317. if (UART_GET_LSR(uart) & THRE)
  318. bfin_serial_tx_chars(uart);
  319. spin_unlock(&uart->port.lock);
  320. return IRQ_HANDLED;
  321. }
  322. #endif
  323. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  324. static void bfin_serial_do_work(struct work_struct *work)
  325. {
  326. struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
  327. bfin_serial_mctrl_check(uart);
  328. }
  329. #endif
  330. #ifdef CONFIG_SERIAL_BFIN_DMA
  331. static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
  332. {
  333. struct circ_buf *xmit = &uart->port.info->xmit;
  334. unsigned short ier;
  335. uart->tx_done = 0;
  336. if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
  337. uart->tx_count = 0;
  338. uart->tx_done = 1;
  339. return;
  340. }
  341. if (uart->port.x_char) {
  342. UART_PUT_CHAR(uart, uart->port.x_char);
  343. uart->port.icount.tx++;
  344. uart->port.x_char = 0;
  345. }
  346. /*
  347. * Check the modem control lines before
  348. * transmitting anything.
  349. */
  350. bfin_serial_mctrl_check(uart);
  351. uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
  352. if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
  353. uart->tx_count = UART_XMIT_SIZE - xmit->tail;
  354. blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
  355. (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
  356. set_dma_config(uart->tx_dma_channel,
  357. set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
  358. INTR_ON_BUF,
  359. DIMENSION_LINEAR,
  360. DATA_SIZE_8,
  361. DMA_SYNC_RESTART));
  362. set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
  363. set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
  364. set_dma_x_modify(uart->tx_dma_channel, 1);
  365. enable_dma(uart->tx_dma_channel);
  366. #ifdef CONFIG_BF54x
  367. UART_SET_IER(uart, ETBEI);
  368. #else
  369. ier = UART_GET_IER(uart);
  370. ier |= ETBEI;
  371. UART_PUT_IER(uart, ier);
  372. #endif
  373. }
  374. static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
  375. {
  376. struct tty_struct *tty = uart->port.info->tty;
  377. int i, flg, status;
  378. status = UART_GET_LSR(uart);
  379. UART_CLEAR_LSR(uart);
  380. uart->port.icount.rx +=
  381. CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
  382. UART_XMIT_SIZE);
  383. if (status & BI) {
  384. uart->port.icount.brk++;
  385. if (uart_handle_break(&uart->port))
  386. goto dma_ignore_char;
  387. status &= ~(PE | FE);
  388. }
  389. if (status & PE)
  390. uart->port.icount.parity++;
  391. if (status & OE)
  392. uart->port.icount.overrun++;
  393. if (status & FE)
  394. uart->port.icount.frame++;
  395. status &= uart->port.read_status_mask;
  396. if (status & BI)
  397. flg = TTY_BREAK;
  398. else if (status & PE)
  399. flg = TTY_PARITY;
  400. else if (status & FE)
  401. flg = TTY_FRAME;
  402. else
  403. flg = TTY_NORMAL;
  404. for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
  405. if (i >= UART_XMIT_SIZE)
  406. i = 0;
  407. if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
  408. uart_insert_char(&uart->port, status, OE,
  409. uart->rx_dma_buf.buf[i], flg);
  410. }
  411. dma_ignore_char:
  412. tty_flip_buffer_push(tty);
  413. }
  414. void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
  415. {
  416. int x_pos, pos;
  417. uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
  418. x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
  419. uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
  420. if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
  421. uart->rx_dma_nrows = 0;
  422. x_pos = DMA_RX_XCOUNT - x_pos;
  423. if (x_pos == DMA_RX_XCOUNT)
  424. x_pos = 0;
  425. pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
  426. if (pos != uart->rx_dma_buf.tail) {
  427. uart->rx_dma_buf.head = pos;
  428. bfin_serial_dma_rx_chars(uart);
  429. uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
  430. }
  431. uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
  432. add_timer(&(uart->rx_dma_timer));
  433. }
  434. static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
  435. {
  436. struct bfin_serial_port *uart = dev_id;
  437. struct circ_buf *xmit = &uart->port.info->xmit;
  438. unsigned short ier;
  439. spin_lock(&uart->port.lock);
  440. if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
  441. disable_dma(uart->tx_dma_channel);
  442. clear_dma_irqstat(uart->tx_dma_channel);
  443. #ifdef CONFIG_BF54x
  444. UART_CLEAR_IER(uart, ETBEI);
  445. #else
  446. ier = UART_GET_IER(uart);
  447. ier &= ~ETBEI;
  448. UART_PUT_IER(uart, ier);
  449. #endif
  450. xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
  451. uart->port.icount.tx += uart->tx_count;
  452. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  453. uart_write_wakeup(&uart->port);
  454. bfin_serial_dma_tx_chars(uart);
  455. }
  456. spin_unlock(&uart->port.lock);
  457. return IRQ_HANDLED;
  458. }
  459. static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
  460. {
  461. struct bfin_serial_port *uart = dev_id;
  462. unsigned short irqstat;
  463. spin_lock(&uart->port.lock);
  464. irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
  465. clear_dma_irqstat(uart->rx_dma_channel);
  466. spin_unlock(&uart->port.lock);
  467. del_timer(&(uart->rx_dma_timer));
  468. uart->rx_dma_timer.expires = jiffies;
  469. add_timer(&(uart->rx_dma_timer));
  470. return IRQ_HANDLED;
  471. }
  472. #endif
  473. /*
  474. * Return TIOCSER_TEMT when transmitter is not busy.
  475. */
  476. static unsigned int bfin_serial_tx_empty(struct uart_port *port)
  477. {
  478. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  479. unsigned short lsr;
  480. lsr = UART_GET_LSR(uart);
  481. if (lsr & TEMT)
  482. return TIOCSER_TEMT;
  483. else
  484. return 0;
  485. }
  486. static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
  487. {
  488. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  489. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  490. if (uart->cts_pin < 0)
  491. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  492. # ifdef BF54x
  493. if (UART_GET_MSR(uart) & CTS)
  494. # else
  495. if (gpio_get_value(uart->cts_pin))
  496. # endif
  497. return TIOCM_DSR | TIOCM_CAR;
  498. else
  499. #endif
  500. return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
  501. }
  502. static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  503. {
  504. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  505. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  506. if (uart->rts_pin < 0)
  507. return;
  508. if (mctrl & TIOCM_RTS)
  509. # ifdef BF54x
  510. UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS);
  511. # else
  512. gpio_set_value(uart->rts_pin, 0);
  513. # endif
  514. else
  515. # ifdef BF54x
  516. UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS);
  517. # else
  518. gpio_set_value(uart->rts_pin, 1);
  519. # endif
  520. #endif
  521. }
  522. /*
  523. * Handle any change of modem status signal since we were last called.
  524. */
  525. static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
  526. {
  527. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  528. unsigned int status;
  529. struct uart_info *info = uart->port.info;
  530. struct tty_struct *tty = info->tty;
  531. status = bfin_serial_get_mctrl(&uart->port);
  532. uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
  533. if (!(status & TIOCM_CTS)) {
  534. tty->hw_stopped = 1;
  535. schedule_work(&uart->cts_workqueue);
  536. } else {
  537. tty->hw_stopped = 0;
  538. }
  539. #endif
  540. }
  541. /*
  542. * Interrupts are always disabled.
  543. */
  544. static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
  545. {
  546. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  547. u16 lcr = UART_GET_LCR(uart);
  548. if (break_state)
  549. lcr |= SB;
  550. else
  551. lcr &= ~SB;
  552. UART_PUT_LCR(uart, lcr);
  553. SSYNC();
  554. }
  555. static int bfin_serial_startup(struct uart_port *port)
  556. {
  557. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  558. #ifdef CONFIG_SERIAL_BFIN_DMA
  559. dma_addr_t dma_handle;
  560. if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
  561. printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
  562. return -EBUSY;
  563. }
  564. if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
  565. printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
  566. free_dma(uart->rx_dma_channel);
  567. return -EBUSY;
  568. }
  569. set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
  570. set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
  571. uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
  572. uart->rx_dma_buf.head = 0;
  573. uart->rx_dma_buf.tail = 0;
  574. uart->rx_dma_nrows = 0;
  575. set_dma_config(uart->rx_dma_channel,
  576. set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
  577. INTR_ON_ROW, DIMENSION_2D,
  578. DATA_SIZE_8,
  579. DMA_SYNC_RESTART));
  580. set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
  581. set_dma_x_modify(uart->rx_dma_channel, 1);
  582. set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
  583. set_dma_y_modify(uart->rx_dma_channel, 1);
  584. set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
  585. enable_dma(uart->rx_dma_channel);
  586. uart->rx_dma_timer.data = (unsigned long)(uart);
  587. uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
  588. uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
  589. add_timer(&(uart->rx_dma_timer));
  590. #else
  591. if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
  592. "BFIN_UART_RX", uart)) {
  593. # ifdef CONFIG_KGDB_UART
  594. if (uart->port.line != CONFIG_KGDB_UART_PORT) {
  595. # endif
  596. printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
  597. return -EBUSY;
  598. # ifdef CONFIG_KGDB_UART
  599. }
  600. # endif
  601. }
  602. if (request_irq
  603. (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
  604. "BFIN_UART_TX", uart)) {
  605. printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
  606. free_irq(uart->port.irq, uart);
  607. return -EBUSY;
  608. }
  609. #endif
  610. #ifdef CONFIG_BF54x
  611. UART_SET_IER(uart, ERBFI);
  612. #else
  613. UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
  614. #endif
  615. return 0;
  616. }
  617. static void bfin_serial_shutdown(struct uart_port *port)
  618. {
  619. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  620. #ifdef CONFIG_SERIAL_BFIN_DMA
  621. disable_dma(uart->tx_dma_channel);
  622. free_dma(uart->tx_dma_channel);
  623. disable_dma(uart->rx_dma_channel);
  624. free_dma(uart->rx_dma_channel);
  625. del_timer(&(uart->rx_dma_timer));
  626. dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
  627. #else
  628. #ifdef CONFIG_KGDB_UART
  629. if (uart->port.line != CONFIG_KGDB_UART_PORT)
  630. #endif
  631. free_irq(uart->port.irq, uart);
  632. free_irq(uart->port.irq+1, uart);
  633. #endif
  634. }
  635. static void
  636. bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
  637. struct ktermios *old)
  638. {
  639. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  640. unsigned long flags;
  641. unsigned int baud, quot;
  642. unsigned short val, ier, lcr = 0;
  643. switch (termios->c_cflag & CSIZE) {
  644. case CS8:
  645. lcr = WLS(8);
  646. break;
  647. case CS7:
  648. lcr = WLS(7);
  649. break;
  650. case CS6:
  651. lcr = WLS(6);
  652. break;
  653. case CS5:
  654. lcr = WLS(5);
  655. break;
  656. default:
  657. printk(KERN_ERR "%s: word lengh not supported\n",
  658. __FUNCTION__);
  659. }
  660. if (termios->c_cflag & CSTOPB)
  661. lcr |= STB;
  662. if (termios->c_cflag & PARENB)
  663. lcr |= PEN;
  664. if (!(termios->c_cflag & PARODD))
  665. lcr |= EPS;
  666. if (termios->c_cflag & CMSPAR)
  667. lcr |= STP;
  668. port->read_status_mask = OE;
  669. if (termios->c_iflag & INPCK)
  670. port->read_status_mask |= (FE | PE);
  671. if (termios->c_iflag & (BRKINT | PARMRK))
  672. port->read_status_mask |= BI;
  673. /*
  674. * Characters to ignore
  675. */
  676. port->ignore_status_mask = 0;
  677. if (termios->c_iflag & IGNPAR)
  678. port->ignore_status_mask |= FE | PE;
  679. if (termios->c_iflag & IGNBRK) {
  680. port->ignore_status_mask |= BI;
  681. /*
  682. * If we're ignoring parity and break indicators,
  683. * ignore overruns too (for real raw support).
  684. */
  685. if (termios->c_iflag & IGNPAR)
  686. port->ignore_status_mask |= OE;
  687. }
  688. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  689. quot = uart_get_divisor(port, baud);
  690. spin_lock_irqsave(&uart->port.lock, flags);
  691. UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
  692. /* Disable UART */
  693. ier = UART_GET_IER(uart);
  694. #ifdef CONFIG_BF54x
  695. UART_CLEAR_IER(uart, 0xF);
  696. #else
  697. UART_PUT_IER(uart, 0);
  698. #endif
  699. #ifndef CONFIG_BF54x
  700. /* Set DLAB in LCR to Access DLL and DLH */
  701. val = UART_GET_LCR(uart);
  702. val |= DLAB;
  703. UART_PUT_LCR(uart, val);
  704. SSYNC();
  705. #endif
  706. UART_PUT_DLL(uart, quot & 0xFF);
  707. SSYNC();
  708. UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
  709. SSYNC();
  710. #ifndef CONFIG_BF54x
  711. /* Clear DLAB in LCR to Access THR RBR IER */
  712. val = UART_GET_LCR(uart);
  713. val &= ~DLAB;
  714. UART_PUT_LCR(uart, val);
  715. SSYNC();
  716. #endif
  717. UART_PUT_LCR(uart, lcr);
  718. /* Enable UART */
  719. #ifdef CONFIG_BF54x
  720. UART_SET_IER(uart, ier);
  721. #else
  722. UART_PUT_IER(uart, ier);
  723. #endif
  724. val = UART_GET_GCTL(uart);
  725. val |= UCEN;
  726. UART_PUT_GCTL(uart, val);
  727. spin_unlock_irqrestore(&uart->port.lock, flags);
  728. }
  729. static const char *bfin_serial_type(struct uart_port *port)
  730. {
  731. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  732. return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
  733. }
  734. /*
  735. * Release the memory region(s) being used by 'port'.
  736. */
  737. static void bfin_serial_release_port(struct uart_port *port)
  738. {
  739. }
  740. /*
  741. * Request the memory region(s) being used by 'port'.
  742. */
  743. static int bfin_serial_request_port(struct uart_port *port)
  744. {
  745. return 0;
  746. }
  747. /*
  748. * Configure/autoconfigure the port.
  749. */
  750. static void bfin_serial_config_port(struct uart_port *port, int flags)
  751. {
  752. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  753. if (flags & UART_CONFIG_TYPE &&
  754. bfin_serial_request_port(&uart->port) == 0)
  755. uart->port.type = PORT_BFIN;
  756. }
  757. /*
  758. * Verify the new serial_struct (for TIOCSSERIAL).
  759. * The only change we allow are to the flags and type, and
  760. * even then only between PORT_BFIN and PORT_UNKNOWN
  761. */
  762. static int
  763. bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
  764. {
  765. return 0;
  766. }
  767. /*
  768. * Enable the IrDA function if tty->ldisc.num is N_IRDA.
  769. * In other cases, disable IrDA function.
  770. */
  771. static void bfin_set_ldisc(struct tty_struct *tty)
  772. {
  773. int line = tty->index;
  774. unsigned short val;
  775. if (line >= tty->driver->num)
  776. return;
  777. switch (tty->ldisc.num) {
  778. case N_IRDA:
  779. val = UART_GET_GCTL(&bfin_serial_ports[line]);
  780. val |= (IREN | RPOLC);
  781. UART_PUT_GCTL(&bfin_serial_ports[line], val);
  782. break;
  783. default:
  784. val = UART_GET_GCTL(&bfin_serial_ports[line]);
  785. val &= ~(IREN | RPOLC);
  786. UART_PUT_GCTL(&bfin_serial_ports[line], val);
  787. }
  788. }
  789. static struct uart_ops bfin_serial_pops = {
  790. .tx_empty = bfin_serial_tx_empty,
  791. .set_mctrl = bfin_serial_set_mctrl,
  792. .get_mctrl = bfin_serial_get_mctrl,
  793. .stop_tx = bfin_serial_stop_tx,
  794. .start_tx = bfin_serial_start_tx,
  795. .stop_rx = bfin_serial_stop_rx,
  796. .enable_ms = bfin_serial_enable_ms,
  797. .break_ctl = bfin_serial_break_ctl,
  798. .startup = bfin_serial_startup,
  799. .shutdown = bfin_serial_shutdown,
  800. .set_termios = bfin_serial_set_termios,
  801. .type = bfin_serial_type,
  802. .release_port = bfin_serial_release_port,
  803. .request_port = bfin_serial_request_port,
  804. .config_port = bfin_serial_config_port,
  805. .verify_port = bfin_serial_verify_port,
  806. };
  807. static void __init bfin_serial_init_ports(void)
  808. {
  809. static int first = 1;
  810. int i;
  811. if (!first)
  812. return;
  813. first = 0;
  814. for (i = 0; i < nr_ports; i++) {
  815. bfin_serial_ports[i].port.uartclk = get_sclk();
  816. bfin_serial_ports[i].port.ops = &bfin_serial_pops;
  817. bfin_serial_ports[i].port.line = i;
  818. bfin_serial_ports[i].port.iotype = UPIO_MEM;
  819. bfin_serial_ports[i].port.membase =
  820. (void __iomem *)bfin_serial_resource[i].uart_base_addr;
  821. bfin_serial_ports[i].port.mapbase =
  822. bfin_serial_resource[i].uart_base_addr;
  823. bfin_serial_ports[i].port.irq =
  824. bfin_serial_resource[i].uart_irq;
  825. bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
  826. #ifdef CONFIG_SERIAL_BFIN_DMA
  827. bfin_serial_ports[i].tx_done = 1;
  828. bfin_serial_ports[i].tx_count = 0;
  829. bfin_serial_ports[i].tx_dma_channel =
  830. bfin_serial_resource[i].uart_tx_dma_channel;
  831. bfin_serial_ports[i].rx_dma_channel =
  832. bfin_serial_resource[i].uart_rx_dma_channel;
  833. init_timer(&(bfin_serial_ports[i].rx_dma_timer));
  834. #endif
  835. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  836. INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
  837. bfin_serial_ports[i].cts_pin =
  838. bfin_serial_resource[i].uart_cts_pin;
  839. bfin_serial_ports[i].rts_pin =
  840. bfin_serial_resource[i].uart_rts_pin;
  841. #endif
  842. bfin_serial_hw_init(&bfin_serial_ports[i]);
  843. }
  844. }
  845. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  846. /*
  847. * If the port was already initialised (eg, by a boot loader),
  848. * try to determine the current setup.
  849. */
  850. static void __init
  851. bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
  852. int *parity, int *bits)
  853. {
  854. unsigned short status;
  855. status = UART_GET_IER(uart) & (ERBFI | ETBEI);
  856. if (status == (ERBFI | ETBEI)) {
  857. /* ok, the port was enabled */
  858. unsigned short lcr, val;
  859. unsigned short dlh, dll;
  860. lcr = UART_GET_LCR(uart);
  861. *parity = 'n';
  862. if (lcr & PEN) {
  863. if (lcr & EPS)
  864. *parity = 'e';
  865. else
  866. *parity = 'o';
  867. }
  868. switch (lcr & 0x03) {
  869. case 0: *bits = 5; break;
  870. case 1: *bits = 6; break;
  871. case 2: *bits = 7; break;
  872. case 3: *bits = 8; break;
  873. }
  874. #ifndef CONFIG_BF54x
  875. /* Set DLAB in LCR to Access DLL and DLH */
  876. val = UART_GET_LCR(uart);
  877. val |= DLAB;
  878. UART_PUT_LCR(uart, val);
  879. #endif
  880. dll = UART_GET_DLL(uart);
  881. dlh = UART_GET_DLH(uart);
  882. #ifndef CONFIG_BF54x
  883. /* Clear DLAB in LCR to Access THR RBR IER */
  884. val = UART_GET_LCR(uart);
  885. val &= ~DLAB;
  886. UART_PUT_LCR(uart, val);
  887. #endif
  888. *baud = get_sclk() / (16*(dll | dlh << 8));
  889. }
  890. pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits);
  891. }
  892. #endif
  893. #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
  894. static struct uart_driver bfin_serial_reg;
  895. static int __init
  896. bfin_serial_console_setup(struct console *co, char *options)
  897. {
  898. struct bfin_serial_port *uart;
  899. # ifdef CONFIG_SERIAL_BFIN_CONSOLE
  900. int baud = 57600;
  901. int bits = 8;
  902. int parity = 'n';
  903. # ifdef CONFIG_SERIAL_BFIN_CTSRTS
  904. int flow = 'r';
  905. # else
  906. int flow = 'n';
  907. # endif
  908. # endif
  909. /*
  910. * Check whether an invalid uart number has been specified, and
  911. * if so, search for the first available port that does have
  912. * console support.
  913. */
  914. if (co->index == -1 || co->index >= nr_ports)
  915. co->index = 0;
  916. uart = &bfin_serial_ports[co->index];
  917. # ifdef CONFIG_SERIAL_BFIN_CONSOLE
  918. if (options)
  919. uart_parse_options(options, &baud, &parity, &bits, &flow);
  920. else
  921. bfin_serial_console_get_options(uart, &baud, &parity, &bits);
  922. return uart_set_options(&uart->port, co, baud, parity, bits, flow);
  923. # else
  924. return 0;
  925. # endif
  926. }
  927. #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
  928. defined (CONFIG_EARLY_PRINTK) */
  929. #ifdef CONFIG_SERIAL_BFIN_CONSOLE
  930. static void bfin_serial_console_putchar(struct uart_port *port, int ch)
  931. {
  932. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  933. while (!(UART_GET_LSR(uart) & THRE))
  934. barrier();
  935. UART_PUT_CHAR(uart, ch);
  936. SSYNC();
  937. }
  938. /*
  939. * Interrupts are disabled on entering
  940. */
  941. static void
  942. bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
  943. {
  944. struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
  945. int flags = 0;
  946. spin_lock_irqsave(&uart->port.lock, flags);
  947. uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
  948. spin_unlock_irqrestore(&uart->port.lock, flags);
  949. }
  950. static struct console bfin_serial_console = {
  951. .name = BFIN_SERIAL_NAME,
  952. .write = bfin_serial_console_write,
  953. .device = uart_console_device,
  954. .setup = bfin_serial_console_setup,
  955. .flags = CON_PRINTBUFFER,
  956. .index = -1,
  957. .data = &bfin_serial_reg,
  958. };
  959. static int __init bfin_serial_rs_console_init(void)
  960. {
  961. bfin_serial_init_ports();
  962. register_console(&bfin_serial_console);
  963. #ifdef CONFIG_KGDB_UART
  964. kgdb_entry_state = 0;
  965. init_kgdb_uart();
  966. #endif
  967. return 0;
  968. }
  969. console_initcall(bfin_serial_rs_console_init);
  970. #define BFIN_SERIAL_CONSOLE &bfin_serial_console
  971. #else
  972. #define BFIN_SERIAL_CONSOLE NULL
  973. #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
  974. #ifdef CONFIG_EARLY_PRINTK
  975. static __init void early_serial_putc(struct uart_port *port, int ch)
  976. {
  977. unsigned timeout = 0xffff;
  978. struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
  979. while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
  980. cpu_relax();
  981. UART_PUT_CHAR(uart, ch);
  982. }
  983. static __init void early_serial_write(struct console *con, const char *s,
  984. unsigned int n)
  985. {
  986. struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
  987. unsigned int i;
  988. for (i = 0; i < n; i++, s++) {
  989. if (*s == '\n')
  990. early_serial_putc(&uart->port, '\r');
  991. early_serial_putc(&uart->port, *s);
  992. }
  993. }
  994. static struct __init console bfin_early_serial_console = {
  995. .name = "early_BFuart",
  996. .write = early_serial_write,
  997. .device = uart_console_device,
  998. .flags = CON_PRINTBUFFER,
  999. .setup = bfin_serial_console_setup,
  1000. .index = -1,
  1001. .data = &bfin_serial_reg,
  1002. };
  1003. struct console __init *bfin_earlyserial_init(unsigned int port,
  1004. unsigned int cflag)
  1005. {
  1006. struct bfin_serial_port *uart;
  1007. struct ktermios t;
  1008. if (port == -1 || port >= nr_ports)
  1009. port = 0;
  1010. bfin_serial_init_ports();
  1011. bfin_early_serial_console.index = port;
  1012. uart = &bfin_serial_ports[port];
  1013. t.c_cflag = cflag;
  1014. t.c_iflag = 0;
  1015. t.c_oflag = 0;
  1016. t.c_lflag = ICANON;
  1017. t.c_line = port;
  1018. bfin_serial_set_termios(&uart->port, &t, &t);
  1019. return &bfin_early_serial_console;
  1020. }
  1021. #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
  1022. static struct uart_driver bfin_serial_reg = {
  1023. .owner = THIS_MODULE,
  1024. .driver_name = "bfin-uart",
  1025. .dev_name = BFIN_SERIAL_NAME,
  1026. .major = BFIN_SERIAL_MAJOR,
  1027. .minor = BFIN_SERIAL_MINOR,
  1028. .nr = NR_PORTS,
  1029. .cons = BFIN_SERIAL_CONSOLE,
  1030. };
  1031. static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
  1032. {
  1033. struct bfin_serial_port *uart = platform_get_drvdata(dev);
  1034. if (uart)
  1035. uart_suspend_port(&bfin_serial_reg, &uart->port);
  1036. return 0;
  1037. }
  1038. static int bfin_serial_resume(struct platform_device *dev)
  1039. {
  1040. struct bfin_serial_port *uart = platform_get_drvdata(dev);
  1041. if (uart)
  1042. uart_resume_port(&bfin_serial_reg, &uart->port);
  1043. return 0;
  1044. }
  1045. static int bfin_serial_probe(struct platform_device *dev)
  1046. {
  1047. struct resource *res = dev->resource;
  1048. int i;
  1049. for (i = 0; i < dev->num_resources; i++, res++)
  1050. if (res->flags & IORESOURCE_MEM)
  1051. break;
  1052. if (i < dev->num_resources) {
  1053. for (i = 0; i < nr_ports; i++, res++) {
  1054. if (bfin_serial_ports[i].port.mapbase != res->start)
  1055. continue;
  1056. bfin_serial_ports[i].port.dev = &dev->dev;
  1057. uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
  1058. platform_set_drvdata(dev, &bfin_serial_ports[i]);
  1059. }
  1060. }
  1061. return 0;
  1062. }
  1063. static int bfin_serial_remove(struct platform_device *pdev)
  1064. {
  1065. struct bfin_serial_port *uart = platform_get_drvdata(pdev);
  1066. #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  1067. gpio_free(uart->cts_pin);
  1068. gpio_free(uart->rts_pin);
  1069. #endif
  1070. platform_set_drvdata(pdev, NULL);
  1071. if (uart)
  1072. uart_remove_one_port(&bfin_serial_reg, &uart->port);
  1073. return 0;
  1074. }
  1075. static struct platform_driver bfin_serial_driver = {
  1076. .probe = bfin_serial_probe,
  1077. .remove = bfin_serial_remove,
  1078. .suspend = bfin_serial_suspend,
  1079. .resume = bfin_serial_resume,
  1080. .driver = {
  1081. .name = "bfin-uart",
  1082. .owner = THIS_MODULE,
  1083. },
  1084. };
  1085. static int __init bfin_serial_init(void)
  1086. {
  1087. int ret;
  1088. #ifdef CONFIG_KGDB_UART
  1089. struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
  1090. struct ktermios t;
  1091. #endif
  1092. pr_info("Serial: Blackfin serial driver\n");
  1093. bfin_serial_init_ports();
  1094. ret = uart_register_driver(&bfin_serial_reg);
  1095. if (ret == 0) {
  1096. bfin_serial_reg.tty_driver->set_ldisc = bfin_set_ldisc;
  1097. ret = platform_driver_register(&bfin_serial_driver);
  1098. if (ret) {
  1099. pr_debug("uart register failed\n");
  1100. uart_unregister_driver(&bfin_serial_reg);
  1101. }
  1102. }
  1103. #ifdef CONFIG_KGDB_UART
  1104. if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
  1105. request_irq(uart->port.irq, bfin_serial_rx_int,
  1106. IRQF_DISABLED, "BFIN_UART_RX", uart);
  1107. pr_info("Request irq for kgdb uart port\n");
  1108. #ifdef CONFIG_BF54x
  1109. UART_SET_IER(uart, ERBFI);
  1110. #else
  1111. UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
  1112. #endif
  1113. SSYNC();
  1114. t.c_cflag = CS8|B57600;
  1115. t.c_iflag = 0;
  1116. t.c_oflag = 0;
  1117. t.c_lflag = ICANON;
  1118. t.c_line = CONFIG_KGDB_UART_PORT;
  1119. bfin_serial_set_termios(&uart->port, &t, &t);
  1120. }
  1121. #endif
  1122. return ret;
  1123. }
  1124. static void __exit bfin_serial_exit(void)
  1125. {
  1126. platform_driver_unregister(&bfin_serial_driver);
  1127. uart_unregister_driver(&bfin_serial_reg);
  1128. }
  1129. module_init(bfin_serial_init);
  1130. module_exit(bfin_serial_exit);
  1131. MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
  1132. MODULE_DESCRIPTION("Blackfin generic serial port driver");
  1133. MODULE_LICENSE("GPL");
  1134. MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
  1135. MODULE_ALIAS("platform:bfin-uart");