pcxhr.c 38 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * main file with alsa callbacks
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <sound/driver.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/slab.h>
  26. #include <linux/pci.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/delay.h>
  29. #include <linux/moduleparam.h>
  30. #include <linux/mutex.h>
  31. #include <linux/dma-mapping.h>
  32. #include <sound/core.h>
  33. #include <sound/initval.h>
  34. #include <sound/info.h>
  35. #include <sound/control.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include "pcxhr.h"
  39. #include "pcxhr_mixer.h"
  40. #include "pcxhr_hwdep.h"
  41. #include "pcxhr_core.h"
  42. #define DRIVER_NAME "pcxhr"
  43. MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
  44. MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
  45. MODULE_LICENSE("GPL");
  46. MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
  47. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  48. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  49. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  50. static int mono[SNDRV_CARDS]; /* capture in mono only */
  51. module_param_array(index, int, NULL, 0444);
  52. MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
  53. module_param_array(id, charp, NULL, 0444);
  54. MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
  55. module_param_array(enable, bool, NULL, 0444);
  56. MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
  57. module_param_array(mono, bool, NULL, 0444);
  58. MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
  59. enum {
  60. PCI_ID_VX882HR,
  61. PCI_ID_PCX882HR,
  62. PCI_ID_VX881HR,
  63. PCI_ID_PCX881HR,
  64. PCI_ID_PCX1222HR,
  65. PCI_ID_PCX1221HR,
  66. PCI_ID_LAST
  67. };
  68. static struct pci_device_id pcxhr_ids[] = {
  69. { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */
  70. { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */
  71. { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */
  72. { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */
  73. { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */
  74. { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */
  75. { 0, }
  76. };
  77. MODULE_DEVICE_TABLE(pci, pcxhr_ids);
  78. struct board_parameters {
  79. char* board_name;
  80. short playback_chips;
  81. short capture_chips;
  82. short firmware_num;
  83. };
  84. static struct board_parameters pcxhr_board_params[] = {
  85. [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, },
  86. [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, },
  87. [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, },
  88. [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, },
  89. [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, },
  90. [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, },
  91. };
  92. static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
  93. unsigned int* realfreq)
  94. {
  95. unsigned int reg;
  96. if (freq < 6900 || freq > 110250)
  97. return -EINVAL;
  98. reg = (28224000 * 10) / freq;
  99. reg = (reg + 5) / 10;
  100. if (reg < 0x200)
  101. *pllreg = reg + 0x800;
  102. else if (reg < 0x400)
  103. *pllreg = reg & 0x1ff;
  104. else if (reg < 0x800) {
  105. *pllreg = ((reg >> 1) & 0x1ff) + 0x200;
  106. reg &= ~1;
  107. } else {
  108. *pllreg = ((reg >> 2) & 0x1ff) + 0x400;
  109. reg &= ~3;
  110. }
  111. if (realfreq)
  112. *realfreq = ((28224000 * 10) / reg + 5) / 10;
  113. return 0;
  114. }
  115. #define PCXHR_FREQ_REG_MASK 0x1f
  116. #define PCXHR_FREQ_QUARTZ_48000 0x00
  117. #define PCXHR_FREQ_QUARTZ_24000 0x01
  118. #define PCXHR_FREQ_QUARTZ_12000 0x09
  119. #define PCXHR_FREQ_QUARTZ_32000 0x08
  120. #define PCXHR_FREQ_QUARTZ_16000 0x04
  121. #define PCXHR_FREQ_QUARTZ_8000 0x0c
  122. #define PCXHR_FREQ_QUARTZ_44100 0x02
  123. #define PCXHR_FREQ_QUARTZ_22050 0x0a
  124. #define PCXHR_FREQ_QUARTZ_11025 0x06
  125. #define PCXHR_FREQ_PLL 0x05
  126. #define PCXHR_FREQ_QUARTZ_192000 0x10
  127. #define PCXHR_FREQ_QUARTZ_96000 0x18
  128. #define PCXHR_FREQ_QUARTZ_176400 0x14
  129. #define PCXHR_FREQ_QUARTZ_88200 0x1c
  130. #define PCXHR_FREQ_QUARTZ_128000 0x12
  131. #define PCXHR_FREQ_QUARTZ_64000 0x1a
  132. #define PCXHR_FREQ_WORD_CLOCK 0x0f
  133. #define PCXHR_FREQ_SYNC_AES 0x0e
  134. #define PCXHR_FREQ_AES_1 0x07
  135. #define PCXHR_FREQ_AES_2 0x0b
  136. #define PCXHR_FREQ_AES_3 0x03
  137. #define PCXHR_FREQ_AES_4 0x0d
  138. #define PCXHR_MODIFY_CLOCK_S_BIT 0x04
  139. #define PCXHR_IRQ_TIMER_FREQ 92000
  140. #define PCXHR_IRQ_TIMER_PERIOD 48
  141. static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
  142. unsigned int *reg, unsigned int *freq)
  143. {
  144. unsigned int val, realfreq, pllreg;
  145. struct pcxhr_rmh rmh;
  146. int err;
  147. realfreq = rate;
  148. switch (mgr->use_clock_type) {
  149. case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */
  150. switch (rate) {
  151. case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break;
  152. case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break;
  153. case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break;
  154. case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break;
  155. case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break;
  156. case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break;
  157. case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break;
  158. case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break;
  159. case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break;
  160. case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break;
  161. case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break;
  162. case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break;
  163. case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break;
  164. case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break;
  165. case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break;
  166. default :
  167. val = PCXHR_FREQ_PLL;
  168. /* get the value for the pll register */
  169. err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
  170. if (err)
  171. return err;
  172. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
  173. rmh.cmd[0] |= IO_NUM_REG_GENCLK;
  174. rmh.cmd[1] = pllreg & MASK_DSP_WORD;
  175. rmh.cmd[2] = pllreg >> 24;
  176. rmh.cmd_len = 3;
  177. err = pcxhr_send_msg(mgr, &rmh);
  178. if (err < 0) {
  179. snd_printk(KERN_ERR
  180. "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
  181. err );
  182. return err;
  183. }
  184. }
  185. break;
  186. case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break;
  187. case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break;
  188. case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break;
  189. case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break;
  190. case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break;
  191. case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break;
  192. default : return -EINVAL;
  193. }
  194. *reg = val;
  195. *freq = realfreq;
  196. return 0;
  197. }
  198. int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
  199. {
  200. unsigned int val, realfreq, speed;
  201. struct pcxhr_rmh rmh;
  202. int err, changed;
  203. if (rate == 0)
  204. return 0; /* nothing to do */
  205. err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
  206. if (err)
  207. return err;
  208. /* codec speed modes */
  209. if (rate < 55000)
  210. speed = 0; /* single speed */
  211. else if (rate < 100000)
  212. speed = 1; /* dual speed */
  213. else
  214. speed = 2; /* quad speed */
  215. if (mgr->codec_speed != speed) {
  216. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
  217. rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
  218. err = pcxhr_send_msg(mgr, &rmh);
  219. if (err)
  220. return err;
  221. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
  222. rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
  223. rmh.cmd[1] = speed;
  224. rmh.cmd_len = 2;
  225. err = pcxhr_send_msg(mgr, &rmh);
  226. if (err)
  227. return err;
  228. }
  229. /* set the new frequency */
  230. snd_printdd("clock register : set %x\n", val);
  231. err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
  232. if (err)
  233. return err;
  234. mgr->sample_rate_real = realfreq;
  235. mgr->cur_clock_type = mgr->use_clock_type;
  236. /* unmute after codec speed modes */
  237. if (mgr->codec_speed != speed) {
  238. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
  239. rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
  240. err = pcxhr_send_msg(mgr, &rmh);
  241. if (err)
  242. return err;
  243. mgr->codec_speed = speed; /* save new codec speed */
  244. }
  245. if (changed) {
  246. pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
  247. rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */
  248. if (rate < PCXHR_IRQ_TIMER_FREQ)
  249. rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
  250. else
  251. rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
  252. rmh.cmd[2] = rate;
  253. rmh.cmd_len = 3;
  254. err = pcxhr_send_msg(mgr, &rmh);
  255. if (err)
  256. return err;
  257. }
  258. snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
  259. return 0;
  260. }
  261. int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
  262. int *sample_rate)
  263. {
  264. struct pcxhr_rmh rmh;
  265. unsigned char reg;
  266. int err, rate;
  267. switch (clock_type) {
  268. case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break;
  269. case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break;
  270. case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break;
  271. case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break;
  272. case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break;
  273. case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break;
  274. default : return -EINVAL;
  275. }
  276. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
  277. rmh.cmd_len = 2;
  278. rmh.cmd[0] |= IO_NUM_REG_STATUS;
  279. if (mgr->last_reg_stat != reg) {
  280. rmh.cmd[1] = reg;
  281. err = pcxhr_send_msg(mgr, &rmh);
  282. if (err)
  283. return err;
  284. udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */
  285. mgr->last_reg_stat = reg;
  286. }
  287. rmh.cmd[1] = REG_STATUS_CURRENT;
  288. err = pcxhr_send_msg(mgr, &rmh);
  289. if (err)
  290. return err;
  291. switch (rmh.stat[1] & 0x0f) {
  292. case REG_STATUS_SYNC_32000 : rate = 32000; break;
  293. case REG_STATUS_SYNC_44100 : rate = 44100; break;
  294. case REG_STATUS_SYNC_48000 : rate = 48000; break;
  295. case REG_STATUS_SYNC_64000 : rate = 64000; break;
  296. case REG_STATUS_SYNC_88200 : rate = 88200; break;
  297. case REG_STATUS_SYNC_96000 : rate = 96000; break;
  298. case REG_STATUS_SYNC_128000 : rate = 128000; break;
  299. case REG_STATUS_SYNC_176400 : rate = 176400; break;
  300. case REG_STATUS_SYNC_192000 : rate = 192000; break;
  301. default: rate = 0;
  302. }
  303. snd_printdd("External clock is at %d Hz\n", rate);
  304. *sample_rate = rate;
  305. return 0;
  306. }
  307. /*
  308. * start or stop playback/capture substream
  309. */
  310. static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
  311. {
  312. int err;
  313. struct snd_pcxhr *chip;
  314. struct pcxhr_rmh rmh;
  315. int stream_mask, start;
  316. if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
  317. start = 1;
  318. else {
  319. if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
  320. snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
  321. return -EINVAL;
  322. }
  323. start = 0;
  324. }
  325. if (!stream->substream)
  326. return -EINVAL;
  327. stream->timer_abs_periods = 0;
  328. stream->timer_period_frag = 0; /* reset theoretical stream pos */
  329. stream->timer_buf_periods = 0;
  330. stream->timer_is_synced = 0;
  331. stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
  332. pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
  333. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
  334. stream->pipe->first_audio, 0, stream_mask);
  335. chip = snd_pcm_substream_chip(stream->substream);
  336. err = pcxhr_send_msg(chip->mgr, &rmh);
  337. if (err)
  338. snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
  339. stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
  340. return err;
  341. }
  342. #define HEADER_FMT_BASE_LIN 0xfed00000
  343. #define HEADER_FMT_BASE_FLOAT 0xfad00000
  344. #define HEADER_FMT_INTEL 0x00008000
  345. #define HEADER_FMT_24BITS 0x00004000
  346. #define HEADER_FMT_16BITS 0x00002000
  347. #define HEADER_FMT_UPTO11 0x00000200
  348. #define HEADER_FMT_UPTO32 0x00000100
  349. #define HEADER_FMT_MONO 0x00000080
  350. static int pcxhr_set_format(struct pcxhr_stream *stream)
  351. {
  352. int err, is_capture, sample_rate, stream_num;
  353. struct snd_pcxhr *chip;
  354. struct pcxhr_rmh rmh;
  355. unsigned int header;
  356. switch (stream->format) {
  357. case SNDRV_PCM_FORMAT_U8:
  358. header = HEADER_FMT_BASE_LIN;
  359. break;
  360. case SNDRV_PCM_FORMAT_S16_LE:
  361. header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
  362. break;
  363. case SNDRV_PCM_FORMAT_S16_BE:
  364. header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
  365. break;
  366. case SNDRV_PCM_FORMAT_S24_3LE:
  367. header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
  368. break;
  369. case SNDRV_PCM_FORMAT_S24_3BE:
  370. header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
  371. break;
  372. case SNDRV_PCM_FORMAT_FLOAT_LE:
  373. header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
  374. break;
  375. default:
  376. snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
  377. return -EINVAL;
  378. }
  379. chip = snd_pcm_substream_chip(stream->substream);
  380. sample_rate = chip->mgr->sample_rate;
  381. if (sample_rate <= 32000 && sample_rate !=0) {
  382. if (sample_rate <= 11025)
  383. header |= HEADER_FMT_UPTO11;
  384. else
  385. header |= HEADER_FMT_UPTO32;
  386. }
  387. if (stream->channels == 1)
  388. header |= HEADER_FMT_MONO;
  389. is_capture = stream->pipe->is_capture;
  390. stream_num = is_capture ? 0 : stream->substream->number;
  391. pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
  392. pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
  393. if (is_capture)
  394. rmh.cmd[0] |= 1<<12;
  395. rmh.cmd[1] = 0;
  396. rmh.cmd[2] = header >> 8;
  397. rmh.cmd[3] = (header & 0xff) << 16;
  398. rmh.cmd_len = 4;
  399. err = pcxhr_send_msg(chip->mgr, &rmh);
  400. if (err)
  401. snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
  402. return err;
  403. }
  404. static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
  405. {
  406. int err, is_capture, stream_num;
  407. struct pcxhr_rmh rmh;
  408. struct snd_pcm_substream *subs = stream->substream;
  409. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  410. is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
  411. stream_num = is_capture ? 0 : subs->number;
  412. snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
  413. is_capture ? 'c' : 'p',
  414. chip->chip_idx, (void*)subs->runtime->dma_addr,
  415. subs->runtime->dma_bytes, subs->number);
  416. pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
  417. pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
  418. snd_assert(subs->runtime->dma_bytes < 0x200000); /* max buffer size is 2 MByte */
  419. rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */
  420. rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */
  421. rmh.cmd[2] |= 1<<19; /* this is a circular buffer */
  422. rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */
  423. rmh.cmd_len = 4;
  424. err = pcxhr_send_msg(chip->mgr, &rmh);
  425. if (err)
  426. snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
  427. return err;
  428. }
  429. #if 0
  430. static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
  431. {
  432. struct pcxhr_rmh rmh;
  433. int err;
  434. pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
  435. pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
  436. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
  437. 1<<stream->pipe->first_audio);
  438. err = pcxhr_send_msg(chip->mgr, &rmh);
  439. if (err == 0) {
  440. *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
  441. *sample_count += (snd_pcm_uframes_t)rmh.stat[1];
  442. }
  443. snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
  444. return err;
  445. }
  446. #endif
  447. static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
  448. struct pcxhr_pipe **pipe)
  449. {
  450. if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
  451. *pipe = stream->pipe;
  452. return 1;
  453. }
  454. return 0;
  455. }
  456. static void pcxhr_trigger_tasklet(unsigned long arg)
  457. {
  458. unsigned long flags;
  459. int i, j, err;
  460. struct pcxhr_pipe *pipe;
  461. struct snd_pcxhr *chip;
  462. struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
  463. int capture_mask = 0;
  464. int playback_mask = 0;
  465. #ifdef CONFIG_SND_DEBUG_DETECT
  466. struct timeval my_tv1, my_tv2;
  467. do_gettimeofday(&my_tv1);
  468. #endif
  469. mutex_lock(&mgr->setup_mutex);
  470. /* check the pipes concerned and build pipe_array */
  471. for (i = 0; i < mgr->num_cards; i++) {
  472. chip = mgr->chip[i];
  473. for (j = 0; j < chip->nb_streams_capt; j++) {
  474. if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
  475. capture_mask |= (1 << pipe->first_audio);
  476. }
  477. for (j = 0; j < chip->nb_streams_play; j++) {
  478. if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
  479. playback_mask |= (1 << pipe->first_audio);
  480. break; /* add only once, as all playback streams of
  481. * one chip use the same pipe
  482. */
  483. }
  484. }
  485. }
  486. if (capture_mask == 0 && playback_mask == 0) {
  487. mutex_unlock(&mgr->setup_mutex);
  488. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
  489. return;
  490. }
  491. snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
  492. playback_mask, capture_mask);
  493. /* synchronous stop of all the pipes concerned */
  494. err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0);
  495. if (err) {
  496. mutex_unlock(&mgr->setup_mutex);
  497. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
  498. playback_mask, capture_mask);
  499. return;
  500. }
  501. /* unfortunately the dsp lost format and buffer info with the stop pipe */
  502. for (i = 0; i < mgr->num_cards; i++) {
  503. struct pcxhr_stream *stream;
  504. chip = mgr->chip[i];
  505. for (j = 0; j < chip->nb_streams_capt; j++) {
  506. stream = &chip->capture_stream[j];
  507. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
  508. err = pcxhr_set_format(stream);
  509. err = pcxhr_update_r_buffer(stream);
  510. }
  511. }
  512. for (j = 0; j < chip->nb_streams_play; j++) {
  513. stream = &chip->playback_stream[j];
  514. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
  515. err = pcxhr_set_format(stream);
  516. err = pcxhr_update_r_buffer(stream);
  517. }
  518. }
  519. }
  520. /* start all the streams */
  521. for (i = 0; i < mgr->num_cards; i++) {
  522. struct pcxhr_stream *stream;
  523. chip = mgr->chip[i];
  524. for (j = 0; j < chip->nb_streams_capt; j++) {
  525. stream = &chip->capture_stream[j];
  526. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
  527. err = pcxhr_set_stream_state(stream);
  528. }
  529. for (j = 0; j < chip->nb_streams_play; j++) {
  530. stream = &chip->playback_stream[j];
  531. if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
  532. err = pcxhr_set_stream_state(stream);
  533. }
  534. }
  535. /* synchronous start of all the pipes concerned */
  536. err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
  537. if (err) {
  538. mutex_unlock(&mgr->setup_mutex);
  539. snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
  540. playback_mask, capture_mask);
  541. return;
  542. }
  543. /* put the streams into the running state now (increment pointer by interrupt) */
  544. spin_lock_irqsave(&mgr->lock, flags);
  545. for ( i =0; i < mgr->num_cards; i++) {
  546. struct pcxhr_stream *stream;
  547. chip = mgr->chip[i];
  548. for(j = 0; j < chip->nb_streams_capt; j++) {
  549. stream = &chip->capture_stream[j];
  550. if(stream->status == PCXHR_STREAM_STATUS_STARTED)
  551. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  552. }
  553. for (j = 0; j < chip->nb_streams_play; j++) {
  554. stream = &chip->playback_stream[j];
  555. if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
  556. /* playback will already have advanced ! */
  557. stream->timer_period_frag += PCXHR_GRANULARITY;
  558. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  559. }
  560. }
  561. }
  562. spin_unlock_irqrestore(&mgr->lock, flags);
  563. mutex_unlock(&mgr->setup_mutex);
  564. #ifdef CONFIG_SND_DEBUG_DETECT
  565. do_gettimeofday(&my_tv2);
  566. snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
  567. my_tv2.tv_usec - my_tv1.tv_usec, err);
  568. #endif
  569. }
  570. /*
  571. * trigger callback
  572. */
  573. static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
  574. {
  575. struct pcxhr_stream *stream;
  576. struct list_head *pos;
  577. struct snd_pcm_substream *s;
  578. int i;
  579. switch (cmd) {
  580. case SNDRV_PCM_TRIGGER_START:
  581. snd_printdd("SNDRV_PCM_TRIGGER_START\n");
  582. i = 0;
  583. snd_pcm_group_for_each(pos, subs) {
  584. s = snd_pcm_group_substream_entry(pos);
  585. stream = s->runtime->private_data;
  586. stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
  587. snd_pcm_trigger_done(s, subs);
  588. i++;
  589. }
  590. if (i==1) {
  591. snd_printdd("Only one Substream %c %d\n",
  592. stream->pipe->is_capture ? 'C' : 'P',
  593. stream->pipe->first_audio);
  594. if (pcxhr_set_format(stream))
  595. return -EINVAL;
  596. if (pcxhr_update_r_buffer(stream))
  597. return -EINVAL;
  598. if (pcxhr_set_stream_state(stream))
  599. return -EINVAL;
  600. stream->status = PCXHR_STREAM_STATUS_RUNNING;
  601. } else {
  602. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  603. tasklet_hi_schedule(&chip->mgr->trigger_taskq);
  604. }
  605. break;
  606. case SNDRV_PCM_TRIGGER_STOP:
  607. snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
  608. snd_pcm_group_for_each(pos, subs) {
  609. s = snd_pcm_group_substream_entry(pos);
  610. stream = s->runtime->private_data;
  611. stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
  612. if (pcxhr_set_stream_state(stream))
  613. return -EINVAL;
  614. snd_pcm_trigger_done(s, subs);
  615. }
  616. break;
  617. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  618. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  619. /* TODO */
  620. default:
  621. return -EINVAL;
  622. }
  623. return 0;
  624. }
  625. static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
  626. {
  627. struct pcxhr_rmh rmh;
  628. int err;
  629. pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
  630. if (start) {
  631. mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */
  632. rmh.cmd[0] |= PCXHR_GRANULARITY;
  633. }
  634. err = pcxhr_send_msg(mgr, &rmh);
  635. if (err < 0)
  636. snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
  637. return err;
  638. }
  639. /*
  640. * prepare callback for all pcms
  641. */
  642. static int pcxhr_prepare(struct snd_pcm_substream *subs)
  643. {
  644. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  645. struct pcxhr_mgr *mgr = chip->mgr;
  646. /*
  647. struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
  648. */
  649. int err = 0;
  650. snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
  651. subs->runtime->period_size, subs->runtime->periods,
  652. subs->runtime->buffer_size);
  653. /*
  654. if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
  655. snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
  656. (unsigned int)subs->runtime->period_size);
  657. return -EINVAL;
  658. }
  659. */
  660. mutex_lock(&mgr->setup_mutex);
  661. do {
  662. /* if the stream was stopped before, format and buffer were reset */
  663. /*
  664. if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
  665. err = pcxhr_set_format(stream);
  666. if(err) break;
  667. err = pcxhr_update_r_buffer(stream);
  668. if(err) break;
  669. }
  670. */
  671. /* only the first stream can choose the sample rate */
  672. /* the further opened streams will be limited to its frequency (see open) */
  673. /* set the clock only once (first stream) */
  674. if (mgr->sample_rate != subs->runtime->rate) {
  675. err = pcxhr_set_clock(mgr, subs->runtime->rate);
  676. if (err)
  677. break;
  678. if (mgr->sample_rate == 0)
  679. /* start the DSP-timer */
  680. err = pcxhr_hardware_timer(mgr, 1);
  681. mgr->sample_rate = subs->runtime->rate;
  682. }
  683. } while(0); /* do only once (so we can use break instead of goto) */
  684. mutex_unlock(&mgr->setup_mutex);
  685. return err;
  686. }
  687. /*
  688. * HW_PARAMS callback for all pcms
  689. */
  690. static int pcxhr_hw_params(struct snd_pcm_substream *subs,
  691. struct snd_pcm_hw_params *hw)
  692. {
  693. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  694. struct pcxhr_mgr *mgr = chip->mgr;
  695. struct pcxhr_stream *stream = subs->runtime->private_data;
  696. snd_pcm_format_t format;
  697. int err;
  698. int channels;
  699. /* set up channels */
  700. channels = params_channels(hw);
  701. /* set up format for the stream */
  702. format = params_format(hw);
  703. mutex_lock(&mgr->setup_mutex);
  704. stream->channels = channels;
  705. stream->format = format;
  706. /* set the format to the board */
  707. /*
  708. err = pcxhr_set_format(stream);
  709. if(err) {
  710. mutex_unlock(&mgr->setup_mutex);
  711. return err;
  712. }
  713. */
  714. /* allocate buffer */
  715. err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
  716. /*
  717. if (err > 0) {
  718. err = pcxhr_update_r_buffer(stream);
  719. }
  720. */
  721. mutex_unlock(&mgr->setup_mutex);
  722. return err;
  723. }
  724. static int pcxhr_hw_free(struct snd_pcm_substream *subs)
  725. {
  726. snd_pcm_lib_free_pages(subs);
  727. return 0;
  728. }
  729. /*
  730. * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
  731. */
  732. static struct snd_pcm_hardware pcxhr_caps =
  733. {
  734. .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  735. SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
  736. 0 /*SNDRV_PCM_INFO_PAUSE*/),
  737. .formats = ( SNDRV_PCM_FMTBIT_U8 |
  738. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
  739. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
  740. SNDRV_PCM_FMTBIT_FLOAT_LE ),
  741. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
  742. .rate_min = 8000,
  743. .rate_max = 192000,
  744. .channels_min = 1,
  745. .channels_max = 2,
  746. .buffer_bytes_max = (32*1024),
  747. /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
  748. .period_bytes_min = (2*PCXHR_GRANULARITY),
  749. .period_bytes_max = (16*1024),
  750. .periods_min = 2,
  751. .periods_max = (32*1024/PCXHR_GRANULARITY),
  752. };
  753. static int pcxhr_open(struct snd_pcm_substream *subs)
  754. {
  755. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  756. struct pcxhr_mgr *mgr = chip->mgr;
  757. struct snd_pcm_runtime *runtime = subs->runtime;
  758. struct pcxhr_stream *stream;
  759. int is_capture;
  760. mutex_lock(&mgr->setup_mutex);
  761. /* copy the struct snd_pcm_hardware struct */
  762. runtime->hw = pcxhr_caps;
  763. if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
  764. snd_printdd("pcxhr_open playback chip%d subs%d\n",
  765. chip->chip_idx, subs->number);
  766. is_capture = 0;
  767. stream = &chip->playback_stream[subs->number];
  768. } else {
  769. snd_printdd("pcxhr_open capture chip%d subs%d\n",
  770. chip->chip_idx, subs->number);
  771. is_capture = 1;
  772. if (mgr->mono_capture)
  773. runtime->hw.channels_max = 1;
  774. else
  775. runtime->hw.channels_min = 2;
  776. stream = &chip->capture_stream[subs->number];
  777. }
  778. if (stream->status != PCXHR_STREAM_STATUS_FREE){
  779. /* streams in use */
  780. snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
  781. chip->chip_idx, subs->number);
  782. mutex_unlock(&mgr->setup_mutex);
  783. return -EBUSY;
  784. }
  785. /* if a sample rate is already used or fixed by external clock,
  786. * the stream cannot change
  787. */
  788. if (mgr->sample_rate)
  789. runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
  790. else {
  791. if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
  792. int external_rate;
  793. if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
  794. &external_rate) ||
  795. external_rate == 0) {
  796. /* cannot detect the external clock rate */
  797. mutex_unlock(&mgr->setup_mutex);
  798. return -EBUSY;
  799. }
  800. runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
  801. }
  802. }
  803. stream->status = PCXHR_STREAM_STATUS_OPEN;
  804. stream->substream = subs;
  805. stream->channels = 0; /* not configured yet */
  806. runtime->private_data = stream;
  807. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
  808. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
  809. mgr->ref_count_rate++;
  810. mutex_unlock(&mgr->setup_mutex);
  811. return 0;
  812. }
  813. static int pcxhr_close(struct snd_pcm_substream *subs)
  814. {
  815. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  816. struct pcxhr_mgr *mgr = chip->mgr;
  817. struct pcxhr_stream *stream = subs->runtime->private_data;
  818. mutex_lock(&mgr->setup_mutex);
  819. snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
  820. /* sample rate released */
  821. if (--mgr->ref_count_rate == 0) {
  822. mgr->sample_rate = 0; /* the sample rate is no more locked */
  823. pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */
  824. }
  825. stream->status = PCXHR_STREAM_STATUS_FREE;
  826. stream->substream = NULL;
  827. mutex_unlock(&mgr->setup_mutex);
  828. return 0;
  829. }
  830. static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
  831. {
  832. unsigned long flags;
  833. u_int32_t timer_period_frag;
  834. int timer_buf_periods;
  835. struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
  836. struct snd_pcm_runtime *runtime = subs->runtime;
  837. struct pcxhr_stream *stream = runtime->private_data;
  838. spin_lock_irqsave(&chip->mgr->lock, flags);
  839. /* get the period fragment and the nb of periods in the buffer */
  840. timer_period_frag = stream->timer_period_frag;
  841. timer_buf_periods = stream->timer_buf_periods;
  842. spin_unlock_irqrestore(&chip->mgr->lock, flags);
  843. return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
  844. timer_period_frag);
  845. }
  846. static struct snd_pcm_ops pcxhr_ops = {
  847. .open = pcxhr_open,
  848. .close = pcxhr_close,
  849. .ioctl = snd_pcm_lib_ioctl,
  850. .prepare = pcxhr_prepare,
  851. .hw_params = pcxhr_hw_params,
  852. .hw_free = pcxhr_hw_free,
  853. .trigger = pcxhr_trigger,
  854. .pointer = pcxhr_stream_pointer,
  855. };
  856. /*
  857. */
  858. int pcxhr_create_pcm(struct snd_pcxhr *chip)
  859. {
  860. int err;
  861. struct snd_pcm *pcm;
  862. char name[32];
  863. sprintf(name, "pcxhr %d", chip->chip_idx);
  864. if ((err = snd_pcm_new(chip->card, name, 0,
  865. chip->nb_streams_play,
  866. chip->nb_streams_capt, &pcm)) < 0) {
  867. snd_printk(KERN_ERR "cannot create pcm %s\n", name);
  868. return err;
  869. }
  870. pcm->private_data = chip;
  871. if (chip->nb_streams_play)
  872. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
  873. if (chip->nb_streams_capt)
  874. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
  875. pcm->info_flags = 0;
  876. strcpy(pcm->name, name);
  877. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  878. snd_dma_pci_data(chip->mgr->pci),
  879. 32*1024, 32*1024);
  880. chip->pcm = pcm;
  881. return 0;
  882. }
  883. static int pcxhr_chip_free(struct snd_pcxhr *chip)
  884. {
  885. kfree(chip);
  886. return 0;
  887. }
  888. static int pcxhr_chip_dev_free(struct snd_device *device)
  889. {
  890. struct snd_pcxhr *chip = device->device_data;
  891. return pcxhr_chip_free(chip);
  892. }
  893. /*
  894. */
  895. static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
  896. {
  897. int err;
  898. struct snd_pcxhr *chip;
  899. static struct snd_device_ops ops = {
  900. .dev_free = pcxhr_chip_dev_free,
  901. };
  902. mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  903. if (! chip) {
  904. snd_printk(KERN_ERR "cannot allocate chip\n");
  905. return -ENOMEM;
  906. }
  907. chip->card = card;
  908. chip->chip_idx = idx;
  909. chip->mgr = mgr;
  910. if (idx < mgr->playback_chips)
  911. /* stereo or mono streams */
  912. chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
  913. if (idx < mgr->capture_chips) {
  914. if (mgr->mono_capture)
  915. chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */
  916. else
  917. chip->nb_streams_capt = 1; /* or 1 stereo stream */
  918. }
  919. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  920. pcxhr_chip_free(chip);
  921. return err;
  922. }
  923. snd_card_set_dev(card, &mgr->pci->dev);
  924. return 0;
  925. }
  926. /* proc interface */
  927. static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  928. {
  929. struct snd_pcxhr *chip = entry->private_data;
  930. struct pcxhr_mgr *mgr = chip->mgr;
  931. snd_iprintf(buffer, "\n%s\n", mgr->longname);
  932. /* stats available when embedded DSP is running */
  933. if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
  934. struct pcxhr_rmh rmh;
  935. short ver_maj = (mgr->dsp_version >> 16) & 0xff;
  936. short ver_min = (mgr->dsp_version >> 8) & 0xff;
  937. short ver_build = mgr->dsp_version & 0xff;
  938. snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
  939. snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
  940. if (mgr->board_has_analog)
  941. snd_iprintf(buffer, "analog io available\n");
  942. else
  943. snd_iprintf(buffer, "digital only board\n");
  944. /* calc cpu load of the dsp */
  945. pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
  946. if( ! pcxhr_send_msg(mgr, &rmh) ) {
  947. int cur = rmh.stat[0];
  948. int ref = rmh.stat[1];
  949. if (ref > 0) {
  950. if (mgr->sample_rate_real != 0 &&
  951. mgr->sample_rate_real != 48000) {
  952. ref = (ref * 48000) / mgr->sample_rate_real;
  953. if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
  954. ref *= 2;
  955. }
  956. cur = 100 - (100 * cur) / ref;
  957. snd_iprintf(buffer, "cpu load %d%%\n", cur);
  958. snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
  959. rmh.stat[2], rmh.stat[3]);
  960. }
  961. }
  962. snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
  963. snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
  964. snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
  965. mgr->async_err_pipe_xrun);
  966. snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
  967. mgr->async_err_stream_xrun);
  968. snd_iprintf(buffer, "dsp async last other error : %x\n",
  969. mgr->async_err_other_last);
  970. /* debug zone dsp */
  971. rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
  972. rmh.cmd_len = 1;
  973. rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
  974. rmh.dsp_stat = 0;
  975. rmh.cmd_idx = CMD_LAST_INDEX;
  976. if( ! pcxhr_send_msg(mgr, &rmh) ) {
  977. int i;
  978. for (i = 0; i < rmh.stat_len; i++)
  979. snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]);
  980. }
  981. } else
  982. snd_iprintf(buffer, "no firmware loaded\n");
  983. snd_iprintf(buffer, "\n");
  984. }
  985. static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  986. {
  987. struct snd_pcxhr *chip = entry->private_data;
  988. struct pcxhr_mgr *mgr = chip->mgr;
  989. static char *texts[7] = {
  990. "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
  991. };
  992. snd_iprintf(buffer, "\n%s\n", mgr->longname);
  993. snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
  994. snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
  995. /* commands available when embedded DSP is running */
  996. if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
  997. int i, err, sample_rate;
  998. for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
  999. err = pcxhr_get_external_clock(mgr, i, &sample_rate);
  1000. if (err)
  1001. break;
  1002. snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
  1003. }
  1004. } else
  1005. snd_iprintf(buffer, "no firmware loaded\n");
  1006. snd_iprintf(buffer, "\n");
  1007. }
  1008. static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
  1009. {
  1010. struct snd_info_entry *entry;
  1011. if (! snd_card_proc_new(chip->card, "info", &entry))
  1012. snd_info_set_text_ops(entry, chip, 1024, pcxhr_proc_info);
  1013. if (! snd_card_proc_new(chip->card, "sync", &entry))
  1014. snd_info_set_text_ops(entry, chip, 1024, pcxhr_proc_sync);
  1015. }
  1016. /* end of proc interface */
  1017. /*
  1018. * release all the cards assigned to a manager instance
  1019. */
  1020. static int pcxhr_free(struct pcxhr_mgr *mgr)
  1021. {
  1022. unsigned int i;
  1023. for (i = 0; i < mgr->num_cards; i++) {
  1024. if (mgr->chip[i])
  1025. snd_card_free(mgr->chip[i]->card);
  1026. }
  1027. /* reset board if some firmware was loaded */
  1028. if(mgr->dsp_loaded) {
  1029. pcxhr_reset_board(mgr);
  1030. snd_printdd("reset pcxhr !\n");
  1031. }
  1032. /* release irq */
  1033. if (mgr->irq >= 0)
  1034. free_irq(mgr->irq, mgr);
  1035. pci_release_regions(mgr->pci);
  1036. /* free hostport purgebuffer */
  1037. if (mgr->hostport.area) {
  1038. snd_dma_free_pages(&mgr->hostport);
  1039. mgr->hostport.area = NULL;
  1040. }
  1041. kfree(mgr->prmh);
  1042. pci_disable_device(mgr->pci);
  1043. kfree(mgr);
  1044. return 0;
  1045. }
  1046. /*
  1047. * probe function - creates the card manager
  1048. */
  1049. static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1050. {
  1051. static int dev;
  1052. struct pcxhr_mgr *mgr;
  1053. unsigned int i;
  1054. int err;
  1055. size_t size;
  1056. char *card_name;
  1057. if (dev >= SNDRV_CARDS)
  1058. return -ENODEV;
  1059. if (! enable[dev]) {
  1060. dev++;
  1061. return -ENOENT;
  1062. }
  1063. /* enable PCI device */
  1064. if ((err = pci_enable_device(pci)) < 0)
  1065. return err;
  1066. pci_set_master(pci);
  1067. /* check if we can restrict PCI DMA transfers to 32 bits */
  1068. if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) {
  1069. snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
  1070. pci_disable_device(pci);
  1071. return -ENXIO;
  1072. }
  1073. /* alloc card manager */
  1074. mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
  1075. if (! mgr) {
  1076. pci_disable_device(pci);
  1077. return -ENOMEM;
  1078. }
  1079. snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV);
  1080. card_name = pcxhr_board_params[pci_id->driver_data].board_name;
  1081. mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
  1082. mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips;
  1083. mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num;
  1084. mgr->mono_capture = mono[dev];
  1085. /* resource assignment */
  1086. if ((err = pci_request_regions(pci, card_name)) < 0) {
  1087. kfree(mgr);
  1088. pci_disable_device(pci);
  1089. return err;
  1090. }
  1091. for (i = 0; i < 3; i++)
  1092. mgr->port[i] = pci_resource_start(pci, i);
  1093. mgr->pci = pci;
  1094. mgr->irq = -1;
  1095. if (request_irq(pci->irq, pcxhr_interrupt, SA_INTERRUPT|SA_SHIRQ,
  1096. card_name, mgr)) {
  1097. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1098. pcxhr_free(mgr);
  1099. return -EBUSY;
  1100. }
  1101. mgr->irq = pci->irq;
  1102. sprintf(mgr->shortname, "Digigram %s", card_name);
  1103. sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
  1104. mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
  1105. /* ISR spinlock */
  1106. spin_lock_init(&mgr->lock);
  1107. spin_lock_init(&mgr->msg_lock);
  1108. /* init setup mutex*/
  1109. mutex_init(&mgr->setup_mutex);
  1110. /* init taslket */
  1111. tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
  1112. tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
  1113. mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
  1114. sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
  1115. GFP_KERNEL);
  1116. if (! mgr->prmh) {
  1117. pcxhr_free(mgr);
  1118. return -ENOMEM;
  1119. }
  1120. for (i=0; i < PCXHR_MAX_CARDS; i++) {
  1121. struct snd_card *card;
  1122. char tmpid[16];
  1123. int idx;
  1124. if (i >= max(mgr->playback_chips, mgr->capture_chips))
  1125. break;
  1126. mgr->num_cards++;
  1127. if (index[dev] < 0)
  1128. idx = index[dev];
  1129. else
  1130. idx = index[dev] + i;
  1131. snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
  1132. card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
  1133. if (! card) {
  1134. snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
  1135. pcxhr_free(mgr);
  1136. return -ENOMEM;
  1137. }
  1138. strcpy(card->driver, DRIVER_NAME);
  1139. sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
  1140. sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
  1141. if ((err = pcxhr_create(mgr, card, i)) < 0) {
  1142. pcxhr_free(mgr);
  1143. return err;
  1144. }
  1145. if (i == 0)
  1146. /* init proc interface only for chip0 */
  1147. pcxhr_proc_init(mgr->chip[i]);
  1148. if ((err = snd_card_register(card)) < 0) {
  1149. pcxhr_free(mgr);
  1150. return err;
  1151. }
  1152. }
  1153. /* create hostport purgebuffer */
  1154. size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
  1155. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  1156. size, &mgr->hostport) < 0) {
  1157. pcxhr_free(mgr);
  1158. return -ENOMEM;
  1159. }
  1160. /* init purgebuffer */
  1161. memset(mgr->hostport.area, 0, size);
  1162. /* create a DSP loader */
  1163. err = pcxhr_setup_firmware(mgr);
  1164. if (err < 0) {
  1165. pcxhr_free(mgr);
  1166. return err;
  1167. }
  1168. pci_set_drvdata(pci, mgr);
  1169. dev++;
  1170. return 0;
  1171. }
  1172. static void __devexit pcxhr_remove(struct pci_dev *pci)
  1173. {
  1174. pcxhr_free(pci_get_drvdata(pci));
  1175. pci_set_drvdata(pci, NULL);
  1176. }
  1177. static struct pci_driver driver = {
  1178. .name = "Digigram pcxhr",
  1179. .id_table = pcxhr_ids,
  1180. .probe = pcxhr_probe,
  1181. .remove = __devexit_p(pcxhr_remove),
  1182. };
  1183. static int __init pcxhr_module_init(void)
  1184. {
  1185. return pci_register_driver(&driver);
  1186. }
  1187. static void __exit pcxhr_module_exit(void)
  1188. {
  1189. pci_unregister_driver(&driver);
  1190. }
  1191. module_init(pcxhr_module_init)
  1192. module_exit(pcxhr_module_exit)