azt3328.c 57 KB

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  1. /*
  2. * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * GPL LICENSE
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. * NOTES
  28. * Since Aztech does not provide any chipset documentation,
  29. * even on repeated request to various addresses,
  30. * and the answer that was finally given was negative
  31. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  32. * in the first place >:-P}),
  33. * I was forced to base this driver on reverse engineering
  34. * (3 weeks' worth of evenings filled with driver work).
  35. * (and no, I did NOT go the easy way: to pick up a PCI128 for 9 Euros)
  36. *
  37. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  38. * for compatibility reasons) has the following features:
  39. *
  40. * - builtin AC97 conformant codec (SNR over 80dB)
  41. * (really AC97 compliant?? I really doubt it when looking
  42. * at the mixer register layout)
  43. * - builtin genuine OPL3
  44. * - full duplex 16bit playback/record at independent sampling rate
  45. * - MPU401 (+ legacy address support) FIXME: how to enable legacy addr??
  46. * - game port (legacy address support)
  47. * - built-in General DirectX timer having a 20 bits counter
  48. * with 1us resolution (see below!)
  49. * - I2S serial port for external DAC
  50. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  51. * - supports hardware volume control
  52. * - single chip low cost solution (128 pin QFP)
  53. * - supports programmable Sub-vendor and Sub-system ID
  54. * required for Microsoft's logo compliance (FIXME: where?)
  55. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  56. *
  57. * Note that this driver now is actually *better* than the Windows driver,
  58. * since it additionally supports the card's 1MHz DirectX timer - just try
  59. * the following snd-seq module parameters etc.:
  60. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  61. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  62. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  63. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  64. * - "pmidi -p 128:0 jazz.mid"
  65. *
  66. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  67. * in some systems (resulting in sound crackling/clicking/popping),
  68. * probably because they don't have a DMA FIFO buffer or so.
  69. * Overview (PCI ID/PCI subID/PCI rev.):
  70. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  71. * - unknown performance: 0x50DC/0x1801/10
  72. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  73. *
  74. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  75. * supposed to be very fast and supposed to get rid of crackling much
  76. * better than a VIA, yet ironically I still get crackling, like many other
  77. * people with the same chipset.
  78. * Possible remedies:
  79. * - plug card into a different PCI slot, preferrably one that isn't shared
  80. * too much (this helps a lot, but not completely!)
  81. * - get rid of PCI VGA card, use AGP instead
  82. * - upgrade or downgrade BIOS
  83. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  84. * Not too helpful.
  85. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  86. *
  87. * BUGS
  88. * - full-duplex might *still* be problematic, not fully tested recently
  89. *
  90. * TODO
  91. * - test MPU401 MIDI playback etc.
  92. * - power management. See e.g. intel8x0 or cs4281.
  93. * This would be nice since the chip runs a bit hot, and it's *required*
  94. * anyway for proper ACPI power management.
  95. * - figure out what all unknown port bits are responsible for
  96. */
  97. #include <sound/driver.h>
  98. #include <asm/io.h>
  99. #include <linux/init.h>
  100. #include <linux/pci.h>
  101. #include <linux/delay.h>
  102. #include <linux/slab.h>
  103. #include <linux/gameport.h>
  104. #include <linux/moduleparam.h>
  105. #include <linux/dma-mapping.h>
  106. #include <sound/core.h>
  107. #include <sound/control.h>
  108. #include <sound/pcm.h>
  109. #include <sound/rawmidi.h>
  110. #include <sound/mpu401.h>
  111. #include <sound/opl3.h>
  112. #include <sound/initval.h>
  113. #include "azt3328.h"
  114. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  115. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  116. MODULE_LICENSE("GPL");
  117. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  118. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  119. #define SUPPORT_JOYSTICK 1
  120. #endif
  121. #define DEBUG_MISC 0
  122. #define DEBUG_CALLS 0
  123. #define DEBUG_MIXER 0
  124. #define DEBUG_PLAY_REC 0
  125. #define DEBUG_IO 0
  126. #define DEBUG_TIMER 0
  127. #define MIXER_TESTING 0
  128. #if DEBUG_MISC
  129. #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
  130. #else
  131. #define snd_azf3328_dbgmisc(format, args...)
  132. #endif
  133. #if DEBUG_CALLS
  134. #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
  135. #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__)
  136. #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__)
  137. #else
  138. #define snd_azf3328_dbgcalls(format, args...)
  139. #define snd_azf3328_dbgcallenter()
  140. #define snd_azf3328_dbgcallleave()
  141. #endif
  142. #if DEBUG_MIXER
  143. #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
  144. #else
  145. #define snd_azf3328_dbgmixer(format, args...)
  146. #endif
  147. #if DEBUG_PLAY_REC
  148. #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
  149. #else
  150. #define snd_azf3328_dbgplay(format, args...)
  151. #endif
  152. #if DEBUG_MISC
  153. #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
  154. #else
  155. #define snd_azf3328_dbgtimer(format, args...)
  156. #endif
  157. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  158. module_param_array(index, int, NULL, 0444);
  159. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  160. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  161. module_param_array(id, charp, NULL, 0444);
  162. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  163. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  164. module_param_array(enable, bool, NULL, 0444);
  165. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  166. #ifdef SUPPORT_JOYSTICK
  167. static int joystick[SNDRV_CARDS];
  168. module_param_array(joystick, bool, NULL, 0444);
  169. MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard.");
  170. #endif
  171. static int seqtimer_scaling = 128;
  172. module_param(seqtimer_scaling, int, 0444);
  173. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  174. struct snd_azf3328 {
  175. /* often-used fields towards beginning, then grouped */
  176. unsigned long codec_port;
  177. unsigned long io2_port;
  178. unsigned long mpu_port;
  179. unsigned long synth_port;
  180. unsigned long mixer_port;
  181. spinlock_t reg_lock;
  182. struct snd_timer *timer;
  183. struct snd_pcm *pcm;
  184. struct snd_pcm_substream *playback_substream;
  185. struct snd_pcm_substream *capture_substream;
  186. unsigned int is_playing;
  187. unsigned int is_recording;
  188. struct snd_card *card;
  189. struct snd_rawmidi *rmidi;
  190. #ifdef SUPPORT_JOYSTICK
  191. struct gameport *gameport;
  192. #endif
  193. struct pci_dev *pci;
  194. int irq;
  195. };
  196. static const struct pci_device_id snd_azf3328_ids[] = {
  197. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  198. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  199. { 0, }
  200. };
  201. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  202. static inline void
  203. snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  204. {
  205. outb(value, chip->codec_port + reg);
  206. }
  207. static inline u8
  208. snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg)
  209. {
  210. return inb(chip->codec_port + reg);
  211. }
  212. static inline void
  213. snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  214. {
  215. outw(value, chip->codec_port + reg);
  216. }
  217. static inline u16
  218. snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg)
  219. {
  220. return inw(chip->codec_port + reg);
  221. }
  222. static inline void
  223. snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value)
  224. {
  225. outl(value, chip->codec_port + reg);
  226. }
  227. static inline void
  228. snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  229. {
  230. outb(value, chip->io2_port + reg);
  231. }
  232. static inline u8
  233. snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg)
  234. {
  235. return inb(chip->io2_port + reg);
  236. }
  237. static inline void
  238. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  239. {
  240. outw(value, chip->mixer_port + reg);
  241. }
  242. static inline u16
  243. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg)
  244. {
  245. return inw(chip->mixer_port + reg);
  246. }
  247. static void
  248. snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute)
  249. {
  250. unsigned long portbase = chip->mixer_port + reg + 1;
  251. unsigned char oldval;
  252. /* the mute bit is on the *second* (i.e. right) register of a
  253. * left/right channel setting */
  254. oldval = inb(portbase);
  255. if (do_mute)
  256. oldval |= 0x80;
  257. else
  258. oldval &= ~0x80;
  259. outb(oldval, portbase);
  260. }
  261. static void
  262. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay)
  263. {
  264. unsigned long portbase = chip->mixer_port + reg;
  265. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  266. int left_done = 0, right_done = 0;
  267. snd_azf3328_dbgcallenter();
  268. if (chan_sel & SET_CHAN_LEFT)
  269. curr_vol_left = inb(portbase + 1);
  270. else
  271. left_done = 1;
  272. if (chan_sel & SET_CHAN_RIGHT)
  273. curr_vol_right = inb(portbase + 0);
  274. else
  275. right_done = 1;
  276. /* take care of muting flag (0x80) contained in left channel */
  277. if (curr_vol_left & 0x80)
  278. dst_vol_left |= 0x80;
  279. else
  280. dst_vol_left &= ~0x80;
  281. do
  282. {
  283. if (!left_done)
  284. {
  285. if (curr_vol_left > dst_vol_left)
  286. curr_vol_left--;
  287. else
  288. if (curr_vol_left < dst_vol_left)
  289. curr_vol_left++;
  290. else
  291. left_done = 1;
  292. outb(curr_vol_left, portbase + 1);
  293. }
  294. if (!right_done)
  295. {
  296. if (curr_vol_right > dst_vol_right)
  297. curr_vol_right--;
  298. else
  299. if (curr_vol_right < dst_vol_right)
  300. curr_vol_right++;
  301. else
  302. right_done = 1;
  303. /* during volume change, the right channel is crackling
  304. * somewhat more than the left channel, unfortunately.
  305. * This seems to be a hardware issue. */
  306. outb(curr_vol_right, portbase + 0);
  307. }
  308. if (delay)
  309. mdelay(delay);
  310. }
  311. while ((!left_done) || (!right_done));
  312. snd_azf3328_dbgcallleave();
  313. }
  314. /*
  315. * general mixer element
  316. */
  317. struct azf3328_mixer_reg {
  318. unsigned int reg;
  319. unsigned int lchan_shift, rchan_shift;
  320. unsigned int mask;
  321. unsigned int invert: 1;
  322. unsigned int stereo: 1;
  323. unsigned int enum_c: 4;
  324. };
  325. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  326. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  327. (mask << 16) | \
  328. (invert << 24) | \
  329. (stereo << 25) | \
  330. (enum_c << 26))
  331. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  332. {
  333. r->reg = val & 0xff;
  334. r->lchan_shift = (val >> 8) & 0x0f;
  335. r->rchan_shift = (val >> 12) & 0x0f;
  336. r->mask = (val >> 16) & 0xff;
  337. r->invert = (val >> 24) & 1;
  338. r->stereo = (val >> 25) & 1;
  339. r->enum_c = (val >> 26) & 0x0f;
  340. }
  341. /*
  342. * mixer switches/volumes
  343. */
  344. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  345. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  346. .info = snd_azf3328_info_mixer, \
  347. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  348. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  349. }
  350. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  351. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  352. .info = snd_azf3328_info_mixer, \
  353. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  354. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  355. }
  356. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  357. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  358. .info = snd_azf3328_info_mixer, \
  359. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  360. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  361. }
  362. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  363. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  364. .info = snd_azf3328_info_mixer, \
  365. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  366. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  367. }
  368. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  369. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  370. .info = snd_azf3328_info_mixer_enum, \
  371. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  372. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  373. }
  374. static int
  375. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  376. struct snd_ctl_elem_info *uinfo)
  377. {
  378. struct azf3328_mixer_reg reg;
  379. snd_azf3328_dbgcallenter();
  380. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  381. uinfo->type = reg.mask == 1 ?
  382. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  383. uinfo->count = reg.stereo + 1;
  384. uinfo->value.integer.min = 0;
  385. uinfo->value.integer.max = reg.mask;
  386. snd_azf3328_dbgcallleave();
  387. return 0;
  388. }
  389. static int
  390. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  391. struct snd_ctl_elem_value *ucontrol)
  392. {
  393. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  394. struct azf3328_mixer_reg reg;
  395. unsigned int oreg, val;
  396. snd_azf3328_dbgcallenter();
  397. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  398. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  399. val = (oreg >> reg.lchan_shift) & reg.mask;
  400. if (reg.invert)
  401. val = reg.mask - val;
  402. ucontrol->value.integer.value[0] = val;
  403. if (reg.stereo) {
  404. val = (oreg >> reg.rchan_shift) & reg.mask;
  405. if (reg.invert)
  406. val = reg.mask - val;
  407. ucontrol->value.integer.value[1] = val;
  408. }
  409. snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
  410. "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  411. reg.reg, oreg,
  412. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  413. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  414. snd_azf3328_dbgcallleave();
  415. return 0;
  416. }
  417. static int
  418. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  419. struct snd_ctl_elem_value *ucontrol)
  420. {
  421. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  422. struct azf3328_mixer_reg reg;
  423. unsigned int oreg, nreg, val;
  424. snd_azf3328_dbgcallenter();
  425. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  426. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  427. val = ucontrol->value.integer.value[0] & reg.mask;
  428. if (reg.invert)
  429. val = reg.mask - val;
  430. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  431. nreg |= (val << reg.lchan_shift);
  432. if (reg.stereo) {
  433. val = ucontrol->value.integer.value[1] & reg.mask;
  434. if (reg.invert)
  435. val = reg.mask - val;
  436. nreg &= ~(reg.mask << reg.rchan_shift);
  437. nreg |= (val << reg.rchan_shift);
  438. }
  439. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  440. snd_azf3328_mixer_write_volume_gradually(
  441. chip, reg.reg, nreg >> 8, nreg & 0xff,
  442. /* just set both channels, doesn't matter */
  443. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  444. 0);
  445. else
  446. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  447. snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
  448. "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  449. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  450. oreg, reg.lchan_shift, reg.rchan_shift,
  451. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  452. snd_azf3328_dbgcallleave();
  453. return (nreg != oreg);
  454. }
  455. static int
  456. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  457. struct snd_ctl_elem_info *uinfo)
  458. {
  459. static const char * const texts1[] = {
  460. "ModemOut1", "ModemOut2"
  461. };
  462. static const char * const texts2[] = {
  463. "MonoSelectSource1", "MonoSelectSource2"
  464. };
  465. static const char * const texts3[] = {
  466. "Mic", "CD", "Video", "Aux",
  467. "Line", "Mix", "Mix Mono", "Phone"
  468. };
  469. struct azf3328_mixer_reg reg;
  470. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  471. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  472. uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
  473. uinfo->value.enumerated.items = reg.enum_c;
  474. if (uinfo->value.enumerated.item > reg.enum_c - 1U)
  475. uinfo->value.enumerated.item = reg.enum_c - 1U;
  476. if (reg.reg == IDX_MIXER_ADVCTL2)
  477. {
  478. if (reg.lchan_shift == 8) /* modem out sel */
  479. strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]);
  480. else /* mono sel source */
  481. strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]);
  482. }
  483. else
  484. strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item]
  485. );
  486. return 0;
  487. }
  488. static int
  489. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  490. struct snd_ctl_elem_value *ucontrol)
  491. {
  492. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  493. struct azf3328_mixer_reg reg;
  494. unsigned short val;
  495. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  496. val = snd_azf3328_mixer_inw(chip, reg.reg);
  497. if (reg.reg == IDX_MIXER_REC_SELECT)
  498. {
  499. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  500. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  501. }
  502. else
  503. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  504. snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  505. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  506. reg.lchan_shift, reg.enum_c);
  507. return 0;
  508. }
  509. static int
  510. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  511. struct snd_ctl_elem_value *ucontrol)
  512. {
  513. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  514. struct azf3328_mixer_reg reg;
  515. unsigned int oreg, nreg, val;
  516. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  517. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  518. val = oreg;
  519. if (reg.reg == IDX_MIXER_REC_SELECT)
  520. {
  521. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  522. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  523. return -EINVAL;
  524. val = (ucontrol->value.enumerated.item[0] << 8) |
  525. (ucontrol->value.enumerated.item[1] << 0);
  526. }
  527. else
  528. {
  529. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  530. return -EINVAL;
  531. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  532. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  533. }
  534. snd_azf3328_mixer_outw(chip, reg.reg, val);
  535. nreg = val;
  536. snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  537. return (nreg != oreg);
  538. }
  539. static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
  540. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  541. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  542. AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  543. AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
  544. AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
  545. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  546. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  547. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  548. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  549. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  550. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  551. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  552. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  553. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  554. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  555. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  556. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  557. AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  558. AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  559. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  560. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  561. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  562. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  563. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  564. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  565. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  566. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  567. AZF3328_MIXER_ENUM("Modem Out Select", IDX_MIXER_ADVCTL2, 2, 8),
  568. AZF3328_MIXER_ENUM("Mono Select Source", IDX_MIXER_ADVCTL2, 2, 9),
  569. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  570. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  571. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  572. AZF3328_MIXER_VOL_SPECIAL("3D Control - Wide", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  573. AZF3328_MIXER_VOL_SPECIAL("3D Control - Space", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  574. #if MIXER_TESTING
  575. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  576. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  577. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  578. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  579. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  580. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  581. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  582. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  583. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  584. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  585. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  586. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  587. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  588. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  589. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  590. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  591. #endif
  592. };
  593. static const u16 __devinitdata snd_azf3328_init_values[][2] = {
  594. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  595. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  596. { IDX_MIXER_BASSTREBLE, 0x0000 },
  597. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  598. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  599. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  600. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  601. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  602. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  603. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  604. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  605. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  606. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  607. };
  608. static int __devinit
  609. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  610. {
  611. struct snd_card *card;
  612. const struct snd_kcontrol_new *sw;
  613. unsigned int idx;
  614. int err;
  615. snd_azf3328_dbgcallenter();
  616. snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
  617. card = chip->card;
  618. /* mixer reset */
  619. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  620. /* mute and zero volume channels */
  621. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) {
  622. snd_azf3328_mixer_outw(chip,
  623. snd_azf3328_init_values[idx][0],
  624. snd_azf3328_init_values[idx][1]);
  625. }
  626. /* add mixer controls */
  627. sw = snd_azf3328_mixer_controls;
  628. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) {
  629. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  630. return err;
  631. }
  632. snd_component_add(card, "AZF3328 mixer");
  633. strcpy(card->mixername, "AZF3328 mixer");
  634. snd_azf3328_dbgcallleave();
  635. return 0;
  636. }
  637. static int
  638. snd_azf3328_hw_params(struct snd_pcm_substream *substream,
  639. struct snd_pcm_hw_params *hw_params)
  640. {
  641. int res;
  642. snd_azf3328_dbgcallenter();
  643. res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  644. snd_azf3328_dbgcallleave();
  645. return res;
  646. }
  647. static int
  648. snd_azf3328_hw_free(struct snd_pcm_substream *substream)
  649. {
  650. snd_azf3328_dbgcallenter();
  651. snd_pcm_lib_free_pages(substream);
  652. snd_azf3328_dbgcallleave();
  653. return 0;
  654. }
  655. static void
  656. snd_azf3328_setfmt(struct snd_azf3328 *chip,
  657. unsigned int reg,
  658. unsigned int bitrate,
  659. unsigned int format_width,
  660. unsigned int channels
  661. )
  662. {
  663. u16 val = 0xff00;
  664. unsigned long flags;
  665. snd_azf3328_dbgcallenter();
  666. switch (bitrate) {
  667. case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  668. case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  669. case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */
  670. case 6620: val |= SOUNDFORMAT_FREQ_6620; break;
  671. case 8000: val |= SOUNDFORMAT_FREQ_8000; break;
  672. case 9600: val |= SOUNDFORMAT_FREQ_9600; break;
  673. case 11025: val |= SOUNDFORMAT_FREQ_11025; break;
  674. case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  675. case 16000: val |= SOUNDFORMAT_FREQ_16000; break;
  676. case 22050: val |= SOUNDFORMAT_FREQ_22050; break;
  677. case 32000: val |= SOUNDFORMAT_FREQ_32000; break;
  678. case 44100: val |= SOUNDFORMAT_FREQ_44100; break;
  679. case 48000: val |= SOUNDFORMAT_FREQ_48000; break;
  680. case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  681. default:
  682. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  683. val |= SOUNDFORMAT_FREQ_44100;
  684. break;
  685. }
  686. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  687. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  688. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  689. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  690. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  691. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  692. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  693. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  694. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  695. if (channels == 2)
  696. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  697. if (format_width == 16)
  698. val |= SOUNDFORMAT_FLAG_16BIT;
  699. spin_lock_irqsave(&chip->reg_lock, flags);
  700. /* set bitrate/format */
  701. snd_azf3328_codec_outw(chip, reg, val);
  702. /* changing the bitrate/format settings switches off the
  703. * audio output with an annoying click in case of 8/16bit format change
  704. * (maybe shutting down DAC/ADC?), thus immediately
  705. * do some tweaking to reenable it and get rid of the clicking
  706. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  707. * FIXME: does this have some side effects for full-duplex
  708. * or other dramatic side effects? */
  709. if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
  710. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  711. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
  712. DMA_PLAY_SOMETHING1 |
  713. DMA_PLAY_SOMETHING2 |
  714. SOMETHING_ALMOST_ALWAYS_SET |
  715. DMA_EPILOGUE_SOMETHING |
  716. DMA_SOMETHING_ELSE
  717. );
  718. spin_unlock_irqrestore(&chip->reg_lock, flags);
  719. snd_azf3328_dbgcallleave();
  720. }
  721. static void
  722. snd_azf3328_setdmaa(struct snd_azf3328 *chip,
  723. long unsigned int addr,
  724. unsigned int count,
  725. unsigned int size,
  726. int do_recording)
  727. {
  728. unsigned long flags, portbase;
  729. unsigned int is_running;
  730. snd_azf3328_dbgcallenter();
  731. if (do_recording)
  732. {
  733. /* access capture registers, i.e. skip playback reg section */
  734. portbase = chip->codec_port + 0x20;
  735. is_running = chip->is_recording;
  736. }
  737. else
  738. {
  739. /* access the playback register section */
  740. portbase = chip->codec_port + 0x00;
  741. is_running = chip->is_playing;
  742. }
  743. /* AZF3328 uses a two buffer pointer DMA playback approach */
  744. if (!is_running)
  745. {
  746. unsigned long addr_area2;
  747. unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */
  748. count_areas = size/2;
  749. addr_area2 = addr+count_areas;
  750. count_areas--; /* max. index */
  751. snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
  752. /* build combined I/O buffer length word */
  753. count_tmp = count_areas;
  754. count_areas |= (count_tmp << 16);
  755. spin_lock_irqsave(&chip->reg_lock, flags);
  756. outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
  757. outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
  758. outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
  759. spin_unlock_irqrestore(&chip->reg_lock, flags);
  760. }
  761. snd_azf3328_dbgcallleave();
  762. }
  763. static int
  764. snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
  765. {
  766. #if 0
  767. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  768. struct snd_pcm_runtime *runtime = substream->runtime;
  769. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  770. unsigned int count = snd_pcm_lib_period_bytes(substream);
  771. #endif
  772. snd_azf3328_dbgcallenter();
  773. #if 0
  774. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  775. runtime->rate,
  776. snd_pcm_format_width(runtime->format),
  777. runtime->channels);
  778. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 0);
  779. #endif
  780. snd_azf3328_dbgcallleave();
  781. return 0;
  782. }
  783. static int
  784. snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
  785. {
  786. #if 0
  787. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  788. struct snd_pcm_runtime *runtime = substream->runtime;
  789. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  790. unsigned int count = snd_pcm_lib_period_bytes(substream);
  791. #endif
  792. snd_azf3328_dbgcallenter();
  793. #if 0
  794. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  795. runtime->rate,
  796. snd_pcm_format_width(runtime->format),
  797. runtime->channels);
  798. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 1);
  799. #endif
  800. snd_azf3328_dbgcallleave();
  801. return 0;
  802. }
  803. static int
  804. snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  805. {
  806. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  807. struct snd_pcm_runtime *runtime = substream->runtime;
  808. int result = 0;
  809. unsigned int status1;
  810. snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
  811. switch (cmd) {
  812. case SNDRV_PCM_TRIGGER_START:
  813. snd_azf3328_dbgplay("START PLAYBACK\n");
  814. /* mute WaveOut */
  815. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  816. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  817. runtime->rate,
  818. snd_pcm_format_width(runtime->format),
  819. runtime->channels);
  820. spin_lock(&chip->reg_lock);
  821. /* stop playback */
  822. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  823. status1 &= ~DMA_RESUME;
  824. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  825. /* FIXME: clear interrupts or what??? */
  826. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
  827. spin_unlock(&chip->reg_lock);
  828. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  829. snd_pcm_lib_period_bytes(substream),
  830. snd_pcm_lib_buffer_bytes(substream),
  831. 0);
  832. spin_lock(&chip->reg_lock);
  833. #ifdef WIN9X
  834. /* FIXME: enable playback/recording??? */
  835. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  836. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  837. /* start playback again */
  838. /* FIXME: what is this value (0x0010)??? */
  839. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  840. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  841. #else /* NT4 */
  842. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  843. 0x0000);
  844. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  845. DMA_PLAY_SOMETHING1);
  846. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  847. DMA_PLAY_SOMETHING1 |
  848. DMA_PLAY_SOMETHING2);
  849. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  850. DMA_RESUME |
  851. SOMETHING_ALMOST_ALWAYS_SET |
  852. DMA_EPILOGUE_SOMETHING |
  853. DMA_SOMETHING_ELSE);
  854. #endif
  855. spin_unlock(&chip->reg_lock);
  856. /* now unmute WaveOut */
  857. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  858. chip->is_playing = 1;
  859. snd_azf3328_dbgplay("STARTED PLAYBACK\n");
  860. break;
  861. case SNDRV_PCM_TRIGGER_STOP:
  862. snd_azf3328_dbgplay("STOP PLAYBACK\n");
  863. /* mute WaveOut */
  864. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  865. spin_lock(&chip->reg_lock);
  866. /* stop playback */
  867. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  868. status1 &= ~DMA_RESUME;
  869. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  870. /* hmm, is this really required? we're resetting the same bit
  871. * immediately thereafter... */
  872. status1 |= DMA_PLAY_SOMETHING1;
  873. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  874. status1 &= ~DMA_PLAY_SOMETHING1;
  875. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  876. spin_unlock(&chip->reg_lock);
  877. /* now unmute WaveOut */
  878. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  879. chip->is_playing = 0;
  880. snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
  881. break;
  882. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  883. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  884. break;
  885. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  886. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  887. break;
  888. default:
  889. return -EINVAL;
  890. }
  891. snd_azf3328_dbgcallleave();
  892. return result;
  893. }
  894. /* this is just analogous to playback; I'm not quite sure whether recording
  895. * should actually be triggered like that */
  896. static int
  897. snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  898. {
  899. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  900. struct snd_pcm_runtime *runtime = substream->runtime;
  901. int result = 0;
  902. unsigned int status1;
  903. snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
  904. switch (cmd) {
  905. case SNDRV_PCM_TRIGGER_START:
  906. snd_azf3328_dbgplay("START CAPTURE\n");
  907. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  908. runtime->rate,
  909. snd_pcm_format_width(runtime->format),
  910. runtime->channels);
  911. spin_lock(&chip->reg_lock);
  912. /* stop recording */
  913. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  914. status1 &= ~DMA_RESUME;
  915. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  916. /* FIXME: clear interrupts or what??? */
  917. snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
  918. spin_unlock(&chip->reg_lock);
  919. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  920. snd_pcm_lib_period_bytes(substream),
  921. snd_pcm_lib_buffer_bytes(substream),
  922. 1);
  923. spin_lock(&chip->reg_lock);
  924. #ifdef WIN9X
  925. /* FIXME: enable playback/recording??? */
  926. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  927. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  928. /* start capture again */
  929. /* FIXME: what is this value (0x0010)??? */
  930. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  931. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  932. #else
  933. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  934. 0x0000);
  935. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  936. DMA_PLAY_SOMETHING1);
  937. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  938. DMA_PLAY_SOMETHING1 |
  939. DMA_PLAY_SOMETHING2);
  940. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  941. DMA_RESUME |
  942. SOMETHING_ALMOST_ALWAYS_SET |
  943. DMA_EPILOGUE_SOMETHING |
  944. DMA_SOMETHING_ELSE);
  945. #endif
  946. spin_unlock(&chip->reg_lock);
  947. chip->is_recording = 1;
  948. snd_azf3328_dbgplay("STARTED CAPTURE\n");
  949. break;
  950. case SNDRV_PCM_TRIGGER_STOP:
  951. snd_azf3328_dbgplay("STOP CAPTURE\n");
  952. spin_lock(&chip->reg_lock);
  953. /* stop recording */
  954. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  955. status1 &= ~DMA_RESUME;
  956. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  957. status1 |= DMA_PLAY_SOMETHING1;
  958. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  959. status1 &= ~DMA_PLAY_SOMETHING1;
  960. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  961. spin_unlock(&chip->reg_lock);
  962. chip->is_recording = 0;
  963. snd_azf3328_dbgplay("STOPPED CAPTURE\n");
  964. break;
  965. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  966. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  967. break;
  968. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  969. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  970. break;
  971. default:
  972. return -EINVAL;
  973. }
  974. snd_azf3328_dbgcallleave();
  975. return result;
  976. }
  977. static snd_pcm_uframes_t
  978. snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
  979. {
  980. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  981. unsigned long bufptr, result;
  982. snd_pcm_uframes_t frmres;
  983. #ifdef QUERY_HARDWARE
  984. bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1);
  985. #else
  986. bufptr = substream->runtime->dma_addr;
  987. #endif
  988. result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS);
  989. /* calculate offset */
  990. result -= bufptr;
  991. frmres = bytes_to_frames( substream->runtime, result);
  992. snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
  993. return frmres;
  994. }
  995. static snd_pcm_uframes_t
  996. snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
  997. {
  998. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  999. unsigned long bufptr, result;
  1000. snd_pcm_uframes_t frmres;
  1001. #ifdef QUERY_HARDWARE
  1002. bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1);
  1003. #else
  1004. bufptr = substream->runtime->dma_addr;
  1005. #endif
  1006. result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS);
  1007. /* calculate offset */
  1008. result -= bufptr;
  1009. frmres = bytes_to_frames( substream->runtime, result);
  1010. snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
  1011. return frmres;
  1012. }
  1013. static irqreturn_t
  1014. snd_azf3328_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  1015. {
  1016. struct snd_azf3328 *chip = dev_id;
  1017. u8 status, which;
  1018. static unsigned long irq_count;
  1019. status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
  1020. /* fast path out, to ease interrupt sharing */
  1021. if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER)))
  1022. return IRQ_NONE; /* must be interrupt for another device */
  1023. snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
  1024. irq_count,
  1025. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
  1026. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
  1027. status);
  1028. if (status & IRQ_TIMER)
  1029. {
  1030. /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */
  1031. if (chip->timer)
  1032. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1033. /* ACK timer */
  1034. spin_lock(&chip->reg_lock);
  1035. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1036. spin_unlock(&chip->reg_lock);
  1037. snd_azf3328_dbgplay("azt3328: timer IRQ\n");
  1038. }
  1039. if (status & IRQ_PLAYBACK)
  1040. {
  1041. spin_lock(&chip->reg_lock);
  1042. which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
  1043. /* ack all IRQ types immediately */
  1044. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
  1045. spin_unlock(&chip->reg_lock);
  1046. if (chip->pcm && chip->playback_substream)
  1047. {
  1048. snd_pcm_period_elapsed(chip->playback_substream);
  1049. snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
  1050. which,
  1051. inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS));
  1052. }
  1053. else
  1054. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1055. if (which & IRQ_PLAY_SOMETHING)
  1056. snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
  1057. }
  1058. if (status & IRQ_RECORDING)
  1059. {
  1060. spin_lock(&chip->reg_lock);
  1061. which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
  1062. /* ack all IRQ types immediately */
  1063. snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
  1064. spin_unlock(&chip->reg_lock);
  1065. if (chip->pcm && chip->capture_substream)
  1066. {
  1067. snd_pcm_period_elapsed(chip->capture_substream);
  1068. snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
  1069. which,
  1070. inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS));
  1071. }
  1072. else
  1073. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1074. if (which & IRQ_REC_SOMETHING)
  1075. snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
  1076. }
  1077. /* MPU401 has less critical IRQ requirements
  1078. * than timer and playback/recording, right? */
  1079. if (status & IRQ_MPU401)
  1080. {
  1081. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
  1082. /* hmm, do we have to ack the IRQ here somehow?
  1083. * If so, then I don't know how... */
  1084. snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
  1085. }
  1086. irq_count++;
  1087. return IRQ_HANDLED;
  1088. }
  1089. /*****************************************************************/
  1090. static const struct snd_pcm_hardware snd_azf3328_playback =
  1091. {
  1092. /* FIXME!! Correct? */
  1093. .info = SNDRV_PCM_INFO_MMAP |
  1094. SNDRV_PCM_INFO_INTERLEAVED |
  1095. SNDRV_PCM_INFO_MMAP_VALID,
  1096. .formats = SNDRV_PCM_FMTBIT_S8 |
  1097. SNDRV_PCM_FMTBIT_U8 |
  1098. SNDRV_PCM_FMTBIT_S16_LE |
  1099. SNDRV_PCM_FMTBIT_U16_LE,
  1100. .rates = SNDRV_PCM_RATE_5512 |
  1101. SNDRV_PCM_RATE_8000_48000 |
  1102. SNDRV_PCM_RATE_KNOT,
  1103. .rate_min = 4000,
  1104. .rate_max = 66200,
  1105. .channels_min = 1,
  1106. .channels_max = 2,
  1107. .buffer_bytes_max = 65536,
  1108. .period_bytes_min = 64,
  1109. .period_bytes_max = 65536,
  1110. .periods_min = 1,
  1111. .periods_max = 1024,
  1112. /* FIXME: maybe that card actually has a FIFO?
  1113. * Hmm, it seems newer revisions do have one, but we still don't know
  1114. * its size... */
  1115. .fifo_size = 0,
  1116. };
  1117. static const struct snd_pcm_hardware snd_azf3328_capture =
  1118. {
  1119. /* FIXME */
  1120. .info = SNDRV_PCM_INFO_MMAP |
  1121. SNDRV_PCM_INFO_INTERLEAVED |
  1122. SNDRV_PCM_INFO_MMAP_VALID,
  1123. .formats = SNDRV_PCM_FMTBIT_S8 |
  1124. SNDRV_PCM_FMTBIT_U8 |
  1125. SNDRV_PCM_FMTBIT_S16_LE |
  1126. SNDRV_PCM_FMTBIT_U16_LE,
  1127. .rates = SNDRV_PCM_RATE_5512 |
  1128. SNDRV_PCM_RATE_8000_48000 |
  1129. SNDRV_PCM_RATE_KNOT,
  1130. .rate_min = 4000,
  1131. .rate_max = 66200,
  1132. .channels_min = 1,
  1133. .channels_max = 2,
  1134. .buffer_bytes_max = 65536,
  1135. .period_bytes_min = 64,
  1136. .period_bytes_max = 65536,
  1137. .periods_min = 1,
  1138. .periods_max = 1024,
  1139. .fifo_size = 0,
  1140. };
  1141. static unsigned int snd_azf3328_fixed_rates[] = {
  1142. 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000,
  1143. 44100, 48000, 66200 };
  1144. static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1145. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1146. .list = snd_azf3328_fixed_rates,
  1147. .mask = 0,
  1148. };
  1149. /*****************************************************************/
  1150. static int
  1151. snd_azf3328_playback_open(struct snd_pcm_substream *substream)
  1152. {
  1153. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1154. struct snd_pcm_runtime *runtime = substream->runtime;
  1155. snd_azf3328_dbgcallenter();
  1156. chip->playback_substream = substream;
  1157. runtime->hw = snd_azf3328_playback;
  1158. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1159. &snd_azf3328_hw_constraints_rates);
  1160. snd_azf3328_dbgcallleave();
  1161. return 0;
  1162. }
  1163. static int
  1164. snd_azf3328_capture_open(struct snd_pcm_substream *substream)
  1165. {
  1166. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1167. struct snd_pcm_runtime *runtime = substream->runtime;
  1168. snd_azf3328_dbgcallenter();
  1169. chip->capture_substream = substream;
  1170. runtime->hw = snd_azf3328_capture;
  1171. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1172. &snd_azf3328_hw_constraints_rates);
  1173. snd_azf3328_dbgcallleave();
  1174. return 0;
  1175. }
  1176. static int
  1177. snd_azf3328_playback_close(struct snd_pcm_substream *substream)
  1178. {
  1179. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1180. snd_azf3328_dbgcallenter();
  1181. chip->playback_substream = NULL;
  1182. snd_azf3328_dbgcallleave();
  1183. return 0;
  1184. }
  1185. static int
  1186. snd_azf3328_capture_close(struct snd_pcm_substream *substream)
  1187. {
  1188. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1189. snd_azf3328_dbgcallenter();
  1190. chip->capture_substream = NULL;
  1191. snd_azf3328_dbgcallleave();
  1192. return 0;
  1193. }
  1194. /******************************************************************/
  1195. static struct snd_pcm_ops snd_azf3328_playback_ops = {
  1196. .open = snd_azf3328_playback_open,
  1197. .close = snd_azf3328_playback_close,
  1198. .ioctl = snd_pcm_lib_ioctl,
  1199. .hw_params = snd_azf3328_hw_params,
  1200. .hw_free = snd_azf3328_hw_free,
  1201. .prepare = snd_azf3328_playback_prepare,
  1202. .trigger = snd_azf3328_playback_trigger,
  1203. .pointer = snd_azf3328_playback_pointer
  1204. };
  1205. static struct snd_pcm_ops snd_azf3328_capture_ops = {
  1206. .open = snd_azf3328_capture_open,
  1207. .close = snd_azf3328_capture_close,
  1208. .ioctl = snd_pcm_lib_ioctl,
  1209. .hw_params = snd_azf3328_hw_params,
  1210. .hw_free = snd_azf3328_hw_free,
  1211. .prepare = snd_azf3328_capture_prepare,
  1212. .trigger = snd_azf3328_capture_trigger,
  1213. .pointer = snd_azf3328_capture_pointer
  1214. };
  1215. static int __devinit
  1216. snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
  1217. {
  1218. struct snd_pcm *pcm;
  1219. int err;
  1220. snd_azf3328_dbgcallenter();
  1221. if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
  1222. return err;
  1223. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
  1224. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
  1225. pcm->private_data = chip;
  1226. pcm->info_flags = 0;
  1227. strcpy(pcm->name, chip->card->shortname);
  1228. chip->pcm = pcm;
  1229. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1230. snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
  1231. snd_azf3328_dbgcallleave();
  1232. return 0;
  1233. }
  1234. /******************************************************************/
  1235. #ifdef SUPPORT_JOYSTICK
  1236. static int __devinit
  1237. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev)
  1238. {
  1239. struct gameport *gp;
  1240. struct resource *r;
  1241. if (!joystick[dev])
  1242. return -ENODEV;
  1243. if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) {
  1244. printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n");
  1245. return -EBUSY;
  1246. }
  1247. chip->gameport = gp = gameport_allocate_port();
  1248. if (!gp) {
  1249. printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n");
  1250. release_and_free_resource(r);
  1251. return -ENOMEM;
  1252. }
  1253. gameport_set_name(gp, "AZF3328 Gameport");
  1254. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1255. gameport_set_dev_parent(gp, &chip->pci->dev);
  1256. gp->io = 0x200;
  1257. gameport_set_port_data(gp, r);
  1258. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1259. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY);
  1260. gameport_register_port(chip->gameport);
  1261. return 0;
  1262. }
  1263. static void
  1264. snd_azf3328_free_joystick(struct snd_azf3328 *chip)
  1265. {
  1266. if (chip->gameport) {
  1267. struct resource *r = gameport_get_port_data(chip->gameport);
  1268. gameport_unregister_port(chip->gameport);
  1269. chip->gameport = NULL;
  1270. /* disable gameport */
  1271. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1272. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1273. release_and_free_resource(r);
  1274. }
  1275. }
  1276. #else
  1277. static inline int
  1278. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1279. static inline void
  1280. snd_azf3328_free_joystick(struct snd_azf3328 *chip) { }
  1281. #endif
  1282. /******************************************************************/
  1283. static int
  1284. snd_azf3328_free(struct snd_azf3328 *chip)
  1285. {
  1286. if (chip->irq < 0)
  1287. goto __end_hw;
  1288. /* reset (close) mixer */
  1289. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */
  1290. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1291. /* interrupt setup - mask everything (FIXME!) */
  1292. /* well, at least we know how to disable the timer IRQ */
  1293. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00);
  1294. synchronize_irq(chip->irq);
  1295. __end_hw:
  1296. snd_azf3328_free_joystick(chip);
  1297. if (chip->irq >= 0)
  1298. free_irq(chip->irq, (void *)chip);
  1299. pci_release_regions(chip->pci);
  1300. pci_disable_device(chip->pci);
  1301. kfree(chip);
  1302. return 0;
  1303. }
  1304. static int
  1305. snd_azf3328_dev_free(struct snd_device *device)
  1306. {
  1307. struct snd_azf3328 *chip = device->device_data;
  1308. return snd_azf3328_free(chip);
  1309. }
  1310. /******************************************************************/
  1311. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second,
  1312. *** but announcing those attributes to user-space would make programs
  1313. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1314. *** timer IRQ storm.
  1315. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1316. *** calculate real timer countdown values internally.
  1317. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1318. ***/
  1319. static int
  1320. snd_azf3328_timer_start(struct snd_timer *timer)
  1321. {
  1322. struct snd_azf3328 *chip;
  1323. unsigned long flags;
  1324. unsigned int delay;
  1325. snd_azf3328_dbgcallenter();
  1326. chip = snd_timer_chip(timer);
  1327. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1328. if (delay < 49)
  1329. {
  1330. /* uhoh, that's not good, since user-space won't know about
  1331. * this timing tweak
  1332. * (we need to do it to avoid a lockup, though) */
  1333. snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
  1334. delay = 49; /* minimum time is 49 ticks */
  1335. }
  1336. snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
  1337. delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ;
  1338. spin_lock_irqsave(&chip->reg_lock, flags);
  1339. snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1340. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1341. snd_azf3328_dbgcallleave();
  1342. return 0;
  1343. }
  1344. static int
  1345. snd_azf3328_timer_stop(struct snd_timer *timer)
  1346. {
  1347. struct snd_azf3328 *chip;
  1348. unsigned long flags;
  1349. snd_azf3328_dbgcallenter();
  1350. chip = snd_timer_chip(timer);
  1351. spin_lock_irqsave(&chip->reg_lock, flags);
  1352. /* disable timer countdown and interrupt */
  1353. /* FIXME: should we write TIMER_ACK_IRQ here? */
  1354. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
  1355. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1356. snd_azf3328_dbgcallleave();
  1357. return 0;
  1358. }
  1359. static int
  1360. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1361. unsigned long *num, unsigned long *den)
  1362. {
  1363. snd_azf3328_dbgcallenter();
  1364. *num = 1;
  1365. *den = 1024000 / seqtimer_scaling;
  1366. snd_azf3328_dbgcallleave();
  1367. return 0;
  1368. }
  1369. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1370. .flags = SNDRV_TIMER_HW_AUTO,
  1371. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1372. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1373. .start = snd_azf3328_timer_start,
  1374. .stop = snd_azf3328_timer_stop,
  1375. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1376. };
  1377. static int __devinit
  1378. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1379. {
  1380. struct snd_timer *timer = NULL;
  1381. struct snd_timer_id tid;
  1382. int err;
  1383. snd_azf3328_dbgcallenter();
  1384. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1385. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1386. tid.card = chip->card->number;
  1387. tid.device = device;
  1388. tid.subdevice = 0;
  1389. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1390. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1391. if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) {
  1392. goto out;
  1393. }
  1394. strcpy(timer->name, "AZF3328 timer");
  1395. timer->private_data = chip;
  1396. timer->hw = snd_azf3328_timer_hw;
  1397. chip->timer = timer;
  1398. err = 0;
  1399. out:
  1400. snd_azf3328_dbgcallleave();
  1401. return err;
  1402. }
  1403. /******************************************************************/
  1404. #if 0
  1405. /* check whether a bit can be modified */
  1406. static void
  1407. snd_azf3328_test_bit(unsigned int reg, int bit)
  1408. {
  1409. unsigned char val, valoff, valon;
  1410. val = inb(reg);
  1411. outb(val & ~(1 << bit), reg);
  1412. valoff = inb(reg);
  1413. outb(val|(1 << bit), reg);
  1414. valon = inb(reg);
  1415. outb(val, reg);
  1416. printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon);
  1417. }
  1418. #endif
  1419. static void
  1420. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  1421. {
  1422. #if DEBUG_MISC
  1423. u16 tmp;
  1424. snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq);
  1425. snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5));
  1426. for (tmp=0; tmp <= 0x01; tmp += 1)
  1427. snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp));
  1428. for (tmp = 0; tmp <= 0x6E; tmp += 2)
  1429. snd_azf3328_dbgmisc("0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inb(chip, tmp));
  1430. #endif
  1431. }
  1432. static int __devinit
  1433. snd_azf3328_create(struct snd_card *card,
  1434. struct pci_dev *pci,
  1435. unsigned long device_type,
  1436. struct snd_azf3328 ** rchip)
  1437. {
  1438. struct snd_azf3328 *chip;
  1439. int err;
  1440. static struct snd_device_ops ops = {
  1441. .dev_free = snd_azf3328_dev_free,
  1442. };
  1443. u16 tmp;
  1444. *rchip = NULL;
  1445. if ((err = pci_enable_device(pci)) < 0)
  1446. return err;
  1447. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1448. if (chip == NULL) {
  1449. err = -ENOMEM;
  1450. goto out_err;
  1451. }
  1452. spin_lock_init(&chip->reg_lock);
  1453. chip->card = card;
  1454. chip->pci = pci;
  1455. chip->irq = -1;
  1456. /* check if we can restrict PCI DMA transfers to 24 bits */
  1457. if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
  1458. pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
  1459. snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n");
  1460. err = -ENXIO;
  1461. goto out_err;
  1462. }
  1463. if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) {
  1464. goto out_err;
  1465. }
  1466. chip->codec_port = pci_resource_start(pci, 0);
  1467. chip->io2_port = pci_resource_start(pci, 1);
  1468. chip->mpu_port = pci_resource_start(pci, 2);
  1469. chip->synth_port = pci_resource_start(pci, 3);
  1470. chip->mixer_port = pci_resource_start(pci, 4);
  1471. if (request_irq(pci->irq, snd_azf3328_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
  1472. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1473. err = -EBUSY;
  1474. goto out_err;
  1475. }
  1476. chip->irq = pci->irq;
  1477. pci_set_master(pci);
  1478. synchronize_irq(chip->irq);
  1479. snd_azf3328_debug_show_ports(chip);
  1480. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1481. goto out_err;
  1482. }
  1483. /* create mixer interface & switches */
  1484. if ((err = snd_azf3328_mixer_new(chip)) < 0)
  1485. goto out_err;
  1486. #if 0
  1487. /* set very low bitrate to reduce noise and power consumption? */
  1488. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 5512, 8, 1);
  1489. #endif
  1490. /* standard chip init stuff */
  1491. /* default IRQ init value */
  1492. tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  1493. spin_lock_irq(&chip->reg_lock);
  1494. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
  1495. snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
  1496. snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
  1497. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */
  1498. spin_unlock_irq(&chip->reg_lock);
  1499. snd_card_set_dev(card, &pci->dev);
  1500. *rchip = chip;
  1501. err = 0;
  1502. goto out;
  1503. out_err:
  1504. if (chip)
  1505. snd_azf3328_free(chip);
  1506. pci_disable_device(pci);
  1507. out:
  1508. return err;
  1509. }
  1510. static int __devinit
  1511. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1512. {
  1513. static int dev;
  1514. struct snd_card *card;
  1515. struct snd_azf3328 *chip;
  1516. struct snd_opl3 *opl3;
  1517. int err;
  1518. snd_azf3328_dbgcallenter();
  1519. if (dev >= SNDRV_CARDS)
  1520. return -ENODEV;
  1521. if (!enable[dev]) {
  1522. dev++;
  1523. return -ENOENT;
  1524. }
  1525. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 );
  1526. if (card == NULL)
  1527. return -ENOMEM;
  1528. strcpy(card->driver, "AZF3328");
  1529. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  1530. if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1531. goto out_err;
  1532. }
  1533. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401,
  1534. chip->mpu_port, 1, pci->irq, 0,
  1535. &chip->rmidi)) < 0) {
  1536. snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port);
  1537. goto out_err;
  1538. }
  1539. if ((err = snd_azf3328_timer(chip, 0)) < 0) {
  1540. goto out_err;
  1541. }
  1542. if ((err = snd_azf3328_pcm(chip, 0)) < 0) {
  1543. goto out_err;
  1544. }
  1545. if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2,
  1546. OPL3_HW_AUTO, 1, &opl3) < 0) {
  1547. snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
  1548. chip->synth_port, chip->synth_port+2 );
  1549. } else {
  1550. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1551. goto out_err;
  1552. }
  1553. }
  1554. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1555. card->shortname, chip->codec_port, chip->irq);
  1556. if ((err = snd_card_register(card)) < 0) {
  1557. goto out_err;
  1558. }
  1559. #ifdef MODULE
  1560. printk(
  1561. "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168\n"
  1562. "azt3328: (hardware was completely undocumented - ZERO support from Aztech).\n"
  1563. "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
  1564. "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  1565. 1024000 / seqtimer_scaling, seqtimer_scaling);
  1566. #endif
  1567. if (snd_azf3328_config_joystick(chip, dev) < 0)
  1568. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1569. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1570. pci_set_drvdata(pci, card);
  1571. dev++;
  1572. err = 0;
  1573. goto out;
  1574. out_err:
  1575. snd_card_free(card);
  1576. out:
  1577. snd_azf3328_dbgcallleave();
  1578. return err;
  1579. }
  1580. static void __devexit
  1581. snd_azf3328_remove(struct pci_dev *pci)
  1582. {
  1583. snd_azf3328_dbgcallenter();
  1584. snd_card_free(pci_get_drvdata(pci));
  1585. pci_set_drvdata(pci, NULL);
  1586. snd_azf3328_dbgcallleave();
  1587. }
  1588. static struct pci_driver driver = {
  1589. .name = "AZF3328",
  1590. .id_table = snd_azf3328_ids,
  1591. .probe = snd_azf3328_probe,
  1592. .remove = __devexit_p(snd_azf3328_remove),
  1593. };
  1594. static int __init
  1595. alsa_card_azf3328_init(void)
  1596. {
  1597. int err;
  1598. snd_azf3328_dbgcallenter();
  1599. err = pci_register_driver(&driver);
  1600. snd_azf3328_dbgcallleave();
  1601. return err;
  1602. }
  1603. static void __exit
  1604. alsa_card_azf3328_exit(void)
  1605. {
  1606. snd_azf3328_dbgcallenter();
  1607. pci_unregister_driver(&driver);
  1608. snd_azf3328_dbgcallleave();
  1609. }
  1610. module_init(alsa_card_azf3328_init)
  1611. module_exit(alsa_card_azf3328_exit)