sonicvibes.c 80 KB

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  1. /*****************************************************************************/
  2. /*
  3. * sonicvibes.c -- S3 Sonic Vibes audio driver.
  4. *
  5. * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. * Special thanks to David C. Niemi
  22. *
  23. *
  24. * Module command line parameters:
  25. * none so far
  26. *
  27. *
  28. * Supported devices:
  29. * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
  30. * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
  31. * /dev/midi simple MIDI UART interface, no ioctl
  32. *
  33. * The card has both an FM and a Wavetable synth, but I have to figure
  34. * out first how to drive them...
  35. *
  36. * Revision history
  37. * 06.05.1998 0.1 Initial release
  38. * 10.05.1998 0.2 Fixed many bugs, esp. ADC rate calculation
  39. * First stab at a simple midi interface (no bells&whistles)
  40. * 13.05.1998 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
  41. * set_dac_rate in the FMODE_WRITE case in sv_open
  42. * Fix hwptr out of bounds (now mpg123 works)
  43. * 14.05.1998 0.4 Don't allow excessive interrupt rates
  44. * 08.06.1998 0.5 First release using Alan Cox' soundcore instead of miscdevice
  45. * 03.08.1998 0.6 Do not include modversions.h
  46. * Now mixer behaviour can basically be selected between
  47. * "OSS documented" and "OSS actual" behaviour
  48. * 31.08.1998 0.7 Fix realplayer problems - dac.count issues
  49. * 10.12.1998 0.8 Fix drain_dac trying to wait on not yet initialized DMA
  50. * 16.12.1998 0.9 Fix a few f_file & FMODE_ bugs
  51. * 06.01.1999 0.10 remove the silly SA_INTERRUPT flag.
  52. * hopefully killed the egcs section type conflict
  53. * 12.03.1999 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
  54. * reported by Johan Maes <joma@telindus.be>
  55. * 22.03.1999 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
  56. * read/write cannot be executed
  57. * 05.04.1999 0.13 added code to sv_read and sv_write which should detect
  58. * lockups of the sound chip and revive it. This is basically
  59. * an ugly hack, but at least applications using this driver
  60. * won't hang forever. I don't know why these lockups happen,
  61. * it might well be the motherboard chipset (an early 486 PCI
  62. * board with ALI chipset), since every busmastering 100MB
  63. * ethernet card I've tried (Realtek 8139 and Macronix tulip clone)
  64. * exhibit similar behaviour (they work for a couple of packets
  65. * and then lock up and can be revived by ifconfig down/up).
  66. * 07.04.1999 0.14 implemented the following ioctl's: SOUND_PCM_READ_RATE,
  67. * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
  68. * Alpha fixes reported by Peter Jones <pjones@redhat.com>
  69. * Note: dmaio hack might still be wrong on archs other than i386
  70. * 15.06.1999 0.15 Fix bad allocation bug.
  71. * Thanks to Deti Fliegl <fliegl@in.tum.de>
  72. * 28.06.1999 0.16 Add pci_set_master
  73. * 03.08.1999 0.17 adapt to Linus' new __setup/__initcall
  74. * added kernel command line options "sonicvibes=reverb" and "sonicvibesdmaio=dmaioaddr"
  75. * 12.08.1999 0.18 module_init/__setup fixes
  76. * 24.08.1999 0.19 get rid of the dmaio kludge, replace with allocate_resource
  77. * 31.08.1999 0.20 add spin_lock_init
  78. * use new resource allocation to allocate DDMA IO space
  79. * replaced current->state = x with set_current_state(x)
  80. * 03.09.1999 0.21 change read semantics for MIDI to match
  81. * OSS more closely; remove possible wakeup race
  82. * 28.10.1999 0.22 More waitqueue races fixed
  83. * 01.12.1999 0.23 New argument to allocate_resource
  84. * 07.12.1999 0.24 More allocate_resource semantics change
  85. * 08.01.2000 0.25 Prevent some ioctl's from returning bad count values on underrun/overrun;
  86. * Tim Janik's BSE (Bedevilled Sound Engine) found this
  87. * use Martin Mares' pci_assign_resource
  88. * 07.02.2000 0.26 Use pci_alloc_consistent and pci_register_driver
  89. * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
  90. * 12.12.2000 0.28 More dma buffer initializations, patch from
  91. * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
  92. * 31.01.2001 0.29 Register/Unregister gameport
  93. * Fix SETTRIGGER non OSS API conformity
  94. * 18.05.2001 0.30 PCI probing and error values cleaned up by Marcus
  95. * Meissner <mm@caldera.de>
  96. * 03.01.2003 0.31 open_mode fixes from Georg Acher <acher@in.tum.de>
  97. *
  98. */
  99. /*****************************************************************************/
  100. #include <linux/module.h>
  101. #include <linux/string.h>
  102. #include <linux/ioport.h>
  103. #include <linux/interrupt.h>
  104. #include <linux/wait.h>
  105. #include <linux/mm.h>
  106. #include <linux/delay.h>
  107. #include <linux/sound.h>
  108. #include <linux/slab.h>
  109. #include <linux/soundcard.h>
  110. #include <linux/pci.h>
  111. #include <linux/init.h>
  112. #include <linux/poll.h>
  113. #include <linux/spinlock.h>
  114. #include <linux/smp_lock.h>
  115. #include <linux/gameport.h>
  116. #include <linux/dma-mapping.h>
  117. #include <linux/mutex.h>
  118. #include <asm/io.h>
  119. #include <asm/uaccess.h>
  120. #include "dm.h"
  121. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  122. #define SUPPORT_JOYSTICK 1
  123. #endif
  124. /* --------------------------------------------------------------------- */
  125. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  126. /* --------------------------------------------------------------------- */
  127. #ifndef PCI_VENDOR_ID_S3
  128. #define PCI_VENDOR_ID_S3 0x5333
  129. #endif
  130. #ifndef PCI_DEVICE_ID_S3_SONICVIBES
  131. #define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
  132. #endif
  133. #define SV_MAGIC ((PCI_VENDOR_ID_S3<<16)|PCI_DEVICE_ID_S3_SONICVIBES)
  134. #define SV_EXTENT_SB 0x10
  135. #define SV_EXTENT_ENH 0x10
  136. #define SV_EXTENT_SYNTH 0x4
  137. #define SV_EXTENT_MIDI 0x4
  138. #define SV_EXTENT_GAME 0x8
  139. #define SV_EXTENT_DMA 0x10
  140. /*
  141. * we are not a bridge and thus use a resource for DDMA that is used for bridges but
  142. * left empty for normal devices
  143. */
  144. #define RESOURCE_SB 0
  145. #define RESOURCE_ENH 1
  146. #define RESOURCE_SYNTH 2
  147. #define RESOURCE_MIDI 3
  148. #define RESOURCE_GAME 4
  149. #define RESOURCE_DDMA 7
  150. #define SV_MIDI_DATA 0
  151. #define SV_MIDI_COMMAND 1
  152. #define SV_MIDI_STATUS 1
  153. #define SV_DMA_ADDR0 0
  154. #define SV_DMA_ADDR1 1
  155. #define SV_DMA_ADDR2 2
  156. #define SV_DMA_ADDR3 3
  157. #define SV_DMA_COUNT0 4
  158. #define SV_DMA_COUNT1 5
  159. #define SV_DMA_COUNT2 6
  160. #define SV_DMA_MODE 0xb
  161. #define SV_DMA_RESET 0xd
  162. #define SV_DMA_MASK 0xf
  163. /*
  164. * DONT reset the DMA controllers unless you understand
  165. * the reset semantics. Assuming reset semantics as in
  166. * the 8237 does not work.
  167. */
  168. #define DMA_MODE_AUTOINIT 0x10
  169. #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
  170. #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
  171. #define SV_CODEC_CONTROL 0
  172. #define SV_CODEC_INTMASK 1
  173. #define SV_CODEC_STATUS 2
  174. #define SV_CODEC_IADDR 4
  175. #define SV_CODEC_IDATA 5
  176. #define SV_CCTRL_RESET 0x80
  177. #define SV_CCTRL_INTADRIVE 0x20
  178. #define SV_CCTRL_WAVETABLE 0x08
  179. #define SV_CCTRL_REVERB 0x04
  180. #define SV_CCTRL_ENHANCED 0x01
  181. #define SV_CINTMASK_DMAA 0x01
  182. #define SV_CINTMASK_DMAC 0x04
  183. #define SV_CINTMASK_SPECIAL 0x08
  184. #define SV_CINTMASK_UPDOWN 0x40
  185. #define SV_CINTMASK_MIDI 0x80
  186. #define SV_CSTAT_DMAA 0x01
  187. #define SV_CSTAT_DMAC 0x04
  188. #define SV_CSTAT_SPECIAL 0x08
  189. #define SV_CSTAT_UPDOWN 0x40
  190. #define SV_CSTAT_MIDI 0x80
  191. #define SV_CIADDR_TRD 0x80
  192. #define SV_CIADDR_MCE 0x40
  193. /* codec indirect registers */
  194. #define SV_CIMIX_ADCINL 0x00
  195. #define SV_CIMIX_ADCINR 0x01
  196. #define SV_CIMIX_AUX1INL 0x02
  197. #define SV_CIMIX_AUX1INR 0x03
  198. #define SV_CIMIX_CDINL 0x04
  199. #define SV_CIMIX_CDINR 0x05
  200. #define SV_CIMIX_LINEINL 0x06
  201. #define SV_CIMIX_LINEINR 0x07
  202. #define SV_CIMIX_MICIN 0x08
  203. #define SV_CIMIX_SYNTHINL 0x0A
  204. #define SV_CIMIX_SYNTHINR 0x0B
  205. #define SV_CIMIX_AUX2INL 0x0C
  206. #define SV_CIMIX_AUX2INR 0x0D
  207. #define SV_CIMIX_ANALOGINL 0x0E
  208. #define SV_CIMIX_ANALOGINR 0x0F
  209. #define SV_CIMIX_PCMINL 0x10
  210. #define SV_CIMIX_PCMINR 0x11
  211. #define SV_CIGAMECONTROL 0x09
  212. #define SV_CIDATAFMT 0x12
  213. #define SV_CIENABLE 0x13
  214. #define SV_CIUPDOWN 0x14
  215. #define SV_CIREVISION 0x15
  216. #define SV_CIADCOUTPUT 0x16
  217. #define SV_CIDMAABASECOUNT1 0x18
  218. #define SV_CIDMAABASECOUNT0 0x19
  219. #define SV_CIDMACBASECOUNT1 0x1c
  220. #define SV_CIDMACBASECOUNT0 0x1d
  221. #define SV_CIPCMSR0 0x1e
  222. #define SV_CIPCMSR1 0x1f
  223. #define SV_CISYNTHSR0 0x20
  224. #define SV_CISYNTHSR1 0x21
  225. #define SV_CIADCCLKSOURCE 0x22
  226. #define SV_CIADCALTSR 0x23
  227. #define SV_CIADCPLLM 0x24
  228. #define SV_CIADCPLLN 0x25
  229. #define SV_CISYNTHPLLM 0x26
  230. #define SV_CISYNTHPLLN 0x27
  231. #define SV_CIUARTCONTROL 0x2a
  232. #define SV_CIDRIVECONTROL 0x2b
  233. #define SV_CISRSSPACE 0x2c
  234. #define SV_CISRSCENTER 0x2d
  235. #define SV_CIWAVETABLESRC 0x2e
  236. #define SV_CIANALOGPWRDOWN 0x30
  237. #define SV_CIDIGITALPWRDOWN 0x31
  238. #define SV_CIMIX_ADCSRC_CD 0x20
  239. #define SV_CIMIX_ADCSRC_DAC 0x40
  240. #define SV_CIMIX_ADCSRC_AUX2 0x60
  241. #define SV_CIMIX_ADCSRC_LINE 0x80
  242. #define SV_CIMIX_ADCSRC_AUX1 0xa0
  243. #define SV_CIMIX_ADCSRC_MIC 0xc0
  244. #define SV_CIMIX_ADCSRC_MIXOUT 0xe0
  245. #define SV_CIMIX_ADCSRC_MASK 0xe0
  246. #define SV_CFMT_STEREO 0x01
  247. #define SV_CFMT_16BIT 0x02
  248. #define SV_CFMT_MASK 0x03
  249. #define SV_CFMT_ASHIFT 0
  250. #define SV_CFMT_CSHIFT 4
  251. static const unsigned sample_size[] = { 1, 2, 2, 4 };
  252. static const unsigned sample_shift[] = { 0, 1, 1, 2 };
  253. #define SV_CENABLE_PPE 0x4
  254. #define SV_CENABLE_RE 0x2
  255. #define SV_CENABLE_PE 0x1
  256. /* MIDI buffer sizes */
  257. #define MIDIINBUF 256
  258. #define MIDIOUTBUF 256
  259. #define FMODE_MIDI_SHIFT 2
  260. #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
  261. #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
  262. #define FMODE_DMFM 0x10
  263. /* --------------------------------------------------------------------- */
  264. struct sv_state {
  265. /* magic */
  266. unsigned int magic;
  267. /* list of sonicvibes devices */
  268. struct list_head devs;
  269. /* the corresponding pci_dev structure */
  270. struct pci_dev *dev;
  271. /* soundcore stuff */
  272. int dev_audio;
  273. int dev_mixer;
  274. int dev_midi;
  275. int dev_dmfm;
  276. /* hardware resources */
  277. unsigned long iosb, ioenh, iosynth, iomidi; /* long for SPARC */
  278. unsigned int iodmaa, iodmac, irq;
  279. /* mixer stuff */
  280. struct {
  281. unsigned int modcnt;
  282. #ifndef OSS_DOCUMENTED_MIXER_SEMANTICS
  283. unsigned short vol[13];
  284. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  285. } mix;
  286. /* wave stuff */
  287. unsigned int rateadc, ratedac;
  288. unsigned char fmt, enable;
  289. spinlock_t lock;
  290. struct mutex open_mutex;
  291. mode_t open_mode;
  292. wait_queue_head_t open_wait;
  293. struct dmabuf {
  294. void *rawbuf;
  295. dma_addr_t dmaaddr;
  296. unsigned buforder;
  297. unsigned numfrag;
  298. unsigned fragshift;
  299. unsigned hwptr, swptr;
  300. unsigned total_bytes;
  301. int count;
  302. unsigned error; /* over/underrun */
  303. wait_queue_head_t wait;
  304. /* redundant, but makes calculations easier */
  305. unsigned fragsize;
  306. unsigned dmasize;
  307. unsigned fragsamples;
  308. /* OSS stuff */
  309. unsigned mapped:1;
  310. unsigned ready:1;
  311. unsigned endcleared:1;
  312. unsigned enabled:1;
  313. unsigned ossfragshift;
  314. int ossmaxfrags;
  315. unsigned subdivision;
  316. } dma_dac, dma_adc;
  317. /* midi stuff */
  318. struct {
  319. unsigned ird, iwr, icnt;
  320. unsigned ord, owr, ocnt;
  321. wait_queue_head_t iwait;
  322. wait_queue_head_t owait;
  323. struct timer_list timer;
  324. unsigned char ibuf[MIDIINBUF];
  325. unsigned char obuf[MIDIOUTBUF];
  326. } midi;
  327. #if SUPPORT_JOYSTICK
  328. struct gameport *gameport;
  329. #endif
  330. };
  331. /* --------------------------------------------------------------------- */
  332. static LIST_HEAD(devs);
  333. static unsigned long wavetable_mem;
  334. /* --------------------------------------------------------------------- */
  335. static inline unsigned ld2(unsigned int x)
  336. {
  337. unsigned r = 0;
  338. if (x >= 0x10000) {
  339. x >>= 16;
  340. r += 16;
  341. }
  342. if (x >= 0x100) {
  343. x >>= 8;
  344. r += 8;
  345. }
  346. if (x >= 0x10) {
  347. x >>= 4;
  348. r += 4;
  349. }
  350. if (x >= 4) {
  351. x >>= 2;
  352. r += 2;
  353. }
  354. if (x >= 2)
  355. r++;
  356. return r;
  357. }
  358. /* --------------------------------------------------------------------- */
  359. /*
  360. * Why use byte IO? Nobody knows, but S3 does it also in their Windows driver.
  361. */
  362. #undef DMABYTEIO
  363. static void set_dmaa(struct sv_state *s, unsigned int addr, unsigned int count)
  364. {
  365. #ifdef DMABYTEIO
  366. unsigned io = s->iodmaa, u;
  367. count--;
  368. for (u = 4; u > 0; u--, addr >>= 8, io++)
  369. outb(addr & 0xff, io);
  370. for (u = 3; u > 0; u--, count >>= 8, io++)
  371. outb(count & 0xff, io);
  372. #else /* DMABYTEIO */
  373. count--;
  374. outl(addr, s->iodmaa + SV_DMA_ADDR0);
  375. outl(count, s->iodmaa + SV_DMA_COUNT0);
  376. #endif /* DMABYTEIO */
  377. outb(0x18, s->iodmaa + SV_DMA_MODE);
  378. }
  379. static void set_dmac(struct sv_state *s, unsigned int addr, unsigned int count)
  380. {
  381. #ifdef DMABYTEIO
  382. unsigned io = s->iodmac, u;
  383. count >>= 1;
  384. count--;
  385. for (u = 4; u > 0; u--, addr >>= 8, io++)
  386. outb(addr & 0xff, io);
  387. for (u = 3; u > 0; u--, count >>= 8, io++)
  388. outb(count & 0xff, io);
  389. #else /* DMABYTEIO */
  390. count >>= 1;
  391. count--;
  392. outl(addr, s->iodmac + SV_DMA_ADDR0);
  393. outl(count, s->iodmac + SV_DMA_COUNT0);
  394. #endif /* DMABYTEIO */
  395. outb(0x14, s->iodmac + SV_DMA_MODE);
  396. }
  397. static inline unsigned get_dmaa(struct sv_state *s)
  398. {
  399. #ifdef DMABYTEIO
  400. unsigned io = s->iodmaa+6, v = 0, u;
  401. for (u = 3; u > 0; u--, io--) {
  402. v <<= 8;
  403. v |= inb(io);
  404. }
  405. return v + 1;
  406. #else /* DMABYTEIO */
  407. return (inl(s->iodmaa + SV_DMA_COUNT0) & 0xffffff) + 1;
  408. #endif /* DMABYTEIO */
  409. }
  410. static inline unsigned get_dmac(struct sv_state *s)
  411. {
  412. #ifdef DMABYTEIO
  413. unsigned io = s->iodmac+6, v = 0, u;
  414. for (u = 3; u > 0; u--, io--) {
  415. v <<= 8;
  416. v |= inb(io);
  417. }
  418. return (v + 1) << 1;
  419. #else /* DMABYTEIO */
  420. return ((inl(s->iodmac + SV_DMA_COUNT0) & 0xffffff) + 1) << 1;
  421. #endif /* DMABYTEIO */
  422. }
  423. static void wrindir(struct sv_state *s, unsigned char idx, unsigned char data)
  424. {
  425. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  426. udelay(10);
  427. outb(data, s->ioenh + SV_CODEC_IDATA);
  428. udelay(10);
  429. }
  430. static unsigned char rdindir(struct sv_state *s, unsigned char idx)
  431. {
  432. unsigned char v;
  433. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  434. udelay(10);
  435. v = inb(s->ioenh + SV_CODEC_IDATA);
  436. udelay(10);
  437. return v;
  438. }
  439. static void set_fmt(struct sv_state *s, unsigned char mask, unsigned char data)
  440. {
  441. unsigned long flags;
  442. spin_lock_irqsave(&s->lock, flags);
  443. outb(SV_CIDATAFMT | SV_CIADDR_MCE, s->ioenh + SV_CODEC_IADDR);
  444. if (mask) {
  445. s->fmt = inb(s->ioenh + SV_CODEC_IDATA);
  446. udelay(10);
  447. }
  448. s->fmt = (s->fmt & mask) | data;
  449. outb(s->fmt, s->ioenh + SV_CODEC_IDATA);
  450. udelay(10);
  451. outb(0, s->ioenh + SV_CODEC_IADDR);
  452. spin_unlock_irqrestore(&s->lock, flags);
  453. udelay(10);
  454. }
  455. static void frobindir(struct sv_state *s, unsigned char idx, unsigned char mask, unsigned char data)
  456. {
  457. outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
  458. udelay(10);
  459. outb((inb(s->ioenh + SV_CODEC_IDATA) & mask) ^ data, s->ioenh + SV_CODEC_IDATA);
  460. udelay(10);
  461. }
  462. #define REFFREQUENCY 24576000
  463. #define ADCMULT 512
  464. #define FULLRATE 48000
  465. static unsigned setpll(struct sv_state *s, unsigned char reg, unsigned rate)
  466. {
  467. unsigned long flags;
  468. unsigned char r, m=0, n=0;
  469. unsigned xm, xn, xr, xd, metric = ~0U;
  470. /* the warnings about m and n used uninitialized are bogus and may safely be ignored */
  471. if (rate < 625000/ADCMULT)
  472. rate = 625000/ADCMULT;
  473. if (rate > 150000000/ADCMULT)
  474. rate = 150000000/ADCMULT;
  475. /* slight violation of specs, needed for continuous sampling rates */
  476. for (r = 0; rate < 75000000/ADCMULT; r += 0x20, rate <<= 1);
  477. for (xn = 3; xn < 35; xn++)
  478. for (xm = 3; xm < 130; xm++) {
  479. xr = REFFREQUENCY/ADCMULT * xm / xn;
  480. xd = abs((signed)(xr - rate));
  481. if (xd < metric) {
  482. metric = xd;
  483. m = xm - 2;
  484. n = xn - 2;
  485. }
  486. }
  487. reg &= 0x3f;
  488. spin_lock_irqsave(&s->lock, flags);
  489. outb(reg, s->ioenh + SV_CODEC_IADDR);
  490. udelay(10);
  491. outb(m, s->ioenh + SV_CODEC_IDATA);
  492. udelay(10);
  493. outb(reg+1, s->ioenh + SV_CODEC_IADDR);
  494. udelay(10);
  495. outb(r | n, s->ioenh + SV_CODEC_IDATA);
  496. spin_unlock_irqrestore(&s->lock, flags);
  497. udelay(10);
  498. return (REFFREQUENCY/ADCMULT * (m + 2) / (n + 2)) >> ((r >> 5) & 7);
  499. }
  500. #if 0
  501. static unsigned getpll(struct sv_state *s, unsigned char reg)
  502. {
  503. unsigned long flags;
  504. unsigned char m, n;
  505. reg &= 0x3f;
  506. spin_lock_irqsave(&s->lock, flags);
  507. outb(reg, s->ioenh + SV_CODEC_IADDR);
  508. udelay(10);
  509. m = inb(s->ioenh + SV_CODEC_IDATA);
  510. udelay(10);
  511. outb(reg+1, s->ioenh + SV_CODEC_IADDR);
  512. udelay(10);
  513. n = inb(s->ioenh + SV_CODEC_IDATA);
  514. spin_unlock_irqrestore(&s->lock, flags);
  515. udelay(10);
  516. return (REFFREQUENCY/ADCMULT * (m + 2) / ((n & 0x1f) + 2)) >> ((n >> 5) & 7);
  517. }
  518. #endif
  519. static void set_dac_rate(struct sv_state *s, unsigned rate)
  520. {
  521. unsigned div;
  522. unsigned long flags;
  523. if (rate > 48000)
  524. rate = 48000;
  525. if (rate < 4000)
  526. rate = 4000;
  527. div = (rate * 65536 + FULLRATE/2) / FULLRATE;
  528. if (div > 65535)
  529. div = 65535;
  530. spin_lock_irqsave(&s->lock, flags);
  531. wrindir(s, SV_CIPCMSR1, div >> 8);
  532. wrindir(s, SV_CIPCMSR0, div);
  533. spin_unlock_irqrestore(&s->lock, flags);
  534. s->ratedac = (div * FULLRATE + 32768) / 65536;
  535. }
  536. static void set_adc_rate(struct sv_state *s, unsigned rate)
  537. {
  538. unsigned long flags;
  539. unsigned rate1, rate2, div;
  540. if (rate > 48000)
  541. rate = 48000;
  542. if (rate < 4000)
  543. rate = 4000;
  544. rate1 = setpll(s, SV_CIADCPLLM, rate);
  545. div = (48000 + rate/2) / rate;
  546. if (div > 8)
  547. div = 8;
  548. rate2 = (48000 + div/2) / div;
  549. spin_lock_irqsave(&s->lock, flags);
  550. wrindir(s, SV_CIADCALTSR, (div-1) << 4);
  551. if (abs((signed)(rate-rate2)) <= abs((signed)(rate-rate1))) {
  552. wrindir(s, SV_CIADCCLKSOURCE, 0x10);
  553. s->rateadc = rate2;
  554. } else {
  555. wrindir(s, SV_CIADCCLKSOURCE, 0x00);
  556. s->rateadc = rate1;
  557. }
  558. spin_unlock_irqrestore(&s->lock, flags);
  559. }
  560. /* --------------------------------------------------------------------- */
  561. static inline void stop_adc(struct sv_state *s)
  562. {
  563. unsigned long flags;
  564. spin_lock_irqsave(&s->lock, flags);
  565. s->enable &= ~SV_CENABLE_RE;
  566. wrindir(s, SV_CIENABLE, s->enable);
  567. spin_unlock_irqrestore(&s->lock, flags);
  568. }
  569. static inline void stop_dac(struct sv_state *s)
  570. {
  571. unsigned long flags;
  572. spin_lock_irqsave(&s->lock, flags);
  573. s->enable &= ~(SV_CENABLE_PPE | SV_CENABLE_PE);
  574. wrindir(s, SV_CIENABLE, s->enable);
  575. spin_unlock_irqrestore(&s->lock, flags);
  576. }
  577. static void start_dac(struct sv_state *s)
  578. {
  579. unsigned long flags;
  580. spin_lock_irqsave(&s->lock, flags);
  581. if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
  582. s->enable = (s->enable & ~SV_CENABLE_PPE) | SV_CENABLE_PE;
  583. wrindir(s, SV_CIENABLE, s->enable);
  584. }
  585. spin_unlock_irqrestore(&s->lock, flags);
  586. }
  587. static void start_adc(struct sv_state *s)
  588. {
  589. unsigned long flags;
  590. spin_lock_irqsave(&s->lock, flags);
  591. if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
  592. && s->dma_adc.ready) {
  593. s->enable |= SV_CENABLE_RE;
  594. wrindir(s, SV_CIENABLE, s->enable);
  595. }
  596. spin_unlock_irqrestore(&s->lock, flags);
  597. }
  598. /* --------------------------------------------------------------------- */
  599. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  600. #define DMABUF_MINORDER 1
  601. static void dealloc_dmabuf(struct sv_state *s, struct dmabuf *db)
  602. {
  603. struct page *page, *pend;
  604. if (db->rawbuf) {
  605. /* undo marking the pages as reserved */
  606. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  607. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  608. ClearPageReserved(page);
  609. pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
  610. }
  611. db->rawbuf = NULL;
  612. db->mapped = db->ready = 0;
  613. }
  614. /* DMAA is used for playback, DMAC is used for recording */
  615. static int prog_dmabuf(struct sv_state *s, unsigned rec)
  616. {
  617. struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
  618. unsigned rate = rec ? s->rateadc : s->ratedac;
  619. int order;
  620. unsigned bytepersec;
  621. unsigned bufs;
  622. struct page *page, *pend;
  623. unsigned char fmt;
  624. unsigned long flags;
  625. spin_lock_irqsave(&s->lock, flags);
  626. fmt = s->fmt;
  627. if (rec) {
  628. s->enable &= ~SV_CENABLE_RE;
  629. fmt >>= SV_CFMT_CSHIFT;
  630. } else {
  631. s->enable &= ~SV_CENABLE_PE;
  632. fmt >>= SV_CFMT_ASHIFT;
  633. }
  634. wrindir(s, SV_CIENABLE, s->enable);
  635. spin_unlock_irqrestore(&s->lock, flags);
  636. fmt &= SV_CFMT_MASK;
  637. db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
  638. if (!db->rawbuf) {
  639. db->ready = db->mapped = 0;
  640. for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
  641. if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
  642. break;
  643. if (!db->rawbuf)
  644. return -ENOMEM;
  645. db->buforder = order;
  646. if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
  647. printk(KERN_DEBUG "sv: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
  648. virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
  649. if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
  650. printk(KERN_DEBUG "sv: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
  651. virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
  652. /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
  653. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  654. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  655. SetPageReserved(page);
  656. }
  657. bytepersec = rate << sample_shift[fmt];
  658. bufs = PAGE_SIZE << db->buforder;
  659. if (db->ossfragshift) {
  660. if ((1000 << db->ossfragshift) < bytepersec)
  661. db->fragshift = ld2(bytepersec/1000);
  662. else
  663. db->fragshift = db->ossfragshift;
  664. } else {
  665. db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
  666. if (db->fragshift < 3)
  667. db->fragshift = 3;
  668. }
  669. db->numfrag = bufs >> db->fragshift;
  670. while (db->numfrag < 4 && db->fragshift > 3) {
  671. db->fragshift--;
  672. db->numfrag = bufs >> db->fragshift;
  673. }
  674. db->fragsize = 1 << db->fragshift;
  675. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  676. db->numfrag = db->ossmaxfrags;
  677. db->fragsamples = db->fragsize >> sample_shift[fmt];
  678. db->dmasize = db->numfrag << db->fragshift;
  679. memset(db->rawbuf, (fmt & SV_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
  680. spin_lock_irqsave(&s->lock, flags);
  681. if (rec) {
  682. set_dmac(s, db->dmaaddr, db->numfrag << db->fragshift);
  683. /* program enhanced mode registers */
  684. wrindir(s, SV_CIDMACBASECOUNT1, (db->fragsamples-1) >> 8);
  685. wrindir(s, SV_CIDMACBASECOUNT0, db->fragsamples-1);
  686. } else {
  687. set_dmaa(s, db->dmaaddr, db->numfrag << db->fragshift);
  688. /* program enhanced mode registers */
  689. wrindir(s, SV_CIDMAABASECOUNT1, (db->fragsamples-1) >> 8);
  690. wrindir(s, SV_CIDMAABASECOUNT0, db->fragsamples-1);
  691. }
  692. spin_unlock_irqrestore(&s->lock, flags);
  693. db->enabled = 1;
  694. db->ready = 1;
  695. return 0;
  696. }
  697. static inline void clear_advance(struct sv_state *s)
  698. {
  699. unsigned char c = (s->fmt & (SV_CFMT_16BIT << SV_CFMT_ASHIFT)) ? 0 : 0x80;
  700. unsigned char *buf = s->dma_dac.rawbuf;
  701. unsigned bsize = s->dma_dac.dmasize;
  702. unsigned bptr = s->dma_dac.swptr;
  703. unsigned len = s->dma_dac.fragsize;
  704. if (bptr + len > bsize) {
  705. unsigned x = bsize - bptr;
  706. memset(buf + bptr, c, x);
  707. bptr = 0;
  708. len -= x;
  709. }
  710. memset(buf + bptr, c, len);
  711. }
  712. /* call with spinlock held! */
  713. static void sv_update_ptr(struct sv_state *s)
  714. {
  715. unsigned hwptr;
  716. int diff;
  717. /* update ADC pointer */
  718. if (s->dma_adc.ready) {
  719. hwptr = (s->dma_adc.dmasize - get_dmac(s)) % s->dma_adc.dmasize;
  720. diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
  721. s->dma_adc.hwptr = hwptr;
  722. s->dma_adc.total_bytes += diff;
  723. s->dma_adc.count += diff;
  724. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  725. wake_up(&s->dma_adc.wait);
  726. if (!s->dma_adc.mapped) {
  727. if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
  728. s->enable &= ~SV_CENABLE_RE;
  729. wrindir(s, SV_CIENABLE, s->enable);
  730. s->dma_adc.error++;
  731. }
  732. }
  733. }
  734. /* update DAC pointer */
  735. if (s->dma_dac.ready) {
  736. hwptr = (s->dma_dac.dmasize - get_dmaa(s)) % s->dma_dac.dmasize;
  737. diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
  738. s->dma_dac.hwptr = hwptr;
  739. s->dma_dac.total_bytes += diff;
  740. if (s->dma_dac.mapped) {
  741. s->dma_dac.count += diff;
  742. if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
  743. wake_up(&s->dma_dac.wait);
  744. } else {
  745. s->dma_dac.count -= diff;
  746. if (s->dma_dac.count <= 0) {
  747. s->enable &= ~SV_CENABLE_PE;
  748. wrindir(s, SV_CIENABLE, s->enable);
  749. s->dma_dac.error++;
  750. } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
  751. clear_advance(s);
  752. s->dma_dac.endcleared = 1;
  753. }
  754. if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
  755. wake_up(&s->dma_dac.wait);
  756. }
  757. }
  758. }
  759. /* hold spinlock for the following! */
  760. static void sv_handle_midi(struct sv_state *s)
  761. {
  762. unsigned char ch;
  763. int wake;
  764. wake = 0;
  765. while (!(inb(s->iomidi+1) & 0x80)) {
  766. ch = inb(s->iomidi);
  767. if (s->midi.icnt < MIDIINBUF) {
  768. s->midi.ibuf[s->midi.iwr] = ch;
  769. s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
  770. s->midi.icnt++;
  771. }
  772. wake = 1;
  773. }
  774. if (wake)
  775. wake_up(&s->midi.iwait);
  776. wake = 0;
  777. while (!(inb(s->iomidi+1) & 0x40) && s->midi.ocnt > 0) {
  778. outb(s->midi.obuf[s->midi.ord], s->iomidi);
  779. s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
  780. s->midi.ocnt--;
  781. if (s->midi.ocnt < MIDIOUTBUF-16)
  782. wake = 1;
  783. }
  784. if (wake)
  785. wake_up(&s->midi.owait);
  786. }
  787. static irqreturn_t sv_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  788. {
  789. struct sv_state *s = (struct sv_state *)dev_id;
  790. unsigned int intsrc;
  791. /* fastpath out, to ease interrupt sharing */
  792. intsrc = inb(s->ioenh + SV_CODEC_STATUS);
  793. if (!(intsrc & (SV_CSTAT_DMAA | SV_CSTAT_DMAC | SV_CSTAT_MIDI)))
  794. return IRQ_NONE;
  795. spin_lock(&s->lock);
  796. sv_update_ptr(s);
  797. sv_handle_midi(s);
  798. spin_unlock(&s->lock);
  799. return IRQ_HANDLED;
  800. }
  801. static void sv_midi_timer(unsigned long data)
  802. {
  803. struct sv_state *s = (struct sv_state *)data;
  804. unsigned long flags;
  805. spin_lock_irqsave(&s->lock, flags);
  806. sv_handle_midi(s);
  807. spin_unlock_irqrestore(&s->lock, flags);
  808. s->midi.timer.expires = jiffies+1;
  809. add_timer(&s->midi.timer);
  810. }
  811. /* --------------------------------------------------------------------- */
  812. static const char invalid_magic[] = KERN_CRIT "sv: invalid magic value\n";
  813. #define VALIDATE_STATE(s) \
  814. ({ \
  815. if (!(s) || (s)->magic != SV_MAGIC) { \
  816. printk(invalid_magic); \
  817. return -ENXIO; \
  818. } \
  819. })
  820. /* --------------------------------------------------------------------- */
  821. #define MT_4 1
  822. #define MT_5MUTE 2
  823. #define MT_4MUTEMONO 3
  824. #define MT_6MUTE 4
  825. static const struct {
  826. unsigned left:5;
  827. unsigned right:5;
  828. unsigned type:3;
  829. unsigned rec:3;
  830. } mixtable[SOUND_MIXER_NRDEVICES] = {
  831. [SOUND_MIXER_RECLEV] = { SV_CIMIX_ADCINL, SV_CIMIX_ADCINR, MT_4, 0 },
  832. [SOUND_MIXER_LINE1] = { SV_CIMIX_AUX1INL, SV_CIMIX_AUX1INR, MT_5MUTE, 5 },
  833. [SOUND_MIXER_CD] = { SV_CIMIX_CDINL, SV_CIMIX_CDINR, MT_5MUTE, 1 },
  834. [SOUND_MIXER_LINE] = { SV_CIMIX_LINEINL, SV_CIMIX_LINEINR, MT_5MUTE, 4 },
  835. [SOUND_MIXER_MIC] = { SV_CIMIX_MICIN, SV_CIMIX_ADCINL, MT_4MUTEMONO, 6 },
  836. [SOUND_MIXER_SYNTH] = { SV_CIMIX_SYNTHINL, SV_CIMIX_SYNTHINR, MT_5MUTE, 2 },
  837. [SOUND_MIXER_LINE2] = { SV_CIMIX_AUX2INL, SV_CIMIX_AUX2INR, MT_5MUTE, 3 },
  838. [SOUND_MIXER_VOLUME] = { SV_CIMIX_ANALOGINL, SV_CIMIX_ANALOGINR, MT_5MUTE, 7 },
  839. [SOUND_MIXER_PCM] = { SV_CIMIX_PCMINL, SV_CIMIX_PCMINR, MT_6MUTE, 0 }
  840. };
  841. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  842. static int return_mixval(struct sv_state *s, unsigned i, int *arg)
  843. {
  844. unsigned long flags;
  845. unsigned char l, r, rl, rr;
  846. spin_lock_irqsave(&s->lock, flags);
  847. l = rdindir(s, mixtable[i].left);
  848. r = rdindir(s, mixtable[i].right);
  849. spin_unlock_irqrestore(&s->lock, flags);
  850. switch (mixtable[i].type) {
  851. case MT_4:
  852. r &= 0xf;
  853. l &= 0xf;
  854. rl = 10 + 6 * (l & 15);
  855. rr = 10 + 6 * (r & 15);
  856. break;
  857. case MT_4MUTEMONO:
  858. rl = 55 - 3 * (l & 15);
  859. if (r & 0x10)
  860. rl += 45;
  861. rr = rl;
  862. r = l;
  863. break;
  864. case MT_5MUTE:
  865. default:
  866. rl = 100 - 3 * (l & 31);
  867. rr = 100 - 3 * (r & 31);
  868. break;
  869. case MT_6MUTE:
  870. rl = 100 - 3 * (l & 63) / 2;
  871. rr = 100 - 3 * (r & 63) / 2;
  872. break;
  873. }
  874. if (l & 0x80)
  875. rl = 0;
  876. if (r & 0x80)
  877. rr = 0;
  878. return put_user((rr << 8) | rl, arg);
  879. }
  880. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  881. static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
  882. {
  883. [SOUND_MIXER_RECLEV] = 1,
  884. [SOUND_MIXER_LINE1] = 2,
  885. [SOUND_MIXER_CD] = 3,
  886. [SOUND_MIXER_LINE] = 4,
  887. [SOUND_MIXER_MIC] = 5,
  888. [SOUND_MIXER_SYNTH] = 6,
  889. [SOUND_MIXER_LINE2] = 7,
  890. [SOUND_MIXER_VOLUME] = 8,
  891. [SOUND_MIXER_PCM] = 9
  892. };
  893. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  894. static unsigned mixer_recmask(struct sv_state *s)
  895. {
  896. unsigned long flags;
  897. int i, j;
  898. spin_lock_irqsave(&s->lock, flags);
  899. j = rdindir(s, SV_CIMIX_ADCINL) >> 5;
  900. spin_unlock_irqrestore(&s->lock, flags);
  901. j &= 7;
  902. for (i = 0; i < SOUND_MIXER_NRDEVICES && mixtable[i].rec != j; i++);
  903. return 1 << i;
  904. }
  905. static int mixer_ioctl(struct sv_state *s, unsigned int cmd, unsigned long arg)
  906. {
  907. unsigned long flags;
  908. int i, val;
  909. unsigned char l, r, rl, rr;
  910. int __user *p = (int __user *)arg;
  911. VALIDATE_STATE(s);
  912. if (cmd == SOUND_MIXER_INFO) {
  913. mixer_info info;
  914. memset(&info, 0, sizeof(info));
  915. strlcpy(info.id, "SonicVibes", sizeof(info.id));
  916. strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
  917. info.modify_counter = s->mix.modcnt;
  918. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  919. return -EFAULT;
  920. return 0;
  921. }
  922. if (cmd == SOUND_OLD_MIXER_INFO) {
  923. _old_mixer_info info;
  924. memset(&info, 0, sizeof(info));
  925. strlcpy(info.id, "SonicVibes", sizeof(info.id));
  926. strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
  927. if (copy_to_user((void __user *)arg, &info, sizeof(info)))
  928. return -EFAULT;
  929. return 0;
  930. }
  931. if (cmd == OSS_GETVERSION)
  932. return put_user(SOUND_VERSION, p);
  933. if (cmd == SOUND_MIXER_PRIVATE1) { /* SRS settings */
  934. if (get_user(val, p))
  935. return -EFAULT;
  936. spin_lock_irqsave(&s->lock, flags);
  937. if (val & 1) {
  938. if (val & 2) {
  939. l = 4 - ((val >> 2) & 7);
  940. if (l & ~3)
  941. l = 4;
  942. r = 4 - ((val >> 5) & 7);
  943. if (r & ~3)
  944. r = 4;
  945. wrindir(s, SV_CISRSSPACE, l);
  946. wrindir(s, SV_CISRSCENTER, r);
  947. } else
  948. wrindir(s, SV_CISRSSPACE, 0x80);
  949. }
  950. l = rdindir(s, SV_CISRSSPACE);
  951. r = rdindir(s, SV_CISRSCENTER);
  952. spin_unlock_irqrestore(&s->lock, flags);
  953. if (l & 0x80)
  954. return put_user(0, p);
  955. return put_user(((4 - (l & 7)) << 2) | ((4 - (r & 7)) << 5) | 2, p);
  956. }
  957. if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
  958. return -EINVAL;
  959. if (_SIOC_DIR(cmd) == _SIOC_READ) {
  960. switch (_IOC_NR(cmd)) {
  961. case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
  962. return put_user(mixer_recmask(s), p);
  963. case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
  964. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  965. if (mixtable[i].type)
  966. val |= 1 << i;
  967. return put_user(val, p);
  968. case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
  969. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  970. if (mixtable[i].rec)
  971. val |= 1 << i;
  972. return put_user(val, p);
  973. case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
  974. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  975. if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
  976. val |= 1 << i;
  977. return put_user(val, p);
  978. case SOUND_MIXER_CAPS:
  979. return put_user(SOUND_CAP_EXCL_INPUT, p);
  980. default:
  981. i = _IOC_NR(cmd);
  982. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
  983. return -EINVAL;
  984. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  985. return return_mixval(s, i, p);
  986. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  987. if (!volidx[i])
  988. return -EINVAL;
  989. return put_user(s->mix.vol[volidx[i]-1], p);
  990. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  991. }
  992. }
  993. if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
  994. return -EINVAL;
  995. s->mix.modcnt++;
  996. switch (_IOC_NR(cmd)) {
  997. case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
  998. if (get_user(val, p))
  999. return -EFAULT;
  1000. i = hweight32(val);
  1001. if (i == 0)
  1002. return 0; /*val = mixer_recmask(s);*/
  1003. else if (i > 1)
  1004. val &= ~mixer_recmask(s);
  1005. for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
  1006. if (!(val & (1 << i)))
  1007. continue;
  1008. if (mixtable[i].rec)
  1009. break;
  1010. }
  1011. if (i == SOUND_MIXER_NRDEVICES)
  1012. return 0;
  1013. spin_lock_irqsave(&s->lock, flags);
  1014. frobindir(s, SV_CIMIX_ADCINL, 0x1f, mixtable[i].rec << 5);
  1015. frobindir(s, SV_CIMIX_ADCINR, 0x1f, mixtable[i].rec << 5);
  1016. spin_unlock_irqrestore(&s->lock, flags);
  1017. return 0;
  1018. default:
  1019. i = _IOC_NR(cmd);
  1020. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
  1021. return -EINVAL;
  1022. if (get_user(val, p))
  1023. return -EFAULT;
  1024. l = val & 0xff;
  1025. r = (val >> 8) & 0xff;
  1026. if (mixtable[i].type == MT_4MUTEMONO)
  1027. l = (r + l) / 2;
  1028. if (l > 100)
  1029. l = 100;
  1030. if (r > 100)
  1031. r = 100;
  1032. spin_lock_irqsave(&s->lock, flags);
  1033. switch (mixtable[i].type) {
  1034. case MT_4:
  1035. if (l >= 10)
  1036. l -= 10;
  1037. if (r >= 10)
  1038. r -= 10;
  1039. frobindir(s, mixtable[i].left, 0xf0, l / 6);
  1040. frobindir(s, mixtable[i].right, 0xf0, l / 6);
  1041. break;
  1042. case MT_4MUTEMONO:
  1043. rr = 0;
  1044. if (l < 10)
  1045. rl = 0x80;
  1046. else {
  1047. if (l >= 55) {
  1048. rr = 0x10;
  1049. l -= 45;
  1050. }
  1051. rl = (55 - l) / 3;
  1052. }
  1053. wrindir(s, mixtable[i].left, rl);
  1054. frobindir(s, mixtable[i].right, ~0x10, rr);
  1055. break;
  1056. case MT_5MUTE:
  1057. if (l < 7)
  1058. rl = 0x80;
  1059. else
  1060. rl = (100 - l) / 3;
  1061. if (r < 7)
  1062. rr = 0x80;
  1063. else
  1064. rr = (100 - r) / 3;
  1065. wrindir(s, mixtable[i].left, rl);
  1066. wrindir(s, mixtable[i].right, rr);
  1067. break;
  1068. case MT_6MUTE:
  1069. if (l < 6)
  1070. rl = 0x80;
  1071. else
  1072. rl = (100 - l) * 2 / 3;
  1073. if (r < 6)
  1074. rr = 0x80;
  1075. else
  1076. rr = (100 - r) * 2 / 3;
  1077. wrindir(s, mixtable[i].left, rl);
  1078. wrindir(s, mixtable[i].right, rr);
  1079. break;
  1080. }
  1081. spin_unlock_irqrestore(&s->lock, flags);
  1082. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1083. return return_mixval(s, i, p);
  1084. #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1085. if (!volidx[i])
  1086. return -EINVAL;
  1087. s->mix.vol[volidx[i]-1] = val;
  1088. return put_user(s->mix.vol[volidx[i]-1], p);
  1089. #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
  1090. }
  1091. }
  1092. /* --------------------------------------------------------------------- */
  1093. static int sv_open_mixdev(struct inode *inode, struct file *file)
  1094. {
  1095. int minor = iminor(inode);
  1096. struct list_head *list;
  1097. struct sv_state *s;
  1098. for (list = devs.next; ; list = list->next) {
  1099. if (list == &devs)
  1100. return -ENODEV;
  1101. s = list_entry(list, struct sv_state, devs);
  1102. if (s->dev_mixer == minor)
  1103. break;
  1104. }
  1105. VALIDATE_STATE(s);
  1106. file->private_data = s;
  1107. return nonseekable_open(inode, file);
  1108. }
  1109. static int sv_release_mixdev(struct inode *inode, struct file *file)
  1110. {
  1111. struct sv_state *s = (struct sv_state *)file->private_data;
  1112. VALIDATE_STATE(s);
  1113. return 0;
  1114. }
  1115. static int sv_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1116. {
  1117. return mixer_ioctl((struct sv_state *)file->private_data, cmd, arg);
  1118. }
  1119. static /*const*/ struct file_operations sv_mixer_fops = {
  1120. .owner = THIS_MODULE,
  1121. .llseek = no_llseek,
  1122. .ioctl = sv_ioctl_mixdev,
  1123. .open = sv_open_mixdev,
  1124. .release = sv_release_mixdev,
  1125. };
  1126. /* --------------------------------------------------------------------- */
  1127. static int drain_dac(struct sv_state *s, int nonblock)
  1128. {
  1129. DECLARE_WAITQUEUE(wait, current);
  1130. unsigned long flags;
  1131. int count, tmo;
  1132. if (s->dma_dac.mapped || !s->dma_dac.ready)
  1133. return 0;
  1134. add_wait_queue(&s->dma_dac.wait, &wait);
  1135. for (;;) {
  1136. __set_current_state(TASK_INTERRUPTIBLE);
  1137. spin_lock_irqsave(&s->lock, flags);
  1138. count = s->dma_dac.count;
  1139. spin_unlock_irqrestore(&s->lock, flags);
  1140. if (count <= 0)
  1141. break;
  1142. if (signal_pending(current))
  1143. break;
  1144. if (nonblock) {
  1145. remove_wait_queue(&s->dma_dac.wait, &wait);
  1146. set_current_state(TASK_RUNNING);
  1147. return -EBUSY;
  1148. }
  1149. tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
  1150. tmo >>= sample_shift[(s->fmt >> SV_CFMT_ASHIFT) & SV_CFMT_MASK];
  1151. if (!schedule_timeout(tmo + 1))
  1152. printk(KERN_DEBUG "sv: dma timed out??\n");
  1153. }
  1154. remove_wait_queue(&s->dma_dac.wait, &wait);
  1155. set_current_state(TASK_RUNNING);
  1156. if (signal_pending(current))
  1157. return -ERESTARTSYS;
  1158. return 0;
  1159. }
  1160. /* --------------------------------------------------------------------- */
  1161. static ssize_t sv_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1162. {
  1163. struct sv_state *s = (struct sv_state *)file->private_data;
  1164. DECLARE_WAITQUEUE(wait, current);
  1165. ssize_t ret;
  1166. unsigned long flags;
  1167. unsigned swptr;
  1168. int cnt;
  1169. VALIDATE_STATE(s);
  1170. if (s->dma_adc.mapped)
  1171. return -ENXIO;
  1172. if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
  1173. return ret;
  1174. if (!access_ok(VERIFY_WRITE, buffer, count))
  1175. return -EFAULT;
  1176. ret = 0;
  1177. #if 0
  1178. spin_lock_irqsave(&s->lock, flags);
  1179. sv_update_ptr(s);
  1180. spin_unlock_irqrestore(&s->lock, flags);
  1181. #endif
  1182. add_wait_queue(&s->dma_adc.wait, &wait);
  1183. while (count > 0) {
  1184. spin_lock_irqsave(&s->lock, flags);
  1185. swptr = s->dma_adc.swptr;
  1186. cnt = s->dma_adc.dmasize-swptr;
  1187. if (s->dma_adc.count < cnt)
  1188. cnt = s->dma_adc.count;
  1189. if (cnt <= 0)
  1190. __set_current_state(TASK_INTERRUPTIBLE);
  1191. spin_unlock_irqrestore(&s->lock, flags);
  1192. if (cnt > count)
  1193. cnt = count;
  1194. if (cnt <= 0) {
  1195. if (s->dma_adc.enabled)
  1196. start_adc(s);
  1197. if (file->f_flags & O_NONBLOCK) {
  1198. if (!ret)
  1199. ret = -EAGAIN;
  1200. break;
  1201. }
  1202. if (!schedule_timeout(HZ)) {
  1203. printk(KERN_DEBUG "sv: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
  1204. s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
  1205. s->dma_adc.hwptr, s->dma_adc.swptr);
  1206. stop_adc(s);
  1207. spin_lock_irqsave(&s->lock, flags);
  1208. set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
  1209. /* program enhanced mode registers */
  1210. wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
  1211. wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
  1212. s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
  1213. spin_unlock_irqrestore(&s->lock, flags);
  1214. }
  1215. if (signal_pending(current)) {
  1216. if (!ret)
  1217. ret = -ERESTARTSYS;
  1218. break;
  1219. }
  1220. continue;
  1221. }
  1222. if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
  1223. if (!ret)
  1224. ret = -EFAULT;
  1225. break;
  1226. }
  1227. swptr = (swptr + cnt) % s->dma_adc.dmasize;
  1228. spin_lock_irqsave(&s->lock, flags);
  1229. s->dma_adc.swptr = swptr;
  1230. s->dma_adc.count -= cnt;
  1231. spin_unlock_irqrestore(&s->lock, flags);
  1232. count -= cnt;
  1233. buffer += cnt;
  1234. ret += cnt;
  1235. if (s->dma_adc.enabled)
  1236. start_adc(s);
  1237. }
  1238. remove_wait_queue(&s->dma_adc.wait, &wait);
  1239. set_current_state(TASK_RUNNING);
  1240. return ret;
  1241. }
  1242. static ssize_t sv_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1243. {
  1244. struct sv_state *s = (struct sv_state *)file->private_data;
  1245. DECLARE_WAITQUEUE(wait, current);
  1246. ssize_t ret;
  1247. unsigned long flags;
  1248. unsigned swptr;
  1249. int cnt;
  1250. VALIDATE_STATE(s);
  1251. if (s->dma_dac.mapped)
  1252. return -ENXIO;
  1253. if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
  1254. return ret;
  1255. if (!access_ok(VERIFY_READ, buffer, count))
  1256. return -EFAULT;
  1257. ret = 0;
  1258. #if 0
  1259. spin_lock_irqsave(&s->lock, flags);
  1260. sv_update_ptr(s);
  1261. spin_unlock_irqrestore(&s->lock, flags);
  1262. #endif
  1263. add_wait_queue(&s->dma_dac.wait, &wait);
  1264. while (count > 0) {
  1265. spin_lock_irqsave(&s->lock, flags);
  1266. if (s->dma_dac.count < 0) {
  1267. s->dma_dac.count = 0;
  1268. s->dma_dac.swptr = s->dma_dac.hwptr;
  1269. }
  1270. swptr = s->dma_dac.swptr;
  1271. cnt = s->dma_dac.dmasize-swptr;
  1272. if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
  1273. cnt = s->dma_dac.dmasize - s->dma_dac.count;
  1274. if (cnt <= 0)
  1275. __set_current_state(TASK_INTERRUPTIBLE);
  1276. spin_unlock_irqrestore(&s->lock, flags);
  1277. if (cnt > count)
  1278. cnt = count;
  1279. if (cnt <= 0) {
  1280. if (s->dma_dac.enabled)
  1281. start_dac(s);
  1282. if (file->f_flags & O_NONBLOCK) {
  1283. if (!ret)
  1284. ret = -EAGAIN;
  1285. break;
  1286. }
  1287. if (!schedule_timeout(HZ)) {
  1288. printk(KERN_DEBUG "sv: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
  1289. s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
  1290. s->dma_dac.hwptr, s->dma_dac.swptr);
  1291. stop_dac(s);
  1292. spin_lock_irqsave(&s->lock, flags);
  1293. set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
  1294. /* program enhanced mode registers */
  1295. wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
  1296. wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
  1297. s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
  1298. spin_unlock_irqrestore(&s->lock, flags);
  1299. }
  1300. if (signal_pending(current)) {
  1301. if (!ret)
  1302. ret = -ERESTARTSYS;
  1303. break;
  1304. }
  1305. continue;
  1306. }
  1307. if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
  1308. if (!ret)
  1309. ret = -EFAULT;
  1310. break;
  1311. }
  1312. swptr = (swptr + cnt) % s->dma_dac.dmasize;
  1313. spin_lock_irqsave(&s->lock, flags);
  1314. s->dma_dac.swptr = swptr;
  1315. s->dma_dac.count += cnt;
  1316. s->dma_dac.endcleared = 0;
  1317. spin_unlock_irqrestore(&s->lock, flags);
  1318. count -= cnt;
  1319. buffer += cnt;
  1320. ret += cnt;
  1321. if (s->dma_dac.enabled)
  1322. start_dac(s);
  1323. }
  1324. remove_wait_queue(&s->dma_dac.wait, &wait);
  1325. set_current_state(TASK_RUNNING);
  1326. return ret;
  1327. }
  1328. /* No kernel lock - we have our own spinlock */
  1329. static unsigned int sv_poll(struct file *file, struct poll_table_struct *wait)
  1330. {
  1331. struct sv_state *s = (struct sv_state *)file->private_data;
  1332. unsigned long flags;
  1333. unsigned int mask = 0;
  1334. VALIDATE_STATE(s);
  1335. if (file->f_mode & FMODE_WRITE) {
  1336. if (!s->dma_dac.ready && prog_dmabuf(s, 1))
  1337. return 0;
  1338. poll_wait(file, &s->dma_dac.wait, wait);
  1339. }
  1340. if (file->f_mode & FMODE_READ) {
  1341. if (!s->dma_adc.ready && prog_dmabuf(s, 0))
  1342. return 0;
  1343. poll_wait(file, &s->dma_adc.wait, wait);
  1344. }
  1345. spin_lock_irqsave(&s->lock, flags);
  1346. sv_update_ptr(s);
  1347. if (file->f_mode & FMODE_READ) {
  1348. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  1349. mask |= POLLIN | POLLRDNORM;
  1350. }
  1351. if (file->f_mode & FMODE_WRITE) {
  1352. if (s->dma_dac.mapped) {
  1353. if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
  1354. mask |= POLLOUT | POLLWRNORM;
  1355. } else {
  1356. if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
  1357. mask |= POLLOUT | POLLWRNORM;
  1358. }
  1359. }
  1360. spin_unlock_irqrestore(&s->lock, flags);
  1361. return mask;
  1362. }
  1363. static int sv_mmap(struct file *file, struct vm_area_struct *vma)
  1364. {
  1365. struct sv_state *s = (struct sv_state *)file->private_data;
  1366. struct dmabuf *db;
  1367. int ret = -EINVAL;
  1368. unsigned long size;
  1369. VALIDATE_STATE(s);
  1370. lock_kernel();
  1371. if (vma->vm_flags & VM_WRITE) {
  1372. if ((ret = prog_dmabuf(s, 1)) != 0)
  1373. goto out;
  1374. db = &s->dma_dac;
  1375. } else if (vma->vm_flags & VM_READ) {
  1376. if ((ret = prog_dmabuf(s, 0)) != 0)
  1377. goto out;
  1378. db = &s->dma_adc;
  1379. } else
  1380. goto out;
  1381. ret = -EINVAL;
  1382. if (vma->vm_pgoff != 0)
  1383. goto out;
  1384. size = vma->vm_end - vma->vm_start;
  1385. if (size > (PAGE_SIZE << db->buforder))
  1386. goto out;
  1387. ret = -EAGAIN;
  1388. if (remap_pfn_range(vma, vma->vm_start,
  1389. virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
  1390. size, vma->vm_page_prot))
  1391. goto out;
  1392. db->mapped = 1;
  1393. ret = 0;
  1394. out:
  1395. unlock_kernel();
  1396. return ret;
  1397. }
  1398. static int sv_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1399. {
  1400. struct sv_state *s = (struct sv_state *)file->private_data;
  1401. unsigned long flags;
  1402. audio_buf_info abinfo;
  1403. count_info cinfo;
  1404. int count;
  1405. int val, mapped, ret;
  1406. unsigned char fmtm, fmtd;
  1407. void __user *argp = (void __user *)arg;
  1408. int __user *p = argp;
  1409. VALIDATE_STATE(s);
  1410. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1411. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1412. switch (cmd) {
  1413. case OSS_GETVERSION:
  1414. return put_user(SOUND_VERSION, p);
  1415. case SNDCTL_DSP_SYNC:
  1416. if (file->f_mode & FMODE_WRITE)
  1417. return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
  1418. return 0;
  1419. case SNDCTL_DSP_SETDUPLEX:
  1420. return 0;
  1421. case SNDCTL_DSP_GETCAPS:
  1422. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1423. case SNDCTL_DSP_RESET:
  1424. if (file->f_mode & FMODE_WRITE) {
  1425. stop_dac(s);
  1426. synchronize_irq(s->irq);
  1427. s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1428. }
  1429. if (file->f_mode & FMODE_READ) {
  1430. stop_adc(s);
  1431. synchronize_irq(s->irq);
  1432. s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1433. }
  1434. return 0;
  1435. case SNDCTL_DSP_SPEED:
  1436. if (get_user(val, p))
  1437. return -EFAULT;
  1438. if (val >= 0) {
  1439. if (file->f_mode & FMODE_READ) {
  1440. stop_adc(s);
  1441. s->dma_adc.ready = 0;
  1442. set_adc_rate(s, val);
  1443. }
  1444. if (file->f_mode & FMODE_WRITE) {
  1445. stop_dac(s);
  1446. s->dma_dac.ready = 0;
  1447. set_dac_rate(s, val);
  1448. }
  1449. }
  1450. return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
  1451. case SNDCTL_DSP_STEREO:
  1452. if (get_user(val, p))
  1453. return -EFAULT;
  1454. fmtd = 0;
  1455. fmtm = ~0;
  1456. if (file->f_mode & FMODE_READ) {
  1457. stop_adc(s);
  1458. s->dma_adc.ready = 0;
  1459. if (val)
  1460. fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
  1461. else
  1462. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
  1463. }
  1464. if (file->f_mode & FMODE_WRITE) {
  1465. stop_dac(s);
  1466. s->dma_dac.ready = 0;
  1467. if (val)
  1468. fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
  1469. else
  1470. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
  1471. }
  1472. set_fmt(s, fmtm, fmtd);
  1473. return 0;
  1474. case SNDCTL_DSP_CHANNELS:
  1475. if (get_user(val, p))
  1476. return -EFAULT;
  1477. if (val != 0) {
  1478. fmtd = 0;
  1479. fmtm = ~0;
  1480. if (file->f_mode & FMODE_READ) {
  1481. stop_adc(s);
  1482. s->dma_adc.ready = 0;
  1483. if (val >= 2)
  1484. fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
  1485. else
  1486. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
  1487. }
  1488. if (file->f_mode & FMODE_WRITE) {
  1489. stop_dac(s);
  1490. s->dma_dac.ready = 0;
  1491. if (val >= 2)
  1492. fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
  1493. else
  1494. fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
  1495. }
  1496. set_fmt(s, fmtm, fmtd);
  1497. }
  1498. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
  1499. : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
  1500. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1501. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1502. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1503. if (get_user(val, p))
  1504. return -EFAULT;
  1505. if (val != AFMT_QUERY) {
  1506. fmtd = 0;
  1507. fmtm = ~0;
  1508. if (file->f_mode & FMODE_READ) {
  1509. stop_adc(s);
  1510. s->dma_adc.ready = 0;
  1511. if (val == AFMT_S16_LE)
  1512. fmtd |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
  1513. else
  1514. fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_CSHIFT);
  1515. }
  1516. if (file->f_mode & FMODE_WRITE) {
  1517. stop_dac(s);
  1518. s->dma_dac.ready = 0;
  1519. if (val == AFMT_S16_LE)
  1520. fmtd |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
  1521. else
  1522. fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_ASHIFT);
  1523. }
  1524. set_fmt(s, fmtm, fmtd);
  1525. }
  1526. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
  1527. : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? AFMT_S16_LE : AFMT_U8, p);
  1528. case SNDCTL_DSP_POST:
  1529. return 0;
  1530. case SNDCTL_DSP_GETTRIGGER:
  1531. val = 0;
  1532. if (file->f_mode & FMODE_READ && s->enable & SV_CENABLE_RE)
  1533. val |= PCM_ENABLE_INPUT;
  1534. if (file->f_mode & FMODE_WRITE && s->enable & SV_CENABLE_PE)
  1535. val |= PCM_ENABLE_OUTPUT;
  1536. return put_user(val, p);
  1537. case SNDCTL_DSP_SETTRIGGER:
  1538. if (get_user(val, p))
  1539. return -EFAULT;
  1540. if (file->f_mode & FMODE_READ) {
  1541. if (val & PCM_ENABLE_INPUT) {
  1542. if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
  1543. return ret;
  1544. s->dma_adc.enabled = 1;
  1545. start_adc(s);
  1546. } else {
  1547. s->dma_adc.enabled = 0;
  1548. stop_adc(s);
  1549. }
  1550. }
  1551. if (file->f_mode & FMODE_WRITE) {
  1552. if (val & PCM_ENABLE_OUTPUT) {
  1553. if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
  1554. return ret;
  1555. s->dma_dac.enabled = 1;
  1556. start_dac(s);
  1557. } else {
  1558. s->dma_dac.enabled = 0;
  1559. stop_dac(s);
  1560. }
  1561. }
  1562. return 0;
  1563. case SNDCTL_DSP_GETOSPACE:
  1564. if (!(file->f_mode & FMODE_WRITE))
  1565. return -EINVAL;
  1566. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1567. return val;
  1568. spin_lock_irqsave(&s->lock, flags);
  1569. sv_update_ptr(s);
  1570. abinfo.fragsize = s->dma_dac.fragsize;
  1571. count = s->dma_dac.count;
  1572. if (count < 0)
  1573. count = 0;
  1574. abinfo.bytes = s->dma_dac.dmasize - count;
  1575. abinfo.fragstotal = s->dma_dac.numfrag;
  1576. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1577. spin_unlock_irqrestore(&s->lock, flags);
  1578. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1579. case SNDCTL_DSP_GETISPACE:
  1580. if (!(file->f_mode & FMODE_READ))
  1581. return -EINVAL;
  1582. if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
  1583. return val;
  1584. spin_lock_irqsave(&s->lock, flags);
  1585. sv_update_ptr(s);
  1586. abinfo.fragsize = s->dma_adc.fragsize;
  1587. count = s->dma_adc.count;
  1588. if (count < 0)
  1589. count = 0;
  1590. abinfo.bytes = count;
  1591. abinfo.fragstotal = s->dma_adc.numfrag;
  1592. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1593. spin_unlock_irqrestore(&s->lock, flags);
  1594. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1595. case SNDCTL_DSP_NONBLOCK:
  1596. file->f_flags |= O_NONBLOCK;
  1597. return 0;
  1598. case SNDCTL_DSP_GETODELAY:
  1599. if (!(file->f_mode & FMODE_WRITE))
  1600. return -EINVAL;
  1601. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1602. return val;
  1603. spin_lock_irqsave(&s->lock, flags);
  1604. sv_update_ptr(s);
  1605. count = s->dma_dac.count;
  1606. spin_unlock_irqrestore(&s->lock, flags);
  1607. if (count < 0)
  1608. count = 0;
  1609. return put_user(count, p);
  1610. case SNDCTL_DSP_GETIPTR:
  1611. if (!(file->f_mode & FMODE_READ))
  1612. return -EINVAL;
  1613. if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
  1614. return val;
  1615. spin_lock_irqsave(&s->lock, flags);
  1616. sv_update_ptr(s);
  1617. cinfo.bytes = s->dma_adc.total_bytes;
  1618. count = s->dma_adc.count;
  1619. if (count < 0)
  1620. count = 0;
  1621. cinfo.blocks = count >> s->dma_adc.fragshift;
  1622. cinfo.ptr = s->dma_adc.hwptr;
  1623. if (s->dma_adc.mapped)
  1624. s->dma_adc.count &= s->dma_adc.fragsize-1;
  1625. spin_unlock_irqrestore(&s->lock, flags);
  1626. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1627. return -EFAULT;
  1628. return 0;
  1629. case SNDCTL_DSP_GETOPTR:
  1630. if (!(file->f_mode & FMODE_WRITE))
  1631. return -EINVAL;
  1632. if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
  1633. return val;
  1634. spin_lock_irqsave(&s->lock, flags);
  1635. sv_update_ptr(s);
  1636. cinfo.bytes = s->dma_dac.total_bytes;
  1637. count = s->dma_dac.count;
  1638. if (count < 0)
  1639. count = 0;
  1640. cinfo.blocks = count >> s->dma_dac.fragshift;
  1641. cinfo.ptr = s->dma_dac.hwptr;
  1642. if (s->dma_dac.mapped)
  1643. s->dma_dac.count &= s->dma_dac.fragsize-1;
  1644. spin_unlock_irqrestore(&s->lock, flags);
  1645. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1646. return -EFAULT;
  1647. return 0;
  1648. case SNDCTL_DSP_GETBLKSIZE:
  1649. if (file->f_mode & FMODE_WRITE) {
  1650. if ((val = prog_dmabuf(s, 0)))
  1651. return val;
  1652. return put_user(s->dma_dac.fragsize, p);
  1653. }
  1654. if ((val = prog_dmabuf(s, 1)))
  1655. return val;
  1656. return put_user(s->dma_adc.fragsize, p);
  1657. case SNDCTL_DSP_SETFRAGMENT:
  1658. if (get_user(val, p))
  1659. return -EFAULT;
  1660. if (file->f_mode & FMODE_READ) {
  1661. s->dma_adc.ossfragshift = val & 0xffff;
  1662. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1663. if (s->dma_adc.ossfragshift < 4)
  1664. s->dma_adc.ossfragshift = 4;
  1665. if (s->dma_adc.ossfragshift > 15)
  1666. s->dma_adc.ossfragshift = 15;
  1667. if (s->dma_adc.ossmaxfrags < 4)
  1668. s->dma_adc.ossmaxfrags = 4;
  1669. }
  1670. if (file->f_mode & FMODE_WRITE) {
  1671. s->dma_dac.ossfragshift = val & 0xffff;
  1672. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1673. if (s->dma_dac.ossfragshift < 4)
  1674. s->dma_dac.ossfragshift = 4;
  1675. if (s->dma_dac.ossfragshift > 15)
  1676. s->dma_dac.ossfragshift = 15;
  1677. if (s->dma_dac.ossmaxfrags < 4)
  1678. s->dma_dac.ossmaxfrags = 4;
  1679. }
  1680. return 0;
  1681. case SNDCTL_DSP_SUBDIVIDE:
  1682. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1683. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1684. return -EINVAL;
  1685. if (get_user(val, p))
  1686. return -EFAULT;
  1687. if (val != 1 && val != 2 && val != 4)
  1688. return -EINVAL;
  1689. if (file->f_mode & FMODE_READ)
  1690. s->dma_adc.subdivision = val;
  1691. if (file->f_mode & FMODE_WRITE)
  1692. s->dma_dac.subdivision = val;
  1693. return 0;
  1694. case SOUND_PCM_READ_RATE:
  1695. return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
  1696. case SOUND_PCM_READ_CHANNELS:
  1697. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
  1698. : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
  1699. case SOUND_PCM_READ_BITS:
  1700. return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
  1701. : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? 16 : 8, p);
  1702. case SOUND_PCM_WRITE_FILTER:
  1703. case SNDCTL_DSP_SETSYNCRO:
  1704. case SOUND_PCM_READ_FILTER:
  1705. return -EINVAL;
  1706. }
  1707. return mixer_ioctl(s, cmd, arg);
  1708. }
  1709. static int sv_open(struct inode *inode, struct file *file)
  1710. {
  1711. int minor = iminor(inode);
  1712. DECLARE_WAITQUEUE(wait, current);
  1713. unsigned char fmtm = ~0, fmts = 0;
  1714. struct list_head *list;
  1715. struct sv_state *s;
  1716. for (list = devs.next; ; list = list->next) {
  1717. if (list == &devs)
  1718. return -ENODEV;
  1719. s = list_entry(list, struct sv_state, devs);
  1720. if (!((s->dev_audio ^ minor) & ~0xf))
  1721. break;
  1722. }
  1723. VALIDATE_STATE(s);
  1724. file->private_data = s;
  1725. /* wait for device to become free */
  1726. mutex_lock(&s->open_mutex);
  1727. while (s->open_mode & file->f_mode) {
  1728. if (file->f_flags & O_NONBLOCK) {
  1729. mutex_unlock(&s->open_mutex);
  1730. return -EBUSY;
  1731. }
  1732. add_wait_queue(&s->open_wait, &wait);
  1733. __set_current_state(TASK_INTERRUPTIBLE);
  1734. mutex_unlock(&s->open_mutex);
  1735. schedule();
  1736. remove_wait_queue(&s->open_wait, &wait);
  1737. set_current_state(TASK_RUNNING);
  1738. if (signal_pending(current))
  1739. return -ERESTARTSYS;
  1740. mutex_lock(&s->open_mutex);
  1741. }
  1742. if (file->f_mode & FMODE_READ) {
  1743. fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_CSHIFT);
  1744. if ((minor & 0xf) == SND_DEV_DSP16)
  1745. fmts |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
  1746. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
  1747. s->dma_adc.enabled = 1;
  1748. set_adc_rate(s, 8000);
  1749. }
  1750. if (file->f_mode & FMODE_WRITE) {
  1751. fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_ASHIFT);
  1752. if ((minor & 0xf) == SND_DEV_DSP16)
  1753. fmts |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
  1754. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
  1755. s->dma_dac.enabled = 1;
  1756. set_dac_rate(s, 8000);
  1757. }
  1758. set_fmt(s, fmtm, fmts);
  1759. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1760. mutex_unlock(&s->open_mutex);
  1761. return nonseekable_open(inode, file);
  1762. }
  1763. static int sv_release(struct inode *inode, struct file *file)
  1764. {
  1765. struct sv_state *s = (struct sv_state *)file->private_data;
  1766. VALIDATE_STATE(s);
  1767. lock_kernel();
  1768. if (file->f_mode & FMODE_WRITE)
  1769. drain_dac(s, file->f_flags & O_NONBLOCK);
  1770. mutex_lock(&s->open_mutex);
  1771. if (file->f_mode & FMODE_WRITE) {
  1772. stop_dac(s);
  1773. dealloc_dmabuf(s, &s->dma_dac);
  1774. }
  1775. if (file->f_mode & FMODE_READ) {
  1776. stop_adc(s);
  1777. dealloc_dmabuf(s, &s->dma_adc);
  1778. }
  1779. s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
  1780. wake_up(&s->open_wait);
  1781. mutex_unlock(&s->open_mutex);
  1782. unlock_kernel();
  1783. return 0;
  1784. }
  1785. static /*const*/ struct file_operations sv_audio_fops = {
  1786. .owner = THIS_MODULE,
  1787. .llseek = no_llseek,
  1788. .read = sv_read,
  1789. .write = sv_write,
  1790. .poll = sv_poll,
  1791. .ioctl = sv_ioctl,
  1792. .mmap = sv_mmap,
  1793. .open = sv_open,
  1794. .release = sv_release,
  1795. };
  1796. /* --------------------------------------------------------------------- */
  1797. static ssize_t sv_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1798. {
  1799. struct sv_state *s = (struct sv_state *)file->private_data;
  1800. DECLARE_WAITQUEUE(wait, current);
  1801. ssize_t ret;
  1802. unsigned long flags;
  1803. unsigned ptr;
  1804. int cnt;
  1805. VALIDATE_STATE(s);
  1806. if (!access_ok(VERIFY_WRITE, buffer, count))
  1807. return -EFAULT;
  1808. if (count == 0)
  1809. return 0;
  1810. ret = 0;
  1811. add_wait_queue(&s->midi.iwait, &wait);
  1812. while (count > 0) {
  1813. spin_lock_irqsave(&s->lock, flags);
  1814. ptr = s->midi.ird;
  1815. cnt = MIDIINBUF - ptr;
  1816. if (s->midi.icnt < cnt)
  1817. cnt = s->midi.icnt;
  1818. if (cnt <= 0)
  1819. __set_current_state(TASK_INTERRUPTIBLE);
  1820. spin_unlock_irqrestore(&s->lock, flags);
  1821. if (cnt > count)
  1822. cnt = count;
  1823. if (cnt <= 0) {
  1824. if (file->f_flags & O_NONBLOCK) {
  1825. if (!ret)
  1826. ret = -EAGAIN;
  1827. break;
  1828. }
  1829. schedule();
  1830. if (signal_pending(current)) {
  1831. if (!ret)
  1832. ret = -ERESTARTSYS;
  1833. break;
  1834. }
  1835. continue;
  1836. }
  1837. if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
  1838. if (!ret)
  1839. ret = -EFAULT;
  1840. break;
  1841. }
  1842. ptr = (ptr + cnt) % MIDIINBUF;
  1843. spin_lock_irqsave(&s->lock, flags);
  1844. s->midi.ird = ptr;
  1845. s->midi.icnt -= cnt;
  1846. spin_unlock_irqrestore(&s->lock, flags);
  1847. count -= cnt;
  1848. buffer += cnt;
  1849. ret += cnt;
  1850. break;
  1851. }
  1852. __set_current_state(TASK_RUNNING);
  1853. remove_wait_queue(&s->midi.iwait, &wait);
  1854. return ret;
  1855. }
  1856. static ssize_t sv_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1857. {
  1858. struct sv_state *s = (struct sv_state *)file->private_data;
  1859. DECLARE_WAITQUEUE(wait, current);
  1860. ssize_t ret;
  1861. unsigned long flags;
  1862. unsigned ptr;
  1863. int cnt;
  1864. VALIDATE_STATE(s);
  1865. if (!access_ok(VERIFY_READ, buffer, count))
  1866. return -EFAULT;
  1867. if (count == 0)
  1868. return 0;
  1869. ret = 0;
  1870. add_wait_queue(&s->midi.owait, &wait);
  1871. while (count > 0) {
  1872. spin_lock_irqsave(&s->lock, flags);
  1873. ptr = s->midi.owr;
  1874. cnt = MIDIOUTBUF - ptr;
  1875. if (s->midi.ocnt + cnt > MIDIOUTBUF)
  1876. cnt = MIDIOUTBUF - s->midi.ocnt;
  1877. if (cnt <= 0) {
  1878. __set_current_state(TASK_INTERRUPTIBLE);
  1879. sv_handle_midi(s);
  1880. }
  1881. spin_unlock_irqrestore(&s->lock, flags);
  1882. if (cnt > count)
  1883. cnt = count;
  1884. if (cnt <= 0) {
  1885. if (file->f_flags & O_NONBLOCK) {
  1886. if (!ret)
  1887. ret = -EAGAIN;
  1888. break;
  1889. }
  1890. schedule();
  1891. if (signal_pending(current)) {
  1892. if (!ret)
  1893. ret = -ERESTARTSYS;
  1894. break;
  1895. }
  1896. continue;
  1897. }
  1898. if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
  1899. if (!ret)
  1900. ret = -EFAULT;
  1901. break;
  1902. }
  1903. ptr = (ptr + cnt) % MIDIOUTBUF;
  1904. spin_lock_irqsave(&s->lock, flags);
  1905. s->midi.owr = ptr;
  1906. s->midi.ocnt += cnt;
  1907. spin_unlock_irqrestore(&s->lock, flags);
  1908. count -= cnt;
  1909. buffer += cnt;
  1910. ret += cnt;
  1911. spin_lock_irqsave(&s->lock, flags);
  1912. sv_handle_midi(s);
  1913. spin_unlock_irqrestore(&s->lock, flags);
  1914. }
  1915. __set_current_state(TASK_RUNNING);
  1916. remove_wait_queue(&s->midi.owait, &wait);
  1917. return ret;
  1918. }
  1919. /* No kernel lock - we have our own spinlock */
  1920. static unsigned int sv_midi_poll(struct file *file, struct poll_table_struct *wait)
  1921. {
  1922. struct sv_state *s = (struct sv_state *)file->private_data;
  1923. unsigned long flags;
  1924. unsigned int mask = 0;
  1925. VALIDATE_STATE(s);
  1926. if (file->f_mode & FMODE_WRITE)
  1927. poll_wait(file, &s->midi.owait, wait);
  1928. if (file->f_mode & FMODE_READ)
  1929. poll_wait(file, &s->midi.iwait, wait);
  1930. spin_lock_irqsave(&s->lock, flags);
  1931. if (file->f_mode & FMODE_READ) {
  1932. if (s->midi.icnt > 0)
  1933. mask |= POLLIN | POLLRDNORM;
  1934. }
  1935. if (file->f_mode & FMODE_WRITE) {
  1936. if (s->midi.ocnt < MIDIOUTBUF)
  1937. mask |= POLLOUT | POLLWRNORM;
  1938. }
  1939. spin_unlock_irqrestore(&s->lock, flags);
  1940. return mask;
  1941. }
  1942. static int sv_midi_open(struct inode *inode, struct file *file)
  1943. {
  1944. int minor = iminor(inode);
  1945. DECLARE_WAITQUEUE(wait, current);
  1946. unsigned long flags;
  1947. struct list_head *list;
  1948. struct sv_state *s;
  1949. for (list = devs.next; ; list = list->next) {
  1950. if (list == &devs)
  1951. return -ENODEV;
  1952. s = list_entry(list, struct sv_state, devs);
  1953. if (s->dev_midi == minor)
  1954. break;
  1955. }
  1956. VALIDATE_STATE(s);
  1957. file->private_data = s;
  1958. /* wait for device to become free */
  1959. mutex_lock(&s->open_mutex);
  1960. while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
  1961. if (file->f_flags & O_NONBLOCK) {
  1962. mutex_unlock(&s->open_mutex);
  1963. return -EBUSY;
  1964. }
  1965. add_wait_queue(&s->open_wait, &wait);
  1966. __set_current_state(TASK_INTERRUPTIBLE);
  1967. mutex_unlock(&s->open_mutex);
  1968. schedule();
  1969. remove_wait_queue(&s->open_wait, &wait);
  1970. set_current_state(TASK_RUNNING);
  1971. if (signal_pending(current))
  1972. return -ERESTARTSYS;
  1973. mutex_lock(&s->open_mutex);
  1974. }
  1975. spin_lock_irqsave(&s->lock, flags);
  1976. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  1977. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  1978. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  1979. //outb(inb(s->ioenh + SV_CODEC_CONTROL) | SV_CCTRL_WAVETABLE, s->ioenh + SV_CODEC_CONTROL);
  1980. outb(inb(s->ioenh + SV_CODEC_INTMASK) | SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
  1981. wrindir(s, SV_CIUARTCONTROL, 5); /* output MIDI data to external and internal synth */
  1982. wrindir(s, SV_CIWAVETABLESRC, 1); /* Wavetable in PC RAM */
  1983. outb(0xff, s->iomidi+1); /* reset command */
  1984. outb(0x3f, s->iomidi+1); /* uart command */
  1985. if (!(inb(s->iomidi+1) & 0x80))
  1986. inb(s->iomidi);
  1987. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  1988. init_timer(&s->midi.timer);
  1989. s->midi.timer.expires = jiffies+1;
  1990. s->midi.timer.data = (unsigned long)s;
  1991. s->midi.timer.function = sv_midi_timer;
  1992. add_timer(&s->midi.timer);
  1993. }
  1994. if (file->f_mode & FMODE_READ) {
  1995. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  1996. }
  1997. if (file->f_mode & FMODE_WRITE) {
  1998. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  1999. }
  2000. spin_unlock_irqrestore(&s->lock, flags);
  2001. s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
  2002. mutex_unlock(&s->open_mutex);
  2003. return nonseekable_open(inode, file);
  2004. }
  2005. static int sv_midi_release(struct inode *inode, struct file *file)
  2006. {
  2007. struct sv_state *s = (struct sv_state *)file->private_data;
  2008. DECLARE_WAITQUEUE(wait, current);
  2009. unsigned long flags;
  2010. unsigned count, tmo;
  2011. VALIDATE_STATE(s);
  2012. lock_kernel();
  2013. if (file->f_mode & FMODE_WRITE) {
  2014. add_wait_queue(&s->midi.owait, &wait);
  2015. for (;;) {
  2016. __set_current_state(TASK_INTERRUPTIBLE);
  2017. spin_lock_irqsave(&s->lock, flags);
  2018. count = s->midi.ocnt;
  2019. spin_unlock_irqrestore(&s->lock, flags);
  2020. if (count <= 0)
  2021. break;
  2022. if (signal_pending(current))
  2023. break;
  2024. if (file->f_flags & O_NONBLOCK) {
  2025. remove_wait_queue(&s->midi.owait, &wait);
  2026. set_current_state(TASK_RUNNING);
  2027. unlock_kernel();
  2028. return -EBUSY;
  2029. }
  2030. tmo = (count * HZ) / 3100;
  2031. if (!schedule_timeout(tmo ? : 1) && tmo)
  2032. printk(KERN_DEBUG "sv: midi timed out??\n");
  2033. }
  2034. remove_wait_queue(&s->midi.owait, &wait);
  2035. set_current_state(TASK_RUNNING);
  2036. }
  2037. mutex_lock(&s->open_mutex);
  2038. s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
  2039. spin_lock_irqsave(&s->lock, flags);
  2040. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2041. outb(inb(s->ioenh + SV_CODEC_INTMASK) & ~SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
  2042. del_timer(&s->midi.timer);
  2043. }
  2044. spin_unlock_irqrestore(&s->lock, flags);
  2045. wake_up(&s->open_wait);
  2046. mutex_unlock(&s->open_mutex);
  2047. unlock_kernel();
  2048. return 0;
  2049. }
  2050. static /*const*/ struct file_operations sv_midi_fops = {
  2051. .owner = THIS_MODULE,
  2052. .llseek = no_llseek,
  2053. .read = sv_midi_read,
  2054. .write = sv_midi_write,
  2055. .poll = sv_midi_poll,
  2056. .open = sv_midi_open,
  2057. .release = sv_midi_release,
  2058. };
  2059. /* --------------------------------------------------------------------- */
  2060. static int sv_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  2061. {
  2062. static const unsigned char op_offset[18] = {
  2063. 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
  2064. 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
  2065. 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
  2066. };
  2067. struct sv_state *s = (struct sv_state *)file->private_data;
  2068. struct dm_fm_voice v;
  2069. struct dm_fm_note n;
  2070. struct dm_fm_params p;
  2071. unsigned int io;
  2072. unsigned int regb;
  2073. switch (cmd) {
  2074. case FM_IOCTL_RESET:
  2075. for (regb = 0xb0; regb < 0xb9; regb++) {
  2076. outb(regb, s->iosynth);
  2077. outb(0, s->iosynth+1);
  2078. outb(regb, s->iosynth+2);
  2079. outb(0, s->iosynth+3);
  2080. }
  2081. return 0;
  2082. case FM_IOCTL_PLAY_NOTE:
  2083. if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
  2084. return -EFAULT;
  2085. if (n.voice >= 18)
  2086. return -EINVAL;
  2087. if (n.voice >= 9) {
  2088. regb = n.voice - 9;
  2089. io = s->iosynth+2;
  2090. } else {
  2091. regb = n.voice;
  2092. io = s->iosynth;
  2093. }
  2094. outb(0xa0 + regb, io);
  2095. outb(n.fnum & 0xff, io+1);
  2096. outb(0xb0 + regb, io);
  2097. outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
  2098. return 0;
  2099. case FM_IOCTL_SET_VOICE:
  2100. if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
  2101. return -EFAULT;
  2102. if (v.voice >= 18)
  2103. return -EINVAL;
  2104. regb = op_offset[v.voice];
  2105. io = s->iosynth + ((v.op & 1) << 1);
  2106. outb(0x20 + regb, io);
  2107. outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
  2108. ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
  2109. outb(0x40 + regb, io);
  2110. outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
  2111. outb(0x60 + regb, io);
  2112. outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
  2113. outb(0x80 + regb, io);
  2114. outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
  2115. outb(0xe0 + regb, io);
  2116. outb(v.waveform & 0x7, io+1);
  2117. if (n.voice >= 9) {
  2118. regb = n.voice - 9;
  2119. io = s->iosynth+2;
  2120. } else {
  2121. regb = n.voice;
  2122. io = s->iosynth;
  2123. }
  2124. outb(0xc0 + regb, io);
  2125. outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
  2126. (v.connection & 1), io+1);
  2127. return 0;
  2128. case FM_IOCTL_SET_PARAMS:
  2129. if (copy_from_user(&p, (void *__user )arg, sizeof(p)))
  2130. return -EFAULT;
  2131. outb(0x08, s->iosynth);
  2132. outb((p.kbd_split & 1) << 6, s->iosynth+1);
  2133. outb(0xbd, s->iosynth);
  2134. outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
  2135. ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->iosynth+1);
  2136. return 0;
  2137. case FM_IOCTL_SET_OPL:
  2138. outb(4, s->iosynth+2);
  2139. outb(arg, s->iosynth+3);
  2140. return 0;
  2141. case FM_IOCTL_SET_MODE:
  2142. outb(5, s->iosynth+2);
  2143. outb(arg & 1, s->iosynth+3);
  2144. return 0;
  2145. default:
  2146. return -EINVAL;
  2147. }
  2148. }
  2149. static int sv_dmfm_open(struct inode *inode, struct file *file)
  2150. {
  2151. int minor = iminor(inode);
  2152. DECLARE_WAITQUEUE(wait, current);
  2153. struct list_head *list;
  2154. struct sv_state *s;
  2155. for (list = devs.next; ; list = list->next) {
  2156. if (list == &devs)
  2157. return -ENODEV;
  2158. s = list_entry(list, struct sv_state, devs);
  2159. if (s->dev_dmfm == minor)
  2160. break;
  2161. }
  2162. VALIDATE_STATE(s);
  2163. file->private_data = s;
  2164. /* wait for device to become free */
  2165. mutex_lock(&s->open_mutex);
  2166. while (s->open_mode & FMODE_DMFM) {
  2167. if (file->f_flags & O_NONBLOCK) {
  2168. mutex_unlock(&s->open_mutex);
  2169. return -EBUSY;
  2170. }
  2171. add_wait_queue(&s->open_wait, &wait);
  2172. __set_current_state(TASK_INTERRUPTIBLE);
  2173. mutex_unlock(&s->open_mutex);
  2174. schedule();
  2175. remove_wait_queue(&s->open_wait, &wait);
  2176. set_current_state(TASK_RUNNING);
  2177. if (signal_pending(current))
  2178. return -ERESTARTSYS;
  2179. mutex_lock(&s->open_mutex);
  2180. }
  2181. /* init the stuff */
  2182. outb(1, s->iosynth);
  2183. outb(0x20, s->iosynth+1); /* enable waveforms */
  2184. outb(4, s->iosynth+2);
  2185. outb(0, s->iosynth+3); /* no 4op enabled */
  2186. outb(5, s->iosynth+2);
  2187. outb(1, s->iosynth+3); /* enable OPL3 */
  2188. s->open_mode |= FMODE_DMFM;
  2189. mutex_unlock(&s->open_mutex);
  2190. return nonseekable_open(inode, file);
  2191. }
  2192. static int sv_dmfm_release(struct inode *inode, struct file *file)
  2193. {
  2194. struct sv_state *s = (struct sv_state *)file->private_data;
  2195. unsigned int regb;
  2196. VALIDATE_STATE(s);
  2197. lock_kernel();
  2198. mutex_lock(&s->open_mutex);
  2199. s->open_mode &= ~FMODE_DMFM;
  2200. for (regb = 0xb0; regb < 0xb9; regb++) {
  2201. outb(regb, s->iosynth);
  2202. outb(0, s->iosynth+1);
  2203. outb(regb, s->iosynth+2);
  2204. outb(0, s->iosynth+3);
  2205. }
  2206. wake_up(&s->open_wait);
  2207. mutex_unlock(&s->open_mutex);
  2208. unlock_kernel();
  2209. return 0;
  2210. }
  2211. static /*const*/ struct file_operations sv_dmfm_fops = {
  2212. .owner = THIS_MODULE,
  2213. .llseek = no_llseek,
  2214. .ioctl = sv_dmfm_ioctl,
  2215. .open = sv_dmfm_open,
  2216. .release = sv_dmfm_release,
  2217. };
  2218. /* --------------------------------------------------------------------- */
  2219. /* maximum number of devices; only used for command line params */
  2220. #define NR_DEVICE 5
  2221. static int reverb[NR_DEVICE];
  2222. #if 0
  2223. static int wavetable[NR_DEVICE];
  2224. #endif
  2225. static unsigned int devindex;
  2226. module_param_array(reverb, bool, NULL, 0);
  2227. MODULE_PARM_DESC(reverb, "if 1 enables the reverb circuitry. NOTE: your card must have the reverb RAM");
  2228. #if 0
  2229. MODULE_PARM(wavetable, "1-" __MODULE_STRING(NR_DEVICE) "i");
  2230. MODULE_PARM_DESC(wavetable, "if 1 the wavetable synth is enabled");
  2231. #endif
  2232. MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
  2233. MODULE_DESCRIPTION("S3 SonicVibes Driver");
  2234. MODULE_LICENSE("GPL");
  2235. /* --------------------------------------------------------------------- */
  2236. static struct initvol {
  2237. int mixch;
  2238. int vol;
  2239. } initvol[] __devinitdata = {
  2240. { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
  2241. { SOUND_MIXER_WRITE_LINE1, 0x4040 },
  2242. { SOUND_MIXER_WRITE_CD, 0x4040 },
  2243. { SOUND_MIXER_WRITE_LINE, 0x4040 },
  2244. { SOUND_MIXER_WRITE_MIC, 0x4040 },
  2245. { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
  2246. { SOUND_MIXER_WRITE_LINE2, 0x4040 },
  2247. { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
  2248. { SOUND_MIXER_WRITE_PCM, 0x4040 }
  2249. };
  2250. #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
  2251. (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
  2252. #ifdef SUPPORT_JOYSTICK
  2253. static int __devinit sv_register_gameport(struct sv_state *s, int io_port)
  2254. {
  2255. struct gameport *gp;
  2256. if (!request_region(io_port, SV_EXTENT_GAME, "S3 SonicVibes Gameport")) {
  2257. printk(KERN_ERR "sv: gameport io ports are in use\n");
  2258. return -EBUSY;
  2259. }
  2260. s->gameport = gp = gameport_allocate_port();
  2261. if (!gp) {
  2262. printk(KERN_ERR "sv: can not allocate memory for gameport\n");
  2263. release_region(io_port, SV_EXTENT_GAME);
  2264. return -ENOMEM;
  2265. }
  2266. gameport_set_name(gp, "S3 SonicVibes Gameport");
  2267. gameport_set_phys(gp, "isa%04x/gameport0", io_port);
  2268. gp->dev.parent = &s->dev->dev;
  2269. gp->io = io_port;
  2270. gameport_register_port(gp);
  2271. return 0;
  2272. }
  2273. static inline void sv_unregister_gameport(struct sv_state *s)
  2274. {
  2275. if (s->gameport) {
  2276. int gpio = s->gameport->io;
  2277. gameport_unregister_port(s->gameport);
  2278. release_region(gpio, SV_EXTENT_GAME);
  2279. }
  2280. }
  2281. #else
  2282. static inline int sv_register_gameport(struct sv_state *s, int io_port) { return -ENOSYS; }
  2283. static inline void sv_unregister_gameport(struct sv_state *s) { }
  2284. #endif /* SUPPORT_JOYSTICK */
  2285. static int __devinit sv_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
  2286. {
  2287. static char __devinitdata sv_ddma_name[] = "S3 Inc. SonicVibes DDMA Controller";
  2288. struct sv_state *s;
  2289. mm_segment_t fs;
  2290. int i, val, ret;
  2291. int gpio;
  2292. char *ddmaname;
  2293. unsigned ddmanamelen;
  2294. if ((ret=pci_enable_device(pcidev)))
  2295. return ret;
  2296. if (!RSRCISIOREGION(pcidev, RESOURCE_SB) ||
  2297. !RSRCISIOREGION(pcidev, RESOURCE_ENH) ||
  2298. !RSRCISIOREGION(pcidev, RESOURCE_SYNTH) ||
  2299. !RSRCISIOREGION(pcidev, RESOURCE_MIDI) ||
  2300. !RSRCISIOREGION(pcidev, RESOURCE_GAME))
  2301. return -ENODEV;
  2302. if (pcidev->irq == 0)
  2303. return -ENODEV;
  2304. if (pci_set_dma_mask(pcidev, DMA_24BIT_MASK)) {
  2305. printk(KERN_WARNING "sonicvibes: architecture does not support 24bit PCI busmaster DMA\n");
  2306. return -ENODEV;
  2307. }
  2308. /* try to allocate a DDMA resource if not already available */
  2309. if (!RSRCISIOREGION(pcidev, RESOURCE_DDMA)) {
  2310. pcidev->resource[RESOURCE_DDMA].start = 0;
  2311. pcidev->resource[RESOURCE_DDMA].end = 2*SV_EXTENT_DMA-1;
  2312. pcidev->resource[RESOURCE_DDMA].flags = PCI_BASE_ADDRESS_SPACE_IO | IORESOURCE_IO;
  2313. ddmanamelen = strlen(sv_ddma_name)+1;
  2314. if (!(ddmaname = kmalloc(ddmanamelen, GFP_KERNEL)))
  2315. return -1;
  2316. memcpy(ddmaname, sv_ddma_name, ddmanamelen);
  2317. pcidev->resource[RESOURCE_DDMA].name = ddmaname;
  2318. if (pci_assign_resource(pcidev, RESOURCE_DDMA)) {
  2319. pcidev->resource[RESOURCE_DDMA].name = NULL;
  2320. kfree(ddmaname);
  2321. printk(KERN_ERR "sv: cannot allocate DDMA controller io ports\n");
  2322. return -EBUSY;
  2323. }
  2324. }
  2325. if (!(s = kmalloc(sizeof(struct sv_state), GFP_KERNEL))) {
  2326. printk(KERN_WARNING "sv: out of memory\n");
  2327. return -ENOMEM;
  2328. }
  2329. memset(s, 0, sizeof(struct sv_state));
  2330. init_waitqueue_head(&s->dma_adc.wait);
  2331. init_waitqueue_head(&s->dma_dac.wait);
  2332. init_waitqueue_head(&s->open_wait);
  2333. init_waitqueue_head(&s->midi.iwait);
  2334. init_waitqueue_head(&s->midi.owait);
  2335. mutex_init(&s->open_mutex);
  2336. spin_lock_init(&s->lock);
  2337. s->magic = SV_MAGIC;
  2338. s->dev = pcidev;
  2339. s->iosb = pci_resource_start(pcidev, RESOURCE_SB);
  2340. s->ioenh = pci_resource_start(pcidev, RESOURCE_ENH);
  2341. s->iosynth = pci_resource_start(pcidev, RESOURCE_SYNTH);
  2342. s->iomidi = pci_resource_start(pcidev, RESOURCE_MIDI);
  2343. s->iodmaa = pci_resource_start(pcidev, RESOURCE_DDMA);
  2344. s->iodmac = pci_resource_start(pcidev, RESOURCE_DDMA) + SV_EXTENT_DMA;
  2345. gpio = pci_resource_start(pcidev, RESOURCE_GAME);
  2346. pci_write_config_dword(pcidev, 0x40, s->iodmaa | 9); /* enable and use extended mode */
  2347. pci_write_config_dword(pcidev, 0x48, s->iodmac | 9); /* enable */
  2348. printk(KERN_DEBUG "sv: io ports: %#lx %#lx %#lx %#lx %#x %#x %#x\n",
  2349. s->iosb, s->ioenh, s->iosynth, s->iomidi, gpio, s->iodmaa, s->iodmac);
  2350. s->irq = pcidev->irq;
  2351. /* hack */
  2352. pci_write_config_dword(pcidev, 0x60, wavetable_mem >> 12); /* wavetable base address */
  2353. ret = -EBUSY;
  2354. if (!request_region(s->ioenh, SV_EXTENT_ENH, "S3 SonicVibes PCM")) {
  2355. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->ioenh, s->ioenh+SV_EXTENT_ENH-1);
  2356. goto err_region5;
  2357. }
  2358. if (!request_region(s->iodmaa, SV_EXTENT_DMA, "S3 SonicVibes DMAA")) {
  2359. printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmaa, s->iodmaa+SV_EXTENT_DMA-1);
  2360. goto err_region4;
  2361. }
  2362. if (!request_region(s->iodmac, SV_EXTENT_DMA, "S3 SonicVibes DMAC")) {
  2363. printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmac, s->iodmac+SV_EXTENT_DMA-1);
  2364. goto err_region3;
  2365. }
  2366. if (!request_region(s->iomidi, SV_EXTENT_MIDI, "S3 SonicVibes Midi")) {
  2367. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iomidi, s->iomidi+SV_EXTENT_MIDI-1);
  2368. goto err_region2;
  2369. }
  2370. if (!request_region(s->iosynth, SV_EXTENT_SYNTH, "S3 SonicVibes Synth")) {
  2371. printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iosynth, s->iosynth+SV_EXTENT_SYNTH-1);
  2372. goto err_region1;
  2373. }
  2374. /* initialize codec registers */
  2375. outb(0x80, s->ioenh + SV_CODEC_CONTROL); /* assert reset */
  2376. udelay(50);
  2377. outb(0x00, s->ioenh + SV_CODEC_CONTROL); /* deassert reset */
  2378. udelay(50);
  2379. outb(SV_CCTRL_INTADRIVE | SV_CCTRL_ENHANCED /*| SV_CCTRL_WAVETABLE */
  2380. | (reverb[devindex] ? SV_CCTRL_REVERB : 0), s->ioenh + SV_CODEC_CONTROL);
  2381. inb(s->ioenh + SV_CODEC_STATUS); /* clear ints */
  2382. wrindir(s, SV_CIDRIVECONTROL, 0); /* drive current 16mA */
  2383. wrindir(s, SV_CIENABLE, s->enable = 0); /* disable DMAA and DMAC */
  2384. outb(~(SV_CINTMASK_DMAA | SV_CINTMASK_DMAC), s->ioenh + SV_CODEC_INTMASK);
  2385. /* outb(0xff, s->iodmaa + SV_DMA_RESET); */
  2386. /* outb(0xff, s->iodmac + SV_DMA_RESET); */
  2387. inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
  2388. wrindir(s, SV_CIADCCLKSOURCE, 0); /* use pll as ADC clock source */
  2389. wrindir(s, SV_CIANALOGPWRDOWN, 0); /* power up the analog parts of the device */
  2390. wrindir(s, SV_CIDIGITALPWRDOWN, 0); /* power up the digital parts of the device */
  2391. setpll(s, SV_CIADCPLLM, 8000);
  2392. wrindir(s, SV_CISRSSPACE, 0x80); /* SRS off */
  2393. wrindir(s, SV_CIPCMSR0, (8000 * 65536 / FULLRATE) & 0xff);
  2394. wrindir(s, SV_CIPCMSR1, ((8000 * 65536 / FULLRATE) >> 8) & 0xff);
  2395. wrindir(s, SV_CIADCOUTPUT, 0);
  2396. /* request irq */
  2397. if ((ret=request_irq(s->irq,sv_interrupt,SA_SHIRQ,"S3 SonicVibes",s))) {
  2398. printk(KERN_ERR "sv: irq %u in use\n", s->irq);
  2399. goto err_irq;
  2400. }
  2401. printk(KERN_INFO "sv: found adapter at io %#lx irq %u dmaa %#06x dmac %#06x revision %u\n",
  2402. s->ioenh, s->irq, s->iodmaa, s->iodmac, rdindir(s, SV_CIREVISION));
  2403. /* register devices */
  2404. if ((s->dev_audio = register_sound_dsp(&sv_audio_fops, -1)) < 0) {
  2405. ret = s->dev_audio;
  2406. goto err_dev1;
  2407. }
  2408. if ((s->dev_mixer = register_sound_mixer(&sv_mixer_fops, -1)) < 0) {
  2409. ret = s->dev_mixer;
  2410. goto err_dev2;
  2411. }
  2412. if ((s->dev_midi = register_sound_midi(&sv_midi_fops, -1)) < 0) {
  2413. ret = s->dev_midi;
  2414. goto err_dev3;
  2415. }
  2416. if ((s->dev_dmfm = register_sound_special(&sv_dmfm_fops, 15 /* ?? */)) < 0) {
  2417. ret = s->dev_dmfm;
  2418. goto err_dev4;
  2419. }
  2420. pci_set_master(pcidev); /* enable bus mastering */
  2421. /* initialize the chips */
  2422. fs = get_fs();
  2423. set_fs(KERNEL_DS);
  2424. val = SOUND_MASK_LINE|SOUND_MASK_SYNTH;
  2425. mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
  2426. for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
  2427. val = initvol[i].vol;
  2428. mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
  2429. }
  2430. set_fs(fs);
  2431. /* register gameport */
  2432. sv_register_gameport(s, gpio);
  2433. /* store it in the driver field */
  2434. pci_set_drvdata(pcidev, s);
  2435. /* put it into driver list */
  2436. list_add_tail(&s->devs, &devs);
  2437. /* increment devindex */
  2438. if (devindex < NR_DEVICE-1)
  2439. devindex++;
  2440. return 0;
  2441. err_dev4:
  2442. unregister_sound_midi(s->dev_midi);
  2443. err_dev3:
  2444. unregister_sound_mixer(s->dev_mixer);
  2445. err_dev2:
  2446. unregister_sound_dsp(s->dev_audio);
  2447. err_dev1:
  2448. printk(KERN_ERR "sv: cannot register misc device\n");
  2449. free_irq(s->irq, s);
  2450. err_irq:
  2451. release_region(s->iosynth, SV_EXTENT_SYNTH);
  2452. err_region1:
  2453. release_region(s->iomidi, SV_EXTENT_MIDI);
  2454. err_region2:
  2455. release_region(s->iodmac, SV_EXTENT_DMA);
  2456. err_region3:
  2457. release_region(s->iodmaa, SV_EXTENT_DMA);
  2458. err_region4:
  2459. release_region(s->ioenh, SV_EXTENT_ENH);
  2460. err_region5:
  2461. kfree(s);
  2462. return ret;
  2463. }
  2464. static void __devexit sv_remove(struct pci_dev *dev)
  2465. {
  2466. struct sv_state *s = pci_get_drvdata(dev);
  2467. if (!s)
  2468. return;
  2469. list_del(&s->devs);
  2470. outb(~0, s->ioenh + SV_CODEC_INTMASK); /* disable ints */
  2471. synchronize_irq(s->irq);
  2472. inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
  2473. wrindir(s, SV_CIENABLE, 0); /* disable DMAA and DMAC */
  2474. /*outb(0, s->iodmaa + SV_DMA_RESET);*/
  2475. /*outb(0, s->iodmac + SV_DMA_RESET);*/
  2476. free_irq(s->irq, s);
  2477. sv_unregister_gameport(s);
  2478. release_region(s->iodmac, SV_EXTENT_DMA);
  2479. release_region(s->iodmaa, SV_EXTENT_DMA);
  2480. release_region(s->ioenh, SV_EXTENT_ENH);
  2481. release_region(s->iomidi, SV_EXTENT_MIDI);
  2482. release_region(s->iosynth, SV_EXTENT_SYNTH);
  2483. unregister_sound_dsp(s->dev_audio);
  2484. unregister_sound_mixer(s->dev_mixer);
  2485. unregister_sound_midi(s->dev_midi);
  2486. unregister_sound_special(s->dev_dmfm);
  2487. kfree(s);
  2488. pci_set_drvdata(dev, NULL);
  2489. }
  2490. static struct pci_device_id id_table[] = {
  2491. { PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SONICVIBES, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2492. { 0, }
  2493. };
  2494. MODULE_DEVICE_TABLE(pci, id_table);
  2495. static struct pci_driver sv_driver = {
  2496. .name = "sonicvibes",
  2497. .id_table = id_table,
  2498. .probe = sv_probe,
  2499. .remove = __devexit_p(sv_remove),
  2500. };
  2501. static int __init init_sonicvibes(void)
  2502. {
  2503. printk(KERN_INFO "sv: version v0.31 time " __TIME__ " " __DATE__ "\n");
  2504. #if 0
  2505. if (!(wavetable_mem = __get_free_pages(GFP_KERNEL, 20-PAGE_SHIFT)))
  2506. printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
  2507. #endif
  2508. return pci_register_driver(&sv_driver);
  2509. }
  2510. static void __exit cleanup_sonicvibes(void)
  2511. {
  2512. printk(KERN_INFO "sv: unloading\n");
  2513. pci_unregister_driver(&sv_driver);
  2514. if (wavetable_mem)
  2515. free_pages(wavetable_mem, 20-PAGE_SHIFT);
  2516. }
  2517. module_init(init_sonicvibes);
  2518. module_exit(cleanup_sonicvibes);
  2519. /* --------------------------------------------------------------------- */
  2520. #ifndef MODULE
  2521. /* format is: sonicvibes=[reverb] sonicvibesdmaio=dmaioaddr */
  2522. static int __init sonicvibes_setup(char *str)
  2523. {
  2524. static unsigned __initdata nr_dev = 0;
  2525. if (nr_dev >= NR_DEVICE)
  2526. return 0;
  2527. #if 0
  2528. if (get_option(&str, &reverb[nr_dev]) == 2)
  2529. (void)get_option(&str, &wavetable[nr_dev]);
  2530. #else
  2531. (void)get_option(&str, &reverb[nr_dev]);
  2532. #endif
  2533. nr_dev++;
  2534. return 1;
  2535. }
  2536. __setup("sonicvibes=", sonicvibes_setup);
  2537. #endif /* MODULE */