ad1848_lib.c 38 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Routines for control of AD1848/AD1847/CS4248
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #define SNDRV_MAIN_OBJECT_FILE
  22. #include <sound/driver.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/slab.h>
  27. #include <linux/ioport.h>
  28. #include <sound/core.h>
  29. #include <sound/ad1848.h>
  30. #include <sound/control.h>
  31. #include <sound/pcm_params.h>
  32. #include <asm/io.h>
  33. #include <asm/dma.h>
  34. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  35. MODULE_DESCRIPTION("Routines for control of AD1848/AD1847/CS4248");
  36. MODULE_LICENSE("GPL");
  37. #if 0
  38. #define SNDRV_DEBUG_MCE
  39. #endif
  40. /*
  41. * Some variables
  42. */
  43. static unsigned char freq_bits[14] = {
  44. /* 5510 */ 0x00 | AD1848_XTAL2,
  45. /* 6620 */ 0x0E | AD1848_XTAL2,
  46. /* 8000 */ 0x00 | AD1848_XTAL1,
  47. /* 9600 */ 0x0E | AD1848_XTAL1,
  48. /* 11025 */ 0x02 | AD1848_XTAL2,
  49. /* 16000 */ 0x02 | AD1848_XTAL1,
  50. /* 18900 */ 0x04 | AD1848_XTAL2,
  51. /* 22050 */ 0x06 | AD1848_XTAL2,
  52. /* 27042 */ 0x04 | AD1848_XTAL1,
  53. /* 32000 */ 0x06 | AD1848_XTAL1,
  54. /* 33075 */ 0x0C | AD1848_XTAL2,
  55. /* 37800 */ 0x08 | AD1848_XTAL2,
  56. /* 44100 */ 0x0A | AD1848_XTAL2,
  57. /* 48000 */ 0x0C | AD1848_XTAL1
  58. };
  59. static unsigned int rates[14] = {
  60. 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
  61. 27042, 32000, 33075, 37800, 44100, 48000
  62. };
  63. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  64. .count = 14,
  65. .list = rates,
  66. .mask = 0,
  67. };
  68. static unsigned char snd_ad1848_original_image[16] =
  69. {
  70. 0x00, /* 00 - lic */
  71. 0x00, /* 01 - ric */
  72. 0x9f, /* 02 - la1ic */
  73. 0x9f, /* 03 - ra1ic */
  74. 0x9f, /* 04 - la2ic */
  75. 0x9f, /* 05 - ra2ic */
  76. 0xbf, /* 06 - loc */
  77. 0xbf, /* 07 - roc */
  78. 0x20, /* 08 - dfr */
  79. AD1848_AUTOCALIB, /* 09 - ic */
  80. 0x00, /* 0a - pc */
  81. 0x00, /* 0b - ti */
  82. 0x00, /* 0c - mi */
  83. 0x00, /* 0d - lbc */
  84. 0x00, /* 0e - dru */
  85. 0x00, /* 0f - drl */
  86. };
  87. /*
  88. * Basic I/O functions
  89. */
  90. void snd_ad1848_out(struct snd_ad1848 *chip,
  91. unsigned char reg,
  92. unsigned char value)
  93. {
  94. int timeout;
  95. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  96. udelay(100);
  97. #ifdef CONFIG_SND_DEBUG
  98. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  99. snd_printk(KERN_WARNING "auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
  100. #endif
  101. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  102. outb(chip->image[reg] = value, AD1848P(chip, REG));
  103. mb();
  104. #if 0
  105. printk("codec out - reg 0x%x = 0x%x\n", chip->mce_bit | reg, value);
  106. #endif
  107. }
  108. static void snd_ad1848_dout(struct snd_ad1848 *chip,
  109. unsigned char reg, unsigned char value)
  110. {
  111. int timeout;
  112. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  113. udelay(100);
  114. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  115. outb(value, AD1848P(chip, REG));
  116. mb();
  117. }
  118. static unsigned char snd_ad1848_in(struct snd_ad1848 *chip, unsigned char reg)
  119. {
  120. int timeout;
  121. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  122. udelay(100);
  123. #ifdef CONFIG_SND_DEBUG
  124. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  125. snd_printk(KERN_WARNING "auto calibration time out - reg = 0x%x\n", reg);
  126. #endif
  127. outb(chip->mce_bit | reg, AD1848P(chip, REGSEL));
  128. mb();
  129. return inb(AD1848P(chip, REG));
  130. }
  131. #if 0
  132. static void snd_ad1848_debug(struct snd_ad1848 *chip)
  133. {
  134. printk("AD1848 REGS: INDEX = 0x%02x ", inb(AD1848P(chip, REGSEL)));
  135. printk(" STATUS = 0x%02x\n", inb(AD1848P(chip, STATUS)));
  136. printk(" 0x00: left input = 0x%02x ", snd_ad1848_in(chip, 0x00));
  137. printk(" 0x08: playback format = 0x%02x\n", snd_ad1848_in(chip, 0x08));
  138. printk(" 0x01: right input = 0x%02x ", snd_ad1848_in(chip, 0x01));
  139. printk(" 0x09: iface (CFIG 1) = 0x%02x\n", snd_ad1848_in(chip, 0x09));
  140. printk(" 0x02: AUXA left = 0x%02x ", snd_ad1848_in(chip, 0x02));
  141. printk(" 0x0a: pin control = 0x%02x\n", snd_ad1848_in(chip, 0x0a));
  142. printk(" 0x03: AUXA right = 0x%02x ", snd_ad1848_in(chip, 0x03));
  143. printk(" 0x0b: init & status = 0x%02x\n", snd_ad1848_in(chip, 0x0b));
  144. printk(" 0x04: AUXB left = 0x%02x ", snd_ad1848_in(chip, 0x04));
  145. printk(" 0x0c: revision & mode = 0x%02x\n", snd_ad1848_in(chip, 0x0c));
  146. printk(" 0x05: AUXB right = 0x%02x ", snd_ad1848_in(chip, 0x05));
  147. printk(" 0x0d: loopback = 0x%02x\n", snd_ad1848_in(chip, 0x0d));
  148. printk(" 0x06: left output = 0x%02x ", snd_ad1848_in(chip, 0x06));
  149. printk(" 0x0e: data upr count = 0x%02x\n", snd_ad1848_in(chip, 0x0e));
  150. printk(" 0x07: right output = 0x%02x ", snd_ad1848_in(chip, 0x07));
  151. printk(" 0x0f: data lwr count = 0x%02x\n", snd_ad1848_in(chip, 0x0f));
  152. }
  153. #endif
  154. /*
  155. * AD1848 detection / MCE routines
  156. */
  157. static void snd_ad1848_mce_up(struct snd_ad1848 *chip)
  158. {
  159. unsigned long flags;
  160. int timeout;
  161. for (timeout = 250; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  162. udelay(100);
  163. #ifdef CONFIG_SND_DEBUG
  164. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  165. snd_printk(KERN_WARNING "mce_up - auto calibration time out (0)\n");
  166. #endif
  167. spin_lock_irqsave(&chip->reg_lock, flags);
  168. chip->mce_bit |= AD1848_MCE;
  169. timeout = inb(AD1848P(chip, REGSEL));
  170. if (timeout == 0x80)
  171. snd_printk(KERN_WARNING "mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
  172. if (!(timeout & AD1848_MCE))
  173. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  174. spin_unlock_irqrestore(&chip->reg_lock, flags);
  175. }
  176. static void snd_ad1848_mce_down(struct snd_ad1848 *chip)
  177. {
  178. unsigned long flags;
  179. int timeout;
  180. signed long time;
  181. spin_lock_irqsave(&chip->reg_lock, flags);
  182. for (timeout = 5; timeout > 0; timeout--)
  183. inb(AD1848P(chip, REGSEL));
  184. /* end of cleanup sequence */
  185. for (timeout = 12000; timeout > 0 && (inb(AD1848P(chip, REGSEL)) & AD1848_INIT); timeout--)
  186. udelay(100);
  187. #if 0
  188. printk("(1) timeout = %i\n", timeout);
  189. #endif
  190. #ifdef CONFIG_SND_DEBUG
  191. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  192. snd_printk(KERN_WARNING "mce_down [0x%lx] - auto calibration time out (0)\n", AD1848P(chip, REGSEL));
  193. #endif
  194. chip->mce_bit &= ~AD1848_MCE;
  195. timeout = inb(AD1848P(chip, REGSEL));
  196. outb(chip->mce_bit | (timeout & 0x1f), AD1848P(chip, REGSEL));
  197. if (timeout == 0x80)
  198. snd_printk(KERN_WARNING "mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
  199. if ((timeout & AD1848_MCE) == 0) {
  200. spin_unlock_irqrestore(&chip->reg_lock, flags);
  201. return;
  202. }
  203. /* calibration process */
  204. for (timeout = 500; timeout > 0 && (snd_ad1848_in(chip, AD1848_TEST_INIT) & AD1848_CALIB_IN_PROGRESS) == 0; timeout--);
  205. if ((snd_ad1848_in(chip, AD1848_TEST_INIT) & AD1848_CALIB_IN_PROGRESS) == 0) {
  206. snd_printd("mce_down - auto calibration time out (1)\n");
  207. spin_unlock_irqrestore(&chip->reg_lock, flags);
  208. return;
  209. }
  210. #if 0
  211. printk("(2) timeout = %i, jiffies = %li\n", timeout, jiffies);
  212. #endif
  213. time = HZ / 4;
  214. while (snd_ad1848_in(chip, AD1848_TEST_INIT) & AD1848_CALIB_IN_PROGRESS) {
  215. spin_unlock_irqrestore(&chip->reg_lock, flags);
  216. if (time <= 0) {
  217. snd_printk(KERN_ERR "mce_down - auto calibration time out (2)\n");
  218. return;
  219. }
  220. time = schedule_timeout_interruptible(time);
  221. spin_lock_irqsave(&chip->reg_lock, flags);
  222. }
  223. #if 0
  224. printk("(3) jiffies = %li\n", jiffies);
  225. #endif
  226. time = HZ / 10;
  227. while (inb(AD1848P(chip, REGSEL)) & AD1848_INIT) {
  228. spin_unlock_irqrestore(&chip->reg_lock, flags);
  229. if (time <= 0) {
  230. snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
  231. return;
  232. }
  233. time = schedule_timeout_interruptible(time);
  234. spin_lock_irqsave(&chip->reg_lock, flags);
  235. }
  236. spin_unlock_irqrestore(&chip->reg_lock, flags);
  237. #if 0
  238. printk("(4) jiffies = %li\n", jiffies);
  239. snd_printk("mce_down - exit = 0x%x\n", inb(AD1848P(chip, REGSEL)));
  240. #endif
  241. }
  242. static unsigned int snd_ad1848_get_count(unsigned char format,
  243. unsigned int size)
  244. {
  245. switch (format & 0xe0) {
  246. case AD1848_LINEAR_16:
  247. size >>= 1;
  248. break;
  249. }
  250. if (format & AD1848_STEREO)
  251. size >>= 1;
  252. return size;
  253. }
  254. static int snd_ad1848_trigger(struct snd_ad1848 *chip, unsigned char what,
  255. int channel, int cmd)
  256. {
  257. int result = 0;
  258. #if 0
  259. printk("codec trigger!!! - what = %i, enable = %i, status = 0x%x\n", what, enable, inb(AD1848P(card, STATUS)));
  260. #endif
  261. spin_lock(&chip->reg_lock);
  262. if (cmd == SNDRV_PCM_TRIGGER_START) {
  263. if (chip->image[AD1848_IFACE_CTRL] & what) {
  264. spin_unlock(&chip->reg_lock);
  265. return 0;
  266. }
  267. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] |= what);
  268. chip->mode |= AD1848_MODE_RUNNING;
  269. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  270. if (!(chip->image[AD1848_IFACE_CTRL] & what)) {
  271. spin_unlock(&chip->reg_lock);
  272. return 0;
  273. }
  274. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL] &= ~what);
  275. chip->mode &= ~AD1848_MODE_RUNNING;
  276. } else {
  277. result = -EINVAL;
  278. }
  279. spin_unlock(&chip->reg_lock);
  280. return result;
  281. }
  282. /*
  283. * CODEC I/O
  284. */
  285. static unsigned char snd_ad1848_get_rate(unsigned int rate)
  286. {
  287. int i;
  288. for (i = 0; i < 14; i++)
  289. if (rate == rates[i])
  290. return freq_bits[i];
  291. snd_BUG();
  292. return freq_bits[13];
  293. }
  294. static int snd_ad1848_ioctl(struct snd_pcm_substream *substream,
  295. unsigned int cmd, void *arg)
  296. {
  297. return snd_pcm_lib_ioctl(substream, cmd, arg);
  298. }
  299. static unsigned char snd_ad1848_get_format(int format, int channels)
  300. {
  301. unsigned char rformat;
  302. rformat = AD1848_LINEAR_8;
  303. switch (format) {
  304. case SNDRV_PCM_FORMAT_A_LAW: rformat = AD1848_ALAW_8; break;
  305. case SNDRV_PCM_FORMAT_MU_LAW: rformat = AD1848_ULAW_8; break;
  306. case SNDRV_PCM_FORMAT_S16_LE: rformat = AD1848_LINEAR_16; break;
  307. }
  308. if (channels > 1)
  309. rformat |= AD1848_STEREO;
  310. #if 0
  311. snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
  312. #endif
  313. return rformat;
  314. }
  315. static void snd_ad1848_calibrate_mute(struct snd_ad1848 *chip, int mute)
  316. {
  317. unsigned long flags;
  318. mute = mute ? 1 : 0;
  319. spin_lock_irqsave(&chip->reg_lock, flags);
  320. if (chip->calibrate_mute == mute) {
  321. spin_unlock_irqrestore(&chip->reg_lock, flags);
  322. return;
  323. }
  324. if (!mute) {
  325. snd_ad1848_dout(chip, AD1848_LEFT_INPUT, chip->image[AD1848_LEFT_INPUT]);
  326. snd_ad1848_dout(chip, AD1848_RIGHT_INPUT, chip->image[AD1848_RIGHT_INPUT]);
  327. }
  328. snd_ad1848_dout(chip, AD1848_AUX1_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_LEFT_INPUT]);
  329. snd_ad1848_dout(chip, AD1848_AUX1_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX1_RIGHT_INPUT]);
  330. snd_ad1848_dout(chip, AD1848_AUX2_LEFT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_LEFT_INPUT]);
  331. snd_ad1848_dout(chip, AD1848_AUX2_RIGHT_INPUT, mute ? 0x80 : chip->image[AD1848_AUX2_RIGHT_INPUT]);
  332. snd_ad1848_dout(chip, AD1848_LEFT_OUTPUT, mute ? 0x80 : chip->image[AD1848_LEFT_OUTPUT]);
  333. snd_ad1848_dout(chip, AD1848_RIGHT_OUTPUT, mute ? 0x80 : chip->image[AD1848_RIGHT_OUTPUT]);
  334. chip->calibrate_mute = mute;
  335. spin_unlock_irqrestore(&chip->reg_lock, flags);
  336. }
  337. static void snd_ad1848_set_data_format(struct snd_ad1848 *chip, struct snd_pcm_hw_params *hw_params)
  338. {
  339. if (hw_params == NULL) {
  340. chip->image[AD1848_DATA_FORMAT] = 0x20;
  341. } else {
  342. chip->image[AD1848_DATA_FORMAT] =
  343. snd_ad1848_get_format(params_format(hw_params), params_channels(hw_params)) |
  344. snd_ad1848_get_rate(params_rate(hw_params));
  345. }
  346. // snd_printk(">>> pmode = 0x%x, dfr = 0x%x\n", pstr->mode, chip->image[AD1848_DATA_FORMAT]);
  347. }
  348. static int snd_ad1848_open(struct snd_ad1848 *chip, unsigned int mode)
  349. {
  350. unsigned long flags;
  351. mutex_lock(&chip->open_mutex);
  352. if (chip->mode & AD1848_MODE_OPEN) {
  353. mutex_unlock(&chip->open_mutex);
  354. return -EAGAIN;
  355. }
  356. snd_ad1848_mce_down(chip);
  357. #ifdef SNDRV_DEBUG_MCE
  358. snd_printk("open: (1)\n");
  359. #endif
  360. snd_ad1848_mce_up(chip);
  361. spin_lock_irqsave(&chip->reg_lock, flags);
  362. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  363. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO |
  364. AD1848_CALIB_MODE);
  365. chip->image[AD1848_IFACE_CTRL] |= AD1848_AUTOCALIB;
  366. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  367. spin_unlock_irqrestore(&chip->reg_lock, flags);
  368. snd_ad1848_mce_down(chip);
  369. #ifdef SNDRV_DEBUG_MCE
  370. snd_printk("open: (2)\n");
  371. #endif
  372. snd_ad1848_set_data_format(chip, NULL);
  373. snd_ad1848_mce_up(chip);
  374. spin_lock_irqsave(&chip->reg_lock, flags);
  375. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  376. spin_unlock_irqrestore(&chip->reg_lock, flags);
  377. snd_ad1848_mce_down(chip);
  378. #ifdef SNDRV_DEBUG_MCE
  379. snd_printk("open: (3)\n");
  380. #endif
  381. /* ok. now enable and ack CODEC IRQ */
  382. spin_lock_irqsave(&chip->reg_lock, flags);
  383. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  384. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  385. chip->image[AD1848_PIN_CTRL] |= AD1848_IRQ_ENABLE;
  386. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  387. spin_unlock_irqrestore(&chip->reg_lock, flags);
  388. chip->mode = mode;
  389. mutex_unlock(&chip->open_mutex);
  390. return 0;
  391. }
  392. static void snd_ad1848_close(struct snd_ad1848 *chip)
  393. {
  394. unsigned long flags;
  395. mutex_lock(&chip->open_mutex);
  396. if (!chip->mode) {
  397. mutex_unlock(&chip->open_mutex);
  398. return;
  399. }
  400. /* disable IRQ */
  401. spin_lock_irqsave(&chip->reg_lock, flags);
  402. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  403. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  404. chip->image[AD1848_PIN_CTRL] &= ~AD1848_IRQ_ENABLE;
  405. snd_ad1848_out(chip, AD1848_PIN_CTRL, chip->image[AD1848_PIN_CTRL]);
  406. spin_unlock_irqrestore(&chip->reg_lock, flags);
  407. /* now disable capture & playback */
  408. snd_ad1848_mce_up(chip);
  409. spin_lock_irqsave(&chip->reg_lock, flags);
  410. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO |
  411. AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  412. snd_ad1848_out(chip, AD1848_IFACE_CTRL, chip->image[AD1848_IFACE_CTRL]);
  413. spin_unlock_irqrestore(&chip->reg_lock, flags);
  414. snd_ad1848_mce_down(chip);
  415. /* clear IRQ again */
  416. spin_lock_irqsave(&chip->reg_lock, flags);
  417. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  418. outb(0, AD1848P(chip, STATUS)); /* clear IRQ */
  419. spin_unlock_irqrestore(&chip->reg_lock, flags);
  420. chip->mode = 0;
  421. mutex_unlock(&chip->open_mutex);
  422. }
  423. /*
  424. * ok.. exported functions..
  425. */
  426. static int snd_ad1848_playback_trigger(struct snd_pcm_substream *substream,
  427. int cmd)
  428. {
  429. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  430. return snd_ad1848_trigger(chip, AD1848_PLAYBACK_ENABLE, SNDRV_PCM_STREAM_PLAYBACK, cmd);
  431. }
  432. static int snd_ad1848_capture_trigger(struct snd_pcm_substream *substream,
  433. int cmd)
  434. {
  435. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  436. return snd_ad1848_trigger(chip, AD1848_CAPTURE_ENABLE, SNDRV_PCM_STREAM_CAPTURE, cmd);
  437. }
  438. static int snd_ad1848_playback_hw_params(struct snd_pcm_substream *substream,
  439. struct snd_pcm_hw_params *hw_params)
  440. {
  441. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  442. unsigned long flags;
  443. int err;
  444. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  445. return err;
  446. snd_ad1848_calibrate_mute(chip, 1);
  447. snd_ad1848_set_data_format(chip, hw_params);
  448. snd_ad1848_mce_up(chip);
  449. spin_lock_irqsave(&chip->reg_lock, flags);
  450. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  451. spin_unlock_irqrestore(&chip->reg_lock, flags);
  452. snd_ad1848_mce_down(chip);
  453. snd_ad1848_calibrate_mute(chip, 0);
  454. return 0;
  455. }
  456. static int snd_ad1848_playback_hw_free(struct snd_pcm_substream *substream)
  457. {
  458. return snd_pcm_lib_free_pages(substream);
  459. }
  460. static int snd_ad1848_playback_prepare(struct snd_pcm_substream *substream)
  461. {
  462. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  463. struct snd_pcm_runtime *runtime = substream->runtime;
  464. unsigned long flags;
  465. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  466. unsigned int count = snd_pcm_lib_period_bytes(substream);
  467. chip->dma_size = size;
  468. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_PLAYBACK_ENABLE | AD1848_PLAYBACK_PIO);
  469. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
  470. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  471. spin_lock_irqsave(&chip->reg_lock, flags);
  472. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  473. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  474. spin_unlock_irqrestore(&chip->reg_lock, flags);
  475. return 0;
  476. }
  477. static int snd_ad1848_capture_hw_params(struct snd_pcm_substream *substream,
  478. struct snd_pcm_hw_params *hw_params)
  479. {
  480. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  481. unsigned long flags;
  482. int err;
  483. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  484. return err;
  485. snd_ad1848_calibrate_mute(chip, 1);
  486. snd_ad1848_set_data_format(chip, hw_params);
  487. snd_ad1848_mce_up(chip);
  488. spin_lock_irqsave(&chip->reg_lock, flags);
  489. snd_ad1848_out(chip, AD1848_DATA_FORMAT, chip->image[AD1848_DATA_FORMAT]);
  490. spin_unlock_irqrestore(&chip->reg_lock, flags);
  491. snd_ad1848_mce_down(chip);
  492. snd_ad1848_calibrate_mute(chip, 0);
  493. return 0;
  494. }
  495. static int snd_ad1848_capture_hw_free(struct snd_pcm_substream *substream)
  496. {
  497. return snd_pcm_lib_free_pages(substream);
  498. }
  499. static int snd_ad1848_capture_prepare(struct snd_pcm_substream *substream)
  500. {
  501. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  502. struct snd_pcm_runtime *runtime = substream->runtime;
  503. unsigned long flags;
  504. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  505. unsigned int count = snd_pcm_lib_period_bytes(substream);
  506. chip->dma_size = size;
  507. chip->image[AD1848_IFACE_CTRL] &= ~(AD1848_CAPTURE_ENABLE | AD1848_CAPTURE_PIO);
  508. snd_dma_program(chip->dma, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
  509. count = snd_ad1848_get_count(chip->image[AD1848_DATA_FORMAT], count) - 1;
  510. spin_lock_irqsave(&chip->reg_lock, flags);
  511. snd_ad1848_out(chip, AD1848_DATA_LWR_CNT, (unsigned char) count);
  512. snd_ad1848_out(chip, AD1848_DATA_UPR_CNT, (unsigned char) (count >> 8));
  513. spin_unlock_irqrestore(&chip->reg_lock, flags);
  514. return 0;
  515. }
  516. static irqreturn_t snd_ad1848_interrupt(int irq, void *dev_id, struct pt_regs *regs)
  517. {
  518. struct snd_ad1848 *chip = dev_id;
  519. if ((chip->mode & AD1848_MODE_PLAY) && chip->playback_substream &&
  520. (chip->mode & AD1848_MODE_RUNNING))
  521. snd_pcm_period_elapsed(chip->playback_substream);
  522. if ((chip->mode & AD1848_MODE_CAPTURE) && chip->capture_substream &&
  523. (chip->mode & AD1848_MODE_RUNNING))
  524. snd_pcm_period_elapsed(chip->capture_substream);
  525. outb(0, AD1848P(chip, STATUS)); /* clear global interrupt bit */
  526. return IRQ_HANDLED;
  527. }
  528. static snd_pcm_uframes_t snd_ad1848_playback_pointer(struct snd_pcm_substream *substream)
  529. {
  530. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  531. size_t ptr;
  532. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_PLAYBACK_ENABLE))
  533. return 0;
  534. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  535. return bytes_to_frames(substream->runtime, ptr);
  536. }
  537. static snd_pcm_uframes_t snd_ad1848_capture_pointer(struct snd_pcm_substream *substream)
  538. {
  539. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  540. size_t ptr;
  541. if (!(chip->image[AD1848_IFACE_CTRL] & AD1848_CAPTURE_ENABLE))
  542. return 0;
  543. ptr = snd_dma_pointer(chip->dma, chip->dma_size);
  544. return bytes_to_frames(substream->runtime, ptr);
  545. }
  546. /*
  547. */
  548. static void snd_ad1848_thinkpad_twiddle(struct snd_ad1848 *chip, int on) {
  549. int tmp;
  550. if (!chip->thinkpad_flag) return;
  551. outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
  552. tmp = inb(AD1848_THINKPAD_CTL_PORT2);
  553. if (on)
  554. /* turn it on */
  555. tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
  556. else
  557. /* turn it off */
  558. tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
  559. outb(tmp, AD1848_THINKPAD_CTL_PORT2);
  560. }
  561. #ifdef CONFIG_PM
  562. static void snd_ad1848_suspend(struct snd_ad1848 *chip)
  563. {
  564. snd_pcm_suspend_all(chip->pcm);
  565. if (chip->thinkpad_flag)
  566. snd_ad1848_thinkpad_twiddle(chip, 0);
  567. }
  568. static void snd_ad1848_resume(struct snd_ad1848 *chip)
  569. {
  570. int i;
  571. if (chip->thinkpad_flag)
  572. snd_ad1848_thinkpad_twiddle(chip, 1);
  573. /* clear any pendings IRQ */
  574. inb(AD1848P(chip, STATUS));
  575. outb(0, AD1848P(chip, STATUS));
  576. mb();
  577. snd_ad1848_mce_down(chip);
  578. for (i = 0; i < 16; i++)
  579. snd_ad1848_out(chip, i, chip->image[i]);
  580. snd_ad1848_mce_up(chip);
  581. snd_ad1848_mce_down(chip);
  582. }
  583. #endif /* CONFIG_PM */
  584. static int snd_ad1848_probe(struct snd_ad1848 * chip)
  585. {
  586. unsigned long flags;
  587. int i, id, rev, ad1847;
  588. unsigned char *ptr;
  589. #if 0
  590. snd_ad1848_debug(chip);
  591. #endif
  592. id = ad1847 = 0;
  593. for (i = 0; i < 1000; i++) {
  594. mb();
  595. if (inb(AD1848P(chip, REGSEL)) & AD1848_INIT)
  596. udelay(500);
  597. else {
  598. spin_lock_irqsave(&chip->reg_lock, flags);
  599. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  600. snd_ad1848_out(chip, AD1848_LEFT_INPUT, 0xaa);
  601. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, 0x45);
  602. rev = snd_ad1848_in(chip, AD1848_RIGHT_INPUT);
  603. if (rev == 0x65) {
  604. spin_unlock_irqrestore(&chip->reg_lock, flags);
  605. id = 1;
  606. ad1847 = 1;
  607. break;
  608. }
  609. if (snd_ad1848_in(chip, AD1848_LEFT_INPUT) == 0xaa && rev == 0x45) {
  610. spin_unlock_irqrestore(&chip->reg_lock, flags);
  611. id = 1;
  612. break;
  613. }
  614. spin_unlock_irqrestore(&chip->reg_lock, flags);
  615. }
  616. }
  617. if (id != 1)
  618. return -ENODEV; /* no valid device found */
  619. if (chip->hardware == AD1848_HW_DETECT) {
  620. if (ad1847) {
  621. chip->hardware = AD1848_HW_AD1847;
  622. } else {
  623. chip->hardware = AD1848_HW_AD1848;
  624. rev = snd_ad1848_in(chip, AD1848_MISC_INFO);
  625. if (rev & 0x80) {
  626. chip->hardware = AD1848_HW_CS4248;
  627. } else if ((rev & 0x0f) == 0x0a) {
  628. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x40);
  629. for (i = 0; i < 16; ++i) {
  630. if (snd_ad1848_in(chip, i) != snd_ad1848_in(chip, i + 16)) {
  631. chip->hardware = AD1848_HW_CMI8330;
  632. break;
  633. }
  634. }
  635. snd_ad1848_out(chip, AD1848_MISC_INFO, 0x00);
  636. }
  637. }
  638. }
  639. spin_lock_irqsave(&chip->reg_lock, flags);
  640. inb(AD1848P(chip, STATUS)); /* clear any pendings IRQ */
  641. outb(0, AD1848P(chip, STATUS));
  642. mb();
  643. spin_unlock_irqrestore(&chip->reg_lock, flags);
  644. chip->image[AD1848_MISC_INFO] = 0x00;
  645. chip->image[AD1848_IFACE_CTRL] =
  646. (chip->image[AD1848_IFACE_CTRL] & ~AD1848_SINGLE_DMA) | AD1848_SINGLE_DMA;
  647. ptr = (unsigned char *) &chip->image;
  648. snd_ad1848_mce_down(chip);
  649. spin_lock_irqsave(&chip->reg_lock, flags);
  650. for (i = 0; i < 16; i++) /* ok.. fill all AD1848 registers */
  651. snd_ad1848_out(chip, i, *ptr++);
  652. spin_unlock_irqrestore(&chip->reg_lock, flags);
  653. snd_ad1848_mce_up(chip);
  654. snd_ad1848_mce_down(chip);
  655. return 0; /* all things are ok.. */
  656. }
  657. /*
  658. */
  659. static struct snd_pcm_hardware snd_ad1848_playback =
  660. {
  661. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  662. SNDRV_PCM_INFO_MMAP_VALID),
  663. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  664. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  665. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  666. .rate_min = 5510,
  667. .rate_max = 48000,
  668. .channels_min = 1,
  669. .channels_max = 2,
  670. .buffer_bytes_max = (128*1024),
  671. .period_bytes_min = 64,
  672. .period_bytes_max = (128*1024),
  673. .periods_min = 1,
  674. .periods_max = 1024,
  675. .fifo_size = 0,
  676. };
  677. static struct snd_pcm_hardware snd_ad1848_capture =
  678. {
  679. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  680. SNDRV_PCM_INFO_MMAP_VALID),
  681. .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW |
  682. SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE),
  683. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  684. .rate_min = 5510,
  685. .rate_max = 48000,
  686. .channels_min = 1,
  687. .channels_max = 2,
  688. .buffer_bytes_max = (128*1024),
  689. .period_bytes_min = 64,
  690. .period_bytes_max = (128*1024),
  691. .periods_min = 1,
  692. .periods_max = 1024,
  693. .fifo_size = 0,
  694. };
  695. /*
  696. */
  697. static int snd_ad1848_playback_open(struct snd_pcm_substream *substream)
  698. {
  699. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  700. struct snd_pcm_runtime *runtime = substream->runtime;
  701. int err;
  702. if ((err = snd_ad1848_open(chip, AD1848_MODE_PLAY)) < 0)
  703. return err;
  704. chip->playback_substream = substream;
  705. runtime->hw = snd_ad1848_playback;
  706. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  707. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  708. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  709. return 0;
  710. }
  711. static int snd_ad1848_capture_open(struct snd_pcm_substream *substream)
  712. {
  713. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  714. struct snd_pcm_runtime *runtime = substream->runtime;
  715. int err;
  716. if ((err = snd_ad1848_open(chip, AD1848_MODE_CAPTURE)) < 0)
  717. return err;
  718. chip->capture_substream = substream;
  719. runtime->hw = snd_ad1848_capture;
  720. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.buffer_bytes_max);
  721. snd_pcm_limit_isa_dma_size(chip->dma, &runtime->hw.period_bytes_max);
  722. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  723. return 0;
  724. }
  725. static int snd_ad1848_playback_close(struct snd_pcm_substream *substream)
  726. {
  727. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  728. chip->mode &= ~AD1848_MODE_PLAY;
  729. chip->playback_substream = NULL;
  730. snd_ad1848_close(chip);
  731. return 0;
  732. }
  733. static int snd_ad1848_capture_close(struct snd_pcm_substream *substream)
  734. {
  735. struct snd_ad1848 *chip = snd_pcm_substream_chip(substream);
  736. chip->mode &= ~AD1848_MODE_CAPTURE;
  737. chip->capture_substream = NULL;
  738. snd_ad1848_close(chip);
  739. return 0;
  740. }
  741. static int snd_ad1848_free(struct snd_ad1848 *chip)
  742. {
  743. release_and_free_resource(chip->res_port);
  744. if (chip->irq >= 0)
  745. free_irq(chip->irq, (void *) chip);
  746. if (chip->dma >= 0) {
  747. snd_dma_disable(chip->dma);
  748. free_dma(chip->dma);
  749. }
  750. kfree(chip);
  751. return 0;
  752. }
  753. static int snd_ad1848_dev_free(struct snd_device *device)
  754. {
  755. struct snd_ad1848 *chip = device->device_data;
  756. return snd_ad1848_free(chip);
  757. }
  758. static const char *snd_ad1848_chip_id(struct snd_ad1848 *chip)
  759. {
  760. switch (chip->hardware) {
  761. case AD1848_HW_AD1847: return "AD1847";
  762. case AD1848_HW_AD1848: return "AD1848";
  763. case AD1848_HW_CS4248: return "CS4248";
  764. case AD1848_HW_CMI8330: return "CMI8330/C3D";
  765. default: return "???";
  766. }
  767. }
  768. int snd_ad1848_create(struct snd_card *card,
  769. unsigned long port,
  770. int irq, int dma,
  771. unsigned short hardware,
  772. struct snd_ad1848 ** rchip)
  773. {
  774. static struct snd_device_ops ops = {
  775. .dev_free = snd_ad1848_dev_free,
  776. };
  777. struct snd_ad1848 *chip;
  778. int err;
  779. *rchip = NULL;
  780. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  781. if (chip == NULL)
  782. return -ENOMEM;
  783. spin_lock_init(&chip->reg_lock);
  784. mutex_init(&chip->open_mutex);
  785. chip->card = card;
  786. chip->port = port;
  787. chip->irq = -1;
  788. chip->dma = -1;
  789. chip->hardware = hardware;
  790. memcpy(&chip->image, &snd_ad1848_original_image, sizeof(snd_ad1848_original_image));
  791. if ((chip->res_port = request_region(port, 4, "AD1848")) == NULL) {
  792. snd_printk(KERN_ERR "ad1848: can't grab port 0x%lx\n", port);
  793. snd_ad1848_free(chip);
  794. return -EBUSY;
  795. }
  796. if (request_irq(irq, snd_ad1848_interrupt, SA_INTERRUPT, "AD1848", (void *) chip)) {
  797. snd_printk(KERN_ERR "ad1848: can't grab IRQ %d\n", irq);
  798. snd_ad1848_free(chip);
  799. return -EBUSY;
  800. }
  801. chip->irq = irq;
  802. if (request_dma(dma, "AD1848")) {
  803. snd_printk(KERN_ERR "ad1848: can't grab DMA %d\n", dma);
  804. snd_ad1848_free(chip);
  805. return -EBUSY;
  806. }
  807. chip->dma = dma;
  808. if (hardware == AD1848_HW_THINKPAD) {
  809. chip->thinkpad_flag = 1;
  810. chip->hardware = AD1848_HW_DETECT; /* reset */
  811. snd_ad1848_thinkpad_twiddle(chip, 1);
  812. }
  813. if (snd_ad1848_probe(chip) < 0) {
  814. snd_ad1848_free(chip);
  815. return -ENODEV;
  816. }
  817. /* Register device */
  818. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  819. snd_ad1848_free(chip);
  820. return err;
  821. }
  822. #ifdef CONFIG_PM
  823. chip->suspend = snd_ad1848_suspend;
  824. chip->resume = snd_ad1848_resume;
  825. #endif
  826. *rchip = chip;
  827. return 0;
  828. }
  829. static struct snd_pcm_ops snd_ad1848_playback_ops = {
  830. .open = snd_ad1848_playback_open,
  831. .close = snd_ad1848_playback_close,
  832. .ioctl = snd_ad1848_ioctl,
  833. .hw_params = snd_ad1848_playback_hw_params,
  834. .hw_free = snd_ad1848_playback_hw_free,
  835. .prepare = snd_ad1848_playback_prepare,
  836. .trigger = snd_ad1848_playback_trigger,
  837. .pointer = snd_ad1848_playback_pointer,
  838. };
  839. static struct snd_pcm_ops snd_ad1848_capture_ops = {
  840. .open = snd_ad1848_capture_open,
  841. .close = snd_ad1848_capture_close,
  842. .ioctl = snd_ad1848_ioctl,
  843. .hw_params = snd_ad1848_capture_hw_params,
  844. .hw_free = snd_ad1848_capture_hw_free,
  845. .prepare = snd_ad1848_capture_prepare,
  846. .trigger = snd_ad1848_capture_trigger,
  847. .pointer = snd_ad1848_capture_pointer,
  848. };
  849. int snd_ad1848_pcm(struct snd_ad1848 *chip, int device, struct snd_pcm **rpcm)
  850. {
  851. struct snd_pcm *pcm;
  852. int err;
  853. if ((err = snd_pcm_new(chip->card, "AD1848", device, 1, 1, &pcm)) < 0)
  854. return err;
  855. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ad1848_playback_ops);
  856. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ad1848_capture_ops);
  857. pcm->private_data = chip;
  858. pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  859. strcpy(pcm->name, snd_ad1848_chip_id(chip));
  860. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  861. snd_dma_isa_data(),
  862. 64*1024, chip->dma > 3 ? 128*1024 : 64*1024);
  863. chip->pcm = pcm;
  864. if (rpcm)
  865. *rpcm = pcm;
  866. return 0;
  867. }
  868. const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction)
  869. {
  870. return direction == SNDRV_PCM_STREAM_PLAYBACK ?
  871. &snd_ad1848_playback_ops : &snd_ad1848_capture_ops;
  872. }
  873. /*
  874. * MIXER part
  875. */
  876. static int snd_ad1848_info_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  877. {
  878. static char *texts[4] = {
  879. "Line", "Aux", "Mic", "Mix"
  880. };
  881. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  882. uinfo->count = 2;
  883. uinfo->value.enumerated.items = 4;
  884. if (uinfo->value.enumerated.item > 3)
  885. uinfo->value.enumerated.item = 3;
  886. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  887. return 0;
  888. }
  889. static int snd_ad1848_get_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  890. {
  891. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  892. unsigned long flags;
  893. spin_lock_irqsave(&chip->reg_lock, flags);
  894. ucontrol->value.enumerated.item[0] = (chip->image[AD1848_LEFT_INPUT] & AD1848_MIXS_ALL) >> 6;
  895. ucontrol->value.enumerated.item[1] = (chip->image[AD1848_RIGHT_INPUT] & AD1848_MIXS_ALL) >> 6;
  896. spin_unlock_irqrestore(&chip->reg_lock, flags);
  897. return 0;
  898. }
  899. static int snd_ad1848_put_mux(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  900. {
  901. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  902. unsigned long flags;
  903. unsigned short left, right;
  904. int change;
  905. if (ucontrol->value.enumerated.item[0] > 3 ||
  906. ucontrol->value.enumerated.item[1] > 3)
  907. return -EINVAL;
  908. left = ucontrol->value.enumerated.item[0] << 6;
  909. right = ucontrol->value.enumerated.item[1] << 6;
  910. spin_lock_irqsave(&chip->reg_lock, flags);
  911. left = (chip->image[AD1848_LEFT_INPUT] & ~AD1848_MIXS_ALL) | left;
  912. right = (chip->image[AD1848_RIGHT_INPUT] & ~AD1848_MIXS_ALL) | right;
  913. change = left != chip->image[AD1848_LEFT_INPUT] ||
  914. right != chip->image[AD1848_RIGHT_INPUT];
  915. snd_ad1848_out(chip, AD1848_LEFT_INPUT, left);
  916. snd_ad1848_out(chip, AD1848_RIGHT_INPUT, right);
  917. spin_unlock_irqrestore(&chip->reg_lock, flags);
  918. return change;
  919. }
  920. static int snd_ad1848_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  921. {
  922. int mask = (kcontrol->private_value >> 16) & 0xff;
  923. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  924. uinfo->count = 1;
  925. uinfo->value.integer.min = 0;
  926. uinfo->value.integer.max = mask;
  927. return 0;
  928. }
  929. static int snd_ad1848_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  930. {
  931. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  932. unsigned long flags;
  933. int reg = kcontrol->private_value & 0xff;
  934. int shift = (kcontrol->private_value >> 8) & 0xff;
  935. int mask = (kcontrol->private_value >> 16) & 0xff;
  936. int invert = (kcontrol->private_value >> 24) & 0xff;
  937. spin_lock_irqsave(&chip->reg_lock, flags);
  938. ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
  939. spin_unlock_irqrestore(&chip->reg_lock, flags);
  940. if (invert)
  941. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  942. return 0;
  943. }
  944. static int snd_ad1848_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  945. {
  946. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  947. unsigned long flags;
  948. int reg = kcontrol->private_value & 0xff;
  949. int shift = (kcontrol->private_value >> 8) & 0xff;
  950. int mask = (kcontrol->private_value >> 16) & 0xff;
  951. int invert = (kcontrol->private_value >> 24) & 0xff;
  952. int change;
  953. unsigned short val;
  954. val = (ucontrol->value.integer.value[0] & mask);
  955. if (invert)
  956. val = mask - val;
  957. val <<= shift;
  958. spin_lock_irqsave(&chip->reg_lock, flags);
  959. val = (chip->image[reg] & ~(mask << shift)) | val;
  960. change = val != chip->image[reg];
  961. snd_ad1848_out(chip, reg, val);
  962. spin_unlock_irqrestore(&chip->reg_lock, flags);
  963. return change;
  964. }
  965. static int snd_ad1848_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  966. {
  967. int mask = (kcontrol->private_value >> 24) & 0xff;
  968. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  969. uinfo->count = 2;
  970. uinfo->value.integer.min = 0;
  971. uinfo->value.integer.max = mask;
  972. return 0;
  973. }
  974. static int snd_ad1848_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  975. {
  976. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  977. unsigned long flags;
  978. int left_reg = kcontrol->private_value & 0xff;
  979. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  980. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  981. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  982. int mask = (kcontrol->private_value >> 24) & 0xff;
  983. int invert = (kcontrol->private_value >> 22) & 1;
  984. spin_lock_irqsave(&chip->reg_lock, flags);
  985. ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
  986. ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
  987. spin_unlock_irqrestore(&chip->reg_lock, flags);
  988. if (invert) {
  989. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  990. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  991. }
  992. return 0;
  993. }
  994. static int snd_ad1848_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  995. {
  996. struct snd_ad1848 *chip = snd_kcontrol_chip(kcontrol);
  997. unsigned long flags;
  998. int left_reg = kcontrol->private_value & 0xff;
  999. int right_reg = (kcontrol->private_value >> 8) & 0xff;
  1000. int shift_left = (kcontrol->private_value >> 16) & 0x07;
  1001. int shift_right = (kcontrol->private_value >> 19) & 0x07;
  1002. int mask = (kcontrol->private_value >> 24) & 0xff;
  1003. int invert = (kcontrol->private_value >> 22) & 1;
  1004. int change;
  1005. unsigned short val1, val2;
  1006. val1 = ucontrol->value.integer.value[0] & mask;
  1007. val2 = ucontrol->value.integer.value[1] & mask;
  1008. if (invert) {
  1009. val1 = mask - val1;
  1010. val2 = mask - val2;
  1011. }
  1012. val1 <<= shift_left;
  1013. val2 <<= shift_right;
  1014. spin_lock_irqsave(&chip->reg_lock, flags);
  1015. if (left_reg != right_reg) {
  1016. val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
  1017. val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
  1018. change = val1 != chip->image[left_reg] || val2 != chip->image[right_reg];
  1019. snd_ad1848_out(chip, left_reg, val1);
  1020. snd_ad1848_out(chip, right_reg, val2);
  1021. } else {
  1022. val1 = (chip->image[left_reg] & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1023. change = val1 != chip->image[left_reg];
  1024. snd_ad1848_out(chip, left_reg, val1);
  1025. }
  1026. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1027. return change;
  1028. }
  1029. /*
  1030. */
  1031. int snd_ad1848_add_ctl(struct snd_ad1848 *chip, const char *name, int index, int type, unsigned long value)
  1032. {
  1033. static struct snd_kcontrol_new newctls[] = {
  1034. [AD1848_MIX_SINGLE] = {
  1035. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1036. .info = snd_ad1848_info_single,
  1037. .get = snd_ad1848_get_single,
  1038. .put = snd_ad1848_put_single,
  1039. },
  1040. [AD1848_MIX_DOUBLE] = {
  1041. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1042. .info = snd_ad1848_info_double,
  1043. .get = snd_ad1848_get_double,
  1044. .put = snd_ad1848_put_double,
  1045. },
  1046. [AD1848_MIX_CAPTURE] = {
  1047. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1048. .info = snd_ad1848_info_mux,
  1049. .get = snd_ad1848_get_mux,
  1050. .put = snd_ad1848_put_mux,
  1051. },
  1052. };
  1053. struct snd_kcontrol *ctl;
  1054. int err;
  1055. ctl = snd_ctl_new1(&newctls[type], chip);
  1056. if (! ctl)
  1057. return -ENOMEM;
  1058. strlcpy(ctl->id.name, name, sizeof(ctl->id.name));
  1059. ctl->id.index = index;
  1060. ctl->private_value = value;
  1061. if ((err = snd_ctl_add(chip->card, ctl)) < 0)
  1062. return err;
  1063. return 0;
  1064. }
  1065. static struct ad1848_mix_elem snd_ad1848_controls[] = {
  1066. AD1848_DOUBLE("PCM Playback Switch", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 7, 7, 1, 1),
  1067. AD1848_DOUBLE("PCM Playback Volume", 0, AD1848_LEFT_OUTPUT, AD1848_RIGHT_OUTPUT, 0, 0, 63, 1),
  1068. AD1848_DOUBLE("Aux Playback Switch", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
  1069. AD1848_DOUBLE("Aux Playback Volume", 0, AD1848_AUX1_LEFT_INPUT, AD1848_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
  1070. AD1848_DOUBLE("Aux Playback Switch", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
  1071. AD1848_DOUBLE("Aux Playback Volume", 1, AD1848_AUX2_LEFT_INPUT, AD1848_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
  1072. AD1848_DOUBLE("Capture Volume", 0, AD1848_LEFT_INPUT, AD1848_RIGHT_INPUT, 0, 0, 15, 0),
  1073. {
  1074. .name = "Capture Source",
  1075. .type = AD1848_MIX_CAPTURE,
  1076. },
  1077. AD1848_SINGLE("Loopback Capture Switch", 0, AD1848_LOOPBACK, 0, 1, 0),
  1078. AD1848_SINGLE("Loopback Capture Volume", 0, AD1848_LOOPBACK, 1, 63, 0)
  1079. };
  1080. int snd_ad1848_mixer(struct snd_ad1848 *chip)
  1081. {
  1082. struct snd_card *card;
  1083. struct snd_pcm *pcm;
  1084. unsigned int idx;
  1085. int err;
  1086. snd_assert(chip != NULL && chip->pcm != NULL, return -EINVAL);
  1087. pcm = chip->pcm;
  1088. card = chip->card;
  1089. strcpy(card->mixername, pcm->name);
  1090. for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++)
  1091. if ((err = snd_ad1848_add_ctl_elem(chip, &snd_ad1848_controls[idx])) < 0)
  1092. return err;
  1093. return 0;
  1094. }
  1095. EXPORT_SYMBOL(snd_ad1848_out);
  1096. EXPORT_SYMBOL(snd_ad1848_create);
  1097. EXPORT_SYMBOL(snd_ad1848_pcm);
  1098. EXPORT_SYMBOL(snd_ad1848_get_pcm_ops);
  1099. EXPORT_SYMBOL(snd_ad1848_mixer);
  1100. EXPORT_SYMBOL(snd_ad1848_add_ctl);
  1101. /*
  1102. * INIT part
  1103. */
  1104. static int __init alsa_ad1848_init(void)
  1105. {
  1106. return 0;
  1107. }
  1108. static void __exit alsa_ad1848_exit(void)
  1109. {
  1110. }
  1111. module_init(alsa_ad1848_init)
  1112. module_exit(alsa_ad1848_exit)