spu_csa.h 6.7 KB

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  1. /*
  2. * spu_csa.h: Definitions for SPU context save area (CSA).
  3. *
  4. * (C) Copyright IBM 2005
  5. *
  6. * Author: Mark Nutter <mnutter@us.ibm.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #ifndef _SPU_CSA_H_
  23. #define _SPU_CSA_H_
  24. #ifdef __KERNEL__
  25. /*
  26. * Total number of 128-bit registers.
  27. */
  28. #define NR_SPU_GPRS 128
  29. #define NR_SPU_SPRS 9
  30. #define NR_SPU_REGS_PAD 7
  31. #define NR_SPU_SPILL_REGS 144 /* GPRS + SPRS + PAD */
  32. #define SIZEOF_SPU_SPILL_REGS NR_SPU_SPILL_REGS * 16
  33. #define SPU_SAVE_COMPLETE 0x3FFB
  34. #define SPU_RESTORE_COMPLETE 0x3FFC
  35. /*
  36. * Definitions for various 'stopped' status conditions,
  37. * to be recreated during context restore.
  38. */
  39. #define SPU_STOPPED_STATUS_P 1
  40. #define SPU_STOPPED_STATUS_I 2
  41. #define SPU_STOPPED_STATUS_H 3
  42. #define SPU_STOPPED_STATUS_S 4
  43. #define SPU_STOPPED_STATUS_S_I 5
  44. #define SPU_STOPPED_STATUS_S_P 6
  45. #define SPU_STOPPED_STATUS_P_H 7
  46. #define SPU_STOPPED_STATUS_P_I 8
  47. #define SPU_STOPPED_STATUS_R 9
  48. #ifndef __ASSEMBLY__
  49. /**
  50. * spu_reg128 - generic 128-bit register definition.
  51. */
  52. struct spu_reg128 {
  53. u32 slot[4];
  54. };
  55. /**
  56. * struct spu_lscsa - Local Store Context Save Area.
  57. * @gprs: Array of saved registers.
  58. * @fpcr: Saved floating point status control register.
  59. * @decr: Saved decrementer value.
  60. * @decr_status: Indicates decrementer run status.
  61. * @ppu_mb: Saved PPU mailbox data.
  62. * @ppuint_mb: Saved PPU interrupting mailbox data.
  63. * @tag_mask: Saved tag group mask.
  64. * @event_mask: Saved event mask.
  65. * @srr0: Saved SRR0.
  66. * @stopped_status: Conditions to be recreated by restore.
  67. * @ls: Saved contents of Local Storage Area.
  68. *
  69. * The LSCSA represents state that is primarily saved and
  70. * restored by SPU-side code.
  71. */
  72. struct spu_lscsa {
  73. struct spu_reg128 gprs[128];
  74. struct spu_reg128 fpcr;
  75. struct spu_reg128 decr;
  76. struct spu_reg128 decr_status;
  77. struct spu_reg128 ppu_mb;
  78. struct spu_reg128 ppuint_mb;
  79. struct spu_reg128 tag_mask;
  80. struct spu_reg128 event_mask;
  81. struct spu_reg128 srr0;
  82. struct spu_reg128 stopped_status;
  83. struct spu_reg128 pad[119]; /* 'ls' must be page-aligned. */
  84. unsigned char ls[LS_SIZE];
  85. };
  86. /*
  87. * struct spu_problem_collapsed - condensed problem state area, w/o pads.
  88. */
  89. struct spu_problem_collapsed {
  90. u64 spc_mssync_RW;
  91. u32 mfc_lsa_W;
  92. u32 unused_pad0;
  93. u64 mfc_ea_W;
  94. union mfc_tag_size_class_cmd mfc_union_W;
  95. u32 dma_qstatus_R;
  96. u32 dma_querytype_RW;
  97. u32 dma_querymask_RW;
  98. u32 dma_tagstatus_R;
  99. u32 pu_mb_R;
  100. u32 spu_mb_W;
  101. u32 mb_stat_R;
  102. u32 spu_runcntl_RW;
  103. u32 spu_status_R;
  104. u32 spu_spc_R;
  105. u32 spu_npc_RW;
  106. u32 signal_notify1;
  107. u32 signal_notify2;
  108. u32 unused_pad1;
  109. };
  110. /*
  111. * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
  112. */
  113. struct spu_priv1_collapsed {
  114. u64 mfc_sr1_RW;
  115. u64 mfc_lpid_RW;
  116. u64 spu_idr_RW;
  117. u64 mfc_vr_RO;
  118. u64 spu_vr_RO;
  119. u64 int_mask_class0_RW;
  120. u64 int_mask_class1_RW;
  121. u64 int_mask_class2_RW;
  122. u64 int_stat_class0_RW;
  123. u64 int_stat_class1_RW;
  124. u64 int_stat_class2_RW;
  125. u64 int_route_RW;
  126. u64 mfc_atomic_flush_RW;
  127. u64 resource_allocation_groupID_RW;
  128. u64 resource_allocation_enable_RW;
  129. u64 mfc_fir_R;
  130. u64 mfc_fir_status_or_W;
  131. u64 mfc_fir_status_and_W;
  132. u64 mfc_fir_mask_R;
  133. u64 mfc_fir_mask_or_W;
  134. u64 mfc_fir_mask_and_W;
  135. u64 mfc_fir_chkstp_enable_RW;
  136. u64 smf_sbi_signal_sel;
  137. u64 smf_ato_signal_sel;
  138. u64 mfc_sdr_RW;
  139. u64 tlb_index_hint_RO;
  140. u64 tlb_index_W;
  141. u64 tlb_vpn_RW;
  142. u64 tlb_rpn_RW;
  143. u64 tlb_invalidate_entry_W;
  144. u64 tlb_invalidate_all_W;
  145. u64 smm_hid;
  146. u64 mfc_accr_RW;
  147. u64 mfc_dsisr_RW;
  148. u64 mfc_dar_RW;
  149. u64 rmt_index_RW;
  150. u64 rmt_data1_RW;
  151. u64 mfc_dsir_R;
  152. u64 mfc_lsacr_RW;
  153. u64 mfc_lscrr_R;
  154. u64 mfc_tclass_id_RW;
  155. u64 mfc_rm_boundary;
  156. u64 smf_dma_signal_sel;
  157. u64 smm_signal_sel;
  158. u64 mfc_cer_R;
  159. u64 pu_ecc_cntl_RW;
  160. u64 pu_ecc_stat_RW;
  161. u64 spu_ecc_addr_RW;
  162. u64 spu_err_mask_RW;
  163. u64 spu_trig0_sel;
  164. u64 spu_trig1_sel;
  165. u64 spu_trig2_sel;
  166. u64 spu_trig3_sel;
  167. u64 spu_trace_sel;
  168. u64 spu_event0_sel;
  169. u64 spu_event1_sel;
  170. u64 spu_event2_sel;
  171. u64 spu_event3_sel;
  172. u64 spu_trace_cntl;
  173. };
  174. /*
  175. * struct spu_priv2_collapsed - condensed priviliged 2 area, w/o pads.
  176. */
  177. struct spu_priv2_collapsed {
  178. u64 slb_index_W;
  179. u64 slb_esid_RW;
  180. u64 slb_vsid_RW;
  181. u64 slb_invalidate_entry_W;
  182. u64 slb_invalidate_all_W;
  183. struct mfc_cq_sr spuq[16];
  184. struct mfc_cq_sr puq[8];
  185. u64 mfc_control_RW;
  186. u64 puint_mb_R;
  187. u64 spu_privcntl_RW;
  188. u64 spu_lslr_RW;
  189. u64 spu_chnlcntptr_RW;
  190. u64 spu_chnlcnt_RW;
  191. u64 spu_chnldata_RW;
  192. u64 spu_cfg_RW;
  193. u64 spu_tag_status_query_RW;
  194. u64 spu_cmd_buf1_RW;
  195. u64 spu_cmd_buf2_RW;
  196. u64 spu_atomic_status_RW;
  197. };
  198. /**
  199. * struct spu_state
  200. * @lscsa: Local Store Context Save Area.
  201. * @prob: Collapsed Problem State Area, w/o pads.
  202. * @priv1: Collapsed Privileged 1 Area, w/o pads.
  203. * @priv2: Collapsed Privileged 2 Area, w/o pads.
  204. * @spu_chnlcnt_RW: Array of saved channel counts.
  205. * @spu_chnldata_RW: Array of saved channel data.
  206. * @suspend_time: Time stamp when decrementer disabled.
  207. * @slb_esid_RW: Array of saved SLB esid entries.
  208. * @slb_vsid_RW: Array of saved SLB vsid entries.
  209. *
  210. * Structure representing the whole of the SPU
  211. * context save area (CSA). This struct contains
  212. * all of the state necessary to suspend and then
  213. * later optionally resume execution of an SPU
  214. * context.
  215. *
  216. * The @lscsa region is by far the largest, and is
  217. * allocated separately so that it may either be
  218. * pinned or mapped to/from application memory, as
  219. * appropriate for the OS environment.
  220. */
  221. struct spu_state {
  222. struct spu_lscsa *lscsa;
  223. struct spu_problem_collapsed prob;
  224. struct spu_priv1_collapsed priv1;
  225. struct spu_priv2_collapsed priv2;
  226. u64 spu_chnlcnt_RW[32];
  227. u64 spu_chnldata_RW[32];
  228. u32 spu_mailbox_data[4];
  229. u32 pu_mailbox_data[1];
  230. unsigned long suspend_time;
  231. u64 slb_esid_RW[8];
  232. u64 slb_vsid_RW[8];
  233. spinlock_t register_lock;
  234. };
  235. extern void spu_init_csa(struct spu_state *csa);
  236. extern void spu_fini_csa(struct spu_state *csa);
  237. extern int spu_save(struct spu_state *prev, struct spu *spu);
  238. extern int spu_restore(struct spu_state *new, struct spu *spu);
  239. extern int spu_switch(struct spu_state *prev, struct spu_state *new,
  240. struct spu *spu);
  241. #endif /* __KERNEL__ */
  242. #endif /* !__ASSEMBLY__ */
  243. #endif /* _SPU_CSA_H_ */