controlfb.c 27 KB

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  1. /*
  2. * controlfb.c -- frame buffer device for the PowerMac 'control' display
  3. *
  4. * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
  5. * Copyright (C) 1998 Dan Jacobowitz
  6. * Copyright (C) 2001 Takashi Oe
  7. *
  8. * Mmap code by Michel Lanners <mlan@cpu.lu>
  9. *
  10. * Frame buffer structure from:
  11. * drivers/video/chipsfb.c -- frame buffer device for
  12. * Chips & Technologies 65550 chip.
  13. *
  14. * Copyright (C) 1998 Paul Mackerras
  15. *
  16. * This file is derived from the Powermac "chips" driver:
  17. * Copyright (C) 1997 Fabio Riccardi.
  18. * And from the frame buffer device for Open Firmware-initialized devices:
  19. * Copyright (C) 1997 Geert Uytterhoeven.
  20. *
  21. * Hardware information from:
  22. * control.c: Console support for PowerMac "control" display adaptor.
  23. * Copyright (C) 1996 Paul Mackerras
  24. *
  25. * Updated to 2.5 framebuffer API by Ben Herrenschmidt
  26. * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
  27. * and James Simmons <jsimmons@infradead.org>.
  28. *
  29. * This file is subject to the terms and conditions of the GNU General Public
  30. * License. See the file COPYING in the main directory of this archive for
  31. * more details.
  32. */
  33. #include <linux/config.h>
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/errno.h>
  37. #include <linux/string.h>
  38. #include <linux/mm.h>
  39. #include <linux/tty.h>
  40. #include <linux/slab.h>
  41. #include <linux/vmalloc.h>
  42. #include <linux/delay.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/fb.h>
  45. #include <linux/init.h>
  46. #include <linux/pci.h>
  47. #include <linux/nvram.h>
  48. #include <linux/adb.h>
  49. #include <linux/cuda.h>
  50. #include <asm/io.h>
  51. #include <asm/prom.h>
  52. #include <asm/pgtable.h>
  53. #include <asm/btext.h>
  54. #include "macmodes.h"
  55. #include "controlfb.h"
  56. struct fb_par_control {
  57. int vmode, cmode;
  58. int xres, yres;
  59. int vxres, vyres;
  60. int xoffset, yoffset;
  61. int pitch;
  62. struct control_regvals regvals;
  63. unsigned long sync;
  64. unsigned char ctrl;
  65. };
  66. #define DIRTY(z) ((x)->z != (y)->z)
  67. #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
  68. static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
  69. {
  70. int i, results;
  71. results = 1;
  72. for (i = 0; i < 3; i++)
  73. results &= !DIRTY(regvals.clock_params[i]);
  74. if (!results)
  75. return 0;
  76. for (i = 0; i < 16; i++)
  77. results &= !DIRTY(regvals.regs[i]);
  78. if (!results)
  79. return 0;
  80. return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
  81. && !DIRTY(vxres) && !DIRTY(vyres));
  82. }
  83. static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
  84. {
  85. return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
  86. && !DIRTY(yres) && !DIRTY(xres_virtual)
  87. && !DIRTY(yres_virtual)
  88. && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
  89. }
  90. struct fb_info_control {
  91. struct fb_info info;
  92. struct fb_par_control par;
  93. u32 pseudo_palette[17];
  94. struct cmap_regs __iomem *cmap_regs;
  95. unsigned long cmap_regs_phys;
  96. struct control_regs __iomem *control_regs;
  97. unsigned long control_regs_phys;
  98. unsigned long control_regs_size;
  99. __u8 __iomem *frame_buffer;
  100. unsigned long frame_buffer_phys;
  101. unsigned long fb_orig_base;
  102. unsigned long fb_orig_size;
  103. int control_use_bank2;
  104. unsigned long total_vram;
  105. unsigned char vram_attr;
  106. };
  107. /* control register access macro */
  108. #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
  109. /******************** Prototypes for exported functions ********************/
  110. /*
  111. * struct fb_ops
  112. */
  113. static int controlfb_pan_display(struct fb_var_screeninfo *var,
  114. struct fb_info *info);
  115. static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  116. u_int transp, struct fb_info *info);
  117. static int controlfb_blank(int blank_mode, struct fb_info *info);
  118. static int controlfb_mmap(struct fb_info *info,
  119. struct vm_area_struct *vma);
  120. static int controlfb_set_par (struct fb_info *info);
  121. static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info);
  122. /******************** Prototypes for internal functions **********************/
  123. static void set_control_clock(unsigned char *params);
  124. static int init_control(struct fb_info_control *p);
  125. static void control_set_hardware(struct fb_info_control *p,
  126. struct fb_par_control *par);
  127. static int control_of_init(struct device_node *dp);
  128. static void find_vram_size(struct fb_info_control *p);
  129. static int read_control_sense(struct fb_info_control *p);
  130. static int calc_clock_params(unsigned long clk, unsigned char *param);
  131. static int control_var_to_par(struct fb_var_screeninfo *var,
  132. struct fb_par_control *par, const struct fb_info *fb_info);
  133. static inline void control_par_to_var(struct fb_par_control *par,
  134. struct fb_var_screeninfo *var);
  135. static void control_init_info(struct fb_info *info, struct fb_info_control *p);
  136. static void control_cleanup(void);
  137. /************************** Internal variables *******************************/
  138. static struct fb_info_control *control_fb;
  139. static int default_vmode __initdata = VMODE_NVRAM;
  140. static int default_cmode __initdata = CMODE_NVRAM;
  141. static struct fb_ops controlfb_ops = {
  142. .owner = THIS_MODULE,
  143. .fb_check_var = controlfb_check_var,
  144. .fb_set_par = controlfb_set_par,
  145. .fb_setcolreg = controlfb_setcolreg,
  146. .fb_pan_display = controlfb_pan_display,
  147. .fb_blank = controlfb_blank,
  148. .fb_mmap = controlfb_mmap,
  149. .fb_fillrect = cfb_fillrect,
  150. .fb_copyarea = cfb_copyarea,
  151. .fb_imageblit = cfb_imageblit,
  152. };
  153. /******************** The functions for controlfb_ops ********************/
  154. #ifdef MODULE
  155. MODULE_LICENSE("GPL");
  156. int init_module(void)
  157. {
  158. struct device_node *dp;
  159. dp = find_devices("control");
  160. if (dp != 0 && !control_of_init(dp))
  161. return 0;
  162. return -ENXIO;
  163. }
  164. void cleanup_module(void)
  165. {
  166. control_cleanup();
  167. }
  168. #endif
  169. /*
  170. * Checks a var structure
  171. */
  172. static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
  173. {
  174. struct fb_par_control par;
  175. int err;
  176. err = control_var_to_par(var, &par, info);
  177. if (err)
  178. return err;
  179. control_par_to_var(&par, var);
  180. return 0;
  181. }
  182. /*
  183. * Applies current var to display
  184. */
  185. static int controlfb_set_par (struct fb_info *info)
  186. {
  187. struct fb_info_control *p = (struct fb_info_control *) info;
  188. struct fb_par_control par;
  189. int err;
  190. if((err = control_var_to_par(&info->var, &par, info))) {
  191. printk (KERN_ERR "controlfb_set_par: error calling"
  192. " control_var_to_par: %d.\n", err);
  193. return err;
  194. }
  195. control_set_hardware(p, &par);
  196. info->fix.visual = (p->par.cmode == CMODE_8) ?
  197. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
  198. info->fix.line_length = p->par.pitch;
  199. info->fix.xpanstep = 32 >> p->par.cmode;
  200. info->fix.ypanstep = 1;
  201. return 0;
  202. }
  203. /*
  204. * Set screen start address according to var offset values
  205. */
  206. static inline void set_screen_start(int xoffset, int yoffset,
  207. struct fb_info_control *p)
  208. {
  209. struct fb_par_control *par = &p->par;
  210. par->xoffset = xoffset;
  211. par->yoffset = yoffset;
  212. out_le32(CNTRL_REG(p,start_addr),
  213. par->yoffset * par->pitch + (par->xoffset << par->cmode));
  214. }
  215. static int controlfb_pan_display(struct fb_var_screeninfo *var,
  216. struct fb_info *info)
  217. {
  218. unsigned int xoffset, hstep;
  219. struct fb_info_control *p = (struct fb_info_control *)info;
  220. struct fb_par_control *par = &p->par;
  221. /*
  222. * make sure start addr will be 32-byte aligned
  223. */
  224. hstep = 0x1f >> par->cmode;
  225. xoffset = (var->xoffset + hstep) & ~hstep;
  226. if (xoffset+par->xres > par->vxres ||
  227. var->yoffset+par->yres > par->vyres)
  228. return -EINVAL;
  229. set_screen_start(xoffset, var->yoffset, p);
  230. return 0;
  231. }
  232. /*
  233. * Private mmap since we want to have a different caching on the framebuffer
  234. * for controlfb.
  235. * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
  236. */
  237. static int controlfb_mmap(struct fb_info *info,
  238. struct vm_area_struct *vma)
  239. {
  240. unsigned long off, start;
  241. u32 len;
  242. off = vma->vm_pgoff << PAGE_SHIFT;
  243. /* frame buffer memory */
  244. start = info->fix.smem_start;
  245. len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.smem_len);
  246. if (off >= len) {
  247. /* memory mapped io */
  248. off -= len;
  249. if (info->var.accel_flags)
  250. return -EINVAL;
  251. start = info->fix.mmio_start;
  252. len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.mmio_len);
  253. pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE|_PAGE_GUARDED;
  254. } else {
  255. /* framebuffer */
  256. pgprot_val(vma->vm_page_prot) |= _PAGE_WRITETHRU;
  257. }
  258. start &= PAGE_MASK;
  259. if ((vma->vm_end - vma->vm_start + off) > len)
  260. return -EINVAL;
  261. off += start;
  262. vma->vm_pgoff = off >> PAGE_SHIFT;
  263. if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
  264. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  265. return -EAGAIN;
  266. return 0;
  267. }
  268. static int controlfb_blank(int blank_mode, struct fb_info *info)
  269. {
  270. struct fb_info_control *p = (struct fb_info_control *) info;
  271. unsigned ctrl;
  272. ctrl = ld_le32(CNTRL_REG(p,ctrl));
  273. if (blank_mode > 0)
  274. switch (blank_mode) {
  275. case FB_BLANK_VSYNC_SUSPEND:
  276. ctrl &= ~3;
  277. break;
  278. case FB_BLANK_HSYNC_SUSPEND:
  279. ctrl &= ~0x30;
  280. break;
  281. case FB_BLANK_POWERDOWN:
  282. ctrl &= ~0x33;
  283. /* fall through */
  284. case FB_BLANK_NORMAL:
  285. ctrl |= 0x400;
  286. break;
  287. default:
  288. break;
  289. }
  290. else {
  291. ctrl &= ~0x400;
  292. ctrl |= 0x33;
  293. }
  294. out_le32(CNTRL_REG(p,ctrl), ctrl);
  295. return 0;
  296. }
  297. static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  298. u_int transp, struct fb_info *info)
  299. {
  300. struct fb_info_control *p = (struct fb_info_control *) info;
  301. __u8 r, g, b;
  302. if (regno > 255)
  303. return 1;
  304. r = red >> 8;
  305. g = green >> 8;
  306. b = blue >> 8;
  307. out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
  308. out_8(&p->cmap_regs->lut, r); /* send one color channel at */
  309. out_8(&p->cmap_regs->lut, g); /* a time... */
  310. out_8(&p->cmap_regs->lut, b);
  311. if (regno < 16) {
  312. int i;
  313. switch (p->par.cmode) {
  314. case CMODE_16:
  315. p->pseudo_palette[regno] =
  316. (regno << 10) | (regno << 5) | regno;
  317. break;
  318. case CMODE_32:
  319. i = (regno << 8) | regno;
  320. p->pseudo_palette[regno] = (i << 16) | i;
  321. break;
  322. }
  323. }
  324. return 0;
  325. }
  326. /******************** End of controlfb_ops implementation ******************/
  327. static void set_control_clock(unsigned char *params)
  328. {
  329. #ifdef CONFIG_ADB_CUDA
  330. struct adb_request req;
  331. int i;
  332. for (i = 0; i < 3; ++i) {
  333. cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
  334. 0x50, i + 1, params[i]);
  335. while (!req.complete)
  336. cuda_poll();
  337. }
  338. #endif
  339. }
  340. /*
  341. * finish off the driver initialization and register
  342. */
  343. static int __init init_control(struct fb_info_control *p)
  344. {
  345. int full, sense, vmode, cmode, vyres;
  346. struct fb_var_screeninfo var;
  347. int rc;
  348. printk(KERN_INFO "controlfb: ");
  349. full = p->total_vram == 0x400000;
  350. /* Try to pick a video mode out of NVRAM if we have one. */
  351. if (default_cmode == CMODE_NVRAM){
  352. cmode = nvram_read_byte(NV_CMODE);
  353. if(cmode < CMODE_8 || cmode > CMODE_32)
  354. cmode = CMODE_8;
  355. } else
  356. cmode=default_cmode;
  357. if (default_vmode == VMODE_NVRAM) {
  358. vmode = nvram_read_byte(NV_VMODE);
  359. if (vmode < 1 || vmode > VMODE_MAX ||
  360. control_mac_modes[vmode - 1].m[full] < cmode) {
  361. sense = read_control_sense(p);
  362. printk("Monitor sense value = 0x%x, ", sense);
  363. vmode = mac_map_monitor_sense(sense);
  364. if (control_mac_modes[vmode - 1].m[full] < cmode)
  365. vmode = VMODE_640_480_60;
  366. }
  367. } else {
  368. vmode=default_vmode;
  369. if (control_mac_modes[vmode - 1].m[full] < cmode) {
  370. if (cmode > CMODE_8)
  371. cmode--;
  372. else
  373. vmode = VMODE_640_480_60;
  374. }
  375. }
  376. /* Initialize info structure */
  377. control_init_info(&p->info, p);
  378. /* Setup default var */
  379. if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
  380. /* This shouldn't happen! */
  381. printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
  382. try_again:
  383. vmode = VMODE_640_480_60;
  384. cmode = CMODE_8;
  385. if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
  386. printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
  387. return -ENXIO;
  388. }
  389. printk(KERN_INFO "controlfb: ");
  390. }
  391. printk("using video mode %d and color mode %d.\n", vmode, cmode);
  392. vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
  393. if (vyres > var.yres)
  394. var.yres_virtual = vyres;
  395. /* Apply default var */
  396. var.activate = FB_ACTIVATE_NOW;
  397. rc = fb_set_var(&p->info, &var);
  398. if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
  399. goto try_again;
  400. /* Register with fbdev layer */
  401. if (register_framebuffer(&p->info) < 0)
  402. return -ENXIO;
  403. printk(KERN_INFO "fb%d: control display adapter\n", p->info.node);
  404. return 0;
  405. }
  406. #define RADACAL_WRITE(a,d) \
  407. out_8(&p->cmap_regs->addr, (a)); \
  408. out_8(&p->cmap_regs->dat, (d))
  409. /* Now how about actually saying, Make it so! */
  410. /* Some things in here probably don't need to be done each time. */
  411. static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
  412. {
  413. struct control_regvals *r;
  414. volatile struct preg __iomem *rp;
  415. int i, cmode;
  416. if (PAR_EQUAL(&p->par, par)) {
  417. /*
  418. * check if only xoffset or yoffset differs.
  419. * this prevents flickers in typical VT switch case.
  420. */
  421. if (p->par.xoffset != par->xoffset ||
  422. p->par.yoffset != par->yoffset)
  423. set_screen_start(par->xoffset, par->yoffset, p);
  424. return;
  425. }
  426. p->par = *par;
  427. cmode = p->par.cmode;
  428. r = &par->regvals;
  429. /* Turn off display */
  430. out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
  431. set_control_clock(r->clock_params);
  432. RADACAL_WRITE(0x20, r->radacal_ctrl);
  433. RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
  434. RADACAL_WRITE(0x10, 0);
  435. RADACAL_WRITE(0x11, 0);
  436. rp = &p->control_regs->vswin;
  437. for (i = 0; i < 16; ++i, ++rp)
  438. out_le32(&rp->r, r->regs[i]);
  439. out_le32(CNTRL_REG(p,pitch), par->pitch);
  440. out_le32(CNTRL_REG(p,mode), r->mode);
  441. out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
  442. out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
  443. + (par->xoffset << cmode));
  444. out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
  445. out_le32(CNTRL_REG(p,intr_ena), 0);
  446. /* Turn on display */
  447. out_le32(CNTRL_REG(p,ctrl), par->ctrl);
  448. #ifdef CONFIG_BOOTX_TEXT
  449. btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
  450. p->par.xres, p->par.yres,
  451. (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
  452. p->par.pitch);
  453. #endif /* CONFIG_BOOTX_TEXT */
  454. }
  455. /*
  456. * Parse user speficied options (`video=controlfb:')
  457. */
  458. static void __init control_setup(char *options)
  459. {
  460. char *this_opt;
  461. if (!options || !*options)
  462. return;
  463. while ((this_opt = strsep(&options, ",")) != NULL) {
  464. if (!strncmp(this_opt, "vmode:", 6)) {
  465. int vmode = simple_strtoul(this_opt+6, NULL, 0);
  466. if (vmode > 0 && vmode <= VMODE_MAX &&
  467. control_mac_modes[vmode - 1].m[1] >= 0)
  468. default_vmode = vmode;
  469. } else if (!strncmp(this_opt, "cmode:", 6)) {
  470. int depth = simple_strtoul(this_opt+6, NULL, 0);
  471. switch (depth) {
  472. case CMODE_8:
  473. case CMODE_16:
  474. case CMODE_32:
  475. default_cmode = depth;
  476. break;
  477. case 8:
  478. default_cmode = CMODE_8;
  479. break;
  480. case 15:
  481. case 16:
  482. default_cmode = CMODE_16;
  483. break;
  484. case 24:
  485. case 32:
  486. default_cmode = CMODE_32;
  487. break;
  488. }
  489. }
  490. }
  491. }
  492. static int __init control_init(void)
  493. {
  494. struct device_node *dp;
  495. char *option = NULL;
  496. if (fb_get_options("controlfb", &option))
  497. return -ENODEV;
  498. control_setup(option);
  499. dp = find_devices("control");
  500. if (dp != 0 && !control_of_init(dp))
  501. return 0;
  502. return -ENXIO;
  503. }
  504. module_init(control_init);
  505. /* Work out which banks of VRAM we have installed. */
  506. /* danj: I guess the card just ignores writes to nonexistant VRAM... */
  507. static void __init find_vram_size(struct fb_info_control *p)
  508. {
  509. int bank1, bank2;
  510. /*
  511. * Set VRAM in 2MB (bank 1) mode
  512. * VRAM Bank 2 will be accessible through offset 0x600000 if present
  513. * and VRAM Bank 1 will not respond at that offset even if present
  514. */
  515. out_le32(CNTRL_REG(p,vram_attr), 0x31);
  516. out_8(&p->frame_buffer[0x600000], 0xb3);
  517. out_8(&p->frame_buffer[0x600001], 0x71);
  518. asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0x600000])
  519. : "memory" );
  520. mb();
  521. asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0x600000])
  522. : "memory" );
  523. mb();
  524. bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
  525. && (in_8(&p->frame_buffer[0x600001]) == 0x71);
  526. /*
  527. * Set VRAM in 2MB (bank 2) mode
  528. * VRAM Bank 1 will be accessible through offset 0x000000 if present
  529. * and VRAM Bank 2 will not respond at that offset even if present
  530. */
  531. out_le32(CNTRL_REG(p,vram_attr), 0x39);
  532. out_8(&p->frame_buffer[0], 0x5a);
  533. out_8(&p->frame_buffer[1], 0xc7);
  534. asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0])
  535. : "memory" );
  536. mb();
  537. asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0])
  538. : "memory" );
  539. mb();
  540. bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
  541. && (in_8(&p->frame_buffer[1]) == 0xc7);
  542. if (bank2) {
  543. if (!bank1) {
  544. /*
  545. * vram bank 2 only
  546. */
  547. p->control_use_bank2 = 1;
  548. p->vram_attr = 0x39;
  549. p->frame_buffer += 0x600000;
  550. p->frame_buffer_phys += 0x600000;
  551. } else {
  552. /*
  553. * 4 MB vram
  554. */
  555. p->vram_attr = 0x51;
  556. }
  557. } else {
  558. /*
  559. * vram bank 1 only
  560. */
  561. p->vram_attr = 0x31;
  562. }
  563. p->total_vram = (bank1 + bank2) * 0x200000;
  564. printk(KERN_INFO "controlfb: VRAM Total = %dMB "
  565. "(%dMB @ bank 1, %dMB @ bank 2)\n",
  566. (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
  567. }
  568. /*
  569. * find "control" and initialize
  570. */
  571. static int __init control_of_init(struct device_node *dp)
  572. {
  573. struct fb_info_control *p;
  574. struct resource fb_res, reg_res;
  575. if (control_fb) {
  576. printk(KERN_ERR "controlfb: only one control is supported\n");
  577. return -ENXIO;
  578. }
  579. if (of_pci_address_to_resource(dp, 2, &fb_res) ||
  580. of_pci_address_to_resource(dp, 1, &reg_res)) {
  581. printk(KERN_ERR "can't get 2 addresses for control\n");
  582. return -ENXIO;
  583. }
  584. p = kmalloc(sizeof(*p), GFP_KERNEL);
  585. if (p == 0)
  586. return -ENXIO;
  587. control_fb = p; /* save it for cleanups */
  588. memset(p, 0, sizeof(*p));
  589. /* Map in frame buffer and registers */
  590. p->fb_orig_base = fb_res.start;
  591. p->fb_orig_size = fb_res.end - fb_res.start + 1;
  592. /* use the big-endian aperture (??) */
  593. p->frame_buffer_phys = fb_res.start + 0x800000;
  594. p->control_regs_phys = reg_res.start;
  595. p->control_regs_size = reg_res.end - reg_res.start + 1;
  596. if (!p->fb_orig_base ||
  597. !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
  598. p->fb_orig_base = 0;
  599. goto error_out;
  600. }
  601. /* map at most 8MB for the frame buffer */
  602. p->frame_buffer = __ioremap(p->frame_buffer_phys, 0x800000,
  603. _PAGE_WRITETHRU);
  604. if (!p->control_regs_phys ||
  605. !request_mem_region(p->control_regs_phys, p->control_regs_size,
  606. "controlfb regs")) {
  607. p->control_regs_phys = 0;
  608. goto error_out;
  609. }
  610. p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
  611. p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
  612. if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
  613. p->cmap_regs_phys = 0;
  614. goto error_out;
  615. }
  616. p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
  617. if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
  618. goto error_out;
  619. find_vram_size(p);
  620. if (!p->total_vram)
  621. goto error_out;
  622. if (init_control(p) < 0)
  623. goto error_out;
  624. return 0;
  625. error_out:
  626. control_cleanup();
  627. return -ENXIO;
  628. }
  629. /*
  630. * Get the monitor sense value.
  631. * Note that this can be called before calibrate_delay,
  632. * so we can't use udelay.
  633. */
  634. static int read_control_sense(struct fb_info_control *p)
  635. {
  636. int sense;
  637. out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
  638. __delay(200);
  639. out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
  640. __delay(2000);
  641. sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
  642. /* drive each sense line low in turn and collect the other 2 */
  643. out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
  644. __delay(2000);
  645. sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
  646. out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
  647. __delay(2000);
  648. sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
  649. | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
  650. out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
  651. __delay(2000);
  652. sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
  653. out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
  654. return sense;
  655. }
  656. /********************** Various translation functions **********************/
  657. #define CONTROL_PIXCLOCK_BASE 256016
  658. #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
  659. /*
  660. * calculate the clock paramaters to be sent to CUDA according to given
  661. * pixclock in pico second.
  662. */
  663. static int calc_clock_params(unsigned long clk, unsigned char *param)
  664. {
  665. unsigned long p0, p1, p2, k, l, m, n, min;
  666. if (clk > (CONTROL_PIXCLOCK_BASE << 3))
  667. return 1;
  668. p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
  669. l = clk << p2;
  670. p0 = 0;
  671. p1 = 0;
  672. for (k = 1, min = l; k < 32; k++) {
  673. unsigned long rem;
  674. m = CONTROL_PIXCLOCK_BASE * k;
  675. n = m / l;
  676. rem = m % l;
  677. if (n && (n < 128) && rem < min) {
  678. p0 = k;
  679. p1 = n;
  680. min = rem;
  681. }
  682. }
  683. if (!p0 || !p1)
  684. return 1;
  685. param[0] = p0;
  686. param[1] = p1;
  687. param[2] = p2;
  688. return 0;
  689. }
  690. /*
  691. * This routine takes a user-supplied var, and picks the best vmode/cmode
  692. * from it.
  693. */
  694. static int control_var_to_par(struct fb_var_screeninfo *var,
  695. struct fb_par_control *par, const struct fb_info *fb_info)
  696. {
  697. int cmode, piped_diff, hstep;
  698. unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
  699. hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
  700. unsigned long pixclock;
  701. struct fb_info_control *p = (struct fb_info_control *) fb_info;
  702. struct control_regvals *r = &par->regvals;
  703. switch (var->bits_per_pixel) {
  704. case 8:
  705. par->cmode = CMODE_8;
  706. if (p->total_vram > 0x200000) {
  707. r->mode = 3;
  708. r->radacal_ctrl = 0x20;
  709. piped_diff = 13;
  710. } else {
  711. r->mode = 2;
  712. r->radacal_ctrl = 0x10;
  713. piped_diff = 9;
  714. }
  715. break;
  716. case 15:
  717. case 16:
  718. par->cmode = CMODE_16;
  719. if (p->total_vram > 0x200000) {
  720. r->mode = 2;
  721. r->radacal_ctrl = 0x24;
  722. piped_diff = 5;
  723. } else {
  724. r->mode = 1;
  725. r->radacal_ctrl = 0x14;
  726. piped_diff = 3;
  727. }
  728. break;
  729. case 32:
  730. par->cmode = CMODE_32;
  731. if (p->total_vram > 0x200000) {
  732. r->mode = 1;
  733. r->radacal_ctrl = 0x28;
  734. } else {
  735. r->mode = 0;
  736. r->radacal_ctrl = 0x18;
  737. }
  738. piped_diff = 1;
  739. break;
  740. default:
  741. return -EINVAL;
  742. }
  743. /*
  744. * adjust xres and vxres so that the corresponding memory widths are
  745. * 32-byte aligned
  746. */
  747. hstep = 31 >> par->cmode;
  748. par->xres = (var->xres + hstep) & ~hstep;
  749. par->vxres = (var->xres_virtual + hstep) & ~hstep;
  750. par->xoffset = (var->xoffset + hstep) & ~hstep;
  751. if (par->vxres < par->xres)
  752. par->vxres = par->xres;
  753. par->pitch = par->vxres << par->cmode;
  754. par->yres = var->yres;
  755. par->vyres = var->yres_virtual;
  756. par->yoffset = var->yoffset;
  757. if (par->vyres < par->yres)
  758. par->vyres = par->yres;
  759. par->sync = var->sync;
  760. if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
  761. return -EINVAL;
  762. if (par->xoffset + par->xres > par->vxres)
  763. par->xoffset = par->vxres - par->xres;
  764. if (par->yoffset + par->yres > par->vyres)
  765. par->yoffset = par->vyres - par->yres;
  766. pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
  767. var->pixclock;
  768. if (calc_clock_params(pixclock, r->clock_params))
  769. return -EINVAL;
  770. hperiod = ((var->left_margin + par->xres + var->right_margin
  771. + var->hsync_len) >> 1) - 2;
  772. hssync = hperiod + 1;
  773. hsblank = hssync - (var->right_margin >> 1);
  774. hesync = (var->hsync_len >> 1) - 1;
  775. heblank = (var->left_margin >> 1) + hesync;
  776. piped = heblank - piped_diff;
  777. heq = var->hsync_len >> 2;
  778. hlfln = (hperiod+2) >> 1;
  779. hserr = hssync-hesync;
  780. vperiod = (var->vsync_len + var->lower_margin + par->yres
  781. + var->upper_margin) << 1;
  782. vssync = vperiod - 2;
  783. vesync = (var->vsync_len << 1) - vperiod + vssync;
  784. veblank = (var->upper_margin << 1) + vesync;
  785. vsblank = vssync - (var->lower_margin << 1);
  786. vswin = (vsblank+vssync) >> 1;
  787. vewin = (vesync+veblank) >> 1;
  788. r->regs[0] = vswin;
  789. r->regs[1] = vsblank;
  790. r->regs[2] = veblank;
  791. r->regs[3] = vewin;
  792. r->regs[4] = vesync;
  793. r->regs[5] = vssync;
  794. r->regs[6] = vperiod;
  795. r->regs[7] = piped;
  796. r->regs[8] = hperiod;
  797. r->regs[9] = hsblank;
  798. r->regs[10] = heblank;
  799. r->regs[11] = hesync;
  800. r->regs[12] = hssync;
  801. r->regs[13] = heq;
  802. r->regs[14] = hlfln;
  803. r->regs[15] = hserr;
  804. if (par->xres >= 1280 && par->cmode >= CMODE_16)
  805. par->ctrl = 0x7f;
  806. else
  807. par->ctrl = 0x3b;
  808. if (mac_var_to_vmode(var, &par->vmode, &cmode))
  809. par->vmode = 0;
  810. return 0;
  811. }
  812. /*
  813. * Convert hardware data in par to an fb_var_screeninfo
  814. */
  815. static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
  816. {
  817. struct control_regints *rv;
  818. rv = (struct control_regints *) par->regvals.regs;
  819. memset(var, 0, sizeof(*var));
  820. var->xres = par->xres;
  821. var->yres = par->yres;
  822. var->xres_virtual = par->vxres;
  823. var->yres_virtual = par->vyres;
  824. var->xoffset = par->xoffset;
  825. var->yoffset = par->yoffset;
  826. switch(par->cmode) {
  827. default:
  828. case CMODE_8:
  829. var->bits_per_pixel = 8;
  830. var->red.length = 8;
  831. var->green.length = 8;
  832. var->blue.length = 8;
  833. break;
  834. case CMODE_16: /* RGB 555 */
  835. var->bits_per_pixel = 16;
  836. var->red.offset = 10;
  837. var->red.length = 5;
  838. var->green.offset = 5;
  839. var->green.length = 5;
  840. var->blue.length = 5;
  841. break;
  842. case CMODE_32: /* RGB 888 */
  843. var->bits_per_pixel = 32;
  844. var->red.offset = 16;
  845. var->red.length = 8;
  846. var->green.offset = 8;
  847. var->green.length = 8;
  848. var->blue.length = 8;
  849. var->transp.offset = 24;
  850. var->transp.length = 8;
  851. break;
  852. }
  853. var->height = -1;
  854. var->width = -1;
  855. var->vmode = FB_VMODE_NONINTERLACED;
  856. var->left_margin = (rv->heblank - rv->hesync) << 1;
  857. var->right_margin = (rv->hssync - rv->hsblank) << 1;
  858. var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
  859. var->upper_margin = (rv->veblank - rv->vesync) >> 1;
  860. var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
  861. var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
  862. var->sync = par->sync;
  863. /*
  864. * 10^12 * clock_params[0] / (3906400 * clock_params[1]
  865. * * 2^clock_params[2])
  866. * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
  867. * >> clock_params[2]
  868. */
  869. /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
  870. var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
  871. var->pixclock /= par->regvals.clock_params[1];
  872. var->pixclock >>= par->regvals.clock_params[2];
  873. }
  874. /*
  875. * Set misc info vars for this driver
  876. */
  877. static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
  878. {
  879. /* Fill fb_info */
  880. info->par = &p->par;
  881. info->fbops = &controlfb_ops;
  882. info->pseudo_palette = p->pseudo_palette;
  883. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  884. info->screen_base = p->frame_buffer + CTRLFB_OFF;
  885. fb_alloc_cmap(&info->cmap, 256, 0);
  886. /* Fill fix common fields */
  887. strcpy(info->fix.id, "control");
  888. info->fix.mmio_start = p->control_regs_phys;
  889. info->fix.mmio_len = sizeof(struct control_regs);
  890. info->fix.type = FB_TYPE_PACKED_PIXELS;
  891. info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
  892. info->fix.smem_len = p->total_vram - CTRLFB_OFF;
  893. info->fix.ywrapstep = 0;
  894. info->fix.type_aux = 0;
  895. info->fix.accel = FB_ACCEL_NONE;
  896. }
  897. static void control_cleanup(void)
  898. {
  899. struct fb_info_control *p = control_fb;
  900. if (!p)
  901. return;
  902. if (p->cmap_regs)
  903. iounmap(p->cmap_regs);
  904. if (p->control_regs)
  905. iounmap(p->control_regs);
  906. if (p->frame_buffer) {
  907. if (p->control_use_bank2)
  908. p->frame_buffer -= 0x600000;
  909. iounmap(p->frame_buffer);
  910. }
  911. if (p->cmap_regs_phys)
  912. release_mem_region(p->cmap_regs_phys, 0x1000);
  913. if (p->control_regs_phys)
  914. release_mem_region(p->control_regs_phys, p->control_regs_size);
  915. if (p->fb_orig_base)
  916. release_mem_region(p->fb_orig_base, p->fb_orig_size);
  917. kfree(p);
  918. }