qla_sup.c 41 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2005 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include <linux/delay.h>
  9. #include <asm/uaccess.h>
  10. static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  11. static void qla2x00_nv_deselect(scsi_qla_host_t *);
  12. static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  13. /*
  14. * NVRAM support routines
  15. */
  16. /**
  17. * qla2x00_lock_nvram_access() -
  18. * @ha: HA context
  19. */
  20. void
  21. qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  22. {
  23. uint16_t data;
  24. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  25. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  26. data = RD_REG_WORD(&reg->nvram);
  27. while (data & NVR_BUSY) {
  28. udelay(100);
  29. data = RD_REG_WORD(&reg->nvram);
  30. }
  31. /* Lock resource */
  32. WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  33. RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  34. udelay(5);
  35. data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  36. while ((data & BIT_0) == 0) {
  37. /* Lock failed */
  38. udelay(100);
  39. WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  40. RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  41. udelay(5);
  42. data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  43. }
  44. }
  45. }
  46. /**
  47. * qla2x00_unlock_nvram_access() -
  48. * @ha: HA context
  49. */
  50. void
  51. qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  52. {
  53. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  54. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  55. WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  56. RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  57. }
  58. }
  59. /**
  60. * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  61. * request routine to get the word from NVRAM.
  62. * @ha: HA context
  63. * @addr: Address in NVRAM to read
  64. *
  65. * Returns the word read from nvram @addr.
  66. */
  67. uint16_t
  68. qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  69. {
  70. uint16_t data;
  71. uint32_t nv_cmd;
  72. nv_cmd = addr << 16;
  73. nv_cmd |= NV_READ_OP;
  74. data = qla2x00_nvram_request(ha, nv_cmd);
  75. return (data);
  76. }
  77. /**
  78. * qla2x00_write_nvram_word() - Write NVRAM data.
  79. * @ha: HA context
  80. * @addr: Address in NVRAM to write
  81. * @data: word to program
  82. */
  83. void
  84. qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  85. {
  86. int count;
  87. uint16_t word;
  88. uint32_t nv_cmd;
  89. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  90. qla2x00_nv_write(ha, NVR_DATA_OUT);
  91. qla2x00_nv_write(ha, 0);
  92. qla2x00_nv_write(ha, 0);
  93. for (word = 0; word < 8; word++)
  94. qla2x00_nv_write(ha, NVR_DATA_OUT);
  95. qla2x00_nv_deselect(ha);
  96. /* Write data */
  97. nv_cmd = (addr << 16) | NV_WRITE_OP;
  98. nv_cmd |= data;
  99. nv_cmd <<= 5;
  100. for (count = 0; count < 27; count++) {
  101. if (nv_cmd & BIT_31)
  102. qla2x00_nv_write(ha, NVR_DATA_OUT);
  103. else
  104. qla2x00_nv_write(ha, 0);
  105. nv_cmd <<= 1;
  106. }
  107. qla2x00_nv_deselect(ha);
  108. /* Wait for NVRAM to become ready */
  109. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  110. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  111. do {
  112. NVRAM_DELAY();
  113. word = RD_REG_WORD(&reg->nvram);
  114. } while ((word & NVR_DATA_IN) == 0);
  115. qla2x00_nv_deselect(ha);
  116. /* Disable writes */
  117. qla2x00_nv_write(ha, NVR_DATA_OUT);
  118. for (count = 0; count < 10; count++)
  119. qla2x00_nv_write(ha, 0);
  120. qla2x00_nv_deselect(ha);
  121. }
  122. static int
  123. qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
  124. uint32_t tmo)
  125. {
  126. int ret, count;
  127. uint16_t word;
  128. uint32_t nv_cmd;
  129. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  130. ret = QLA_SUCCESS;
  131. qla2x00_nv_write(ha, NVR_DATA_OUT);
  132. qla2x00_nv_write(ha, 0);
  133. qla2x00_nv_write(ha, 0);
  134. for (word = 0; word < 8; word++)
  135. qla2x00_nv_write(ha, NVR_DATA_OUT);
  136. qla2x00_nv_deselect(ha);
  137. /* Write data */
  138. nv_cmd = (addr << 16) | NV_WRITE_OP;
  139. nv_cmd |= data;
  140. nv_cmd <<= 5;
  141. for (count = 0; count < 27; count++) {
  142. if (nv_cmd & BIT_31)
  143. qla2x00_nv_write(ha, NVR_DATA_OUT);
  144. else
  145. qla2x00_nv_write(ha, 0);
  146. nv_cmd <<= 1;
  147. }
  148. qla2x00_nv_deselect(ha);
  149. /* Wait for NVRAM to become ready */
  150. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  151. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  152. do {
  153. NVRAM_DELAY();
  154. word = RD_REG_WORD(&reg->nvram);
  155. if (!--tmo) {
  156. ret = QLA_FUNCTION_FAILED;
  157. break;
  158. }
  159. } while ((word & NVR_DATA_IN) == 0);
  160. qla2x00_nv_deselect(ha);
  161. /* Disable writes */
  162. qla2x00_nv_write(ha, NVR_DATA_OUT);
  163. for (count = 0; count < 10; count++)
  164. qla2x00_nv_write(ha, 0);
  165. qla2x00_nv_deselect(ha);
  166. return ret;
  167. }
  168. /**
  169. * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
  170. * NVRAM.
  171. * @ha: HA context
  172. * @nv_cmd: NVRAM command
  173. *
  174. * Bit definitions for NVRAM command:
  175. *
  176. * Bit 26 = start bit
  177. * Bit 25, 24 = opcode
  178. * Bit 23-16 = address
  179. * Bit 15-0 = write data
  180. *
  181. * Returns the word read from nvram @addr.
  182. */
  183. static uint16_t
  184. qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
  185. {
  186. uint8_t cnt;
  187. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  188. uint16_t data = 0;
  189. uint16_t reg_data;
  190. /* Send command to NVRAM. */
  191. nv_cmd <<= 5;
  192. for (cnt = 0; cnt < 11; cnt++) {
  193. if (nv_cmd & BIT_31)
  194. qla2x00_nv_write(ha, NVR_DATA_OUT);
  195. else
  196. qla2x00_nv_write(ha, 0);
  197. nv_cmd <<= 1;
  198. }
  199. /* Read data from NVRAM. */
  200. for (cnt = 0; cnt < 16; cnt++) {
  201. WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
  202. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  203. NVRAM_DELAY();
  204. data <<= 1;
  205. reg_data = RD_REG_WORD(&reg->nvram);
  206. if (reg_data & NVR_DATA_IN)
  207. data |= BIT_0;
  208. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  209. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  210. NVRAM_DELAY();
  211. }
  212. /* Deselect chip. */
  213. WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
  214. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  215. NVRAM_DELAY();
  216. return (data);
  217. }
  218. /**
  219. * qla2x00_nv_write() - Clean NVRAM operations.
  220. * @ha: HA context
  221. */
  222. static void
  223. qla2x00_nv_deselect(scsi_qla_host_t *ha)
  224. {
  225. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  226. WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
  227. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  228. NVRAM_DELAY();
  229. }
  230. /**
  231. * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
  232. * @ha: HA context
  233. * @data: Serial interface selector
  234. */
  235. static void
  236. qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
  237. {
  238. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  239. WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  240. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  241. NVRAM_DELAY();
  242. WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
  243. NVR_WRT_ENABLE);
  244. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  245. NVRAM_DELAY();
  246. WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
  247. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  248. NVRAM_DELAY();
  249. }
  250. /**
  251. * qla2x00_clear_nvram_protection() -
  252. * @ha: HA context
  253. */
  254. static int
  255. qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
  256. {
  257. int ret, stat;
  258. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  259. uint32_t word;
  260. uint16_t wprot, wprot_old;
  261. /* Clear NVRAM write protection. */
  262. ret = QLA_FUNCTION_FAILED;
  263. wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
  264. stat = qla2x00_write_nvram_word_tmo(ha, 0,
  265. __constant_cpu_to_le16(0x1234), 100000);
  266. wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
  267. if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
  268. /* Write enable. */
  269. qla2x00_nv_write(ha, NVR_DATA_OUT);
  270. qla2x00_nv_write(ha, 0);
  271. qla2x00_nv_write(ha, 0);
  272. for (word = 0; word < 8; word++)
  273. qla2x00_nv_write(ha, NVR_DATA_OUT);
  274. qla2x00_nv_deselect(ha);
  275. /* Enable protection register. */
  276. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  277. qla2x00_nv_write(ha, NVR_PR_ENABLE);
  278. qla2x00_nv_write(ha, NVR_PR_ENABLE);
  279. for (word = 0; word < 8; word++)
  280. qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
  281. qla2x00_nv_deselect(ha);
  282. /* Clear protection register (ffff is cleared). */
  283. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  284. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  285. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  286. for (word = 0; word < 8; word++)
  287. qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
  288. qla2x00_nv_deselect(ha);
  289. /* Wait for NVRAM to become ready. */
  290. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  291. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  292. do {
  293. NVRAM_DELAY();
  294. word = RD_REG_WORD(&reg->nvram);
  295. } while ((word & NVR_DATA_IN) == 0);
  296. ret = QLA_SUCCESS;
  297. } else
  298. qla2x00_write_nvram_word(ha, 0, wprot_old);
  299. return ret;
  300. }
  301. static void
  302. qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
  303. {
  304. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  305. uint32_t word;
  306. if (stat != QLA_SUCCESS)
  307. return;
  308. /* Set NVRAM write protection. */
  309. /* Write enable. */
  310. qla2x00_nv_write(ha, NVR_DATA_OUT);
  311. qla2x00_nv_write(ha, 0);
  312. qla2x00_nv_write(ha, 0);
  313. for (word = 0; word < 8; word++)
  314. qla2x00_nv_write(ha, NVR_DATA_OUT);
  315. qla2x00_nv_deselect(ha);
  316. /* Enable protection register. */
  317. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  318. qla2x00_nv_write(ha, NVR_PR_ENABLE);
  319. qla2x00_nv_write(ha, NVR_PR_ENABLE);
  320. for (word = 0; word < 8; word++)
  321. qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
  322. qla2x00_nv_deselect(ha);
  323. /* Enable protection register. */
  324. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  325. qla2x00_nv_write(ha, NVR_PR_ENABLE);
  326. qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
  327. for (word = 0; word < 8; word++)
  328. qla2x00_nv_write(ha, NVR_PR_ENABLE);
  329. qla2x00_nv_deselect(ha);
  330. /* Wait for NVRAM to become ready. */
  331. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  332. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  333. do {
  334. NVRAM_DELAY();
  335. word = RD_REG_WORD(&reg->nvram);
  336. } while ((word & NVR_DATA_IN) == 0);
  337. }
  338. /*****************************************************************************/
  339. /* Flash Manipulation Routines */
  340. /*****************************************************************************/
  341. static inline uint32_t
  342. flash_conf_to_access_addr(uint32_t faddr)
  343. {
  344. return FARX_ACCESS_FLASH_CONF | faddr;
  345. }
  346. static inline uint32_t
  347. flash_data_to_access_addr(uint32_t faddr)
  348. {
  349. return FARX_ACCESS_FLASH_DATA | faddr;
  350. }
  351. static inline uint32_t
  352. nvram_conf_to_access_addr(uint32_t naddr)
  353. {
  354. return FARX_ACCESS_NVRAM_CONF | naddr;
  355. }
  356. static inline uint32_t
  357. nvram_data_to_access_addr(uint32_t naddr)
  358. {
  359. return FARX_ACCESS_NVRAM_DATA | naddr;
  360. }
  361. uint32_t
  362. qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
  363. {
  364. int rval;
  365. uint32_t cnt, data;
  366. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  367. WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
  368. /* Wait for READ cycle to complete. */
  369. rval = QLA_SUCCESS;
  370. for (cnt = 3000;
  371. (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
  372. rval == QLA_SUCCESS; cnt--) {
  373. if (cnt)
  374. udelay(10);
  375. else
  376. rval = QLA_FUNCTION_TIMEOUT;
  377. }
  378. /* TODO: What happens if we time out? */
  379. data = 0xDEADDEAD;
  380. if (rval == QLA_SUCCESS)
  381. data = RD_REG_DWORD(&reg->flash_data);
  382. return data;
  383. }
  384. uint32_t *
  385. qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
  386. uint32_t dwords)
  387. {
  388. uint32_t i;
  389. /* Dword reads to flash. */
  390. for (i = 0; i < dwords; i++, faddr++)
  391. dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
  392. flash_data_to_access_addr(faddr)));
  393. return dwptr;
  394. }
  395. int
  396. qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
  397. {
  398. int rval;
  399. uint32_t cnt;
  400. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  401. WRT_REG_DWORD(&reg->flash_data, data);
  402. RD_REG_DWORD(&reg->flash_data); /* PCI Posting. */
  403. WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
  404. /* Wait for Write cycle to complete. */
  405. rval = QLA_SUCCESS;
  406. for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
  407. rval == QLA_SUCCESS; cnt--) {
  408. if (cnt)
  409. udelay(10);
  410. else
  411. rval = QLA_FUNCTION_TIMEOUT;
  412. }
  413. return rval;
  414. }
  415. void
  416. qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
  417. uint8_t *flash_id)
  418. {
  419. uint32_t ids;
  420. ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
  421. *man_id = LSB(ids);
  422. *flash_id = MSB(ids);
  423. }
  424. int
  425. qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
  426. uint32_t dwords)
  427. {
  428. int ret;
  429. uint32_t liter;
  430. uint32_t sec_mask, rest_addr, conf_addr;
  431. uint32_t fdata;
  432. uint8_t man_id, flash_id;
  433. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  434. ret = QLA_SUCCESS;
  435. qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
  436. DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
  437. ha->host_no, man_id, flash_id));
  438. conf_addr = flash_conf_to_access_addr(0x03d8);
  439. switch (man_id) {
  440. case 0xbf: /* STT flash. */
  441. rest_addr = 0x1fff;
  442. sec_mask = 0x3e000;
  443. if (flash_id == 0x80)
  444. conf_addr = flash_conf_to_access_addr(0x0352);
  445. break;
  446. case 0x13: /* ST M25P80. */
  447. rest_addr = 0x3fff;
  448. sec_mask = 0x3c000;
  449. break;
  450. default:
  451. /* Default to 64 kb sector size. */
  452. rest_addr = 0x3fff;
  453. sec_mask = 0x3c000;
  454. break;
  455. }
  456. /* Enable flash write. */
  457. WRT_REG_DWORD(&reg->ctrl_status,
  458. RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
  459. RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
  460. /* Disable flash write-protection. */
  461. qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
  462. do { /* Loop once to provide quick error exit. */
  463. for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
  464. /* Are we at the beginning of a sector? */
  465. if ((faddr & rest_addr) == 0) {
  466. fdata = (faddr & sec_mask) << 2;
  467. ret = qla24xx_write_flash_dword(ha, conf_addr,
  468. (fdata & 0xff00) |((fdata << 16) &
  469. 0xff0000) | ((fdata >> 16) & 0xff));
  470. if (ret != QLA_SUCCESS) {
  471. DEBUG9(printk("%s(%ld) Unable to flash "
  472. "sector: address=%x.\n", __func__,
  473. ha->host_no, faddr));
  474. break;
  475. }
  476. }
  477. ret = qla24xx_write_flash_dword(ha,
  478. flash_data_to_access_addr(faddr),
  479. cpu_to_le32(*dwptr));
  480. if (ret != QLA_SUCCESS) {
  481. DEBUG9(printk("%s(%ld) Unable to program flash "
  482. "address=%x data=%x.\n", __func__,
  483. ha->host_no, faddr, *dwptr));
  484. break;
  485. }
  486. }
  487. } while (0);
  488. /* Enable flash write-protection. */
  489. qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
  490. /* Disable flash write. */
  491. WRT_REG_DWORD(&reg->ctrl_status,
  492. RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
  493. RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
  494. return ret;
  495. }
  496. uint8_t *
  497. qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
  498. uint32_t bytes)
  499. {
  500. uint32_t i;
  501. uint16_t *wptr;
  502. /* Word reads to NVRAM via registers. */
  503. wptr = (uint16_t *)buf;
  504. qla2x00_lock_nvram_access(ha);
  505. for (i = 0; i < bytes >> 1; i++, naddr++)
  506. wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
  507. naddr));
  508. qla2x00_unlock_nvram_access(ha);
  509. return buf;
  510. }
  511. uint8_t *
  512. qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
  513. uint32_t bytes)
  514. {
  515. uint32_t i;
  516. uint32_t *dwptr;
  517. /* Dword reads to flash. */
  518. dwptr = (uint32_t *)buf;
  519. for (i = 0; i < bytes >> 2; i++, naddr++)
  520. dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
  521. nvram_data_to_access_addr(naddr)));
  522. return buf;
  523. }
  524. int
  525. qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
  526. uint32_t bytes)
  527. {
  528. int ret, stat;
  529. uint32_t i;
  530. uint16_t *wptr;
  531. ret = QLA_SUCCESS;
  532. qla2x00_lock_nvram_access(ha);
  533. /* Disable NVRAM write-protection. */
  534. stat = qla2x00_clear_nvram_protection(ha);
  535. wptr = (uint16_t *)buf;
  536. for (i = 0; i < bytes >> 1; i++, naddr++) {
  537. qla2x00_write_nvram_word(ha, naddr,
  538. cpu_to_le16(*wptr));
  539. wptr++;
  540. }
  541. /* Enable NVRAM write-protection. */
  542. qla2x00_set_nvram_protection(ha, stat);
  543. qla2x00_unlock_nvram_access(ha);
  544. return ret;
  545. }
  546. int
  547. qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
  548. uint32_t bytes)
  549. {
  550. int ret;
  551. uint32_t i;
  552. uint32_t *dwptr;
  553. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  554. ret = QLA_SUCCESS;
  555. /* Enable flash write. */
  556. WRT_REG_DWORD(&reg->ctrl_status,
  557. RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
  558. RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
  559. /* Disable NVRAM write-protection. */
  560. qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
  561. 0);
  562. qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
  563. 0);
  564. /* Dword writes to flash. */
  565. dwptr = (uint32_t *)buf;
  566. for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
  567. ret = qla24xx_write_flash_dword(ha,
  568. nvram_data_to_access_addr(naddr),
  569. cpu_to_le32(*dwptr));
  570. if (ret != QLA_SUCCESS) {
  571. DEBUG9(printk("%s(%ld) Unable to program "
  572. "nvram address=%x data=%x.\n", __func__,
  573. ha->host_no, naddr, *dwptr));
  574. break;
  575. }
  576. }
  577. /* Enable NVRAM write-protection. */
  578. qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
  579. 0x8c);
  580. /* Disable flash write. */
  581. WRT_REG_DWORD(&reg->ctrl_status,
  582. RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
  583. RD_REG_DWORD(&reg->ctrl_status); /* PCI Posting. */
  584. return ret;
  585. }
  586. static inline void
  587. qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
  588. {
  589. if (IS_QLA2322(ha)) {
  590. /* Flip all colors. */
  591. if (ha->beacon_color_state == QLA_LED_ALL_ON) {
  592. /* Turn off. */
  593. ha->beacon_color_state = 0;
  594. *pflags = GPIO_LED_ALL_OFF;
  595. } else {
  596. /* Turn on. */
  597. ha->beacon_color_state = QLA_LED_ALL_ON;
  598. *pflags = GPIO_LED_RGA_ON;
  599. }
  600. } else {
  601. /* Flip green led only. */
  602. if (ha->beacon_color_state == QLA_LED_GRN_ON) {
  603. /* Turn off. */
  604. ha->beacon_color_state = 0;
  605. *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
  606. } else {
  607. /* Turn on. */
  608. ha->beacon_color_state = QLA_LED_GRN_ON;
  609. *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
  610. }
  611. }
  612. }
  613. void
  614. qla2x00_beacon_blink(struct scsi_qla_host *ha)
  615. {
  616. uint16_t gpio_enable;
  617. uint16_t gpio_data;
  618. uint16_t led_color = 0;
  619. unsigned long flags;
  620. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  621. if (ha->pio_address)
  622. reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
  623. spin_lock_irqsave(&ha->hardware_lock, flags);
  624. /* Save the Original GPIOE. */
  625. if (ha->pio_address) {
  626. gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
  627. gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
  628. } else {
  629. gpio_enable = RD_REG_WORD(&reg->gpioe);
  630. gpio_data = RD_REG_WORD(&reg->gpiod);
  631. }
  632. /* Set the modified gpio_enable values */
  633. gpio_enable |= GPIO_LED_MASK;
  634. if (ha->pio_address) {
  635. WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
  636. } else {
  637. WRT_REG_WORD(&reg->gpioe, gpio_enable);
  638. RD_REG_WORD(&reg->gpioe);
  639. }
  640. qla2x00_flip_colors(ha, &led_color);
  641. /* Clear out any previously set LED color. */
  642. gpio_data &= ~GPIO_LED_MASK;
  643. /* Set the new input LED color to GPIOD. */
  644. gpio_data |= led_color;
  645. /* Set the modified gpio_data values */
  646. if (ha->pio_address) {
  647. WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
  648. } else {
  649. WRT_REG_WORD(&reg->gpiod, gpio_data);
  650. RD_REG_WORD(&reg->gpiod);
  651. }
  652. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  653. }
  654. int
  655. qla2x00_beacon_on(struct scsi_qla_host *ha)
  656. {
  657. uint16_t gpio_enable;
  658. uint16_t gpio_data;
  659. unsigned long flags;
  660. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  661. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  662. ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
  663. if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
  664. qla_printk(KERN_WARNING, ha,
  665. "Unable to update fw options (beacon on).\n");
  666. return QLA_FUNCTION_FAILED;
  667. }
  668. if (ha->pio_address)
  669. reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
  670. /* Turn off LEDs. */
  671. spin_lock_irqsave(&ha->hardware_lock, flags);
  672. if (ha->pio_address) {
  673. gpio_enable = RD_REG_WORD_PIO(&reg->gpioe);
  674. gpio_data = RD_REG_WORD_PIO(&reg->gpiod);
  675. } else {
  676. gpio_enable = RD_REG_WORD(&reg->gpioe);
  677. gpio_data = RD_REG_WORD(&reg->gpiod);
  678. }
  679. gpio_enable |= GPIO_LED_MASK;
  680. /* Set the modified gpio_enable values. */
  681. if (ha->pio_address) {
  682. WRT_REG_WORD_PIO(&reg->gpioe, gpio_enable);
  683. } else {
  684. WRT_REG_WORD(&reg->gpioe, gpio_enable);
  685. RD_REG_WORD(&reg->gpioe);
  686. }
  687. /* Clear out previously set LED colour. */
  688. gpio_data &= ~GPIO_LED_MASK;
  689. if (ha->pio_address) {
  690. WRT_REG_WORD_PIO(&reg->gpiod, gpio_data);
  691. } else {
  692. WRT_REG_WORD(&reg->gpiod, gpio_data);
  693. RD_REG_WORD(&reg->gpiod);
  694. }
  695. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  696. /*
  697. * Let the per HBA timer kick off the blinking process based on
  698. * the following flags. No need to do anything else now.
  699. */
  700. ha->beacon_blink_led = 1;
  701. ha->beacon_color_state = 0;
  702. return QLA_SUCCESS;
  703. }
  704. int
  705. qla2x00_beacon_off(struct scsi_qla_host *ha)
  706. {
  707. int rval = QLA_SUCCESS;
  708. ha->beacon_blink_led = 0;
  709. /* Set the on flag so when it gets flipped it will be off. */
  710. if (IS_QLA2322(ha))
  711. ha->beacon_color_state = QLA_LED_ALL_ON;
  712. else
  713. ha->beacon_color_state = QLA_LED_GRN_ON;
  714. ha->isp_ops.beacon_blink(ha); /* This turns green LED off */
  715. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  716. ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
  717. rval = qla2x00_set_fw_options(ha, ha->fw_options);
  718. if (rval != QLA_SUCCESS)
  719. qla_printk(KERN_WARNING, ha,
  720. "Unable to update fw options (beacon off).\n");
  721. return rval;
  722. }
  723. static inline void
  724. qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
  725. {
  726. /* Flip all colors. */
  727. if (ha->beacon_color_state == QLA_LED_ALL_ON) {
  728. /* Turn off. */
  729. ha->beacon_color_state = 0;
  730. *pflags = 0;
  731. } else {
  732. /* Turn on. */
  733. ha->beacon_color_state = QLA_LED_ALL_ON;
  734. *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
  735. }
  736. }
  737. void
  738. qla24xx_beacon_blink(struct scsi_qla_host *ha)
  739. {
  740. uint16_t led_color = 0;
  741. uint32_t gpio_data;
  742. unsigned long flags;
  743. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  744. /* Save the Original GPIOD. */
  745. spin_lock_irqsave(&ha->hardware_lock, flags);
  746. gpio_data = RD_REG_DWORD(&reg->gpiod);
  747. /* Enable the gpio_data reg for update. */
  748. gpio_data |= GPDX_LED_UPDATE_MASK;
  749. WRT_REG_DWORD(&reg->gpiod, gpio_data);
  750. gpio_data = RD_REG_DWORD(&reg->gpiod);
  751. /* Set the color bits. */
  752. qla24xx_flip_colors(ha, &led_color);
  753. /* Clear out any previously set LED color. */
  754. gpio_data &= ~GPDX_LED_COLOR_MASK;
  755. /* Set the new input LED color to GPIOD. */
  756. gpio_data |= led_color;
  757. /* Set the modified gpio_data values. */
  758. WRT_REG_DWORD(&reg->gpiod, gpio_data);
  759. gpio_data = RD_REG_DWORD(&reg->gpiod);
  760. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  761. }
  762. int
  763. qla24xx_beacon_on(struct scsi_qla_host *ha)
  764. {
  765. uint32_t gpio_data;
  766. unsigned long flags;
  767. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  768. if (ha->beacon_blink_led == 0) {
  769. /* Enable firmware for update */
  770. ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
  771. if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
  772. return QLA_FUNCTION_FAILED;
  773. if (qla2x00_get_fw_options(ha, ha->fw_options) !=
  774. QLA_SUCCESS) {
  775. qla_printk(KERN_WARNING, ha,
  776. "Unable to update fw options (beacon on).\n");
  777. return QLA_FUNCTION_FAILED;
  778. }
  779. spin_lock_irqsave(&ha->hardware_lock, flags);
  780. gpio_data = RD_REG_DWORD(&reg->gpiod);
  781. /* Enable the gpio_data reg for update. */
  782. gpio_data |= GPDX_LED_UPDATE_MASK;
  783. WRT_REG_DWORD(&reg->gpiod, gpio_data);
  784. RD_REG_DWORD(&reg->gpiod);
  785. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  786. }
  787. /* So all colors blink together. */
  788. ha->beacon_color_state = 0;
  789. /* Let the per HBA timer kick off the blinking process. */
  790. ha->beacon_blink_led = 1;
  791. return QLA_SUCCESS;
  792. }
  793. int
  794. qla24xx_beacon_off(struct scsi_qla_host *ha)
  795. {
  796. uint32_t gpio_data;
  797. unsigned long flags;
  798. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  799. ha->beacon_blink_led = 0;
  800. ha->beacon_color_state = QLA_LED_ALL_ON;
  801. ha->isp_ops.beacon_blink(ha); /* Will flip to all off. */
  802. /* Give control back to firmware. */
  803. spin_lock_irqsave(&ha->hardware_lock, flags);
  804. gpio_data = RD_REG_DWORD(&reg->gpiod);
  805. /* Disable the gpio_data reg for update. */
  806. gpio_data &= ~GPDX_LED_UPDATE_MASK;
  807. WRT_REG_DWORD(&reg->gpiod, gpio_data);
  808. RD_REG_DWORD(&reg->gpiod);
  809. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  810. ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
  811. if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
  812. qla_printk(KERN_WARNING, ha,
  813. "Unable to update fw options (beacon off).\n");
  814. return QLA_FUNCTION_FAILED;
  815. }
  816. if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
  817. qla_printk(KERN_WARNING, ha,
  818. "Unable to get fw options (beacon off).\n");
  819. return QLA_FUNCTION_FAILED;
  820. }
  821. return QLA_SUCCESS;
  822. }
  823. /*
  824. * Flash support routines
  825. */
  826. /**
  827. * qla2x00_flash_enable() - Setup flash for reading and writing.
  828. * @ha: HA context
  829. */
  830. static void
  831. qla2x00_flash_enable(scsi_qla_host_t *ha)
  832. {
  833. uint16_t data;
  834. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  835. data = RD_REG_WORD(&reg->ctrl_status);
  836. data |= CSR_FLASH_ENABLE;
  837. WRT_REG_WORD(&reg->ctrl_status, data);
  838. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  839. }
  840. /**
  841. * qla2x00_flash_disable() - Disable flash and allow RISC to run.
  842. * @ha: HA context
  843. */
  844. static void
  845. qla2x00_flash_disable(scsi_qla_host_t *ha)
  846. {
  847. uint16_t data;
  848. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  849. data = RD_REG_WORD(&reg->ctrl_status);
  850. data &= ~(CSR_FLASH_ENABLE);
  851. WRT_REG_WORD(&reg->ctrl_status, data);
  852. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  853. }
  854. /**
  855. * qla2x00_read_flash_byte() - Reads a byte from flash
  856. * @ha: HA context
  857. * @addr: Address in flash to read
  858. *
  859. * A word is read from the chip, but, only the lower byte is valid.
  860. *
  861. * Returns the byte read from flash @addr.
  862. */
  863. static uint8_t
  864. qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
  865. {
  866. uint16_t data;
  867. uint16_t bank_select;
  868. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  869. bank_select = RD_REG_WORD(&reg->ctrl_status);
  870. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  871. /* Specify 64K address range: */
  872. /* clear out Module Select and Flash Address bits [19:16]. */
  873. bank_select &= ~0xf8;
  874. bank_select |= addr >> 12 & 0xf0;
  875. bank_select |= CSR_FLASH_64K_BANK;
  876. WRT_REG_WORD(&reg->ctrl_status, bank_select);
  877. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  878. WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
  879. data = RD_REG_WORD(&reg->flash_data);
  880. return (uint8_t)data;
  881. }
  882. /* Setup bit 16 of flash address. */
  883. if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
  884. bank_select |= CSR_FLASH_64K_BANK;
  885. WRT_REG_WORD(&reg->ctrl_status, bank_select);
  886. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  887. } else if (((addr & BIT_16) == 0) &&
  888. (bank_select & CSR_FLASH_64K_BANK)) {
  889. bank_select &= ~(CSR_FLASH_64K_BANK);
  890. WRT_REG_WORD(&reg->ctrl_status, bank_select);
  891. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  892. }
  893. /* Always perform IO mapped accesses to the FLASH registers. */
  894. if (ha->pio_address) {
  895. uint16_t data2;
  896. reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
  897. WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
  898. do {
  899. data = RD_REG_WORD_PIO(&reg->flash_data);
  900. barrier();
  901. cpu_relax();
  902. data2 = RD_REG_WORD_PIO(&reg->flash_data);
  903. } while (data != data2);
  904. } else {
  905. WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
  906. data = qla2x00_debounce_register(&reg->flash_data);
  907. }
  908. return (uint8_t)data;
  909. }
  910. /**
  911. * qla2x00_write_flash_byte() - Write a byte to flash
  912. * @ha: HA context
  913. * @addr: Address in flash to write
  914. * @data: Data to write
  915. */
  916. static void
  917. qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
  918. {
  919. uint16_t bank_select;
  920. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  921. bank_select = RD_REG_WORD(&reg->ctrl_status);
  922. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  923. /* Specify 64K address range: */
  924. /* clear out Module Select and Flash Address bits [19:16]. */
  925. bank_select &= ~0xf8;
  926. bank_select |= addr >> 12 & 0xf0;
  927. bank_select |= CSR_FLASH_64K_BANK;
  928. WRT_REG_WORD(&reg->ctrl_status, bank_select);
  929. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  930. WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
  931. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  932. WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
  933. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  934. return;
  935. }
  936. /* Setup bit 16 of flash address. */
  937. if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
  938. bank_select |= CSR_FLASH_64K_BANK;
  939. WRT_REG_WORD(&reg->ctrl_status, bank_select);
  940. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  941. } else if (((addr & BIT_16) == 0) &&
  942. (bank_select & CSR_FLASH_64K_BANK)) {
  943. bank_select &= ~(CSR_FLASH_64K_BANK);
  944. WRT_REG_WORD(&reg->ctrl_status, bank_select);
  945. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  946. }
  947. /* Always perform IO mapped accesses to the FLASH registers. */
  948. if (ha->pio_address) {
  949. reg = (struct device_reg_2xxx __iomem *)ha->pio_address;
  950. WRT_REG_WORD_PIO(&reg->flash_address, (uint16_t)addr);
  951. WRT_REG_WORD_PIO(&reg->flash_data, (uint16_t)data);
  952. } else {
  953. WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
  954. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  955. WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
  956. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  957. }
  958. }
  959. /**
  960. * qla2x00_poll_flash() - Polls flash for completion.
  961. * @ha: HA context
  962. * @addr: Address in flash to poll
  963. * @poll_data: Data to be polled
  964. * @man_id: Flash manufacturer ID
  965. * @flash_id: Flash ID
  966. *
  967. * This function polls the device until bit 7 of what is read matches data
  968. * bit 7 or until data bit 5 becomes a 1. If that hapens, the flash ROM timed
  969. * out (a fatal error). The flash book recommeds reading bit 7 again after
  970. * reading bit 5 as a 1.
  971. *
  972. * Returns 0 on success, else non-zero.
  973. */
  974. static int
  975. qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
  976. uint8_t man_id, uint8_t flash_id)
  977. {
  978. int status;
  979. uint8_t flash_data;
  980. uint32_t cnt;
  981. status = 1;
  982. /* Wait for 30 seconds for command to finish. */
  983. poll_data &= BIT_7;
  984. for (cnt = 3000000; cnt; cnt--) {
  985. flash_data = qla2x00_read_flash_byte(ha, addr);
  986. if ((flash_data & BIT_7) == poll_data) {
  987. status = 0;
  988. break;
  989. }
  990. if (man_id != 0x40 && man_id != 0xda) {
  991. if ((flash_data & BIT_5) && cnt > 2)
  992. cnt = 2;
  993. }
  994. udelay(10);
  995. barrier();
  996. }
  997. return status;
  998. }
  999. /**
  1000. * qla2x00_program_flash_address() - Programs a flash address
  1001. * @ha: HA context
  1002. * @addr: Address in flash to program
  1003. * @data: Data to be written in flash
  1004. * @man_id: Flash manufacturer ID
  1005. * @flash_id: Flash ID
  1006. *
  1007. * Returns 0 on success, else non-zero.
  1008. */
  1009. static int
  1010. qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
  1011. uint8_t man_id, uint8_t flash_id)
  1012. {
  1013. /* Write Program Command Sequence. */
  1014. if (IS_OEM_001(ha)) {
  1015. qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
  1016. qla2x00_write_flash_byte(ha, 0x555, 0x55);
  1017. qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
  1018. qla2x00_write_flash_byte(ha, addr, data);
  1019. } else {
  1020. if (man_id == 0xda && flash_id == 0xc1) {
  1021. qla2x00_write_flash_byte(ha, addr, data);
  1022. if (addr & 0x7e)
  1023. return 0;
  1024. } else {
  1025. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1026. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1027. qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
  1028. qla2x00_write_flash_byte(ha, addr, data);
  1029. }
  1030. }
  1031. udelay(150);
  1032. /* Wait for write to complete. */
  1033. return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
  1034. }
  1035. /**
  1036. * qla2x00_erase_flash() - Erase the flash.
  1037. * @ha: HA context
  1038. * @man_id: Flash manufacturer ID
  1039. * @flash_id: Flash ID
  1040. *
  1041. * Returns 0 on success, else non-zero.
  1042. */
  1043. static int
  1044. qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
  1045. {
  1046. /* Individual Sector Erase Command Sequence */
  1047. if (IS_OEM_001(ha)) {
  1048. qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
  1049. qla2x00_write_flash_byte(ha, 0x555, 0x55);
  1050. qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
  1051. qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
  1052. qla2x00_write_flash_byte(ha, 0x555, 0x55);
  1053. qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
  1054. } else {
  1055. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1056. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1057. qla2x00_write_flash_byte(ha, 0x5555, 0x80);
  1058. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1059. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1060. qla2x00_write_flash_byte(ha, 0x5555, 0x10);
  1061. }
  1062. udelay(150);
  1063. /* Wait for erase to complete. */
  1064. return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
  1065. }
  1066. /**
  1067. * qla2x00_erase_flash_sector() - Erase a flash sector.
  1068. * @ha: HA context
  1069. * @addr: Flash sector to erase
  1070. * @sec_mask: Sector address mask
  1071. * @man_id: Flash manufacturer ID
  1072. * @flash_id: Flash ID
  1073. *
  1074. * Returns 0 on success, else non-zero.
  1075. */
  1076. static int
  1077. qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
  1078. uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
  1079. {
  1080. /* Individual Sector Erase Command Sequence */
  1081. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1082. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1083. qla2x00_write_flash_byte(ha, 0x5555, 0x80);
  1084. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1085. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1086. if (man_id == 0x1f && flash_id == 0x13)
  1087. qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
  1088. else
  1089. qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
  1090. udelay(150);
  1091. /* Wait for erase to complete. */
  1092. return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
  1093. }
  1094. /**
  1095. * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
  1096. * @man_id: Flash manufacturer ID
  1097. * @flash_id: Flash ID
  1098. */
  1099. static void
  1100. qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
  1101. uint8_t *flash_id)
  1102. {
  1103. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1104. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1105. qla2x00_write_flash_byte(ha, 0x5555, 0x90);
  1106. *man_id = qla2x00_read_flash_byte(ha, 0x0000);
  1107. *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
  1108. qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
  1109. qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
  1110. qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
  1111. }
  1112. static inline void
  1113. qla2x00_suspend_hba(struct scsi_qla_host *ha)
  1114. {
  1115. int cnt;
  1116. unsigned long flags;
  1117. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1118. /* Suspend HBA. */
  1119. scsi_block_requests(ha->host);
  1120. ha->isp_ops.disable_intrs(ha);
  1121. set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
  1122. /* Pause RISC. */
  1123. spin_lock_irqsave(&ha->hardware_lock, flags);
  1124. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  1125. RD_REG_WORD(&reg->hccr);
  1126. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  1127. for (cnt = 0; cnt < 30000; cnt++) {
  1128. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  1129. break;
  1130. udelay(100);
  1131. }
  1132. } else {
  1133. udelay(10);
  1134. }
  1135. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1136. }
  1137. static inline void
  1138. qla2x00_resume_hba(struct scsi_qla_host *ha)
  1139. {
  1140. /* Resume HBA. */
  1141. clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
  1142. set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
  1143. qla2xxx_wake_dpc(ha);
  1144. qla2x00_wait_for_hba_online(ha);
  1145. scsi_unblock_requests(ha->host);
  1146. }
  1147. uint8_t *
  1148. qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
  1149. uint32_t offset, uint32_t length)
  1150. {
  1151. unsigned long flags;
  1152. uint32_t addr, midpoint;
  1153. uint8_t *data;
  1154. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1155. /* Suspend HBA. */
  1156. qla2x00_suspend_hba(ha);
  1157. /* Go with read. */
  1158. spin_lock_irqsave(&ha->hardware_lock, flags);
  1159. midpoint = ha->optrom_size / 2;
  1160. qla2x00_flash_enable(ha);
  1161. WRT_REG_WORD(&reg->nvram, 0);
  1162. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  1163. for (addr = offset, data = buf; addr < length; addr++, data++) {
  1164. if (addr == midpoint) {
  1165. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  1166. RD_REG_WORD(&reg->nvram); /* PCI Posting. */
  1167. }
  1168. *data = qla2x00_read_flash_byte(ha, addr);
  1169. }
  1170. qla2x00_flash_disable(ha);
  1171. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1172. /* Resume HBA. */
  1173. qla2x00_resume_hba(ha);
  1174. return buf;
  1175. }
  1176. int
  1177. qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
  1178. uint32_t offset, uint32_t length)
  1179. {
  1180. int rval;
  1181. unsigned long flags;
  1182. uint8_t man_id, flash_id, sec_number, data;
  1183. uint16_t wd;
  1184. uint32_t addr, liter, sec_mask, rest_addr;
  1185. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1186. /* Suspend HBA. */
  1187. qla2x00_suspend_hba(ha);
  1188. rval = QLA_SUCCESS;
  1189. sec_number = 0;
  1190. /* Reset ISP chip. */
  1191. spin_lock_irqsave(&ha->hardware_lock, flags);
  1192. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  1193. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  1194. /* Go with write. */
  1195. qla2x00_flash_enable(ha);
  1196. do { /* Loop once to provide quick error exit */
  1197. /* Structure of flash memory based on manufacturer */
  1198. if (IS_OEM_001(ha)) {
  1199. /* OEM variant with special flash part. */
  1200. man_id = flash_id = 0;
  1201. rest_addr = 0xffff;
  1202. sec_mask = 0x10000;
  1203. goto update_flash;
  1204. }
  1205. qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
  1206. switch (man_id) {
  1207. case 0x20: /* ST flash. */
  1208. if (flash_id == 0xd2 || flash_id == 0xe3) {
  1209. /*
  1210. * ST m29w008at part - 64kb sector size with
  1211. * 32kb,8kb,8kb,16kb sectors at memory address
  1212. * 0xf0000.
  1213. */
  1214. rest_addr = 0xffff;
  1215. sec_mask = 0x10000;
  1216. break;
  1217. }
  1218. /*
  1219. * ST m29w010b part - 16kb sector size
  1220. * Default to 16kb sectors
  1221. */
  1222. rest_addr = 0x3fff;
  1223. sec_mask = 0x1c000;
  1224. break;
  1225. case 0x40: /* Mostel flash. */
  1226. /* Mostel v29c51001 part - 512 byte sector size. */
  1227. rest_addr = 0x1ff;
  1228. sec_mask = 0x1fe00;
  1229. break;
  1230. case 0xbf: /* SST flash. */
  1231. /* SST39sf10 part - 4kb sector size. */
  1232. rest_addr = 0xfff;
  1233. sec_mask = 0x1f000;
  1234. break;
  1235. case 0xda: /* Winbond flash. */
  1236. /* Winbond W29EE011 part - 256 byte sector size. */
  1237. rest_addr = 0x7f;
  1238. sec_mask = 0x1ff80;
  1239. break;
  1240. case 0xc2: /* Macronix flash. */
  1241. /* 64k sector size. */
  1242. if (flash_id == 0x38 || flash_id == 0x4f) {
  1243. rest_addr = 0xffff;
  1244. sec_mask = 0x10000;
  1245. break;
  1246. }
  1247. /* Fall through... */
  1248. case 0x1f: /* Atmel flash. */
  1249. /* 512k sector size. */
  1250. if (flash_id == 0x13) {
  1251. rest_addr = 0x7fffffff;
  1252. sec_mask = 0x80000000;
  1253. break;
  1254. }
  1255. /* Fall through... */
  1256. case 0x01: /* AMD flash. */
  1257. if (flash_id == 0x38 || flash_id == 0x40 ||
  1258. flash_id == 0x4f) {
  1259. /* Am29LV081 part - 64kb sector size. */
  1260. /* Am29LV002BT part - 64kb sector size. */
  1261. rest_addr = 0xffff;
  1262. sec_mask = 0x10000;
  1263. break;
  1264. } else if (flash_id == 0x3e) {
  1265. /*
  1266. * Am29LV008b part - 64kb sector size with
  1267. * 32kb,8kb,8kb,16kb sector at memory address
  1268. * h0xf0000.
  1269. */
  1270. rest_addr = 0xffff;
  1271. sec_mask = 0x10000;
  1272. break;
  1273. } else if (flash_id == 0x20 || flash_id == 0x6e) {
  1274. /*
  1275. * Am29LV010 part or AM29f010 - 16kb sector
  1276. * size.
  1277. */
  1278. rest_addr = 0x3fff;
  1279. sec_mask = 0x1c000;
  1280. break;
  1281. } else if (flash_id == 0x6d) {
  1282. /* Am29LV001 part - 8kb sector size. */
  1283. rest_addr = 0x1fff;
  1284. sec_mask = 0x1e000;
  1285. break;
  1286. }
  1287. default:
  1288. /* Default to 16 kb sector size. */
  1289. rest_addr = 0x3fff;
  1290. sec_mask = 0x1c000;
  1291. break;
  1292. }
  1293. update_flash:
  1294. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  1295. if (qla2x00_erase_flash(ha, man_id, flash_id)) {
  1296. rval = QLA_FUNCTION_FAILED;
  1297. break;
  1298. }
  1299. }
  1300. for (addr = offset, liter = 0; liter < length; liter++,
  1301. addr++) {
  1302. data = buf[liter];
  1303. /* Are we at the beginning of a sector? */
  1304. if ((addr & rest_addr) == 0) {
  1305. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  1306. if (addr >= 0x10000UL) {
  1307. if (((addr >> 12) & 0xf0) &&
  1308. ((man_id == 0x01 &&
  1309. flash_id == 0x3e) ||
  1310. (man_id == 0x20 &&
  1311. flash_id == 0xd2))) {
  1312. sec_number++;
  1313. if (sec_number == 1) {
  1314. rest_addr =
  1315. 0x7fff;
  1316. sec_mask =
  1317. 0x18000;
  1318. } else if (
  1319. sec_number == 2 ||
  1320. sec_number == 3) {
  1321. rest_addr =
  1322. 0x1fff;
  1323. sec_mask =
  1324. 0x1e000;
  1325. } else if (
  1326. sec_number == 4) {
  1327. rest_addr =
  1328. 0x3fff;
  1329. sec_mask =
  1330. 0x1c000;
  1331. }
  1332. }
  1333. }
  1334. } else if (addr == ha->optrom_size / 2) {
  1335. WRT_REG_WORD(&reg->nvram, NVR_SELECT);
  1336. RD_REG_WORD(&reg->nvram);
  1337. }
  1338. if (flash_id == 0xda && man_id == 0xc1) {
  1339. qla2x00_write_flash_byte(ha, 0x5555,
  1340. 0xaa);
  1341. qla2x00_write_flash_byte(ha, 0x2aaa,
  1342. 0x55);
  1343. qla2x00_write_flash_byte(ha, 0x5555,
  1344. 0xa0);
  1345. } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
  1346. /* Then erase it */
  1347. if (qla2x00_erase_flash_sector(ha,
  1348. addr, sec_mask, man_id,
  1349. flash_id)) {
  1350. rval = QLA_FUNCTION_FAILED;
  1351. break;
  1352. }
  1353. if (man_id == 0x01 && flash_id == 0x6d)
  1354. sec_number++;
  1355. }
  1356. }
  1357. if (man_id == 0x01 && flash_id == 0x6d) {
  1358. if (sec_number == 1 &&
  1359. addr == (rest_addr - 1)) {
  1360. rest_addr = 0x0fff;
  1361. sec_mask = 0x1f000;
  1362. } else if (sec_number == 3 && (addr & 0x7ffe)) {
  1363. rest_addr = 0x3fff;
  1364. sec_mask = 0x1c000;
  1365. }
  1366. }
  1367. if (qla2x00_program_flash_address(ha, addr, data,
  1368. man_id, flash_id)) {
  1369. rval = QLA_FUNCTION_FAILED;
  1370. break;
  1371. }
  1372. }
  1373. } while (0);
  1374. qla2x00_flash_disable(ha);
  1375. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1376. /* Resume HBA. */
  1377. qla2x00_resume_hba(ha);
  1378. return rval;
  1379. }
  1380. uint8_t *
  1381. qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
  1382. uint32_t offset, uint32_t length)
  1383. {
  1384. /* Suspend HBA. */
  1385. scsi_block_requests(ha->host);
  1386. ha->isp_ops.disable_intrs(ha);
  1387. set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
  1388. /* Go with read. */
  1389. qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
  1390. /* Resume HBA. */
  1391. clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
  1392. ha->isp_ops.enable_intrs(ha);
  1393. scsi_unblock_requests(ha->host);
  1394. return buf;
  1395. }
  1396. int
  1397. qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
  1398. uint32_t offset, uint32_t length)
  1399. {
  1400. int rval;
  1401. /* Suspend HBA. */
  1402. scsi_block_requests(ha->host);
  1403. ha->isp_ops.disable_intrs(ha);
  1404. set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
  1405. /* Go with write. */
  1406. rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
  1407. length >> 2);
  1408. /* Resume HBA -- RISC reset needed. */
  1409. clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
  1410. set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
  1411. qla2xxx_wake_dpc(ha);
  1412. qla2x00_wait_for_hba_online(ha);
  1413. scsi_unblock_requests(ha->host);
  1414. return rval;
  1415. }