lpfc_mbox.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653
  1. /*******************************************************************
  2. * This file is part of the Emulex Linux Device Driver for *
  3. * Fibre Channel Host Bus Adapters. *
  4. * Copyright (C) 2004-2006 Emulex. All rights reserved. *
  5. * EMULEX and SLI are trademarks of Emulex. *
  6. * www.emulex.com *
  7. * Portions Copyright (C) 2004-2005 Christoph Hellwig *
  8. * *
  9. * This program is free software; you can redistribute it and/or *
  10. * modify it under the terms of version 2 of the GNU General *
  11. * Public License as published by the Free Software Foundation. *
  12. * This program is distributed in the hope that it will be useful. *
  13. * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
  14. * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
  15. * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
  16. * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  17. * TO BE LEGALLY INVALID. See the GNU General Public License for *
  18. * more details, a copy of which can be found in the file COPYING *
  19. * included with this package. *
  20. *******************************************************************/
  21. #include <linux/blkdev.h>
  22. #include <linux/pci.h>
  23. #include <linux/interrupt.h>
  24. #include <scsi/scsi_device.h>
  25. #include <scsi/scsi_transport_fc.h>
  26. #include <scsi/scsi.h>
  27. #include "lpfc_hw.h"
  28. #include "lpfc_sli.h"
  29. #include "lpfc_disc.h"
  30. #include "lpfc_scsi.h"
  31. #include "lpfc.h"
  32. #include "lpfc_logmsg.h"
  33. #include "lpfc_crtn.h"
  34. #include "lpfc_compat.h"
  35. /**********************************************/
  36. /* mailbox command */
  37. /**********************************************/
  38. void
  39. lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset)
  40. {
  41. MAILBOX_t *mb;
  42. void *ctx;
  43. mb = &pmb->mb;
  44. ctx = pmb->context2;
  45. /* Setup to dump VPD region */
  46. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  47. mb->mbxCommand = MBX_DUMP_MEMORY;
  48. mb->un.varDmp.cv = 1;
  49. mb->un.varDmp.type = DMP_NV_PARAMS;
  50. mb->un.varDmp.entry_index = offset;
  51. mb->un.varDmp.region_id = DMP_REGION_VPD;
  52. mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t));
  53. mb->un.varDmp.co = 0;
  54. mb->un.varDmp.resp_offset = 0;
  55. pmb->context2 = ctx;
  56. mb->mbxOwner = OWN_HOST;
  57. return;
  58. }
  59. /**********************************************/
  60. /* lpfc_read_nv Issue a READ NVPARAM */
  61. /* mailbox command */
  62. /**********************************************/
  63. void
  64. lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  65. {
  66. MAILBOX_t *mb;
  67. mb = &pmb->mb;
  68. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  69. mb->mbxCommand = MBX_READ_NV;
  70. mb->mbxOwner = OWN_HOST;
  71. return;
  72. }
  73. /**********************************************/
  74. /* lpfc_read_la Issue a READ LA */
  75. /* mailbox command */
  76. /**********************************************/
  77. int
  78. lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp)
  79. {
  80. MAILBOX_t *mb;
  81. struct lpfc_sli *psli;
  82. psli = &phba->sli;
  83. mb = &pmb->mb;
  84. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  85. INIT_LIST_HEAD(&mp->list);
  86. mb->mbxCommand = MBX_READ_LA64;
  87. mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128;
  88. mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys);
  89. mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys);
  90. /* Save address for later completion and set the owner to host so that
  91. * the FW knows this mailbox is available for processing.
  92. */
  93. pmb->context1 = (uint8_t *) mp;
  94. mb->mbxOwner = OWN_HOST;
  95. return (0);
  96. }
  97. /**********************************************/
  98. /* lpfc_clear_la Issue a CLEAR LA */
  99. /* mailbox command */
  100. /**********************************************/
  101. void
  102. lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  103. {
  104. MAILBOX_t *mb;
  105. mb = &pmb->mb;
  106. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  107. mb->un.varClearLA.eventTag = phba->fc_eventTag;
  108. mb->mbxCommand = MBX_CLEAR_LA;
  109. mb->mbxOwner = OWN_HOST;
  110. return;
  111. }
  112. /**************************************************/
  113. /* lpfc_config_link Issue a CONFIG LINK */
  114. /* mailbox command */
  115. /**************************************************/
  116. void
  117. lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  118. {
  119. MAILBOX_t *mb = &pmb->mb;
  120. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  121. /* NEW_FEATURE
  122. * SLI-2, Coalescing Response Feature.
  123. */
  124. if (phba->cfg_cr_delay) {
  125. mb->un.varCfgLnk.cr = 1;
  126. mb->un.varCfgLnk.ci = 1;
  127. mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay;
  128. mb->un.varCfgLnk.cr_count = phba->cfg_cr_count;
  129. }
  130. mb->un.varCfgLnk.myId = phba->fc_myDID;
  131. mb->un.varCfgLnk.edtov = phba->fc_edtov;
  132. mb->un.varCfgLnk.arbtov = phba->fc_arbtov;
  133. mb->un.varCfgLnk.ratov = phba->fc_ratov;
  134. mb->un.varCfgLnk.rttov = phba->fc_rttov;
  135. mb->un.varCfgLnk.altov = phba->fc_altov;
  136. mb->un.varCfgLnk.crtov = phba->fc_crtov;
  137. mb->un.varCfgLnk.citov = phba->fc_citov;
  138. if (phba->cfg_ack0)
  139. mb->un.varCfgLnk.ack0_enable = 1;
  140. mb->mbxCommand = MBX_CONFIG_LINK;
  141. mb->mbxOwner = OWN_HOST;
  142. return;
  143. }
  144. /**********************************************/
  145. /* lpfc_init_link Issue an INIT LINK */
  146. /* mailbox command */
  147. /**********************************************/
  148. void
  149. lpfc_init_link(struct lpfc_hba * phba,
  150. LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed)
  151. {
  152. lpfc_vpd_t *vpd;
  153. struct lpfc_sli *psli;
  154. MAILBOX_t *mb;
  155. mb = &pmb->mb;
  156. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  157. psli = &phba->sli;
  158. switch (topology) {
  159. case FLAGS_TOPOLOGY_MODE_LOOP_PT:
  160. mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP;
  161. mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER;
  162. break;
  163. case FLAGS_TOPOLOGY_MODE_PT_PT:
  164. mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT;
  165. break;
  166. case FLAGS_TOPOLOGY_MODE_LOOP:
  167. mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP;
  168. break;
  169. case FLAGS_TOPOLOGY_MODE_PT_LOOP:
  170. mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT;
  171. mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER;
  172. break;
  173. case FLAGS_LOCAL_LB:
  174. mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB;
  175. break;
  176. }
  177. /* Enable asynchronous ABTS responses from firmware */
  178. mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT;
  179. /* NEW_FEATURE
  180. * Setting up the link speed
  181. */
  182. vpd = &phba->vpd;
  183. if (vpd->rev.feaLevelHigh >= 0x02){
  184. switch(linkspeed){
  185. case LINK_SPEED_1G:
  186. case LINK_SPEED_2G:
  187. case LINK_SPEED_4G:
  188. mb->un.varInitLnk.link_flags |=
  189. FLAGS_LINK_SPEED;
  190. mb->un.varInitLnk.link_speed = linkspeed;
  191. break;
  192. case LINK_SPEED_AUTO:
  193. default:
  194. mb->un.varInitLnk.link_speed =
  195. LINK_SPEED_AUTO;
  196. break;
  197. }
  198. }
  199. else
  200. mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO;
  201. mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK;
  202. mb->mbxOwner = OWN_HOST;
  203. mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA;
  204. return;
  205. }
  206. /**********************************************/
  207. /* lpfc_read_sparam Issue a READ SPARAM */
  208. /* mailbox command */
  209. /**********************************************/
  210. int
  211. lpfc_read_sparam(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  212. {
  213. struct lpfc_dmabuf *mp;
  214. MAILBOX_t *mb;
  215. struct lpfc_sli *psli;
  216. psli = &phba->sli;
  217. mb = &pmb->mb;
  218. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  219. mb->mbxOwner = OWN_HOST;
  220. /* Get a buffer to hold the HBAs Service Parameters */
  221. if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) ||
  222. ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) {
  223. kfree(mp);
  224. mb->mbxCommand = MBX_READ_SPARM64;
  225. /* READ_SPARAM: no buffers */
  226. lpfc_printf_log(phba,
  227. KERN_WARNING,
  228. LOG_MBOX,
  229. "%d:0301 READ_SPARAM: no buffers\n",
  230. phba->brd_no);
  231. return (1);
  232. }
  233. INIT_LIST_HEAD(&mp->list);
  234. mb->mbxCommand = MBX_READ_SPARM64;
  235. mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm);
  236. mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys);
  237. mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys);
  238. /* save address for completion */
  239. pmb->context1 = mp;
  240. return (0);
  241. }
  242. /********************************************/
  243. /* lpfc_unreg_did Issue a UNREG_DID */
  244. /* mailbox command */
  245. /********************************************/
  246. void
  247. lpfc_unreg_did(struct lpfc_hba * phba, uint32_t did, LPFC_MBOXQ_t * pmb)
  248. {
  249. MAILBOX_t *mb;
  250. mb = &pmb->mb;
  251. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  252. mb->un.varUnregDID.did = did;
  253. mb->mbxCommand = MBX_UNREG_D_ID;
  254. mb->mbxOwner = OWN_HOST;
  255. return;
  256. }
  257. /**********************************************/
  258. /* lpfc_read_nv Issue a READ CONFIG */
  259. /* mailbox command */
  260. /**********************************************/
  261. void
  262. lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  263. {
  264. MAILBOX_t *mb;
  265. mb = &pmb->mb;
  266. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  267. mb->mbxCommand = MBX_READ_CONFIG;
  268. mb->mbxOwner = OWN_HOST;
  269. return;
  270. }
  271. /*************************************************/
  272. /* lpfc_read_lnk_stat Issue a READ LINK STATUS */
  273. /* mailbox command */
  274. /*************************************************/
  275. void
  276. lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  277. {
  278. MAILBOX_t *mb;
  279. mb = &pmb->mb;
  280. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  281. mb->mbxCommand = MBX_READ_LNK_STAT;
  282. mb->mbxOwner = OWN_HOST;
  283. return;
  284. }
  285. /********************************************/
  286. /* lpfc_reg_login Issue a REG_LOGIN */
  287. /* mailbox command */
  288. /********************************************/
  289. int
  290. lpfc_reg_login(struct lpfc_hba * phba,
  291. uint32_t did, uint8_t * param, LPFC_MBOXQ_t * pmb, uint32_t flag)
  292. {
  293. uint8_t *sparam;
  294. struct lpfc_dmabuf *mp;
  295. MAILBOX_t *mb;
  296. struct lpfc_sli *psli;
  297. psli = &phba->sli;
  298. mb = &pmb->mb;
  299. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  300. mb->un.varRegLogin.rpi = 0;
  301. mb->un.varRegLogin.did = did;
  302. mb->un.varWords[30] = flag; /* Set flag to issue action on cmpl */
  303. mb->mbxOwner = OWN_HOST;
  304. /* Get a buffer to hold NPorts Service Parameters */
  305. if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) ||
  306. ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) {
  307. kfree(mp);
  308. mb->mbxCommand = MBX_REG_LOGIN64;
  309. /* REG_LOGIN: no buffers */
  310. lpfc_printf_log(phba,
  311. KERN_WARNING,
  312. LOG_MBOX,
  313. "%d:0302 REG_LOGIN: no buffers Data x%x x%x\n",
  314. phba->brd_no,
  315. (uint32_t) did, (uint32_t) flag);
  316. return (1);
  317. }
  318. INIT_LIST_HEAD(&mp->list);
  319. sparam = mp->virt;
  320. /* Copy param's into a new buffer */
  321. memcpy(sparam, param, sizeof (struct serv_parm));
  322. /* save address for completion */
  323. pmb->context1 = (uint8_t *) mp;
  324. mb->mbxCommand = MBX_REG_LOGIN64;
  325. mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm);
  326. mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys);
  327. mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys);
  328. return (0);
  329. }
  330. /**********************************************/
  331. /* lpfc_unreg_login Issue a UNREG_LOGIN */
  332. /* mailbox command */
  333. /**********************************************/
  334. void
  335. lpfc_unreg_login(struct lpfc_hba * phba, uint32_t rpi, LPFC_MBOXQ_t * pmb)
  336. {
  337. MAILBOX_t *mb;
  338. mb = &pmb->mb;
  339. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  340. mb->un.varUnregLogin.rpi = (uint16_t) rpi;
  341. mb->un.varUnregLogin.rsvd1 = 0;
  342. mb->mbxCommand = MBX_UNREG_LOGIN;
  343. mb->mbxOwner = OWN_HOST;
  344. return;
  345. }
  346. static void
  347. lpfc_config_pcb_setup(struct lpfc_hba * phba)
  348. {
  349. struct lpfc_sli *psli = &phba->sli;
  350. struct lpfc_sli_ring *pring;
  351. PCB_t *pcbp = &phba->slim2p->pcb;
  352. dma_addr_t pdma_addr;
  353. uint32_t offset;
  354. uint32_t iocbCnt;
  355. int i;
  356. pcbp->maxRing = (psli->num_rings - 1);
  357. iocbCnt = 0;
  358. for (i = 0; i < psli->num_rings; i++) {
  359. pring = &psli->ring[i];
  360. /* A ring MUST have both cmd and rsp entries defined to be
  361. valid */
  362. if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) {
  363. pcbp->rdsc[i].cmdEntries = 0;
  364. pcbp->rdsc[i].rspEntries = 0;
  365. pcbp->rdsc[i].cmdAddrHigh = 0;
  366. pcbp->rdsc[i].rspAddrHigh = 0;
  367. pcbp->rdsc[i].cmdAddrLow = 0;
  368. pcbp->rdsc[i].rspAddrLow = 0;
  369. pring->cmdringaddr = NULL;
  370. pring->rspringaddr = NULL;
  371. continue;
  372. }
  373. /* Command ring setup for ring */
  374. pring->cmdringaddr =
  375. (void *)&phba->slim2p->IOCBs[iocbCnt];
  376. pcbp->rdsc[i].cmdEntries = pring->numCiocb;
  377. offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] -
  378. (uint8_t *)phba->slim2p;
  379. pdma_addr = phba->slim2p_mapping + offset;
  380. pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr);
  381. pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr);
  382. iocbCnt += pring->numCiocb;
  383. /* Response ring setup for ring */
  384. pring->rspringaddr =
  385. (void *)&phba->slim2p->IOCBs[iocbCnt];
  386. pcbp->rdsc[i].rspEntries = pring->numRiocb;
  387. offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] -
  388. (uint8_t *)phba->slim2p;
  389. pdma_addr = phba->slim2p_mapping + offset;
  390. pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr);
  391. pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr);
  392. iocbCnt += pring->numRiocb;
  393. }
  394. }
  395. void
  396. lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  397. {
  398. MAILBOX_t *mb;
  399. mb = &pmb->mb;
  400. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  401. mb->un.varRdRev.cv = 1;
  402. mb->mbxCommand = MBX_READ_REV;
  403. mb->mbxOwner = OWN_HOST;
  404. return;
  405. }
  406. void
  407. lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb)
  408. {
  409. int i;
  410. MAILBOX_t *mb = &pmb->mb;
  411. struct lpfc_sli *psli;
  412. struct lpfc_sli_ring *pring;
  413. memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  414. mb->un.varCfgRing.ring = ring;
  415. mb->un.varCfgRing.maxOrigXchg = 0;
  416. mb->un.varCfgRing.maxRespXchg = 0;
  417. mb->un.varCfgRing.recvNotify = 1;
  418. psli = &phba->sli;
  419. pring = &psli->ring[ring];
  420. mb->un.varCfgRing.numMask = pring->num_mask;
  421. mb->mbxCommand = MBX_CONFIG_RING;
  422. mb->mbxOwner = OWN_HOST;
  423. /* Is this ring configured for a specific profile */
  424. if (pring->prt[0].profile) {
  425. mb->un.varCfgRing.profile = pring->prt[0].profile;
  426. return;
  427. }
  428. /* Otherwise we setup specific rctl / type masks for this ring */
  429. for (i = 0; i < pring->num_mask; i++) {
  430. mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl;
  431. if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ)
  432. mb->un.varCfgRing.rrRegs[i].rmask = 0xff;
  433. else
  434. mb->un.varCfgRing.rrRegs[i].rmask = 0xfe;
  435. mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type;
  436. mb->un.varCfgRing.rrRegs[i].tmask = 0xff;
  437. }
  438. return;
  439. }
  440. void
  441. lpfc_config_port(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  442. {
  443. MAILBOX_t *mb = &pmb->mb;
  444. dma_addr_t pdma_addr;
  445. uint32_t bar_low, bar_high;
  446. size_t offset;
  447. struct lpfc_hgp hgp;
  448. void __iomem *to_slim;
  449. int i;
  450. memset(pmb, 0, sizeof(LPFC_MBOXQ_t));
  451. mb->mbxCommand = MBX_CONFIG_PORT;
  452. mb->mbxOwner = OWN_HOST;
  453. mb->un.varCfgPort.pcbLen = sizeof(PCB_t);
  454. offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p;
  455. pdma_addr = phba->slim2p_mapping + offset;
  456. mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr);
  457. mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr);
  458. /* Now setup pcb */
  459. phba->slim2p->pcb.type = TYPE_NATIVE_SLI2;
  460. phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2;
  461. /* Setup Mailbox pointers */
  462. phba->slim2p->pcb.mailBoxSize = sizeof(MAILBOX_t);
  463. offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p;
  464. pdma_addr = phba->slim2p_mapping + offset;
  465. phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr);
  466. phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr);
  467. /*
  468. * Setup Host Group ring pointer.
  469. *
  470. * For efficiency reasons, the ring get/put pointers can be
  471. * placed in adapter memory (SLIM) rather than in host memory.
  472. * This allows firmware to avoid PCI reads/writes when updating
  473. * and checking pointers.
  474. *
  475. * The firmware recognizes the use of SLIM memory by comparing
  476. * the address of the get/put pointers structure with that of
  477. * the SLIM BAR (BAR0).
  478. *
  479. * Caution: be sure to use the PCI config space value of BAR0/BAR1
  480. * (the hardware's view of the base address), not the OS's
  481. * value of pci_resource_start() as the OS value may be a cookie
  482. * for ioremap/iomap.
  483. */
  484. pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low);
  485. pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high);
  486. /* mask off BAR0's flag bits 0 - 3 */
  487. phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) +
  488. (SLIMOFF*sizeof(uint32_t));
  489. if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64)
  490. phba->slim2p->pcb.hgpAddrHigh = bar_high;
  491. else
  492. phba->slim2p->pcb.hgpAddrHigh = 0;
  493. /* write HGP data to SLIM at the required longword offset */
  494. memset(&hgp, 0, sizeof(struct lpfc_hgp));
  495. to_slim = phba->MBslimaddr + (SLIMOFF*sizeof (uint32_t));
  496. for (i=0; i < phba->sli.num_rings; i++) {
  497. lpfc_memcpy_to_slim(to_slim, &hgp, sizeof(struct lpfc_hgp));
  498. to_slim += sizeof (struct lpfc_hgp);
  499. }
  500. /* Setup Port Group ring pointer */
  501. offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port -
  502. (uint8_t *)phba->slim2p;
  503. pdma_addr = phba->slim2p_mapping + offset;
  504. phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr);
  505. phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr);
  506. /* Use callback routine to setp rings in the pcb */
  507. lpfc_config_pcb_setup(phba);
  508. /* special handling for LC HBAs */
  509. if (lpfc_is_LC_HBA(phba->pcidev->device)) {
  510. uint32_t hbainit[5];
  511. lpfc_hba_init(phba, hbainit);
  512. memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20);
  513. }
  514. /* Swap PCB if needed */
  515. lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb,
  516. sizeof (PCB_t));
  517. lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
  518. "%d:0405 Service Level Interface (SLI) 2 selected\n",
  519. phba->brd_no);
  520. }
  521. void
  522. lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  523. {
  524. MAILBOX_t *mb = &pmb->mb;
  525. memset(pmb, 0, sizeof(LPFC_MBOXQ_t));
  526. mb->mbxCommand = MBX_KILL_BOARD;
  527. mb->mbxOwner = OWN_HOST;
  528. return;
  529. }
  530. void
  531. lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq)
  532. {
  533. struct lpfc_sli *psli;
  534. psli = &phba->sli;
  535. list_add_tail(&mbq->list, &psli->mboxq);
  536. psli->mboxq_cnt++;
  537. return;
  538. }
  539. LPFC_MBOXQ_t *
  540. lpfc_mbox_get(struct lpfc_hba * phba)
  541. {
  542. LPFC_MBOXQ_t *mbq = NULL;
  543. struct lpfc_sli *psli = &phba->sli;
  544. list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t,
  545. list);
  546. if (mbq) {
  547. psli->mboxq_cnt--;
  548. }
  549. return mbq;
  550. }