initio.c 94 KB

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  1. /**************************************************************************
  2. * Initio 9100 device driver for Linux.
  3. *
  4. * Copyright (c) 1994-1998 Initio Corporation
  5. * Copyright (c) 1998 Bas Vermeulen <bvermeul@blackstar.xs4all.nl>
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2, or (at your option)
  11. * any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; see the file COPYING. If not, write to
  20. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  21. *
  22. * --------------------------------------------------------------------------
  23. *
  24. * Redistribution and use in source and binary forms, with or without
  25. * modification, are permitted provided that the following conditions
  26. * are met:
  27. * 1. Redistributions of source code must retain the above copyright
  28. * notice, this list of conditions, and the following disclaimer,
  29. * without modification, immediately at the beginning of the file.
  30. * 2. Redistributions in binary form must reproduce the above copyright
  31. * notice, this list of conditions and the following disclaimer in the
  32. * documentation and/or other materials provided with the distribution.
  33. * 3. The name of the author may not be used to endorse or promote products
  34. * derived from this software without specific prior written permission.
  35. *
  36. * Where this Software is combined with software released under the terms of
  37. * the GNU General Public License ("GPL") and the terms of the GPL would require the
  38. * combined work to also be released under the terms of the GPL, the terms
  39. * and conditions of this License will apply in addition to those of the
  40. * GPL with the exception of any terms or conditions of this License that
  41. * conflict with, or are expressly prohibited by, the GPL.
  42. *
  43. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  44. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  45. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  46. * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  47. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  48. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  49. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  50. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  51. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  52. * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  53. * SUCH DAMAGE.
  54. *
  55. *************************************************************************
  56. *
  57. * DESCRIPTION:
  58. *
  59. * This is the Linux low-level SCSI driver for Initio INI-9X00U/UW SCSI host
  60. * adapters
  61. *
  62. * 08/06/97 hc - v1.01h
  63. * - Support inic-940 and inic-935
  64. * 09/26/97 hc - v1.01i
  65. * - Make correction from J.W. Schultz suggestion
  66. * 10/13/97 hc - Support reset function
  67. * 10/21/97 hc - v1.01j
  68. * - Support 32 LUN (SCSI 3)
  69. * 01/14/98 hc - v1.01k
  70. * - Fix memory allocation problem
  71. * 03/04/98 hc - v1.01l
  72. * - Fix tape rewind which will hang the system problem
  73. * - Set can_queue to tul_num_scb
  74. * 06/25/98 hc - v1.01m
  75. * - Get it work for kernel version >= 2.1.75
  76. * - Dynamic assign SCSI bus reset holding time in init_tulip()
  77. * 07/02/98 hc - v1.01n
  78. * - Support 0002134A
  79. * 08/07/98 hc - v1.01o
  80. * - Change the tul_abort_srb routine to use scsi_done. <01>
  81. * 09/07/98 hl - v1.02
  82. * - Change the INI9100U define and proc_dir_entry to
  83. * reflect the newer Kernel 2.1.118, but the v1.o1o
  84. * should work with Kernel 2.1.118.
  85. * 09/20/98 wh - v1.02a
  86. * - Support Abort command.
  87. * - Handle reset routine.
  88. * 09/21/98 hl - v1.03
  89. * - remove comments.
  90. * 12/09/98 bv - v1.03a
  91. * - Removed unused code
  92. * 12/13/98 bv - v1.03b
  93. * - Remove cli() locking for kernels >= 2.1.95. This uses
  94. * spinlocks to serialize access to the pSRB_head and
  95. * pSRB_tail members of the HCS structure.
  96. * 09/01/99 bv - v1.03d
  97. * - Fixed a deadlock problem in SMP.
  98. * 21/01/99 bv - v1.03e
  99. * - Add support for the Domex 3192U PCI SCSI
  100. * This is a slightly modified patch by
  101. * Brian Macy <bmacy@sunshinecomputing.com>
  102. * 22/02/99 bv - v1.03f
  103. * - Didn't detect the INIC-950 in 2.0.x correctly.
  104. * Now fixed.
  105. * 05/07/99 bv - v1.03g
  106. * - Changed the assumption that HZ = 100
  107. * 10/17/03 mc - v1.04
  108. * - added new DMA API support
  109. * 06/01/04 jmd - v1.04a
  110. * - Re-add reset_bus support
  111. **************************************************************************/
  112. #include <linux/module.h>
  113. #include <linux/errno.h>
  114. #include <linux/delay.h>
  115. #include <linux/pci.h>
  116. #include <linux/init.h>
  117. #include <linux/blkdev.h>
  118. #include <linux/spinlock.h>
  119. #include <linux/stat.h>
  120. #include <linux/config.h>
  121. #include <linux/kernel.h>
  122. #include <linux/proc_fs.h>
  123. #include <linux/string.h>
  124. #include <linux/interrupt.h>
  125. #include <linux/ioport.h>
  126. #include <linux/sched.h>
  127. #include <linux/slab.h>
  128. #include <linux/jiffies.h>
  129. #include <linux/dma-mapping.h>
  130. #include <asm/io.h>
  131. #include <scsi/scsi.h>
  132. #include <scsi/scsi_cmnd.h>
  133. #include <scsi/scsi_device.h>
  134. #include <scsi/scsi_host.h>
  135. #include <scsi/scsi_tcq.h>
  136. #include "initio.h"
  137. #define SENSE_SIZE 14
  138. #define i91u_MAXQUEUE 2
  139. #define i91u_REVID "Initio INI-9X00U/UW SCSI device driver; Revision: 1.04a"
  140. #define INI_VENDOR_ID 0x1101 /* Initio's PCI vendor ID */
  141. #define DMX_VENDOR_ID 0x134a /* Domex's PCI vendor ID */
  142. #define I950_DEVICE_ID 0x9500 /* Initio's inic-950 product ID */
  143. #define I940_DEVICE_ID 0x9400 /* Initio's inic-940 product ID */
  144. #define I935_DEVICE_ID 0x9401 /* Initio's inic-935 product ID */
  145. #define I920_DEVICE_ID 0x0002 /* Initio's other product ID */
  146. #ifdef DEBUG_i91u
  147. static unsigned int i91u_debug = DEBUG_DEFAULT;
  148. #endif
  149. #define TULSZ(sz) (sizeof(sz) / sizeof(sz[0]))
  150. #define TUL_RDWORD(x,y) (short)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
  151. typedef struct PCI_ID_Struc {
  152. unsigned short vendor_id;
  153. unsigned short device_id;
  154. } PCI_ID;
  155. static int tul_num_ch = 4; /* Maximum 4 adapters */
  156. static int tul_num_scb;
  157. static int tul_tag_enable = 1;
  158. static SCB *tul_scb;
  159. #ifdef DEBUG_i91u
  160. static int setup_debug = 0;
  161. #endif
  162. static void i91uSCBPost(BYTE * pHcb, BYTE * pScb);
  163. static const PCI_ID i91u_pci_devices[] = {
  164. { INI_VENDOR_ID, I950_DEVICE_ID },
  165. { INI_VENDOR_ID, I940_DEVICE_ID },
  166. { INI_VENDOR_ID, I935_DEVICE_ID },
  167. { INI_VENDOR_ID, I920_DEVICE_ID },
  168. { DMX_VENDOR_ID, I920_DEVICE_ID },
  169. };
  170. #define DEBUG_INTERRUPT 0
  171. #define DEBUG_QUEUE 0
  172. #define DEBUG_STATE 0
  173. #define INT_DISC 0
  174. /*--- external functions --*/
  175. static void tul_se2_wait(void);
  176. /*--- forward refrence ---*/
  177. static SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun);
  178. static SCB *tul_find_done_scb(HCS * pCurHcb);
  179. static int tulip_main(HCS * pCurHcb);
  180. static int tul_next_state(HCS * pCurHcb);
  181. static int tul_state_1(HCS * pCurHcb);
  182. static int tul_state_2(HCS * pCurHcb);
  183. static int tul_state_3(HCS * pCurHcb);
  184. static int tul_state_4(HCS * pCurHcb);
  185. static int tul_state_5(HCS * pCurHcb);
  186. static int tul_state_6(HCS * pCurHcb);
  187. static int tul_state_7(HCS * pCurHcb);
  188. static int tul_xfer_data_in(HCS * pCurHcb);
  189. static int tul_xfer_data_out(HCS * pCurHcb);
  190. static int tul_xpad_in(HCS * pCurHcb);
  191. static int tul_xpad_out(HCS * pCurHcb);
  192. static int tul_status_msg(HCS * pCurHcb);
  193. static int tul_msgin(HCS * pCurHcb);
  194. static int tul_msgin_sync(HCS * pCurHcb);
  195. static int tul_msgin_accept(HCS * pCurHcb);
  196. static int tul_msgout_reject(HCS * pCurHcb);
  197. static int tul_msgin_extend(HCS * pCurHcb);
  198. static int tul_msgout_ide(HCS * pCurHcb);
  199. static int tul_msgout_abort_targ(HCS * pCurHcb);
  200. static int tul_msgout_abort_tag(HCS * pCurHcb);
  201. static int tul_bus_device_reset(HCS * pCurHcb);
  202. static void tul_select_atn(HCS * pCurHcb, SCB * pCurScb);
  203. static void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb);
  204. static void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb);
  205. static int int_tul_busfree(HCS * pCurHcb);
  206. static int int_tul_scsi_rst(HCS * pCurHcb);
  207. static int int_tul_bad_seq(HCS * pCurHcb);
  208. static int int_tul_resel(HCS * pCurHcb);
  209. static int tul_sync_done(HCS * pCurHcb);
  210. static int wdtr_done(HCS * pCurHcb);
  211. static int wait_tulip(HCS * pCurHcb);
  212. static int tul_wait_done_disc(HCS * pCurHcb);
  213. static int tul_wait_disc(HCS * pCurHcb);
  214. static void tulip_scsi(HCS * pCurHcb);
  215. static int tul_post_scsi_rst(HCS * pCurHcb);
  216. static void tul_se2_ew_en(WORD CurBase);
  217. static void tul_se2_ew_ds(WORD CurBase);
  218. static int tul_se2_rd_all(WORD CurBase);
  219. static void tul_se2_update_all(WORD CurBase); /* setup default pattern */
  220. static void tul_read_eeprom(WORD CurBase);
  221. /* ---- INTERNAL VARIABLES ---- */
  222. static HCS tul_hcs[MAX_SUPPORTED_ADAPTERS];
  223. static INI_ADPT_STRUCT i91u_adpt[MAX_SUPPORTED_ADAPTERS];
  224. /*NVRAM nvram, *nvramp = &nvram; */
  225. static NVRAM i91unvram;
  226. static NVRAM *i91unvramp;
  227. static UCHAR i91udftNvRam[64] =
  228. {
  229. /*----------- header -----------*/
  230. 0x25, 0xc9, /* Signature */
  231. 0x40, /* Size */
  232. 0x01, /* Revision */
  233. /* -- Host Adapter Structure -- */
  234. 0x95, /* ModelByte0 */
  235. 0x00, /* ModelByte1 */
  236. 0x00, /* ModelInfo */
  237. 0x01, /* NumOfCh */
  238. NBC1_DEFAULT, /* BIOSConfig1 */
  239. 0, /* BIOSConfig2 */
  240. 0, /* HAConfig1 */
  241. 0, /* HAConfig2 */
  242. /* SCSI channel 0 and target Structure */
  243. 7, /* SCSIid */
  244. NCC1_DEFAULT, /* SCSIconfig1 */
  245. 0, /* SCSIconfig2 */
  246. 0x10, /* NumSCSItarget */
  247. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  248. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  249. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  250. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  251. /* SCSI channel 1 and target Structure */
  252. 7, /* SCSIid */
  253. NCC1_DEFAULT, /* SCSIconfig1 */
  254. 0, /* SCSIconfig2 */
  255. 0x10, /* NumSCSItarget */
  256. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  257. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  258. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  259. NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT, NTC_DEFAULT,
  260. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  261. 0, 0}; /* - CheckSum - */
  262. static UCHAR tul_rate_tbl[8] = /* fast 20 */
  263. {
  264. /* nanosecond devide by 4 */
  265. 12, /* 50ns, 20M */
  266. 18, /* 75ns, 13.3M */
  267. 25, /* 100ns, 10M */
  268. 31, /* 125ns, 8M */
  269. 37, /* 150ns, 6.6M */
  270. 43, /* 175ns, 5.7M */
  271. 50, /* 200ns, 5M */
  272. 62 /* 250ns, 4M */
  273. };
  274. static void tul_do_pause(unsigned amount)
  275. { /* Pause for amount jiffies */
  276. unsigned long the_time = jiffies + amount;
  277. while (time_before_eq(jiffies, the_time));
  278. }
  279. /*-- forward reference --*/
  280. /*******************************************************************
  281. Use memeory refresh time ~ 15us * 2
  282. ********************************************************************/
  283. void tul_se2_wait(void)
  284. {
  285. #if 1
  286. udelay(30);
  287. #else
  288. UCHAR readByte;
  289. readByte = TUL_RD(0, 0x61);
  290. if ((readByte & 0x10) == 0x10) {
  291. for (;;) {
  292. readByte = TUL_RD(0, 0x61);
  293. if ((readByte & 0x10) == 0x10)
  294. break;
  295. }
  296. for (;;) {
  297. readByte = TUL_RD(0, 0x61);
  298. if ((readByte & 0x10) != 0x10)
  299. break;
  300. }
  301. } else {
  302. for (;;) {
  303. readByte = TUL_RD(0, 0x61);
  304. if ((readByte & 0x10) == 0x10)
  305. break;
  306. }
  307. for (;;) {
  308. readByte = TUL_RD(0, 0x61);
  309. if ((readByte & 0x10) != 0x10)
  310. break;
  311. }
  312. }
  313. #endif
  314. }
  315. /******************************************************************
  316. Input: instruction for Serial E2PROM
  317. EX: se2_rd(0 call se2_instr() to send address and read command
  318. StartBit OP_Code Address Data
  319. --------- -------- ------------------ -------
  320. 1 1 , 0 A5,A4,A3,A2,A1,A0 D15-D0
  321. +-----------------------------------------------------
  322. |
  323. CS -----+
  324. +--+ +--+ +--+ +--+ +--+
  325. ^ | ^ | ^ | ^ | ^ |
  326. | | | | | | | | | |
  327. CLK -------+ +--+ +--+ +--+ +--+ +--
  328. (leading edge trigger)
  329. +--1-----1--+
  330. | SB OP | OP A5 A4
  331. DI ----+ +--0------------------
  332. (address and cmd sent to nvram)
  333. -------------------------------------------+
  334. |
  335. DO +---
  336. (data sent from nvram)
  337. ******************************************************************/
  338. static void tul_se2_instr(WORD CurBase, UCHAR instr)
  339. {
  340. int i;
  341. UCHAR b;
  342. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* cs+start bit */
  343. tul_se2_wait();
  344. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK | SE2DO); /* +CLK */
  345. tul_se2_wait();
  346. for (i = 0; i < 8; i++) {
  347. if (instr & 0x80)
  348. b = SE2CS | SE2DO; /* -CLK+dataBit */
  349. else
  350. b = SE2CS; /* -CLK */
  351. TUL_WR(CurBase + TUL_NVRAM, b);
  352. tul_se2_wait();
  353. TUL_WR(CurBase + TUL_NVRAM, b | SE2CLK); /* +CLK */
  354. tul_se2_wait();
  355. instr <<= 1;
  356. }
  357. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  358. tul_se2_wait();
  359. return;
  360. }
  361. /******************************************************************
  362. Function name : tul_se2_ew_en
  363. Description : Enable erase/write state of serial EEPROM
  364. ******************************************************************/
  365. void tul_se2_ew_en(WORD CurBase)
  366. {
  367. tul_se2_instr(CurBase, 0x30); /* EWEN */
  368. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  369. tul_se2_wait();
  370. return;
  371. }
  372. /************************************************************************
  373. Disable erase/write state of serial EEPROM
  374. *************************************************************************/
  375. void tul_se2_ew_ds(WORD CurBase)
  376. {
  377. tul_se2_instr(CurBase, 0); /* EWDS */
  378. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  379. tul_se2_wait();
  380. return;
  381. }
  382. /******************************************************************
  383. Input :address of Serial E2PROM
  384. Output :value stored in Serial E2PROM
  385. *******************************************************************/
  386. static USHORT tul_se2_rd(WORD CurBase, ULONG adr)
  387. {
  388. UCHAR instr, readByte;
  389. USHORT readWord;
  390. int i;
  391. instr = (UCHAR) (adr | 0x80);
  392. tul_se2_instr(CurBase, instr); /* READ INSTR */
  393. readWord = 0;
  394. for (i = 15; i >= 0; i--) {
  395. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  396. tul_se2_wait();
  397. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  398. /* sample data after the following edge of clock */
  399. readByte = TUL_RD(CurBase, TUL_NVRAM);
  400. readByte &= SE2DI;
  401. readWord += (readByte << i);
  402. tul_se2_wait(); /* 6/20/95 */
  403. }
  404. TUL_WR(CurBase + TUL_NVRAM, 0); /* no chip select */
  405. tul_se2_wait();
  406. return readWord;
  407. }
  408. /******************************************************************
  409. Input: new value in Serial E2PROM, address of Serial E2PROM
  410. *******************************************************************/
  411. static void tul_se2_wr(WORD CurBase, UCHAR adr, USHORT writeWord)
  412. {
  413. UCHAR readByte;
  414. UCHAR instr;
  415. int i;
  416. instr = (UCHAR) (adr | 0x40);
  417. tul_se2_instr(CurBase, instr); /* WRITE INSTR */
  418. for (i = 15; i >= 0; i--) {
  419. if (writeWord & 0x8000)
  420. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2DO); /* -CLK+dataBit 1 */
  421. else
  422. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK+dataBit 0 */
  423. tul_se2_wait();
  424. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  425. tul_se2_wait();
  426. writeWord <<= 1;
  427. }
  428. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  429. tul_se2_wait();
  430. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  431. tul_se2_wait();
  432. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* +CS */
  433. tul_se2_wait();
  434. for (;;) {
  435. TUL_WR(CurBase + TUL_NVRAM, SE2CS | SE2CLK); /* +CLK */
  436. tul_se2_wait();
  437. TUL_WR(CurBase + TUL_NVRAM, SE2CS); /* -CLK */
  438. tul_se2_wait();
  439. if ((readByte = TUL_RD(CurBase, TUL_NVRAM)) & SE2DI)
  440. break; /* write complete */
  441. }
  442. TUL_WR(CurBase + TUL_NVRAM, 0); /* -CS */
  443. return;
  444. }
  445. /***********************************************************************
  446. Read SCSI H/A configuration parameters from serial EEPROM
  447. ************************************************************************/
  448. int tul_se2_rd_all(WORD CurBase)
  449. {
  450. int i;
  451. ULONG chksum = 0;
  452. USHORT *np;
  453. i91unvramp = &i91unvram;
  454. np = (USHORT *) i91unvramp;
  455. for (i = 0; i < 32; i++) {
  456. *np++ = tul_se2_rd(CurBase, i);
  457. }
  458. /*--------------------Is signature "ini" ok ? ----------------*/
  459. if (i91unvramp->NVM_Signature != INI_SIGNATURE)
  460. return -1;
  461. /*---------------------- Is ckecksum ok ? ----------------------*/
  462. np = (USHORT *) i91unvramp;
  463. for (i = 0; i < 31; i++)
  464. chksum += *np++;
  465. if (i91unvramp->NVM_CheckSum != (USHORT) chksum)
  466. return -1;
  467. return 1;
  468. }
  469. /***********************************************************************
  470. Update SCSI H/A configuration parameters from serial EEPROM
  471. ************************************************************************/
  472. void tul_se2_update_all(WORD CurBase)
  473. { /* setup default pattern */
  474. int i;
  475. ULONG chksum = 0;
  476. USHORT *np, *np1;
  477. i91unvramp = &i91unvram;
  478. /* Calculate checksum first */
  479. np = (USHORT *) i91udftNvRam;
  480. for (i = 0; i < 31; i++)
  481. chksum += *np++;
  482. *np = (USHORT) chksum;
  483. tul_se2_ew_en(CurBase); /* Enable write */
  484. np = (USHORT *) i91udftNvRam;
  485. np1 = (USHORT *) i91unvramp;
  486. for (i = 0; i < 32; i++, np++, np1++) {
  487. if (*np != *np1) {
  488. tul_se2_wr(CurBase, i, *np);
  489. }
  490. }
  491. tul_se2_ew_ds(CurBase); /* Disable write */
  492. return;
  493. }
  494. /*************************************************************************
  495. Function name : read_eeprom
  496. **************************************************************************/
  497. void tul_read_eeprom(WORD CurBase)
  498. {
  499. UCHAR gctrl;
  500. i91unvramp = &i91unvram;
  501. /*------Enable EEProm programming ---*/
  502. gctrl = TUL_RD(CurBase, TUL_GCTRL);
  503. TUL_WR(CurBase + TUL_GCTRL, gctrl | TUL_GCTRL_EEPROM_BIT);
  504. if (tul_se2_rd_all(CurBase) != 1) {
  505. tul_se2_update_all(CurBase); /* setup default pattern */
  506. tul_se2_rd_all(CurBase); /* load again */
  507. }
  508. /*------ Disable EEProm programming ---*/
  509. gctrl = TUL_RD(CurBase, TUL_GCTRL);
  510. TUL_WR(CurBase + TUL_GCTRL, gctrl & ~TUL_GCTRL_EEPROM_BIT);
  511. } /* read_eeprom */
  512. static int Addi91u_into_Adapter_table(WORD wBIOS, WORD wBASE, BYTE bInterrupt,
  513. BYTE bBus, BYTE bDevice)
  514. {
  515. int i, j;
  516. for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) {
  517. if (i91u_adpt[i].ADPT_BIOS < wBIOS)
  518. continue;
  519. if (i91u_adpt[i].ADPT_BIOS == wBIOS) {
  520. if (i91u_adpt[i].ADPT_BASE == wBASE) {
  521. if (i91u_adpt[i].ADPT_Bus != 0xFF)
  522. return 1;
  523. } else if (i91u_adpt[i].ADPT_BASE < wBASE)
  524. continue;
  525. }
  526. for (j = MAX_SUPPORTED_ADAPTERS - 1; j > i; j--) {
  527. i91u_adpt[j].ADPT_BASE = i91u_adpt[j - 1].ADPT_BASE;
  528. i91u_adpt[j].ADPT_INTR = i91u_adpt[j - 1].ADPT_INTR;
  529. i91u_adpt[j].ADPT_BIOS = i91u_adpt[j - 1].ADPT_BIOS;
  530. i91u_adpt[j].ADPT_Bus = i91u_adpt[j - 1].ADPT_Bus;
  531. i91u_adpt[j].ADPT_Device = i91u_adpt[j - 1].ADPT_Device;
  532. }
  533. i91u_adpt[i].ADPT_BASE = wBASE;
  534. i91u_adpt[i].ADPT_INTR = bInterrupt;
  535. i91u_adpt[i].ADPT_BIOS = wBIOS;
  536. i91u_adpt[i].ADPT_Bus = bBus;
  537. i91u_adpt[i].ADPT_Device = bDevice;
  538. return 0;
  539. }
  540. return 1;
  541. }
  542. static void init_i91uAdapter_table(void)
  543. {
  544. int i;
  545. for (i = 0; i < MAX_SUPPORTED_ADAPTERS; i++) { /* Initialize adapter structure */
  546. i91u_adpt[i].ADPT_BIOS = 0xffff;
  547. i91u_adpt[i].ADPT_BASE = 0xffff;
  548. i91u_adpt[i].ADPT_INTR = 0xff;
  549. i91u_adpt[i].ADPT_Bus = 0xff;
  550. i91u_adpt[i].ADPT_Device = 0xff;
  551. }
  552. return;
  553. }
  554. static void tul_stop_bm(HCS * pCurHcb)
  555. {
  556. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
  557. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
  558. /* wait Abort DMA xfer done */
  559. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0);
  560. }
  561. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  562. }
  563. /***************************************************************************/
  564. static void get_tulipPCIConfig(HCS * pCurHcb, int ch_idx)
  565. {
  566. pCurHcb->HCS_Base = i91u_adpt[ch_idx].ADPT_BASE; /* Supply base address */
  567. pCurHcb->HCS_BIOS = i91u_adpt[ch_idx].ADPT_BIOS; /* Supply BIOS address */
  568. pCurHcb->HCS_Intr = i91u_adpt[ch_idx].ADPT_INTR; /* Supply interrupt line */
  569. return;
  570. }
  571. /***************************************************************************/
  572. static int tul_reset_scsi(HCS * pCurHcb, int seconds)
  573. {
  574. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_BUS);
  575. while (!((pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt)) & TSS_SCSIRST_INT));
  576. /* reset tulip chip */
  577. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, 0);
  578. /* Stall for a while, wait for target's firmware ready,make it 2 sec ! */
  579. /* SONY 5200 tape drive won't work if only stall for 1 sec */
  580. tul_do_pause(seconds * HZ);
  581. TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  582. return (SCSI_RESET_SUCCESS);
  583. }
  584. /***************************************************************************/
  585. static int init_tulip(HCS * pCurHcb, SCB * scbp, int tul_num_scb,
  586. BYTE * pbBiosAdr, int seconds)
  587. {
  588. int i;
  589. BYTE *pwFlags;
  590. BYTE *pbHeads;
  591. SCB *pTmpScb, *pPrevScb = NULL;
  592. pCurHcb->HCS_NumScbs = tul_num_scb;
  593. pCurHcb->HCS_Semaph = 1;
  594. spin_lock_init(&pCurHcb->HCS_SemaphLock);
  595. pCurHcb->HCS_JSStatus0 = 0;
  596. pCurHcb->HCS_Scb = scbp;
  597. pCurHcb->HCS_NxtPend = scbp;
  598. pCurHcb->HCS_NxtAvail = scbp;
  599. for (i = 0, pTmpScb = scbp; i < tul_num_scb; i++, pTmpScb++) {
  600. pTmpScb->SCB_TagId = i;
  601. if (i != 0)
  602. pPrevScb->SCB_NxtScb = pTmpScb;
  603. pPrevScb = pTmpScb;
  604. }
  605. pPrevScb->SCB_NxtScb = NULL;
  606. pCurHcb->HCS_ScbEnd = pTmpScb;
  607. pCurHcb->HCS_FirstAvail = scbp;
  608. pCurHcb->HCS_LastAvail = pPrevScb;
  609. spin_lock_init(&pCurHcb->HCS_AvailLock);
  610. pCurHcb->HCS_FirstPend = NULL;
  611. pCurHcb->HCS_LastPend = NULL;
  612. pCurHcb->HCS_FirstBusy = NULL;
  613. pCurHcb->HCS_LastBusy = NULL;
  614. pCurHcb->HCS_FirstDone = NULL;
  615. pCurHcb->HCS_LastDone = NULL;
  616. pCurHcb->HCS_ActScb = NULL;
  617. pCurHcb->HCS_ActTcs = NULL;
  618. tul_read_eeprom(pCurHcb->HCS_Base);
  619. /*---------- get H/A configuration -------------*/
  620. if (i91unvramp->NVM_SCSIInfo[0].NVM_NumOfTarg == 8)
  621. pCurHcb->HCS_MaxTar = 8;
  622. else
  623. pCurHcb->HCS_MaxTar = 16;
  624. pCurHcb->HCS_Config = i91unvramp->NVM_SCSIInfo[0].NVM_ChConfig1;
  625. pCurHcb->HCS_SCSI_ID = i91unvramp->NVM_SCSIInfo[0].NVM_ChSCSIID;
  626. pCurHcb->HCS_IdMask = ~(1 << pCurHcb->HCS_SCSI_ID);
  627. #ifdef CHK_PARITY
  628. /* Enable parity error response */
  629. TUL_WR(pCurHcb->HCS_Base + TUL_PCMD, TUL_RD(pCurHcb->HCS_Base, TUL_PCMD) | 0x40);
  630. #endif
  631. /* Mask all the interrupt */
  632. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  633. tul_stop_bm(pCurHcb);
  634. /* --- Initialize the tulip --- */
  635. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_RST_CHIP);
  636. /* program HBA's SCSI ID */
  637. TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId, pCurHcb->HCS_SCSI_ID << 4);
  638. /* Enable Initiator Mode ,phase latch,alternate sync period mode,
  639. disable SCSI reset */
  640. if (pCurHcb->HCS_Config & HCC_EN_PAR)
  641. pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT | TSC_EN_SCSI_PAR);
  642. else
  643. pCurHcb->HCS_SConf1 = (TSC_INITDEFAULT);
  644. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_SConf1);
  645. /* Enable HW reselect */
  646. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT);
  647. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, 0);
  648. /* selection time out = 250 ms */
  649. TUL_WR(pCurHcb->HCS_Base + TUL_STimeOut, 153);
  650. /*--------- Enable SCSI terminator -----*/
  651. TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, (pCurHcb->HCS_Config & (HCC_ACT_TERM1 | HCC_ACT_TERM2)));
  652. TUL_WR(pCurHcb->HCS_Base + TUL_GCTRL1,
  653. ((pCurHcb->HCS_Config & HCC_AUTO_TERM) >> 4) | (TUL_RD(pCurHcb->HCS_Base, TUL_GCTRL1) & 0xFE));
  654. for (i = 0,
  655. pwFlags = & (i91unvramp->NVM_SCSIInfo[0].NVM_Targ0Config),
  656. pbHeads = pbBiosAdr + 0x180;
  657. i < pCurHcb->HCS_MaxTar;
  658. i++, pwFlags++) {
  659. pCurHcb->HCS_Tcs[i].TCS_Flags = *pwFlags & ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  660. if (pCurHcb->HCS_Tcs[i].TCS_Flags & TCF_EN_255)
  661. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63;
  662. else
  663. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0;
  664. pCurHcb->HCS_Tcs[i].TCS_JS_Period = 0;
  665. pCurHcb->HCS_Tcs[i].TCS_SConfig0 = pCurHcb->HCS_SConf1;
  666. pCurHcb->HCS_Tcs[i].TCS_DrvHead = *pbHeads++;
  667. if (pCurHcb->HCS_Tcs[i].TCS_DrvHead == 255)
  668. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = TCF_DRV_255_63;
  669. else
  670. pCurHcb->HCS_Tcs[i].TCS_DrvFlags = 0;
  671. pCurHcb->HCS_Tcs[i].TCS_DrvSector = *pbHeads++;
  672. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY;
  673. pCurHcb->HCS_ActTags[i] = 0;
  674. pCurHcb->HCS_MaxTags[i] = 0xFF;
  675. } /* for */
  676. printk("i91u: PCI Base=0x%04X, IRQ=%d, BIOS=0x%04X0, SCSI ID=%d\n",
  677. pCurHcb->HCS_Base, pCurHcb->HCS_Intr,
  678. pCurHcb->HCS_BIOS, pCurHcb->HCS_SCSI_ID);
  679. /*------------------- reset SCSI Bus ---------------------------*/
  680. if (pCurHcb->HCS_Config & HCC_SCSI_RESET) {
  681. printk("i91u: Reset SCSI Bus ... \n");
  682. tul_reset_scsi(pCurHcb, seconds);
  683. }
  684. TUL_WR(pCurHcb->HCS_Base + TUL_SCFG1, 0x17);
  685. TUL_WR(pCurHcb->HCS_Base + TUL_SIntEnable, 0xE9);
  686. return (0);
  687. }
  688. /***************************************************************************/
  689. static SCB *tul_alloc_scb(HCS * hcsp)
  690. {
  691. SCB *pTmpScb;
  692. ULONG flags;
  693. spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags);
  694. if ((pTmpScb = hcsp->HCS_FirstAvail) != NULL) {
  695. #if DEBUG_QUEUE
  696. printk("find scb at %08lx\n", (ULONG) pTmpScb);
  697. #endif
  698. if ((hcsp->HCS_FirstAvail = pTmpScb->SCB_NxtScb) == NULL)
  699. hcsp->HCS_LastAvail = NULL;
  700. pTmpScb->SCB_NxtScb = NULL;
  701. pTmpScb->SCB_Status = SCB_RENT;
  702. }
  703. spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags);
  704. return (pTmpScb);
  705. }
  706. /***************************************************************************/
  707. static void tul_release_scb(HCS * hcsp, SCB * scbp)
  708. {
  709. ULONG flags;
  710. #if DEBUG_QUEUE
  711. printk("Release SCB %lx; ", (ULONG) scbp);
  712. #endif
  713. spin_lock_irqsave(&(hcsp->HCS_AvailLock), flags);
  714. scbp->SCB_Srb = NULL;
  715. scbp->SCB_Status = 0;
  716. scbp->SCB_NxtScb = NULL;
  717. if (hcsp->HCS_LastAvail != NULL) {
  718. hcsp->HCS_LastAvail->SCB_NxtScb = scbp;
  719. hcsp->HCS_LastAvail = scbp;
  720. } else {
  721. hcsp->HCS_FirstAvail = scbp;
  722. hcsp->HCS_LastAvail = scbp;
  723. }
  724. spin_unlock_irqrestore(&(hcsp->HCS_AvailLock), flags);
  725. }
  726. /***************************************************************************/
  727. static void tul_append_pend_scb(HCS * pCurHcb, SCB * scbp)
  728. {
  729. #if DEBUG_QUEUE
  730. printk("Append pend SCB %lx; ", (ULONG) scbp);
  731. #endif
  732. scbp->SCB_Status = SCB_PEND;
  733. scbp->SCB_NxtScb = NULL;
  734. if (pCurHcb->HCS_LastPend != NULL) {
  735. pCurHcb->HCS_LastPend->SCB_NxtScb = scbp;
  736. pCurHcb->HCS_LastPend = scbp;
  737. } else {
  738. pCurHcb->HCS_FirstPend = scbp;
  739. pCurHcb->HCS_LastPend = scbp;
  740. }
  741. }
  742. /***************************************************************************/
  743. static void tul_push_pend_scb(HCS * pCurHcb, SCB * scbp)
  744. {
  745. #if DEBUG_QUEUE
  746. printk("Push pend SCB %lx; ", (ULONG) scbp);
  747. #endif
  748. scbp->SCB_Status = SCB_PEND;
  749. if ((scbp->SCB_NxtScb = pCurHcb->HCS_FirstPend) != NULL) {
  750. pCurHcb->HCS_FirstPend = scbp;
  751. } else {
  752. pCurHcb->HCS_FirstPend = scbp;
  753. pCurHcb->HCS_LastPend = scbp;
  754. }
  755. }
  756. /***************************************************************************/
  757. static SCB *tul_find_first_pend_scb(HCS * pCurHcb)
  758. {
  759. SCB *pFirstPend;
  760. pFirstPend = pCurHcb->HCS_FirstPend;
  761. while (pFirstPend != NULL) {
  762. if (pFirstPend->SCB_Opcode != ExecSCSI) {
  763. return (pFirstPend);
  764. }
  765. if (pFirstPend->SCB_TagMsg == 0) {
  766. if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] == 0) &&
  767. !(pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) {
  768. return (pFirstPend);
  769. }
  770. } else {
  771. if ((pCurHcb->HCS_ActTags[pFirstPend->SCB_Target] >=
  772. pCurHcb->HCS_MaxTags[pFirstPend->SCB_Target]) |
  773. (pCurHcb->HCS_Tcs[pFirstPend->SCB_Target].TCS_Flags & TCF_BUSY)) {
  774. pFirstPend = pFirstPend->SCB_NxtScb;
  775. continue;
  776. }
  777. return (pFirstPend);
  778. }
  779. pFirstPend = pFirstPend->SCB_NxtScb;
  780. }
  781. return (pFirstPend);
  782. }
  783. /***************************************************************************/
  784. static void tul_unlink_pend_scb(HCS * pCurHcb, SCB * pCurScb)
  785. {
  786. SCB *pTmpScb, *pPrevScb;
  787. #if DEBUG_QUEUE
  788. printk("unlink pend SCB %lx; ", (ULONG) pCurScb);
  789. #endif
  790. pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend;
  791. while (pTmpScb != NULL) {
  792. if (pCurScb == pTmpScb) { /* Unlink this SCB */
  793. if (pTmpScb == pCurHcb->HCS_FirstPend) {
  794. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  795. pCurHcb->HCS_LastPend = NULL;
  796. } else {
  797. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  798. if (pTmpScb == pCurHcb->HCS_LastPend)
  799. pCurHcb->HCS_LastPend = pPrevScb;
  800. }
  801. pTmpScb->SCB_NxtScb = NULL;
  802. break;
  803. }
  804. pPrevScb = pTmpScb;
  805. pTmpScb = pTmpScb->SCB_NxtScb;
  806. }
  807. return;
  808. }
  809. /***************************************************************************/
  810. static void tul_append_busy_scb(HCS * pCurHcb, SCB * scbp)
  811. {
  812. #if DEBUG_QUEUE
  813. printk("append busy SCB %lx; ", (ULONG) scbp);
  814. #endif
  815. if (scbp->SCB_TagMsg)
  816. pCurHcb->HCS_ActTags[scbp->SCB_Target]++;
  817. else
  818. pCurHcb->HCS_Tcs[scbp->SCB_Target].TCS_Flags |= TCF_BUSY;
  819. scbp->SCB_Status = SCB_BUSY;
  820. scbp->SCB_NxtScb = NULL;
  821. if (pCurHcb->HCS_LastBusy != NULL) {
  822. pCurHcb->HCS_LastBusy->SCB_NxtScb = scbp;
  823. pCurHcb->HCS_LastBusy = scbp;
  824. } else {
  825. pCurHcb->HCS_FirstBusy = scbp;
  826. pCurHcb->HCS_LastBusy = scbp;
  827. }
  828. }
  829. /***************************************************************************/
  830. static SCB *tul_pop_busy_scb(HCS * pCurHcb)
  831. {
  832. SCB *pTmpScb;
  833. if ((pTmpScb = pCurHcb->HCS_FirstBusy) != NULL) {
  834. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  835. pCurHcb->HCS_LastBusy = NULL;
  836. pTmpScb->SCB_NxtScb = NULL;
  837. if (pTmpScb->SCB_TagMsg)
  838. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  839. else
  840. pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY;
  841. }
  842. #if DEBUG_QUEUE
  843. printk("Pop busy SCB %lx; ", (ULONG) pTmpScb);
  844. #endif
  845. return (pTmpScb);
  846. }
  847. /***************************************************************************/
  848. static void tul_unlink_busy_scb(HCS * pCurHcb, SCB * pCurScb)
  849. {
  850. SCB *pTmpScb, *pPrevScb;
  851. #if DEBUG_QUEUE
  852. printk("unlink busy SCB %lx; ", (ULONG) pCurScb);
  853. #endif
  854. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy;
  855. while (pTmpScb != NULL) {
  856. if (pCurScb == pTmpScb) { /* Unlink this SCB */
  857. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  858. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  859. pCurHcb->HCS_LastBusy = NULL;
  860. } else {
  861. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  862. if (pTmpScb == pCurHcb->HCS_LastBusy)
  863. pCurHcb->HCS_LastBusy = pPrevScb;
  864. }
  865. pTmpScb->SCB_NxtScb = NULL;
  866. if (pTmpScb->SCB_TagMsg)
  867. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  868. else
  869. pCurHcb->HCS_Tcs[pTmpScb->SCB_Target].TCS_Flags &= ~TCF_BUSY;
  870. break;
  871. }
  872. pPrevScb = pTmpScb;
  873. pTmpScb = pTmpScb->SCB_NxtScb;
  874. }
  875. return;
  876. }
  877. /***************************************************************************/
  878. SCB *tul_find_busy_scb(HCS * pCurHcb, WORD tarlun)
  879. {
  880. SCB *pTmpScb, *pPrevScb;
  881. WORD scbp_tarlun;
  882. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy;
  883. while (pTmpScb != NULL) {
  884. scbp_tarlun = (pTmpScb->SCB_Lun << 8) | (pTmpScb->SCB_Target);
  885. if (scbp_tarlun == tarlun) { /* Unlink this SCB */
  886. break;
  887. }
  888. pPrevScb = pTmpScb;
  889. pTmpScb = pTmpScb->SCB_NxtScb;
  890. }
  891. #if DEBUG_QUEUE
  892. printk("find busy SCB %lx; ", (ULONG) pTmpScb);
  893. #endif
  894. return (pTmpScb);
  895. }
  896. /***************************************************************************/
  897. static void tul_append_done_scb(HCS * pCurHcb, SCB * scbp)
  898. {
  899. #if DEBUG_QUEUE
  900. printk("append done SCB %lx; ", (ULONG) scbp);
  901. #endif
  902. scbp->SCB_Status = SCB_DONE;
  903. scbp->SCB_NxtScb = NULL;
  904. if (pCurHcb->HCS_LastDone != NULL) {
  905. pCurHcb->HCS_LastDone->SCB_NxtScb = scbp;
  906. pCurHcb->HCS_LastDone = scbp;
  907. } else {
  908. pCurHcb->HCS_FirstDone = scbp;
  909. pCurHcb->HCS_LastDone = scbp;
  910. }
  911. }
  912. /***************************************************************************/
  913. SCB *tul_find_done_scb(HCS * pCurHcb)
  914. {
  915. SCB *pTmpScb;
  916. if ((pTmpScb = pCurHcb->HCS_FirstDone) != NULL) {
  917. if ((pCurHcb->HCS_FirstDone = pTmpScb->SCB_NxtScb) == NULL)
  918. pCurHcb->HCS_LastDone = NULL;
  919. pTmpScb->SCB_NxtScb = NULL;
  920. }
  921. #if DEBUG_QUEUE
  922. printk("find done SCB %lx; ", (ULONG) pTmpScb);
  923. #endif
  924. return (pTmpScb);
  925. }
  926. /***************************************************************************/
  927. static int tul_abort_srb(HCS * pCurHcb, struct scsi_cmnd *srbp)
  928. {
  929. ULONG flags;
  930. SCB *pTmpScb, *pPrevScb;
  931. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  932. if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
  933. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  934. /* disable Jasmin SCSI Int */
  935. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  936. tulip_main(pCurHcb);
  937. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  938. pCurHcb->HCS_Semaph = 1;
  939. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  940. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  941. return SCSI_ABORT_SNOOZE;
  942. }
  943. pPrevScb = pTmpScb = pCurHcb->HCS_FirstPend; /* Check Pend queue */
  944. while (pTmpScb != NULL) {
  945. /* 07/27/98 */
  946. if (pTmpScb->SCB_Srb == srbp) {
  947. if (pTmpScb == pCurHcb->HCS_ActScb) {
  948. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  949. return SCSI_ABORT_BUSY;
  950. } else if (pTmpScb == pCurHcb->HCS_FirstPend) {
  951. if ((pCurHcb->HCS_FirstPend = pTmpScb->SCB_NxtScb) == NULL)
  952. pCurHcb->HCS_LastPend = NULL;
  953. } else {
  954. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  955. if (pTmpScb == pCurHcb->HCS_LastPend)
  956. pCurHcb->HCS_LastPend = pPrevScb;
  957. }
  958. pTmpScb->SCB_HaStat = HOST_ABORTED;
  959. pTmpScb->SCB_Flags |= SCF_DONE;
  960. if (pTmpScb->SCB_Flags & SCF_POST)
  961. (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb);
  962. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  963. return SCSI_ABORT_SUCCESS;
  964. }
  965. pPrevScb = pTmpScb;
  966. pTmpScb = pTmpScb->SCB_NxtScb;
  967. }
  968. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  969. while (pTmpScb != NULL) {
  970. if (pTmpScb->SCB_Srb == srbp) {
  971. if (pTmpScb == pCurHcb->HCS_ActScb) {
  972. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  973. return SCSI_ABORT_BUSY;
  974. } else if (pTmpScb->SCB_TagMsg == 0) {
  975. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  976. return SCSI_ABORT_BUSY;
  977. } else {
  978. pCurHcb->HCS_ActTags[pTmpScb->SCB_Target]--;
  979. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  980. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  981. pCurHcb->HCS_LastBusy = NULL;
  982. } else {
  983. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  984. if (pTmpScb == pCurHcb->HCS_LastBusy)
  985. pCurHcb->HCS_LastBusy = pPrevScb;
  986. }
  987. pTmpScb->SCB_NxtScb = NULL;
  988. pTmpScb->SCB_HaStat = HOST_ABORTED;
  989. pTmpScb->SCB_Flags |= SCF_DONE;
  990. if (pTmpScb->SCB_Flags & SCF_POST)
  991. (*pTmpScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pTmpScb);
  992. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  993. return SCSI_ABORT_SUCCESS;
  994. }
  995. }
  996. pPrevScb = pTmpScb;
  997. pTmpScb = pTmpScb->SCB_NxtScb;
  998. }
  999. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1000. return (SCSI_ABORT_NOT_RUNNING);
  1001. }
  1002. /***************************************************************************/
  1003. static int tul_bad_seq(HCS * pCurHcb)
  1004. {
  1005. SCB *pCurScb;
  1006. printk("tul_bad_seg c=%d\n", pCurHcb->HCS_Index);
  1007. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
  1008. tul_unlink_busy_scb(pCurHcb, pCurScb);
  1009. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1010. pCurScb->SCB_TaStat = 0;
  1011. tul_append_done_scb(pCurHcb, pCurScb);
  1012. }
  1013. tul_stop_bm(pCurHcb);
  1014. tul_reset_scsi(pCurHcb, 8); /* 7/29/98 */
  1015. return (tul_post_scsi_rst(pCurHcb));
  1016. }
  1017. #if 0
  1018. /************************************************************************/
  1019. static int tul_device_reset(HCS * pCurHcb, struct scsi_cmnd *pSrb,
  1020. unsigned int target, unsigned int ResetFlags)
  1021. {
  1022. ULONG flags;
  1023. SCB *pScb;
  1024. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1025. if (ResetFlags & SCSI_RESET_ASYNCHRONOUS) {
  1026. if ((pCurHcb->HCS_Semaph == 0) && (pCurHcb->HCS_ActScb == NULL)) {
  1027. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1028. /* disable Jasmin SCSI Int */
  1029. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1030. tulip_main(pCurHcb);
  1031. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1032. pCurHcb->HCS_Semaph = 1;
  1033. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1034. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1035. return SCSI_RESET_SNOOZE;
  1036. }
  1037. pScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  1038. while (pScb != NULL) {
  1039. if (pScb->SCB_Srb == pSrb)
  1040. break;
  1041. pScb = pScb->SCB_NxtScb;
  1042. }
  1043. if (pScb == NULL) {
  1044. printk("Unable to Reset - No SCB Found\n");
  1045. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1046. return SCSI_RESET_NOT_RUNNING;
  1047. }
  1048. }
  1049. if ((pScb = tul_alloc_scb(pCurHcb)) == NULL) {
  1050. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1051. return SCSI_RESET_NOT_RUNNING;
  1052. }
  1053. pScb->SCB_Opcode = BusDevRst;
  1054. pScb->SCB_Flags = SCF_POST;
  1055. pScb->SCB_Target = target;
  1056. pScb->SCB_Mode = 0;
  1057. pScb->SCB_Srb = NULL;
  1058. if (ResetFlags & SCSI_RESET_SYNCHRONOUS) {
  1059. pScb->SCB_Srb = pSrb;
  1060. }
  1061. tul_push_pend_scb(pCurHcb, pScb); /* push this SCB to Pending queue */
  1062. if (pCurHcb->HCS_Semaph == 1) {
  1063. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1064. /* disable Jasmin SCSI Int */
  1065. pCurHcb->HCS_Semaph = 0;
  1066. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1067. tulip_main(pCurHcb);
  1068. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1069. pCurHcb->HCS_Semaph = 1;
  1070. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1071. }
  1072. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1073. return SCSI_RESET_PENDING;
  1074. }
  1075. static int tul_reset_scsi_bus(HCS * pCurHcb)
  1076. {
  1077. ULONG flags;
  1078. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1079. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1080. pCurHcb->HCS_Semaph = 0;
  1081. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1082. tul_stop_bm(pCurHcb);
  1083. tul_reset_scsi(pCurHcb, 2); /* 7/29/98 */
  1084. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1085. tul_post_scsi_rst(pCurHcb);
  1086. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1087. tulip_main(pCurHcb);
  1088. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1089. pCurHcb->HCS_Semaph = 1;
  1090. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1091. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1092. return (SCSI_RESET_SUCCESS | SCSI_RESET_HOST_RESET);
  1093. }
  1094. #endif /* 0 */
  1095. /************************************************************************/
  1096. static void tul_exec_scb(HCS * pCurHcb, SCB * pCurScb)
  1097. {
  1098. ULONG flags;
  1099. pCurScb->SCB_Mode = 0;
  1100. pCurScb->SCB_SGIdx = 0;
  1101. pCurScb->SCB_SGMax = pCurScb->SCB_SGLen;
  1102. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1103. tul_append_pend_scb(pCurHcb, pCurScb); /* Append this SCB to Pending queue */
  1104. /* VVVVV 07/21/98 */
  1105. if (pCurHcb->HCS_Semaph == 1) {
  1106. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1107. /* disable Jasmin SCSI Int */
  1108. pCurHcb->HCS_Semaph = 0;
  1109. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1110. tulip_main(pCurHcb);
  1111. spin_lock_irqsave(&(pCurHcb->HCS_SemaphLock), flags);
  1112. pCurHcb->HCS_Semaph = 1;
  1113. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1114. }
  1115. spin_unlock_irqrestore(&(pCurHcb->HCS_SemaphLock), flags);
  1116. return;
  1117. }
  1118. /***************************************************************************/
  1119. static int tul_isr(HCS * pCurHcb)
  1120. {
  1121. /* Enter critical section */
  1122. if (TUL_RD(pCurHcb->HCS_Base, TUL_Int) & TSS_INT_PENDING) {
  1123. if (pCurHcb->HCS_Semaph == 1) {
  1124. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x1F);
  1125. /* Disable Tulip SCSI Int */
  1126. pCurHcb->HCS_Semaph = 0;
  1127. tulip_main(pCurHcb);
  1128. pCurHcb->HCS_Semaph = 1;
  1129. TUL_WR(pCurHcb->HCS_Base + TUL_Mask, 0x0F);
  1130. return (1);
  1131. }
  1132. }
  1133. return (0);
  1134. }
  1135. /***************************************************************************/
  1136. int tulip_main(HCS * pCurHcb)
  1137. {
  1138. SCB *pCurScb;
  1139. for (;;) {
  1140. tulip_scsi(pCurHcb); /* Call tulip_scsi */
  1141. while ((pCurScb = tul_find_done_scb(pCurHcb)) != NULL) { /* find done entry */
  1142. if (pCurScb->SCB_TaStat == INI_QUEUE_FULL) {
  1143. pCurHcb->HCS_MaxTags[pCurScb->SCB_Target] =
  1144. pCurHcb->HCS_ActTags[pCurScb->SCB_Target] - 1;
  1145. pCurScb->SCB_TaStat = 0;
  1146. tul_append_pend_scb(pCurHcb, pCurScb);
  1147. continue;
  1148. }
  1149. if (!(pCurScb->SCB_Mode & SCM_RSENS)) { /* not in auto req. sense mode */
  1150. if (pCurScb->SCB_TaStat == 2) {
  1151. /* clr sync. nego flag */
  1152. if (pCurScb->SCB_Flags & SCF_SENSE) {
  1153. BYTE len;
  1154. len = pCurScb->SCB_SenseLen;
  1155. if (len == 0)
  1156. len = 1;
  1157. pCurScb->SCB_BufLen = pCurScb->SCB_SenseLen;
  1158. pCurScb->SCB_BufPtr = pCurScb->SCB_SensePtr;
  1159. pCurScb->SCB_Flags &= ~(SCF_SG | SCF_DIR); /* for xfer_data_in */
  1160. /* pCurScb->SCB_Flags |= SCF_NO_DCHK; */
  1161. /* so, we won't report worng direction in xfer_data_in,
  1162. and won't report HOST_DO_DU in state_6 */
  1163. pCurScb->SCB_Mode = SCM_RSENS;
  1164. pCurScb->SCB_Ident &= 0xBF; /* Disable Disconnect */
  1165. pCurScb->SCB_TagMsg = 0;
  1166. pCurScb->SCB_TaStat = 0;
  1167. pCurScb->SCB_CDBLen = 6;
  1168. pCurScb->SCB_CDB[0] = SCSICMD_RequestSense;
  1169. pCurScb->SCB_CDB[1] = 0;
  1170. pCurScb->SCB_CDB[2] = 0;
  1171. pCurScb->SCB_CDB[3] = 0;
  1172. pCurScb->SCB_CDB[4] = len;
  1173. pCurScb->SCB_CDB[5] = 0;
  1174. tul_push_pend_scb(pCurHcb, pCurScb);
  1175. break;
  1176. }
  1177. }
  1178. } else { /* in request sense mode */
  1179. if (pCurScb->SCB_TaStat == 2) { /* check contition status again after sending
  1180. requset sense cmd 0x3 */
  1181. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1182. }
  1183. pCurScb->SCB_TaStat = 2;
  1184. }
  1185. pCurScb->SCB_Flags |= SCF_DONE;
  1186. if (pCurScb->SCB_Flags & SCF_POST) {
  1187. (*pCurScb->SCB_Post) ((BYTE *) pCurHcb, (BYTE *) pCurScb);
  1188. }
  1189. } /* while */
  1190. /* find_active: */
  1191. if (TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0) & TSS_INT_PENDING)
  1192. continue;
  1193. if (pCurHcb->HCS_ActScb) { /* return to OS and wait for xfer_done_ISR/Selected_ISR */
  1194. return 1; /* return to OS, enable interrupt */
  1195. }
  1196. /* Check pending SCB */
  1197. if (tul_find_first_pend_scb(pCurHcb) == NULL) {
  1198. return 1; /* return to OS, enable interrupt */
  1199. }
  1200. } /* End of for loop */
  1201. /* statement won't reach here */
  1202. }
  1203. /*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ */
  1204. /***************************************************************************/
  1205. /***************************************************************************/
  1206. /***************************************************************************/
  1207. /***************************************************************************/
  1208. /***************************************************************************/
  1209. void tulip_scsi(HCS * pCurHcb)
  1210. {
  1211. SCB *pCurScb;
  1212. TCS *pCurTcb;
  1213. /* make sure to service interrupt asap */
  1214. if ((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0)) & TSS_INT_PENDING) {
  1215. pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK;
  1216. pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1);
  1217. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  1218. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* SCSI bus reset detected */
  1219. int_tul_scsi_rst(pCurHcb);
  1220. return;
  1221. }
  1222. if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if selected/reselected interrupt */
  1223. if (int_tul_resel(pCurHcb) == 0)
  1224. tul_next_state(pCurHcb);
  1225. return;
  1226. }
  1227. if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) {
  1228. int_tul_busfree(pCurHcb);
  1229. return;
  1230. }
  1231. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  1232. int_tul_busfree(pCurHcb); /* unexpected bus free or sel timeout */
  1233. return;
  1234. }
  1235. if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) { /* func complete or Bus service */
  1236. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL)
  1237. tul_next_state(pCurHcb);
  1238. return;
  1239. }
  1240. }
  1241. if (pCurHcb->HCS_ActScb != NULL)
  1242. return;
  1243. if ((pCurScb = tul_find_first_pend_scb(pCurHcb)) == NULL)
  1244. return;
  1245. /* program HBA's SCSI ID & target SCSI ID */
  1246. TUL_WR(pCurHcb->HCS_Base + TUL_SScsiId,
  1247. (pCurHcb->HCS_SCSI_ID << 4) | (pCurScb->SCB_Target & 0x0F));
  1248. if (pCurScb->SCB_Opcode == ExecSCSI) {
  1249. pCurTcb = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  1250. if (pCurScb->SCB_TagMsg)
  1251. pCurTcb->TCS_DrvFlags |= TCF_DRV_EN_TAG;
  1252. else
  1253. pCurTcb->TCS_DrvFlags &= ~TCF_DRV_EN_TAG;
  1254. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period);
  1255. if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) { /* do wdtr negotiation */
  1256. tul_select_atn_stop(pCurHcb, pCurScb);
  1257. } else {
  1258. if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync negotiation */
  1259. tul_select_atn_stop(pCurHcb, pCurScb);
  1260. } else {
  1261. if (pCurScb->SCB_TagMsg)
  1262. tul_select_atn3(pCurHcb, pCurScb);
  1263. else
  1264. tul_select_atn(pCurHcb, pCurScb);
  1265. }
  1266. }
  1267. if (pCurScb->SCB_Flags & SCF_POLL) {
  1268. while (wait_tulip(pCurHcb) != -1) {
  1269. if (tul_next_state(pCurHcb) == -1)
  1270. break;
  1271. }
  1272. }
  1273. } else if (pCurScb->SCB_Opcode == BusDevRst) {
  1274. tul_select_atn_stop(pCurHcb, pCurScb);
  1275. pCurScb->SCB_NxtStat = 8;
  1276. if (pCurScb->SCB_Flags & SCF_POLL) {
  1277. while (wait_tulip(pCurHcb) != -1) {
  1278. if (tul_next_state(pCurHcb) == -1)
  1279. break;
  1280. }
  1281. }
  1282. } else if (pCurScb->SCB_Opcode == AbortCmd) {
  1283. if (tul_abort_srb(pCurHcb, pCurScb->SCB_Srb) != 0) {
  1284. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1285. tul_release_scb(pCurHcb, pCurScb);
  1286. } else {
  1287. pCurScb->SCB_Opcode = BusDevRst;
  1288. tul_select_atn_stop(pCurHcb, pCurScb);
  1289. pCurScb->SCB_NxtStat = 8;
  1290. }
  1291. /* 08/03/98 */
  1292. } else {
  1293. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1294. pCurScb->SCB_HaStat = 0x16; /* bad command */
  1295. tul_append_done_scb(pCurHcb, pCurScb);
  1296. }
  1297. return;
  1298. }
  1299. /***************************************************************************/
  1300. int tul_next_state(HCS * pCurHcb)
  1301. {
  1302. int next;
  1303. next = pCurHcb->HCS_ActScb->SCB_NxtStat;
  1304. for (;;) {
  1305. switch (next) {
  1306. case 1:
  1307. next = tul_state_1(pCurHcb);
  1308. break;
  1309. case 2:
  1310. next = tul_state_2(pCurHcb);
  1311. break;
  1312. case 3:
  1313. next = tul_state_3(pCurHcb);
  1314. break;
  1315. case 4:
  1316. next = tul_state_4(pCurHcb);
  1317. break;
  1318. case 5:
  1319. next = tul_state_5(pCurHcb);
  1320. break;
  1321. case 6:
  1322. next = tul_state_6(pCurHcb);
  1323. break;
  1324. case 7:
  1325. next = tul_state_7(pCurHcb);
  1326. break;
  1327. case 8:
  1328. return (tul_bus_device_reset(pCurHcb));
  1329. default:
  1330. return (tul_bad_seq(pCurHcb));
  1331. }
  1332. if (next <= 0)
  1333. return next;
  1334. }
  1335. }
  1336. /***************************************************************************/
  1337. /* sTate after selection with attention & stop */
  1338. int tul_state_1(HCS * pCurHcb)
  1339. {
  1340. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1341. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1342. #if DEBUG_STATE
  1343. printk("-s1-");
  1344. #endif
  1345. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1346. tul_append_busy_scb(pCurHcb, pCurScb);
  1347. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1348. /* ATN on */
  1349. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1350. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, (TSC_EN_BUS_IN | TSC_HW_RESELECT));
  1351. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  1352. if (pCurScb->SCB_TagMsg) {
  1353. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg);
  1354. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId);
  1355. }
  1356. if ((pCurTcb->TCS_Flags & (TCF_WDTR_DONE | TCF_NO_WDTR)) == 0) {
  1357. pCurTcb->TCS_Flags |= TCF_WDTR_DONE;
  1358. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1359. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2); /* Extended msg length */
  1360. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* Sync request */
  1361. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* Start from 16 bits */
  1362. } else if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) {
  1363. pCurTcb->TCS_Flags |= TCF_SYNC_DONE;
  1364. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1365. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* extended msg length */
  1366. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */
  1367. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]);
  1368. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */
  1369. }
  1370. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1371. if (wait_tulip(pCurHcb) == -1)
  1372. return (-1);
  1373. }
  1374. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1375. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1376. return (3);
  1377. }
  1378. /***************************************************************************/
  1379. /* state after selection with attention */
  1380. /* state after selection with attention3 */
  1381. int tul_state_2(HCS * pCurHcb)
  1382. {
  1383. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1384. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1385. #if DEBUG_STATE
  1386. printk("-s2-");
  1387. #endif
  1388. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1389. tul_append_busy_scb(pCurHcb, pCurScb);
  1390. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1391. if (pCurHcb->HCS_JSStatus1 & TSS_CMD_PH_CMP) {
  1392. return (4);
  1393. }
  1394. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1395. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1396. return (3);
  1397. }
  1398. /***************************************************************************/
  1399. /* state before CDB xfer is done */
  1400. int tul_state_3(HCS * pCurHcb)
  1401. {
  1402. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1403. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1404. int i;
  1405. #if DEBUG_STATE
  1406. printk("-s3-");
  1407. #endif
  1408. for (;;) {
  1409. switch (pCurHcb->HCS_Phase) {
  1410. case CMD_OUT: /* Command out phase */
  1411. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  1412. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  1413. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1414. if (wait_tulip(pCurHcb) == -1)
  1415. return (-1);
  1416. if (pCurHcb->HCS_Phase == CMD_OUT) {
  1417. return (tul_bad_seq(pCurHcb));
  1418. }
  1419. return (4);
  1420. case MSG_IN: /* Message in phase */
  1421. pCurScb->SCB_NxtStat = 3;
  1422. if (tul_msgin(pCurHcb) == -1)
  1423. return (-1);
  1424. break;
  1425. case STATUS_IN: /* Status phase */
  1426. if (tul_status_msg(pCurHcb) == -1)
  1427. return (-1);
  1428. break;
  1429. case MSG_OUT: /* Message out phase */
  1430. if (pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) {
  1431. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1432. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1433. if (wait_tulip(pCurHcb) == -1)
  1434. return (-1);
  1435. } else {
  1436. pCurTcb->TCS_Flags |= TCF_SYNC_DONE;
  1437. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  1438. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3); /* ext. msg len */
  1439. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1); /* sync request */
  1440. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, tul_rate_tbl[pCurTcb->TCS_Flags & TCF_SCSI_RATE]);
  1441. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MAX_OFFSET); /* REQ/ACK offset */
  1442. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1443. if (wait_tulip(pCurHcb) == -1)
  1444. return (-1);
  1445. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1446. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7));
  1447. }
  1448. break;
  1449. default:
  1450. return (tul_bad_seq(pCurHcb));
  1451. }
  1452. }
  1453. }
  1454. /***************************************************************************/
  1455. int tul_state_4(HCS * pCurHcb)
  1456. {
  1457. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1458. #if DEBUG_STATE
  1459. printk("-s4-");
  1460. #endif
  1461. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_NO_XF) {
  1462. return (6); /* Go to state 6 */
  1463. }
  1464. for (;;) {
  1465. if (pCurScb->SCB_BufLen == 0)
  1466. return (6); /* Go to state 6 */
  1467. switch (pCurHcb->HCS_Phase) {
  1468. case STATUS_IN: /* Status phase */
  1469. if ((pCurScb->SCB_Flags & SCF_DIR) != 0) { /* if direction bit set then report data underrun */
  1470. pCurScb->SCB_HaStat = HOST_DO_DU;
  1471. }
  1472. if ((tul_status_msg(pCurHcb)) == -1)
  1473. return (-1);
  1474. break;
  1475. case MSG_IN: /* Message in phase */
  1476. pCurScb->SCB_NxtStat = 0x4;
  1477. if (tul_msgin(pCurHcb) == -1)
  1478. return (-1);
  1479. break;
  1480. case MSG_OUT: /* Message out phase */
  1481. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1482. pCurScb->SCB_BufLen = 0;
  1483. pCurScb->SCB_HaStat = HOST_DO_DU;
  1484. if (tul_msgout_ide(pCurHcb) == -1)
  1485. return (-1);
  1486. return (6); /* Go to state 6 */
  1487. } else {
  1488. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1489. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1490. if (wait_tulip(pCurHcb) == -1)
  1491. return (-1);
  1492. }
  1493. break;
  1494. case DATA_IN: /* Data in phase */
  1495. return (tul_xfer_data_in(pCurHcb));
  1496. case DATA_OUT: /* Data out phase */
  1497. return (tul_xfer_data_out(pCurHcb));
  1498. default:
  1499. return (tul_bad_seq(pCurHcb));
  1500. }
  1501. }
  1502. }
  1503. /***************************************************************************/
  1504. /* state after dma xfer done or phase change before xfer done */
  1505. int tul_state_5(HCS * pCurHcb)
  1506. {
  1507. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1508. long cnt, xcnt; /* cannot use unsigned !! code: if (xcnt < 0) */
  1509. #if DEBUG_STATE
  1510. printk("-s5-");
  1511. #endif
  1512. /*------ get remaining count -------*/
  1513. cnt = TUL_RDLONG(pCurHcb->HCS_Base, TUL_SCnt0) & 0x0FFFFFF;
  1514. if (TUL_RD(pCurHcb->HCS_Base, TUL_XCmd) & 0x20) {
  1515. /* ----------------------- DATA_IN ----------------------------- */
  1516. /* check scsi parity error */
  1517. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1518. pCurScb->SCB_HaStat = HOST_DO_DU;
  1519. }
  1520. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* DMA xfer pending, Send STOP */
  1521. /* tell Hardware scsi xfer has been terminated */
  1522. TUL_WR(pCurHcb->HCS_Base + TUL_XCtrl, TUL_RD(pCurHcb->HCS_Base, TUL_XCtrl) | 0x80);
  1523. /* wait until DMA xfer not pending */
  1524. while (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND);
  1525. }
  1526. } else {
  1527. /*-------- DATA OUT -----------*/
  1528. if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0) {
  1529. if (pCurHcb->HCS_ActTcs->TCS_JS_Period & TSC_WIDE_SCSI)
  1530. cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F) << 1;
  1531. else
  1532. cnt += (TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F);
  1533. }
  1534. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & XPEND) { /* if DMA xfer is pending, abort DMA xfer */
  1535. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT);
  1536. /* wait Abort DMA xfer done */
  1537. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & XABT) == 0);
  1538. }
  1539. if ((cnt == 1) && (pCurHcb->HCS_Phase == DATA_OUT)) {
  1540. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1541. if (wait_tulip(pCurHcb) == -1) {
  1542. return (-1);
  1543. }
  1544. cnt = 0;
  1545. } else {
  1546. if ((TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1) & TSS_XFER_CMP) == 0)
  1547. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1548. }
  1549. }
  1550. if (cnt == 0) {
  1551. pCurScb->SCB_BufLen = 0;
  1552. return (6); /* Go to state 6 */
  1553. }
  1554. /* Update active data pointer */
  1555. xcnt = (long) pCurScb->SCB_BufLen - cnt; /* xcnt== bytes already xferred */
  1556. pCurScb->SCB_BufLen = (U32) cnt; /* cnt == bytes left to be xferred */
  1557. if (pCurScb->SCB_Flags & SCF_SG) {
  1558. register SG *sgp;
  1559. ULONG i;
  1560. sgp = &pCurScb->SCB_SGList[pCurScb->SCB_SGIdx];
  1561. for (i = pCurScb->SCB_SGIdx; i < pCurScb->SCB_SGMax; sgp++, i++) {
  1562. xcnt -= (long) sgp->SG_Len;
  1563. if (xcnt < 0) { /* this sgp xfer half done */
  1564. xcnt += (long) sgp->SG_Len; /* xcnt == bytes xferred in this sgp */
  1565. sgp->SG_Ptr += (U32) xcnt; /* new ptr to be xfer */
  1566. sgp->SG_Len -= (U32) xcnt; /* new len to be xfer */
  1567. pCurScb->SCB_BufPtr += ((U32) (i - pCurScb->SCB_SGIdx) << 3);
  1568. /* new SG table ptr */
  1569. pCurScb->SCB_SGLen = (BYTE) (pCurScb->SCB_SGMax - i);
  1570. /* new SG table len */
  1571. pCurScb->SCB_SGIdx = (WORD) i;
  1572. /* for next disc and come in this loop */
  1573. return (4); /* Go to state 4 */
  1574. }
  1575. /* else (xcnt >= 0 , i.e. this sgp already xferred */
  1576. } /* for */
  1577. return (6); /* Go to state 6 */
  1578. } else {
  1579. pCurScb->SCB_BufPtr += (U32) xcnt;
  1580. }
  1581. return (4); /* Go to state 4 */
  1582. }
  1583. /***************************************************************************/
  1584. /* state after Data phase */
  1585. int tul_state_6(HCS * pCurHcb)
  1586. {
  1587. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1588. #if DEBUG_STATE
  1589. printk("-s6-");
  1590. #endif
  1591. for (;;) {
  1592. switch (pCurHcb->HCS_Phase) {
  1593. case STATUS_IN: /* Status phase */
  1594. if ((tul_status_msg(pCurHcb)) == -1)
  1595. return (-1);
  1596. break;
  1597. case MSG_IN: /* Message in phase */
  1598. pCurScb->SCB_NxtStat = 6;
  1599. if ((tul_msgin(pCurHcb)) == -1)
  1600. return (-1);
  1601. break;
  1602. case MSG_OUT: /* Message out phase */
  1603. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP); /* msg nop */
  1604. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1605. if (wait_tulip(pCurHcb) == -1)
  1606. return (-1);
  1607. break;
  1608. case DATA_IN: /* Data in phase */
  1609. return (tul_xpad_in(pCurHcb));
  1610. case DATA_OUT: /* Data out phase */
  1611. return (tul_xpad_out(pCurHcb));
  1612. default:
  1613. return (tul_bad_seq(pCurHcb));
  1614. }
  1615. }
  1616. }
  1617. /***************************************************************************/
  1618. int tul_state_7(HCS * pCurHcb)
  1619. {
  1620. int cnt, i;
  1621. #if DEBUG_STATE
  1622. printk("-s7-");
  1623. #endif
  1624. /* flush SCSI FIFO */
  1625. cnt = TUL_RD(pCurHcb->HCS_Base, TUL_SFifoCnt) & 0x1F;
  1626. if (cnt) {
  1627. for (i = 0; i < cnt; i++)
  1628. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1629. }
  1630. switch (pCurHcb->HCS_Phase) {
  1631. case DATA_IN: /* Data in phase */
  1632. case DATA_OUT: /* Data out phase */
  1633. return (tul_bad_seq(pCurHcb));
  1634. default:
  1635. return (6); /* Go to state 6 */
  1636. }
  1637. }
  1638. /***************************************************************************/
  1639. int tul_xfer_data_in(HCS * pCurHcb)
  1640. {
  1641. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1642. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DOUT) {
  1643. return (6); /* wrong direction */
  1644. }
  1645. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
  1646. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_IN); /* 7/25/95 */
  1647. if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */
  1648. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3);
  1649. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1650. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_IN);
  1651. } else {
  1652. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen);
  1653. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1654. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_IN);
  1655. }
  1656. pCurScb->SCB_NxtStat = 0x5;
  1657. return (0); /* return to OS, wait xfer done , let jas_isr come in */
  1658. }
  1659. /***************************************************************************/
  1660. int tul_xfer_data_out(HCS * pCurHcb)
  1661. {
  1662. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1663. if ((pCurScb->SCB_Flags & SCF_DIR) == SCF_DIN) {
  1664. return (6); /* wrong direction */
  1665. }
  1666. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, pCurScb->SCB_BufLen);
  1667. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_DMA_OUT);
  1668. if (pCurScb->SCB_Flags & SCF_SG) { /* S/G xfer */
  1669. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, ((ULONG) pCurScb->SCB_SGLen) << 3);
  1670. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1671. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_SG_OUT);
  1672. } else {
  1673. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XCntH, pCurScb->SCB_BufLen);
  1674. TUL_WRLONG(pCurHcb->HCS_Base + TUL_XAddH, pCurScb->SCB_BufPtr);
  1675. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_OUT);
  1676. }
  1677. pCurScb->SCB_NxtStat = 0x5;
  1678. return (0); /* return to OS, wait xfer done , let jas_isr come in */
  1679. }
  1680. /***************************************************************************/
  1681. int tul_xpad_in(HCS * pCurHcb)
  1682. {
  1683. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1684. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1685. if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) {
  1686. pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */
  1687. }
  1688. for (;;) {
  1689. if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI)
  1690. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2);
  1691. else
  1692. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1693. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1694. if ((wait_tulip(pCurHcb)) == -1) {
  1695. return (-1);
  1696. }
  1697. if (pCurHcb->HCS_Phase != DATA_IN) {
  1698. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1699. return (6);
  1700. }
  1701. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1702. }
  1703. }
  1704. int tul_xpad_out(HCS * pCurHcb)
  1705. {
  1706. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1707. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  1708. if ((pCurScb->SCB_Flags & SCF_DIR) != SCF_NO_DCHK) {
  1709. pCurScb->SCB_HaStat = HOST_DO_DU; /* over run */
  1710. }
  1711. for (;;) {
  1712. if (pCurTcb->TCS_JS_Period & TSC_WIDE_SCSI)
  1713. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 2);
  1714. else
  1715. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1716. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0);
  1717. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1718. if ((wait_tulip(pCurHcb)) == -1) {
  1719. return (-1);
  1720. }
  1721. if (pCurHcb->HCS_Phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */
  1722. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT);
  1723. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1724. return (6);
  1725. }
  1726. }
  1727. }
  1728. /***************************************************************************/
  1729. int tul_status_msg(HCS * pCurHcb)
  1730. { /* status & MSG_IN */
  1731. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1732. BYTE msg;
  1733. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_CMD_COMP);
  1734. if ((wait_tulip(pCurHcb)) == -1) {
  1735. return (-1);
  1736. }
  1737. /* get status */
  1738. pCurScb->SCB_TaStat = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1739. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1740. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) {
  1741. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY);
  1742. } else {
  1743. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_NOP);
  1744. }
  1745. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1746. return (wait_tulip(pCurHcb));
  1747. }
  1748. if (pCurHcb->HCS_Phase == MSG_IN) {
  1749. msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  1750. if (pCurHcb->HCS_JSStatus0 & TSS_PAR_ERROR) { /* Parity error */
  1751. if ((tul_msgin_accept(pCurHcb)) == -1)
  1752. return (-1);
  1753. if (pCurHcb->HCS_Phase != MSG_OUT)
  1754. return (tul_bad_seq(pCurHcb));
  1755. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_PARITY);
  1756. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1757. return (wait_tulip(pCurHcb));
  1758. }
  1759. if (msg == 0) { /* Command complete */
  1760. if ((pCurScb->SCB_TaStat & 0x18) == 0x10) { /* No link support */
  1761. return (tul_bad_seq(pCurHcb));
  1762. }
  1763. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1764. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1765. return tul_wait_done_disc(pCurHcb);
  1766. }
  1767. if ((msg == MSG_LINK_COMP) || (msg == MSG_LINK_FLAG)) {
  1768. if ((pCurScb->SCB_TaStat & 0x18) == 0x10)
  1769. return (tul_msgin_accept(pCurHcb));
  1770. }
  1771. }
  1772. return (tul_bad_seq(pCurHcb));
  1773. }
  1774. /***************************************************************************/
  1775. /* scsi bus free */
  1776. int int_tul_busfree(HCS * pCurHcb)
  1777. {
  1778. SCB *pCurScb = pCurHcb->HCS_ActScb;
  1779. if (pCurScb != NULL) {
  1780. if (pCurScb->SCB_Status & SCB_SELECT) { /* selection timeout */
  1781. tul_unlink_pend_scb(pCurHcb, pCurScb);
  1782. pCurScb->SCB_HaStat = HOST_SEL_TOUT;
  1783. tul_append_done_scb(pCurHcb, pCurScb);
  1784. } else { /* Unexpected bus free */
  1785. tul_unlink_busy_scb(pCurHcb, pCurScb);
  1786. pCurScb->SCB_HaStat = HOST_BUS_FREE;
  1787. tul_append_done_scb(pCurHcb, pCurScb);
  1788. }
  1789. pCurHcb->HCS_ActScb = NULL;
  1790. pCurHcb->HCS_ActTcs = NULL;
  1791. }
  1792. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  1793. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  1794. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  1795. return (-1);
  1796. }
  1797. /***************************************************************************/
  1798. /* scsi bus reset */
  1799. static int int_tul_scsi_rst(HCS * pCurHcb)
  1800. {
  1801. SCB *pCurScb;
  1802. int i;
  1803. /* if DMA xfer is pending, abort DMA xfer */
  1804. if (TUL_RD(pCurHcb->HCS_Base, TUL_XStatus) & 0x01) {
  1805. TUL_WR(pCurHcb->HCS_Base + TUL_XCmd, TAX_X_ABT | TAX_X_CLR_FIFO);
  1806. /* wait Abort DMA xfer done */
  1807. while ((TUL_RD(pCurHcb->HCS_Base, TUL_Int) & 0x04) == 0);
  1808. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1809. }
  1810. /* Abort all active & disconnected scb */
  1811. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  1812. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1813. tul_append_done_scb(pCurHcb, pCurScb);
  1814. }
  1815. pCurHcb->HCS_ActScb = NULL;
  1816. pCurHcb->HCS_ActTcs = NULL;
  1817. /* clr sync nego. done flag */
  1818. for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
  1819. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  1820. }
  1821. return (-1);
  1822. }
  1823. /***************************************************************************/
  1824. /* scsi reselection */
  1825. int int_tul_resel(HCS * pCurHcb)
  1826. {
  1827. SCB *pCurScb;
  1828. TCS *pCurTcb;
  1829. BYTE tag, msg = 0;
  1830. BYTE tar, lun;
  1831. if ((pCurScb = pCurHcb->HCS_ActScb) != NULL) {
  1832. if (pCurScb->SCB_Status & SCB_SELECT) { /* if waiting for selection complete */
  1833. pCurScb->SCB_Status &= ~SCB_SELECT;
  1834. }
  1835. pCurHcb->HCS_ActScb = NULL;
  1836. }
  1837. /* --------- get target id---------------------- */
  1838. tar = TUL_RD(pCurHcb->HCS_Base, TUL_SBusId);
  1839. /* ------ get LUN from Identify message----------- */
  1840. lun = TUL_RD(pCurHcb->HCS_Base, TUL_SIdent) & 0x0F;
  1841. /* 07/22/98 from 0x1F -> 0x0F */
  1842. pCurTcb = &pCurHcb->HCS_Tcs[tar];
  1843. pCurHcb->HCS_ActTcs = pCurTcb;
  1844. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurTcb->TCS_SConfig0);
  1845. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurTcb->TCS_JS_Period);
  1846. /* ------------- tag queueing ? ------------------- */
  1847. if (pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG) {
  1848. if ((tul_msgin_accept(pCurHcb)) == -1)
  1849. return (-1);
  1850. if (pCurHcb->HCS_Phase != MSG_IN)
  1851. goto no_tag;
  1852. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1853. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1854. if ((wait_tulip(pCurHcb)) == -1)
  1855. return (-1);
  1856. msg = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag Message */
  1857. if ((msg < MSG_STAG) || (msg > MSG_OTAG)) /* Is simple Tag */
  1858. goto no_tag;
  1859. if ((tul_msgin_accept(pCurHcb)) == -1)
  1860. return (-1);
  1861. if (pCurHcb->HCS_Phase != MSG_IN)
  1862. goto no_tag;
  1863. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1864. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1865. if ((wait_tulip(pCurHcb)) == -1)
  1866. return (-1);
  1867. tag = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* Read Tag ID */
  1868. pCurScb = pCurHcb->HCS_Scb + tag;
  1869. if ((pCurScb->SCB_Target != tar) || (pCurScb->SCB_Lun != lun)) {
  1870. return tul_msgout_abort_tag(pCurHcb);
  1871. }
  1872. if (pCurScb->SCB_Status != SCB_BUSY) { /* 03/24/95 */
  1873. return tul_msgout_abort_tag(pCurHcb);
  1874. }
  1875. pCurHcb->HCS_ActScb = pCurScb;
  1876. if ((tul_msgin_accept(pCurHcb)) == -1)
  1877. return (-1);
  1878. } else { /* No tag */
  1879. no_tag:
  1880. if ((pCurScb = tul_find_busy_scb(pCurHcb, tar | (lun << 8))) == NULL) {
  1881. return tul_msgout_abort_targ(pCurHcb);
  1882. }
  1883. pCurHcb->HCS_ActScb = pCurScb;
  1884. if (!(pCurTcb->TCS_DrvFlags & TCF_DRV_EN_TAG)) {
  1885. if ((tul_msgin_accept(pCurHcb)) == -1)
  1886. return (-1);
  1887. }
  1888. }
  1889. return 0;
  1890. }
  1891. /***************************************************************************/
  1892. static int int_tul_bad_seq(HCS * pCurHcb)
  1893. { /* target wrong phase */
  1894. SCB *pCurScb;
  1895. int i;
  1896. tul_reset_scsi(pCurHcb, 10);
  1897. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  1898. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  1899. tul_append_done_scb(pCurHcb, pCurScb);
  1900. }
  1901. for (i = 0; i < pCurHcb->HCS_MaxTar; i++) {
  1902. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  1903. }
  1904. return (-1);
  1905. }
  1906. /***************************************************************************/
  1907. int tul_msgout_abort_targ(HCS * pCurHcb)
  1908. {
  1909. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1910. if (tul_msgin_accept(pCurHcb) == -1)
  1911. return (-1);
  1912. if (pCurHcb->HCS_Phase != MSG_OUT)
  1913. return (tul_bad_seq(pCurHcb));
  1914. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT);
  1915. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1916. return tul_wait_disc(pCurHcb);
  1917. }
  1918. /***************************************************************************/
  1919. int tul_msgout_abort_tag(HCS * pCurHcb)
  1920. {
  1921. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1922. if (tul_msgin_accept(pCurHcb) == -1)
  1923. return (-1);
  1924. if (pCurHcb->HCS_Phase != MSG_OUT)
  1925. return (tul_bad_seq(pCurHcb));
  1926. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_ABORT_TAG);
  1927. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1928. return tul_wait_disc(pCurHcb);
  1929. }
  1930. /***************************************************************************/
  1931. int tul_msgin(HCS * pCurHcb)
  1932. {
  1933. TCS *pCurTcb;
  1934. for (;;) {
  1935. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1936. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  1937. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1938. if ((wait_tulip(pCurHcb)) == -1)
  1939. return (-1);
  1940. switch (TUL_RD(pCurHcb->HCS_Base, TUL_SFifo)) {
  1941. case MSG_DISC: /* Disconnect msg */
  1942. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1943. return tul_wait_disc(pCurHcb);
  1944. case MSG_SDP:
  1945. case MSG_RESTORE:
  1946. case MSG_NOP:
  1947. tul_msgin_accept(pCurHcb);
  1948. break;
  1949. case MSG_REJ: /* Clear ATN first */
  1950. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal,
  1951. (TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)));
  1952. pCurTcb = pCurHcb->HCS_ActTcs;
  1953. if ((pCurTcb->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0) { /* do sync nego */
  1954. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1955. }
  1956. tul_msgin_accept(pCurHcb);
  1957. break;
  1958. case MSG_EXTEND: /* extended msg */
  1959. tul_msgin_extend(pCurHcb);
  1960. break;
  1961. case MSG_IGNOREWIDE:
  1962. tul_msgin_accept(pCurHcb);
  1963. break;
  1964. /* get */
  1965. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  1966. if (wait_tulip(pCurHcb) == -1)
  1967. return -1;
  1968. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 0); /* put pad */
  1969. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get IGNORE field */
  1970. TUL_RD(pCurHcb->HCS_Base, TUL_SFifo); /* get pad */
  1971. tul_msgin_accept(pCurHcb);
  1972. break;
  1973. case MSG_COMP:
  1974. {
  1975. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  1976. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  1977. return tul_wait_done_disc(pCurHcb);
  1978. }
  1979. default:
  1980. tul_msgout_reject(pCurHcb);
  1981. break;
  1982. }
  1983. if (pCurHcb->HCS_Phase != MSG_IN)
  1984. return (pCurHcb->HCS_Phase);
  1985. }
  1986. /* statement won't reach here */
  1987. }
  1988. /***************************************************************************/
  1989. int tul_msgout_reject(HCS * pCurHcb)
  1990. {
  1991. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  1992. if ((tul_msgin_accept(pCurHcb)) == -1)
  1993. return (-1);
  1994. if (pCurHcb->HCS_Phase == MSG_OUT) {
  1995. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_REJ); /* Msg reject */
  1996. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  1997. return (wait_tulip(pCurHcb));
  1998. }
  1999. return (pCurHcb->HCS_Phase);
  2000. }
  2001. /***************************************************************************/
  2002. int tul_msgout_ide(HCS * pCurHcb)
  2003. {
  2004. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_IDE); /* Initiator Detected Error */
  2005. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2006. return (wait_tulip(pCurHcb));
  2007. }
  2008. /***************************************************************************/
  2009. int tul_msgin_extend(HCS * pCurHcb)
  2010. {
  2011. BYTE len, idx;
  2012. if (tul_msgin_accept(pCurHcb) != MSG_IN)
  2013. return (pCurHcb->HCS_Phase);
  2014. /* Get extended msg length */
  2015. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  2016. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  2017. if (wait_tulip(pCurHcb) == -1)
  2018. return (-1);
  2019. len = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  2020. pCurHcb->HCS_Msg[0] = len;
  2021. for (idx = 1; len != 0; len--) {
  2022. if ((tul_msgin_accept(pCurHcb)) != MSG_IN)
  2023. return (pCurHcb->HCS_Phase);
  2024. TUL_WRLONG(pCurHcb->HCS_Base + TUL_SCnt0, 1);
  2025. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_IN);
  2026. if (wait_tulip(pCurHcb) == -1)
  2027. return (-1);
  2028. pCurHcb->HCS_Msg[idx++] = TUL_RD(pCurHcb->HCS_Base, TUL_SFifo);
  2029. }
  2030. if (pCurHcb->HCS_Msg[1] == 1) { /* if it's synchronous data transfer request */
  2031. if (pCurHcb->HCS_Msg[0] != 3) /* if length is not right */
  2032. return (tul_msgout_reject(pCurHcb));
  2033. if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_SYNC_NEGO) { /* Set OFFSET=0 to do async, nego back */
  2034. pCurHcb->HCS_Msg[3] = 0;
  2035. } else {
  2036. if ((tul_msgin_sync(pCurHcb) == 0) &&
  2037. (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SYNC_DONE)) {
  2038. tul_sync_done(pCurHcb);
  2039. return (tul_msgin_accept(pCurHcb));
  2040. }
  2041. }
  2042. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2043. if ((tul_msgin_accept(pCurHcb)) != MSG_OUT)
  2044. return (pCurHcb->HCS_Phase);
  2045. /* sync msg out */
  2046. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO);
  2047. tul_sync_done(pCurHcb);
  2048. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  2049. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3);
  2050. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 1);
  2051. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]);
  2052. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[3]);
  2053. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2054. return (wait_tulip(pCurHcb));
  2055. }
  2056. if ((pCurHcb->HCS_Msg[0] != 2) || (pCurHcb->HCS_Msg[1] != 3))
  2057. return (tul_msgout_reject(pCurHcb));
  2058. /* if it's WIDE DATA XFER REQ */
  2059. if (pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) {
  2060. pCurHcb->HCS_Msg[2] = 0;
  2061. } else {
  2062. if (pCurHcb->HCS_Msg[2] > 2) /* > 32 bits */
  2063. return (tul_msgout_reject(pCurHcb));
  2064. if (pCurHcb->HCS_Msg[2] == 2) { /* == 32 */
  2065. pCurHcb->HCS_Msg[2] = 1;
  2066. } else {
  2067. if ((pCurHcb->HCS_ActTcs->TCS_Flags & TCF_NO_WDTR) == 0) {
  2068. wdtr_done(pCurHcb);
  2069. if ((pCurHcb->HCS_ActTcs->TCS_Flags & (TCF_SYNC_DONE | TCF_NO_SYNC_NEGO)) == 0)
  2070. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2071. return (tul_msgin_accept(pCurHcb));
  2072. }
  2073. }
  2074. }
  2075. TUL_WR(pCurHcb->HCS_Base + TUL_SSignal, ((TUL_RD(pCurHcb->HCS_Base, TUL_SSignal) & (TSC_SET_ACK | 7)) | TSC_SET_ATN));
  2076. if (tul_msgin_accept(pCurHcb) != MSG_OUT)
  2077. return (pCurHcb->HCS_Phase);
  2078. /* WDTR msg out */
  2079. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_EXTEND);
  2080. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 2);
  2081. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, 3);
  2082. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurHcb->HCS_Msg[2]);
  2083. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2084. return (wait_tulip(pCurHcb));
  2085. }
  2086. /***************************************************************************/
  2087. int tul_msgin_sync(HCS * pCurHcb)
  2088. {
  2089. char default_period;
  2090. default_period = tul_rate_tbl[pCurHcb->HCS_ActTcs->TCS_Flags & TCF_SCSI_RATE];
  2091. if (pCurHcb->HCS_Msg[3] > MAX_OFFSET) {
  2092. pCurHcb->HCS_Msg[3] = MAX_OFFSET;
  2093. if (pCurHcb->HCS_Msg[2] < default_period) {
  2094. pCurHcb->HCS_Msg[2] = default_period;
  2095. return 1;
  2096. }
  2097. if (pCurHcb->HCS_Msg[2] >= 59) { /* Change to async */
  2098. pCurHcb->HCS_Msg[3] = 0;
  2099. }
  2100. return 1;
  2101. }
  2102. /* offset requests asynchronous transfers ? */
  2103. if (pCurHcb->HCS_Msg[3] == 0) {
  2104. return 0;
  2105. }
  2106. if (pCurHcb->HCS_Msg[2] < default_period) {
  2107. pCurHcb->HCS_Msg[2] = default_period;
  2108. return 1;
  2109. }
  2110. if (pCurHcb->HCS_Msg[2] >= 59) {
  2111. pCurHcb->HCS_Msg[3] = 0;
  2112. return 1;
  2113. }
  2114. return 0;
  2115. }
  2116. /***************************************************************************/
  2117. int wdtr_done(HCS * pCurHcb)
  2118. {
  2119. pCurHcb->HCS_ActTcs->TCS_Flags &= ~TCF_SYNC_DONE;
  2120. pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_WDTR_DONE;
  2121. pCurHcb->HCS_ActTcs->TCS_JS_Period = 0;
  2122. if (pCurHcb->HCS_Msg[2]) { /* if 16 bit */
  2123. pCurHcb->HCS_ActTcs->TCS_JS_Period |= TSC_WIDE_SCSI;
  2124. }
  2125. pCurHcb->HCS_ActTcs->TCS_SConfig0 &= ~TSC_ALT_PERIOD;
  2126. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0);
  2127. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
  2128. return 1;
  2129. }
  2130. /***************************************************************************/
  2131. int tul_sync_done(HCS * pCurHcb)
  2132. {
  2133. int i;
  2134. pCurHcb->HCS_ActTcs->TCS_Flags |= TCF_SYNC_DONE;
  2135. if (pCurHcb->HCS_Msg[3]) {
  2136. pCurHcb->HCS_ActTcs->TCS_JS_Period |= pCurHcb->HCS_Msg[3];
  2137. for (i = 0; i < 8; i++) {
  2138. if (tul_rate_tbl[i] >= pCurHcb->HCS_Msg[2]) /* pick the big one */
  2139. break;
  2140. }
  2141. pCurHcb->HCS_ActTcs->TCS_JS_Period |= (i << 4);
  2142. pCurHcb->HCS_ActTcs->TCS_SConfig0 |= TSC_ALT_PERIOD;
  2143. }
  2144. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, pCurHcb->HCS_ActTcs->TCS_SConfig0);
  2145. TUL_WR(pCurHcb->HCS_Base + TUL_SPeriod, pCurHcb->HCS_ActTcs->TCS_JS_Period);
  2146. return (-1);
  2147. }
  2148. int tul_post_scsi_rst(HCS * pCurHcb)
  2149. {
  2150. SCB *pCurScb;
  2151. TCS *pCurTcb;
  2152. int i;
  2153. pCurHcb->HCS_ActScb = NULL;
  2154. pCurHcb->HCS_ActTcs = NULL;
  2155. pCurHcb->HCS_Flags = 0;
  2156. while ((pCurScb = tul_pop_busy_scb(pCurHcb)) != NULL) {
  2157. pCurScb->SCB_HaStat = HOST_BAD_PHAS;
  2158. tul_append_done_scb(pCurHcb, pCurScb);
  2159. }
  2160. /* clear sync done flag */
  2161. pCurTcb = &pCurHcb->HCS_Tcs[0];
  2162. for (i = 0; i < pCurHcb->HCS_MaxTar; pCurTcb++, i++) {
  2163. pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE);
  2164. /* Initialize the sync. xfer register values to an asyn xfer */
  2165. pCurTcb->TCS_JS_Period = 0;
  2166. pCurTcb->TCS_SConfig0 = pCurHcb->HCS_SConf1;
  2167. pCurHcb->HCS_ActTags[0] = 0; /* 07/22/98 */
  2168. pCurHcb->HCS_Tcs[i].TCS_Flags &= ~TCF_BUSY; /* 07/22/98 */
  2169. } /* for */
  2170. return (-1);
  2171. }
  2172. /***************************************************************************/
  2173. void tul_select_atn_stop(HCS * pCurHcb, SCB * pCurScb)
  2174. {
  2175. pCurScb->SCB_Status |= SCB_SELECT;
  2176. pCurScb->SCB_NxtStat = 0x1;
  2177. pCurHcb->HCS_ActScb = pCurScb;
  2178. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2179. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SELATNSTOP);
  2180. return;
  2181. }
  2182. /***************************************************************************/
  2183. void tul_select_atn(HCS * pCurHcb, SCB * pCurScb)
  2184. {
  2185. int i;
  2186. pCurScb->SCB_Status |= SCB_SELECT;
  2187. pCurScb->SCB_NxtStat = 0x2;
  2188. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  2189. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  2190. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  2191. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2192. pCurHcb->HCS_ActScb = pCurScb;
  2193. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN);
  2194. return;
  2195. }
  2196. /***************************************************************************/
  2197. void tul_select_atn3(HCS * pCurHcb, SCB * pCurScb)
  2198. {
  2199. int i;
  2200. pCurScb->SCB_Status |= SCB_SELECT;
  2201. pCurScb->SCB_NxtStat = 0x2;
  2202. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_Ident);
  2203. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagMsg);
  2204. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_TagId);
  2205. for (i = 0; i < (int) pCurScb->SCB_CDBLen; i++)
  2206. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, pCurScb->SCB_CDB[i]);
  2207. pCurHcb->HCS_ActTcs = &pCurHcb->HCS_Tcs[pCurScb->SCB_Target];
  2208. pCurHcb->HCS_ActScb = pCurScb;
  2209. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_SEL_ATN3);
  2210. return;
  2211. }
  2212. /***************************************************************************/
  2213. /* SCSI Bus Device Reset */
  2214. int tul_bus_device_reset(HCS * pCurHcb)
  2215. {
  2216. SCB *pCurScb = pCurHcb->HCS_ActScb;
  2217. TCS *pCurTcb = pCurHcb->HCS_ActTcs;
  2218. SCB *pTmpScb, *pPrevScb;
  2219. BYTE tar;
  2220. if (pCurHcb->HCS_Phase != MSG_OUT) {
  2221. return (int_tul_bad_seq(pCurHcb)); /* Unexpected phase */
  2222. }
  2223. tul_unlink_pend_scb(pCurHcb, pCurScb);
  2224. tul_release_scb(pCurHcb, pCurScb);
  2225. tar = pCurScb->SCB_Target; /* target */
  2226. pCurTcb->TCS_Flags &= ~(TCF_SYNC_DONE | TCF_WDTR_DONE | TCF_BUSY);
  2227. /* clr sync. nego & WDTR flags 07/22/98 */
  2228. /* abort all SCB with same target */
  2229. pPrevScb = pTmpScb = pCurHcb->HCS_FirstBusy; /* Check Busy queue */
  2230. while (pTmpScb != NULL) {
  2231. if (pTmpScb->SCB_Target == tar) {
  2232. /* unlink it */
  2233. if (pTmpScb == pCurHcb->HCS_FirstBusy) {
  2234. if ((pCurHcb->HCS_FirstBusy = pTmpScb->SCB_NxtScb) == NULL)
  2235. pCurHcb->HCS_LastBusy = NULL;
  2236. } else {
  2237. pPrevScb->SCB_NxtScb = pTmpScb->SCB_NxtScb;
  2238. if (pTmpScb == pCurHcb->HCS_LastBusy)
  2239. pCurHcb->HCS_LastBusy = pPrevScb;
  2240. }
  2241. pTmpScb->SCB_HaStat = HOST_ABORTED;
  2242. tul_append_done_scb(pCurHcb, pTmpScb);
  2243. }
  2244. /* Previous haven't change */
  2245. else {
  2246. pPrevScb = pTmpScb;
  2247. }
  2248. pTmpScb = pTmpScb->SCB_NxtScb;
  2249. }
  2250. TUL_WR(pCurHcb->HCS_Base + TUL_SFifo, MSG_DEVRST);
  2251. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_XF_FIFO_OUT);
  2252. return tul_wait_disc(pCurHcb);
  2253. }
  2254. /***************************************************************************/
  2255. int tul_msgin_accept(HCS * pCurHcb)
  2256. {
  2257. TUL_WR(pCurHcb->HCS_Base + TUL_SCmd, TSC_MSG_ACCEPT);
  2258. return (wait_tulip(pCurHcb));
  2259. }
  2260. /***************************************************************************/
  2261. int wait_tulip(HCS * pCurHcb)
  2262. {
  2263. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2264. & TSS_INT_PENDING));
  2265. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2266. pCurHcb->HCS_Phase = pCurHcb->HCS_JSStatus0 & TSS_PH_MASK;
  2267. pCurHcb->HCS_JSStatus1 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus1);
  2268. if (pCurHcb->HCS_JSInt & TSS_RESEL_INT) { /* if SCSI bus reset detected */
  2269. return (int_tul_resel(pCurHcb));
  2270. }
  2271. if (pCurHcb->HCS_JSInt & TSS_SEL_TIMEOUT) { /* if selected/reselected timeout interrupt */
  2272. return (int_tul_busfree(pCurHcb));
  2273. }
  2274. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2275. return (int_tul_scsi_rst(pCurHcb));
  2276. }
  2277. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2278. if (pCurHcb->HCS_Flags & HCF_EXPECT_DONE_DISC) {
  2279. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2280. tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2281. pCurHcb->HCS_ActScb->SCB_HaStat = 0;
  2282. tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2283. pCurHcb->HCS_ActScb = NULL;
  2284. pCurHcb->HCS_ActTcs = NULL;
  2285. pCurHcb->HCS_Flags &= ~HCF_EXPECT_DONE_DISC;
  2286. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2287. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2288. return (-1);
  2289. }
  2290. if (pCurHcb->HCS_Flags & HCF_EXPECT_DISC) {
  2291. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2292. pCurHcb->HCS_ActScb = NULL;
  2293. pCurHcb->HCS_ActTcs = NULL;
  2294. pCurHcb->HCS_Flags &= ~HCF_EXPECT_DISC;
  2295. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2296. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2297. return (-1);
  2298. }
  2299. return (int_tul_busfree(pCurHcb));
  2300. }
  2301. if (pCurHcb->HCS_JSInt & (TSS_FUNC_COMP | TSS_BUS_SERV)) {
  2302. return (pCurHcb->HCS_Phase);
  2303. }
  2304. return (pCurHcb->HCS_Phase);
  2305. }
  2306. /***************************************************************************/
  2307. int tul_wait_disc(HCS * pCurHcb)
  2308. {
  2309. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2310. & TSS_INT_PENDING));
  2311. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2312. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2313. return (int_tul_scsi_rst(pCurHcb));
  2314. }
  2315. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2316. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2317. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2318. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2319. pCurHcb->HCS_ActScb = NULL;
  2320. return (-1);
  2321. }
  2322. return (tul_bad_seq(pCurHcb));
  2323. }
  2324. /***************************************************************************/
  2325. int tul_wait_done_disc(HCS * pCurHcb)
  2326. {
  2327. while (!((pCurHcb->HCS_JSStatus0 = TUL_RD(pCurHcb->HCS_Base, TUL_SStatus0))
  2328. & TSS_INT_PENDING));
  2329. pCurHcb->HCS_JSInt = TUL_RD(pCurHcb->HCS_Base, TUL_SInt);
  2330. if (pCurHcb->HCS_JSInt & TSS_SCSIRST_INT) { /* if SCSI bus reset detected */
  2331. return (int_tul_scsi_rst(pCurHcb));
  2332. }
  2333. if (pCurHcb->HCS_JSInt & TSS_DISC_INT) { /* BUS disconnection */
  2334. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl0, TSC_FLUSH_FIFO); /* Flush SCSI FIFO */
  2335. TUL_WR(pCurHcb->HCS_Base + TUL_SConfig, TSC_INITDEFAULT);
  2336. TUL_WR(pCurHcb->HCS_Base + TUL_SCtrl1, TSC_HW_RESELECT); /* Enable HW reselect */
  2337. tul_unlink_busy_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2338. tul_append_done_scb(pCurHcb, pCurHcb->HCS_ActScb);
  2339. pCurHcb->HCS_ActScb = NULL;
  2340. return (-1);
  2341. }
  2342. return (tul_bad_seq(pCurHcb));
  2343. }
  2344. static irqreturn_t i91u_intr(int irqno, void *dev_id, struct pt_regs *regs)
  2345. {
  2346. struct Scsi_Host *dev = dev_id;
  2347. unsigned long flags;
  2348. spin_lock_irqsave(dev->host_lock, flags);
  2349. tul_isr((HCS *)dev->base);
  2350. spin_unlock_irqrestore(dev->host_lock, flags);
  2351. return IRQ_HANDLED;
  2352. }
  2353. static int tul_NewReturnNumberOfAdapters(void)
  2354. {
  2355. struct pci_dev *pDev = NULL; /* Start from none */
  2356. int iAdapters = 0;
  2357. long dRegValue;
  2358. WORD wBIOS;
  2359. int i = 0;
  2360. init_i91uAdapter_table();
  2361. for (i = 0; i < TULSZ(i91u_pci_devices); i++)
  2362. {
  2363. while ((pDev = pci_find_device(i91u_pci_devices[i].vendor_id, i91u_pci_devices[i].device_id, pDev)) != NULL) {
  2364. if (pci_enable_device(pDev))
  2365. continue;
  2366. pci_read_config_dword(pDev, 0x44, (u32 *) & dRegValue);
  2367. wBIOS = (UWORD) (dRegValue & 0xFF);
  2368. if (((dRegValue & 0xFF00) >> 8) == 0xFF)
  2369. dRegValue = 0;
  2370. wBIOS = (wBIOS << 8) + ((UWORD) ((dRegValue & 0xFF00) >> 8));
  2371. if (pci_set_dma_mask(pDev, DMA_32BIT_MASK)) {
  2372. printk(KERN_WARNING
  2373. "i91u: Could not set 32 bit DMA mask\n");
  2374. continue;
  2375. }
  2376. if (Addi91u_into_Adapter_table(wBIOS,
  2377. (pDev->resource[0].start),
  2378. pDev->irq,
  2379. pDev->bus->number,
  2380. (pDev->devfn >> 3)
  2381. ) == 0)
  2382. iAdapters++;
  2383. }
  2384. }
  2385. return (iAdapters);
  2386. }
  2387. static int i91u_detect(struct scsi_host_template * tpnt)
  2388. {
  2389. HCS *pHCB;
  2390. struct Scsi_Host *hreg;
  2391. unsigned long i; /* 01/14/98 */
  2392. int ok = 0, iAdapters;
  2393. ULONG dBiosAdr;
  2394. BYTE *pbBiosAdr;
  2395. /* Get total number of adapters in the motherboard */
  2396. iAdapters = tul_NewReturnNumberOfAdapters();
  2397. if (iAdapters == 0) /* If no tulip founded, return */
  2398. return (0);
  2399. tul_num_ch = (iAdapters > tul_num_ch) ? tul_num_ch : iAdapters;
  2400. /* Update actually channel number */
  2401. if (tul_tag_enable) { /* 1.01i */
  2402. tul_num_scb = MAX_TARGETS * i91u_MAXQUEUE;
  2403. } else {
  2404. tul_num_scb = MAX_TARGETS + 3; /* 1-tape, 1-CD_ROM, 1- extra */
  2405. } /* Update actually SCBs per adapter */
  2406. /* Get total memory needed for HCS */
  2407. i = tul_num_ch * sizeof(HCS);
  2408. memset((unsigned char *) &tul_hcs[0], 0, i); /* Initialize tul_hcs 0 */
  2409. /* Get total memory needed for SCB */
  2410. for (; tul_num_scb >= MAX_TARGETS + 3; tul_num_scb--) {
  2411. i = tul_num_ch * tul_num_scb * sizeof(SCB);
  2412. if ((tul_scb = (SCB *) kmalloc(i, GFP_ATOMIC | GFP_DMA)) != NULL)
  2413. break;
  2414. }
  2415. if (tul_scb == NULL) {
  2416. printk("i91u: SCB memory allocation error\n");
  2417. return (0);
  2418. }
  2419. memset((unsigned char *) tul_scb, 0, i);
  2420. for (i = 0, pHCB = &tul_hcs[0]; /* Get pointer for control block */
  2421. i < tul_num_ch;
  2422. i++, pHCB++) {
  2423. get_tulipPCIConfig(pHCB, i);
  2424. dBiosAdr = pHCB->HCS_BIOS;
  2425. dBiosAdr = (dBiosAdr << 4);
  2426. pbBiosAdr = phys_to_virt(dBiosAdr);
  2427. init_tulip(pHCB, tul_scb + (i * tul_num_scb), tul_num_scb, pbBiosAdr, 10);
  2428. request_region(pHCB->HCS_Base, 256, "i91u"); /* Register */
  2429. pHCB->HCS_Index = i; /* 7/29/98 */
  2430. hreg = scsi_register(tpnt, sizeof(HCS));
  2431. if(hreg == NULL) {
  2432. release_region(pHCB->HCS_Base, 256);
  2433. return 0;
  2434. }
  2435. hreg->io_port = pHCB->HCS_Base;
  2436. hreg->n_io_port = 0xff;
  2437. hreg->can_queue = tul_num_scb; /* 03/05/98 */
  2438. hreg->unique_id = pHCB->HCS_Base;
  2439. hreg->max_id = pHCB->HCS_MaxTar;
  2440. hreg->max_lun = 32; /* 10/21/97 */
  2441. hreg->irq = pHCB->HCS_Intr;
  2442. hreg->this_id = pHCB->HCS_SCSI_ID; /* Assign HCS index */
  2443. hreg->base = (unsigned long)pHCB;
  2444. hreg->sg_tablesize = TOTAL_SG_ENTRY; /* Maximun support is 32 */
  2445. /* Initial tulip chip */
  2446. ok = request_irq(pHCB->HCS_Intr, i91u_intr, SA_INTERRUPT | SA_SHIRQ, "i91u", hreg);
  2447. if (ok < 0) {
  2448. printk(KERN_WARNING "i91u: unable to request IRQ %d\n\n", pHCB->HCS_Intr);
  2449. return 0;
  2450. }
  2451. }
  2452. tpnt->this_id = -1;
  2453. tpnt->can_queue = 1;
  2454. return 1;
  2455. }
  2456. static void i91uBuildSCB(HCS * pHCB, SCB * pSCB, struct scsi_cmnd * SCpnt)
  2457. { /* Create corresponding SCB */
  2458. struct scatterlist *pSrbSG;
  2459. SG *pSG; /* Pointer to SG list */
  2460. int i;
  2461. long TotalLen;
  2462. dma_addr_t dma_addr;
  2463. pSCB->SCB_Post = i91uSCBPost; /* i91u's callback routine */
  2464. pSCB->SCB_Srb = SCpnt;
  2465. pSCB->SCB_Opcode = ExecSCSI;
  2466. pSCB->SCB_Flags = SCF_POST; /* After SCSI done, call post routine */
  2467. pSCB->SCB_Target = SCpnt->device->id;
  2468. pSCB->SCB_Lun = SCpnt->device->lun;
  2469. pSCB->SCB_Ident = SCpnt->device->lun | DISC_ALLOW;
  2470. pSCB->SCB_Flags |= SCF_SENSE; /* Turn on auto request sense */
  2471. dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->sense_buffer,
  2472. SENSE_SIZE, DMA_FROM_DEVICE);
  2473. pSCB->SCB_SensePtr = cpu_to_le32((u32)dma_addr);
  2474. pSCB->SCB_SenseLen = cpu_to_le32(SENSE_SIZE);
  2475. SCpnt->SCp.ptr = (char *)(unsigned long)dma_addr;
  2476. pSCB->SCB_CDBLen = SCpnt->cmd_len;
  2477. pSCB->SCB_HaStat = 0;
  2478. pSCB->SCB_TaStat = 0;
  2479. memcpy(&pSCB->SCB_CDB[0], &SCpnt->cmnd, SCpnt->cmd_len);
  2480. if (SCpnt->device->tagged_supported) { /* Tag Support */
  2481. pSCB->SCB_TagMsg = SIMPLE_QUEUE_TAG; /* Do simple tag only */
  2482. } else {
  2483. pSCB->SCB_TagMsg = 0; /* No tag support */
  2484. }
  2485. /* todo handle map_sg error */
  2486. if (SCpnt->use_sg) {
  2487. dma_addr = dma_map_single(&pHCB->pci_dev->dev, &pSCB->SCB_SGList[0],
  2488. sizeof(struct SG_Struc) * TOTAL_SG_ENTRY,
  2489. DMA_BIDIRECTIONAL);
  2490. pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr);
  2491. SCpnt->SCp.dma_handle = dma_addr;
  2492. pSrbSG = (struct scatterlist *) SCpnt->request_buffer;
  2493. pSCB->SCB_SGLen = dma_map_sg(&pHCB->pci_dev->dev, pSrbSG,
  2494. SCpnt->use_sg, SCpnt->sc_data_direction);
  2495. pSCB->SCB_Flags |= SCF_SG; /* Turn on SG list flag */
  2496. for (i = 0, TotalLen = 0, pSG = &pSCB->SCB_SGList[0]; /* 1.01g */
  2497. i < pSCB->SCB_SGLen; i++, pSG++, pSrbSG++) {
  2498. pSG->SG_Ptr = cpu_to_le32((u32)sg_dma_address(pSrbSG));
  2499. TotalLen += pSG->SG_Len = cpu_to_le32((u32)sg_dma_len(pSrbSG));
  2500. }
  2501. pSCB->SCB_BufLen = (SCpnt->request_bufflen > TotalLen) ?
  2502. TotalLen : SCpnt->request_bufflen;
  2503. } else if (SCpnt->request_bufflen) { /* Non SG */
  2504. dma_addr = dma_map_single(&pHCB->pci_dev->dev, SCpnt->request_buffer,
  2505. SCpnt->request_bufflen,
  2506. SCpnt->sc_data_direction);
  2507. SCpnt->SCp.dma_handle = dma_addr;
  2508. pSCB->SCB_BufPtr = cpu_to_le32((u32)dma_addr);
  2509. pSCB->SCB_BufLen = cpu_to_le32((u32)SCpnt->request_bufflen);
  2510. pSCB->SCB_SGLen = 0;
  2511. } else {
  2512. pSCB->SCB_BufLen = 0;
  2513. pSCB->SCB_SGLen = 0;
  2514. }
  2515. }
  2516. static int i91u_queuecommand(struct scsi_cmnd *cmd,
  2517. void (*done)(struct scsi_cmnd *))
  2518. {
  2519. HCS *pHCB = (HCS *) cmd->device->host->base;
  2520. register SCB *pSCB;
  2521. cmd->scsi_done = done;
  2522. pSCB = tul_alloc_scb(pHCB);
  2523. if (!pSCB)
  2524. return SCSI_MLQUEUE_HOST_BUSY;
  2525. i91uBuildSCB(pHCB, pSCB, cmd);
  2526. tul_exec_scb(pHCB, pSCB);
  2527. return 0;
  2528. }
  2529. #if 0 /* no new EH yet */
  2530. /*
  2531. * Abort a queued command
  2532. * (commands that are on the bus can't be aborted easily)
  2533. */
  2534. static int i91u_abort(struct scsi_cmnd * SCpnt)
  2535. {
  2536. HCS *pHCB;
  2537. pHCB = (HCS *) SCpnt->device->host->base;
  2538. return tul_abort_srb(pHCB, SCpnt);
  2539. }
  2540. /*
  2541. * Reset registers, reset a hanging bus and
  2542. * kill active and disconnected commands for target w/o soft reset
  2543. */
  2544. static int i91u_reset(struct scsi_cmnd * SCpnt, unsigned int reset_flags)
  2545. { /* I need Host Control Block Information */
  2546. HCS *pHCB;
  2547. pHCB = (HCS *) SCpnt->device->host->base;
  2548. if (reset_flags & (SCSI_RESET_SUGGEST_BUS_RESET | SCSI_RESET_SUGGEST_HOST_RESET))
  2549. return tul_reset_scsi_bus(pHCB);
  2550. else
  2551. return tul_device_reset(pHCB, SCpnt, SCpnt->device->id, reset_flags);
  2552. }
  2553. #endif
  2554. static int i91u_bus_reset(struct scsi_cmnd * SCpnt)
  2555. {
  2556. HCS *pHCB;
  2557. pHCB = (HCS *) SCpnt->device->host->base;
  2558. spin_lock_irq(SCpnt->device->host->host_lock);
  2559. tul_reset_scsi(pHCB, 0);
  2560. spin_unlock_irq(SCpnt->device->host->host_lock);
  2561. return SUCCESS;
  2562. }
  2563. /*
  2564. * Return the "logical geometry"
  2565. */
  2566. static int i91u_biosparam(struct scsi_device *sdev, struct block_device *dev,
  2567. sector_t capacity, int *info_array)
  2568. {
  2569. HCS *pHcb; /* Point to Host adapter control block */
  2570. TCS *pTcb;
  2571. pHcb = (HCS *) sdev->host->base;
  2572. pTcb = &pHcb->HCS_Tcs[sdev->id];
  2573. if (pTcb->TCS_DrvHead) {
  2574. info_array[0] = pTcb->TCS_DrvHead;
  2575. info_array[1] = pTcb->TCS_DrvSector;
  2576. info_array[2] = (unsigned long)capacity / pTcb->TCS_DrvHead / pTcb->TCS_DrvSector;
  2577. } else {
  2578. if (pTcb->TCS_DrvFlags & TCF_DRV_255_63) {
  2579. info_array[0] = 255;
  2580. info_array[1] = 63;
  2581. info_array[2] = (unsigned long)capacity / 255 / 63;
  2582. } else {
  2583. info_array[0] = 64;
  2584. info_array[1] = 32;
  2585. info_array[2] = (unsigned long)capacity >> 11;
  2586. }
  2587. }
  2588. #if defined(DEBUG_BIOSPARAM)
  2589. if (i91u_debug & debug_biosparam) {
  2590. printk("bios geometry: head=%d, sec=%d, cyl=%d\n",
  2591. info_array[0], info_array[1], info_array[2]);
  2592. printk("WARNING: check, if the bios geometry is correct.\n");
  2593. }
  2594. #endif
  2595. return 0;
  2596. }
  2597. static void i91u_unmap_cmnd(struct pci_dev *pci_dev, struct scsi_cmnd *cmnd)
  2598. {
  2599. /* auto sense buffer */
  2600. if (cmnd->SCp.ptr) {
  2601. dma_unmap_single(&pci_dev->dev,
  2602. (dma_addr_t)((unsigned long)cmnd->SCp.ptr),
  2603. SENSE_SIZE, DMA_FROM_DEVICE);
  2604. cmnd->SCp.ptr = NULL;
  2605. }
  2606. /* request buffer */
  2607. if (cmnd->use_sg) {
  2608. dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
  2609. sizeof(struct SG_Struc) * TOTAL_SG_ENTRY,
  2610. DMA_BIDIRECTIONAL);
  2611. dma_unmap_sg(&pci_dev->dev, cmnd->request_buffer,
  2612. cmnd->use_sg,
  2613. cmnd->sc_data_direction);
  2614. } else if (cmnd->request_bufflen) {
  2615. dma_unmap_single(&pci_dev->dev, cmnd->SCp.dma_handle,
  2616. cmnd->request_bufflen,
  2617. cmnd->sc_data_direction);
  2618. }
  2619. }
  2620. /*****************************************************************************
  2621. Function name : i91uSCBPost
  2622. Description : This is callback routine be called when tulip finish one
  2623. SCSI command.
  2624. Input : pHCB - Pointer to host adapter control block.
  2625. pSCB - Pointer to SCSI control block.
  2626. Output : None.
  2627. Return : None.
  2628. *****************************************************************************/
  2629. static void i91uSCBPost(BYTE * pHcb, BYTE * pScb)
  2630. {
  2631. struct scsi_cmnd *pSRB; /* Pointer to SCSI request block */
  2632. HCS *pHCB;
  2633. SCB *pSCB;
  2634. pHCB = (HCS *) pHcb;
  2635. pSCB = (SCB *) pScb;
  2636. if ((pSRB = pSCB->SCB_Srb) == 0) {
  2637. printk("i91uSCBPost: SRB pointer is empty\n");
  2638. tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */
  2639. return;
  2640. }
  2641. switch (pSCB->SCB_HaStat) {
  2642. case 0x0:
  2643. case 0xa: /* Linked command complete without error and linked normally */
  2644. case 0xb: /* Linked command complete without error interrupt generated */
  2645. pSCB->SCB_HaStat = 0;
  2646. break;
  2647. case 0x11: /* Selection time out-The initiator selection or target
  2648. reselection was not complete within the SCSI Time out period */
  2649. pSCB->SCB_HaStat = DID_TIME_OUT;
  2650. break;
  2651. case 0x14: /* Target bus phase sequence failure-An invalid bus phase or bus
  2652. phase sequence was requested by the target. The host adapter
  2653. will generate a SCSI Reset Condition, notifying the host with
  2654. a SCRD interrupt */
  2655. pSCB->SCB_HaStat = DID_RESET;
  2656. break;
  2657. case 0x1a: /* SCB Aborted. 07/21/98 */
  2658. pSCB->SCB_HaStat = DID_ABORT;
  2659. break;
  2660. case 0x12: /* Data overrun/underrun-The target attempted to transfer more data
  2661. than was allocated by the Data Length field or the sum of the
  2662. Scatter / Gather Data Length fields. */
  2663. case 0x13: /* Unexpected bus free-The target dropped the SCSI BSY at an unexpected time. */
  2664. case 0x16: /* Invalid SCB Operation Code. */
  2665. default:
  2666. printk("ini9100u: %x %x\n", pSCB->SCB_HaStat, pSCB->SCB_TaStat);
  2667. pSCB->SCB_HaStat = DID_ERROR; /* Couldn't find any better */
  2668. break;
  2669. }
  2670. pSRB->result = pSCB->SCB_TaStat | (pSCB->SCB_HaStat << 16);
  2671. if (pSRB == NULL) {
  2672. printk("pSRB is NULL\n");
  2673. }
  2674. i91u_unmap_cmnd(pHCB->pci_dev, pSRB);
  2675. pSRB->scsi_done(pSRB); /* Notify system DONE */
  2676. tul_release_scb(pHCB, pSCB); /* Release SCB for current channel */
  2677. }
  2678. /*
  2679. * Release ressources
  2680. */
  2681. static int i91u_release(struct Scsi_Host *hreg)
  2682. {
  2683. free_irq(hreg->irq, hreg);
  2684. release_region(hreg->io_port, 256);
  2685. return 0;
  2686. }
  2687. MODULE_LICENSE("Dual BSD/GPL");
  2688. static struct scsi_host_template driver_template = {
  2689. .proc_name = "INI9100U",
  2690. .name = i91u_REVID,
  2691. .detect = i91u_detect,
  2692. .release = i91u_release,
  2693. .queuecommand = i91u_queuecommand,
  2694. // .abort = i91u_abort,
  2695. // .reset = i91u_reset,
  2696. .eh_bus_reset_handler = i91u_bus_reset,
  2697. .bios_param = i91u_biosparam,
  2698. .can_queue = 1,
  2699. .this_id = 1,
  2700. .sg_tablesize = SG_ALL,
  2701. .cmd_per_lun = 1,
  2702. .use_clustering = ENABLE_CLUSTERING,
  2703. };
  2704. #include "scsi_module.c"