gdth.c 203 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-04 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-04 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.2.x, 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.73 2004/03/31 13:33:03 achim
  34. * Special command 0xfd implemented to detect 64-bit DMA support
  35. *
  36. * Revision 1.72 2004/03/17 08:56:04 achim
  37. * 64-bit DMA only enabled if FW >= x.43
  38. *
  39. * Revision 1.71 2004/03/05 15:51:29 achim
  40. * Screen service: separate message buffer, bugfixes
  41. *
  42. * Revision 1.70 2004/02/27 12:19:07 achim
  43. * Bugfix: Reset bit in config (0xfe) call removed
  44. *
  45. * Revision 1.69 2004/02/20 09:50:24 achim
  46. * Compatibility changes for kernels < 2.4.20
  47. * Bugfix screen service command size
  48. * pci_set_dma_mask() error handling added
  49. *
  50. * Revision 1.68 2004/02/19 15:46:54 achim
  51. * 64-bit DMA bugfixes
  52. * Drive size bugfix for drives > 1TB
  53. *
  54. * Revision 1.67 2004/01/14 13:11:57 achim
  55. * Tool access over /proc no longer supported
  56. * Bugfixes IOCTLs
  57. *
  58. * Revision 1.66 2003/12/19 15:04:06 achim
  59. * Bugfixes support for drives > 2TB
  60. *
  61. * Revision 1.65 2003/12/15 11:21:56 achim
  62. * 64-bit DMA support added
  63. * Support for drives > 2 TB implemented
  64. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  65. *
  66. * Revision 1.64 2003/09/17 08:30:26 achim
  67. * EISA/ISA controller scan disabled
  68. * Command line switch probe_eisa_isa added
  69. *
  70. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  71. * Minor cleanups in gdth_ioctl.
  72. *
  73. * Revision 1.62 2003/02/27 15:01:59 achim
  74. * Dynamic DMA mapping implemented
  75. * New (character device) IOCTL interface added
  76. * Other controller related changes made
  77. *
  78. * Revision 1.61 2002/11/08 13:09:52 boji
  79. * Added support for XSCALE based RAID Controllers
  80. * Fixed SCREENSERVICE initialization in SMP cases
  81. * Added checks for gdth_polling before GDTH_HA_LOCK
  82. *
  83. * Revision 1.60 2002/02/05 09:35:22 achim
  84. * MODULE_LICENSE only if kernel >= 2.4.11
  85. *
  86. * Revision 1.59 2002/01/30 09:46:33 achim
  87. * Small changes
  88. *
  89. * Revision 1.58 2002/01/29 15:30:02 achim
  90. * Set default value of shared_access to Y
  91. * New status S_CACHE_RESERV for clustering added
  92. *
  93. * Revision 1.57 2001/08/21 11:16:35 achim
  94. * Bugfix free_irq()
  95. *
  96. * Revision 1.56 2001/08/09 11:19:39 achim
  97. * struct scsi_host_template changes
  98. *
  99. * Revision 1.55 2001/08/09 10:11:28 achim
  100. * Command HOST_UNFREEZE_IO before cache service init.
  101. *
  102. * Revision 1.54 2001/07/20 13:48:12 achim
  103. * Expand: gdth_analyse_hdrive() removed
  104. *
  105. * Revision 1.53 2001/07/17 09:52:49 achim
  106. * Small OEM related change
  107. *
  108. * Revision 1.52 2001/06/19 15:06:20 achim
  109. * New host command GDT_UNFREEZE_IO added
  110. *
  111. * Revision 1.51 2001/05/22 06:42:37 achim
  112. * PCI: Subdevice ID added
  113. *
  114. * Revision 1.50 2001/05/17 13:42:16 achim
  115. * Support for Intel Storage RAID Controllers added
  116. *
  117. * Revision 1.50 2001/05/17 12:12:34 achim
  118. * Support for Intel Storage RAID Controllers added
  119. *
  120. * Revision 1.49 2001/03/15 15:07:17 achim
  121. * New __setup interface for boot command line options added
  122. *
  123. * Revision 1.48 2001/02/06 12:36:28 achim
  124. * Bugfix Cluster protocol
  125. *
  126. * Revision 1.47 2001/01/10 14:42:06 achim
  127. * New switch shared_access added
  128. *
  129. * Revision 1.46 2001/01/09 08:11:35 achim
  130. * gdth_command() removed
  131. * meaning of Scsi_Pointer members changed
  132. *
  133. * Revision 1.45 2000/11/16 12:02:24 achim
  134. * Changes for kernel 2.4
  135. *
  136. * Revision 1.44 2000/10/11 08:44:10 achim
  137. * Clustering changes: New flag media_changed added
  138. *
  139. * Revision 1.43 2000/09/20 12:59:01 achim
  140. * DPMEM remap functions for all PCI controller types implemented
  141. * Small changes for ia64 platform
  142. *
  143. * Revision 1.42 2000/07/20 09:04:50 achim
  144. * Small changes for kernel 2.4
  145. *
  146. * Revision 1.41 2000/07/04 14:11:11 achim
  147. * gdth_analyse_hdrive() added to rescan drives after online expansion
  148. *
  149. * Revision 1.40 2000/06/27 11:24:16 achim
  150. * Changes Clustering, Screenservice
  151. *
  152. * Revision 1.39 2000/06/15 13:09:04 achim
  153. * Changes for gdth_do_cmd()
  154. *
  155. * Revision 1.38 2000/06/15 12:08:43 achim
  156. * Bugfix gdth_sync_event(), service SCREENSERVICE
  157. * Data direction for command 0xc2 changed to DOU
  158. *
  159. * Revision 1.37 2000/05/25 13:50:10 achim
  160. * New driver parameter virt_ctr added
  161. *
  162. * Revision 1.36 2000/05/04 08:50:46 achim
  163. * Event buffer now in gdth_ha_str
  164. *
  165. * Revision 1.35 2000/03/03 10:44:08 achim
  166. * New event_string only valid for the RP controller family
  167. *
  168. * Revision 1.34 2000/03/02 14:55:29 achim
  169. * New mechanism for async. event handling implemented
  170. *
  171. * Revision 1.33 2000/02/21 15:37:37 achim
  172. * Bugfix Alpha platform + DPMEM above 4GB
  173. *
  174. * Revision 1.32 2000/02/14 16:17:37 achim
  175. * Bugfix sense_buffer[] + raw devices
  176. *
  177. * Revision 1.31 2000/02/10 10:29:00 achim
  178. * Delete sense_buffer[0], if command OK
  179. *
  180. * Revision 1.30 1999/11/02 13:42:39 achim
  181. * ARRAY_DRV_LIST2 implemented
  182. * Now 255 log. and 100 host drives supported
  183. *
  184. * Revision 1.29 1999/10/05 13:28:47 achim
  185. * GDT_CLUST_RESET added
  186. *
  187. * Revision 1.28 1999/08/12 13:44:54 achim
  188. * MOUNTALL removed
  189. * Cluster drives -> removeable drives
  190. *
  191. * Revision 1.27 1999/06/22 07:22:38 achim
  192. * Small changes
  193. *
  194. * Revision 1.26 1999/06/10 16:09:12 achim
  195. * Cluster Host Drive support: Bugfixes
  196. *
  197. * Revision 1.25 1999/06/01 16:03:56 achim
  198. * gdth_init_pci(): Manipulate config. space to start RP controller
  199. *
  200. * Revision 1.24 1999/05/26 11:53:06 achim
  201. * Cluster Host Drive support added
  202. *
  203. * Revision 1.23 1999/03/26 09:12:31 achim
  204. * Default value for hdr_channel set to 0
  205. *
  206. * Revision 1.22 1999/03/22 16:27:16 achim
  207. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  208. *
  209. * Revision 1.21 1999/03/16 13:40:34 achim
  210. * Problems with reserved drives solved
  211. * gdth_eh_bus_reset() implemented
  212. *
  213. * Revision 1.20 1999/03/10 09:08:13 achim
  214. * Bugfix: Corrections in gdth_direction_tab[] made
  215. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  216. *
  217. * Revision 1.19 1999/03/05 14:38:16 achim
  218. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  219. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  220. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  221. * with BIOS disabled and memory test set to Intensive
  222. * Enhanced /proc support
  223. *
  224. * Revision 1.18 1999/02/24 09:54:33 achim
  225. * Command line parameter hdr_channel implemented
  226. * Bugfix for EISA controllers + Linux 2.2.x
  227. *
  228. * Revision 1.17 1998/12/17 15:58:11 achim
  229. * Command line parameters implemented
  230. * Changes for Alpha platforms
  231. * PCI controller scan changed
  232. * SMP support improved (spin_lock_irqsave(),...)
  233. * New async. events, new scan/reserve commands included
  234. *
  235. * Revision 1.16 1998/09/28 16:08:46 achim
  236. * GDT_PCIMPR: DPMEM remapping, if required
  237. * mdelay() added
  238. *
  239. * Revision 1.15 1998/06/03 14:54:06 achim
  240. * gdth_delay(), gdth_flush() implemented
  241. * Bugfix: gdth_release() changed
  242. *
  243. * Revision 1.14 1998/05/22 10:01:17 achim
  244. * mj: pcibios_strerror() removed
  245. * Improved SMP support (if version >= 2.1.95)
  246. * gdth_halt(): halt_called flag added (if version < 2.1)
  247. *
  248. * Revision 1.13 1998/04/16 09:14:57 achim
  249. * Reserve drives (for raw service) implemented
  250. * New error handling code enabled
  251. * Get controller name from board_info() IOCTL
  252. * Final round of PCI device driver patches by Martin Mares
  253. *
  254. * Revision 1.12 1998/03/03 09:32:37 achim
  255. * Fibre channel controller support added
  256. *
  257. * Revision 1.11 1998/01/27 16:19:14 achim
  258. * SA_SHIRQ added
  259. * add_timer()/del_timer() instead of GDTH_TIMER
  260. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  261. * New error handling included
  262. *
  263. * Revision 1.10 1997/10/31 12:29:57 achim
  264. * Read heads/sectors from host drive
  265. *
  266. * Revision 1.9 1997/09/04 10:07:25 achim
  267. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  268. * register_reboot_notifier() to get a notify on shutown used
  269. *
  270. * Revision 1.8 1997/04/02 12:14:30 achim
  271. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  272. *
  273. * Revision 1.7 1997/03/12 13:33:37 achim
  274. * gdth_reset() changed, new async. events
  275. *
  276. * Revision 1.6 1997/03/04 14:01:11 achim
  277. * Shutdown routine gdth_halt() implemented
  278. *
  279. * Revision 1.5 1997/02/21 09:08:36 achim
  280. * New controller included (RP, RP1, RP2 series)
  281. * IOCTL interface implemented
  282. *
  283. * Revision 1.4 1996/07/05 12:48:55 achim
  284. * Function gdth_bios_param() implemented
  285. * New constant GDTH_MAXC_P_L inserted
  286. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  287. * Function gdth_reset() changed
  288. *
  289. * Revision 1.3 1996/05/10 09:04:41 achim
  290. * Small changes for Linux 1.2.13
  291. *
  292. * Revision 1.2 1996/05/09 12:45:27 achim
  293. * Loadable module support implemented
  294. * /proc support corrections made
  295. *
  296. * Revision 1.1 1996/04/11 07:35:57 achim
  297. * Initial revision
  298. *
  299. ************************************************************************/
  300. /* All GDT Disk Array Controllers are fully supported by this driver.
  301. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  302. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  303. * list of all controller types.
  304. *
  305. * If you have one or more GDT3000/3020 EISA controllers with
  306. * controller BIOS disabled, you have to set the IRQ values with the
  307. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  308. * the IRQ values for the EISA controllers.
  309. *
  310. * After the optional list of IRQ values, other possible
  311. * command line options are:
  312. * disable:Y disable driver
  313. * disable:N enable driver
  314. * reserve_mode:0 reserve no drives for the raw service
  315. * reserve_mode:1 reserve all not init., removable drives
  316. * reserve_mode:2 reserve all not init. drives
  317. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  318. * h- controller no., b- channel no.,
  319. * t- target ID, l- LUN
  320. * reverse_scan:Y reverse scan order for PCI controllers
  321. * reverse_scan:N scan PCI controllers like BIOS
  322. * max_ids:x x - target ID count per channel (1..MAXID)
  323. * rescan:Y rescan all channels/IDs
  324. * rescan:N use all devices found until now
  325. * virt_ctr:Y map every channel to a virtual controller
  326. * virt_ctr:N use multi channel support
  327. * hdr_channel:x x - number of virtual bus for host drives
  328. * shared_access:Y disable driver reserve/release protocol to
  329. * access a shared resource from several nodes,
  330. * appropriate controller firmware required
  331. * shared_access:N enable driver reserve/release protocol
  332. * probe_eisa_isa:Y scan for EISA/ISA controllers
  333. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  334. * force_dma32:Y use only 32 bit DMA mode
  335. * force_dma32:N use 64 bit DMA mode, if supported
  336. *
  337. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  338. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  339. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  340. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  341. *
  342. * When loading the gdth driver as a module, the same options are available.
  343. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  344. * options changes slightly. You must replace all ',' between options
  345. * with ' ' and all ':' with '=' and you must use
  346. * '1' in place of 'Y' and '0' in place of 'N'.
  347. *
  348. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  349. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  350. * probe_eisa_isa=0 force_dma32=0"
  351. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  352. */
  353. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  354. * ptr: Chaining
  355. * this_residual: Command priority
  356. * buffer: phys. DMA sense buffer
  357. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  358. * buffers_residual: Timeout value
  359. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  360. * Message: Additional info (gdth_do_cmd()), DMA direction
  361. * have_data_in: Flag for gdth_wait_completion()
  362. * sent_command: Opcode special command
  363. * phase: Service/parameter/return code special command
  364. */
  365. /* interrupt coalescing */
  366. /* #define INT_COAL */
  367. /* statistics */
  368. #define GDTH_STATISTICS
  369. #include <linux/module.h>
  370. #include <linux/version.h>
  371. #include <linux/kernel.h>
  372. #include <linux/types.h>
  373. #include <linux/pci.h>
  374. #include <linux/string.h>
  375. #include <linux/ctype.h>
  376. #include <linux/ioport.h>
  377. #include <linux/delay.h>
  378. #include <linux/sched.h>
  379. #include <linux/interrupt.h>
  380. #include <linux/in.h>
  381. #include <linux/proc_fs.h>
  382. #include <linux/time.h>
  383. #include <linux/timer.h>
  384. #include <linux/dma-mapping.h>
  385. #ifdef GDTH_RTC
  386. #include <linux/mc146818rtc.h>
  387. #endif
  388. #include <linux/reboot.h>
  389. #include <asm/dma.h>
  390. #include <asm/system.h>
  391. #include <asm/io.h>
  392. #include <asm/uaccess.h>
  393. #include <linux/spinlock.h>
  394. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  395. #include <linux/blkdev.h>
  396. #else
  397. #include <linux/blk.h>
  398. #include "sd.h"
  399. #endif
  400. #include "scsi.h"
  401. #include <scsi/scsi_host.h>
  402. #include "gdth.h"
  403. #include "gdth_kcompat.h"
  404. static void gdth_delay(int milliseconds);
  405. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  406. static irqreturn_t gdth_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  407. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  408. static int gdth_async_event(int hanum);
  409. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  410. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  411. static void gdth_next(int hanum);
  412. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  413. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  414. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  415. ushort idx, gdth_evt_data *evt);
  416. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  417. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  418. gdth_evt_str *estr);
  419. static void gdth_clear_events(void);
  420. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  421. char *buffer,ushort count);
  422. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  423. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  424. static int gdth_search_eisa(ushort eisa_adr);
  425. static int gdth_search_isa(ulong32 bios_adr);
  426. static int gdth_search_pci(gdth_pci_str *pcistr);
  427. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  428. ushort vendor, ushort dev);
  429. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  430. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  431. static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
  432. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  433. static void gdth_enable_int(int hanum);
  434. static int gdth_get_status(unchar *pIStatus,int irq);
  435. static int gdth_test_busy(int hanum);
  436. static int gdth_get_cmd_index(int hanum);
  437. static void gdth_release_event(int hanum);
  438. static int gdth_wait(int hanum,int index,ulong32 time);
  439. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  440. ulong64 p2,ulong64 p3);
  441. static int gdth_search_drives(int hanum);
  442. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  443. static const char *gdth_ctr_name(int hanum);
  444. static int gdth_open(struct inode *inode, struct file *filep);
  445. static int gdth_close(struct inode *inode, struct file *filep);
  446. static int gdth_ioctl(struct inode *inode, struct file *filep,
  447. unsigned int cmd, unsigned long arg);
  448. static void gdth_flush(int hanum);
  449. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  450. #ifdef DEBUG_GDTH
  451. static unchar DebugState = DEBUG_GDTH;
  452. #ifdef __SERIAL__
  453. #define MAX_SERBUF 160
  454. static void ser_init(void);
  455. static void ser_puts(char *str);
  456. static void ser_putc(char c);
  457. static int ser_printk(const char *fmt, ...);
  458. static char strbuf[MAX_SERBUF+1];
  459. #ifdef __COM2__
  460. #define COM_BASE 0x2f8
  461. #else
  462. #define COM_BASE 0x3f8
  463. #endif
  464. static void ser_init()
  465. {
  466. unsigned port=COM_BASE;
  467. outb(0x80,port+3);
  468. outb(0,port+1);
  469. /* 19200 Baud, if 9600: outb(12,port) */
  470. outb(6, port);
  471. outb(3,port+3);
  472. outb(0,port+1);
  473. /*
  474. ser_putc('I');
  475. ser_putc(' ');
  476. */
  477. }
  478. static void ser_puts(char *str)
  479. {
  480. char *ptr;
  481. ser_init();
  482. for (ptr=str;*ptr;++ptr)
  483. ser_putc(*ptr);
  484. }
  485. static void ser_putc(char c)
  486. {
  487. unsigned port=COM_BASE;
  488. while ((inb(port+5) & 0x20)==0);
  489. outb(c,port);
  490. if (c==0x0a)
  491. {
  492. while ((inb(port+5) & 0x20)==0);
  493. outb(0x0d,port);
  494. }
  495. }
  496. static int ser_printk(const char *fmt, ...)
  497. {
  498. va_list args;
  499. int i;
  500. va_start(args,fmt);
  501. i = vsprintf(strbuf,fmt,args);
  502. ser_puts(strbuf);
  503. va_end(args);
  504. return i;
  505. }
  506. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  507. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  508. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  509. #else /* !__SERIAL__ */
  510. #define TRACE(a) {if (DebugState==1) {printk a;}}
  511. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  512. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  513. #endif
  514. #else /* !DEBUG */
  515. #define TRACE(a)
  516. #define TRACE2(a)
  517. #define TRACE3(a)
  518. #endif
  519. #ifdef GDTH_STATISTICS
  520. static ulong32 max_rq=0, max_index=0, max_sg=0;
  521. #ifdef INT_COAL
  522. static ulong32 max_int_coal=0;
  523. #endif
  524. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  525. static struct timer_list gdth_timer;
  526. #endif
  527. #define PTR2USHORT(a) (ushort)(ulong)(a)
  528. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  529. #define INDEX_OK(i,t) ((i)<sizeof(t)/sizeof((t)[0]))
  530. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  531. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  532. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  533. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  534. #define gdth_readb(addr) readb(addr)
  535. #define gdth_readw(addr) readw(addr)
  536. #define gdth_readl(addr) readl(addr)
  537. #define gdth_writeb(b,addr) writeb((b),(addr))
  538. #define gdth_writew(b,addr) writew((b),(addr))
  539. #define gdth_writel(b,addr) writel((b),(addr))
  540. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  541. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  542. static unchar gdth_polling; /* polling if TRUE */
  543. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  544. static int wait_index,wait_hanum; /* gdth_wait() */
  545. static int gdth_ctr_count = 0; /* controller count */
  546. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  547. static int gdth_ctr_released = 0; /* gdth_release() */
  548. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  549. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  550. static unchar gdth_write_through = FALSE; /* write through */
  551. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  552. static int elastidx;
  553. static int eoldidx;
  554. static int major;
  555. #define DIN 1 /* IN data direction */
  556. #define DOU 2 /* OUT data direction */
  557. #define DNO DIN /* no data transfer */
  558. #define DUN DIN /* unknown data direction */
  559. static unchar gdth_direction_tab[0x100] = {
  560. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  561. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  562. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  563. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  564. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  565. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  566. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  567. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  568. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  569. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  570. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  571. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  572. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  573. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  574. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  575. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  576. };
  577. /* LILO and modprobe/insmod parameters */
  578. /* IRQ list for GDT3000/3020 EISA controllers */
  579. static int irq[MAXHA] __initdata =
  580. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  581. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  582. /* disable driver flag */
  583. static int disable __initdata = 0;
  584. /* reserve flag */
  585. static int reserve_mode = 1;
  586. /* reserve list */
  587. static int reserve_list[MAX_RES_ARGS] =
  588. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  589. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  590. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  591. /* scan order for PCI controllers */
  592. static int reverse_scan = 0;
  593. /* virtual channel for the host drives */
  594. static int hdr_channel = 0;
  595. /* max. IDs per channel */
  596. static int max_ids = MAXID;
  597. /* rescan all IDs */
  598. static int rescan = 0;
  599. /* map channels to virtual controllers */
  600. static int virt_ctr = 0;
  601. /* shared access */
  602. static int shared_access = 1;
  603. /* enable support for EISA and ISA controllers */
  604. static int probe_eisa_isa = 0;
  605. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  606. static int force_dma32 = 0;
  607. /* parameters for modprobe/insmod */
  608. module_param_array(irq, int, NULL, 0);
  609. module_param(disable, int, 0);
  610. module_param(reserve_mode, int, 0);
  611. module_param_array(reserve_list, int, NULL, 0);
  612. module_param(reverse_scan, int, 0);
  613. module_param(hdr_channel, int, 0);
  614. module_param(max_ids, int, 0);
  615. module_param(rescan, int, 0);
  616. module_param(virt_ctr, int, 0);
  617. module_param(shared_access, int, 0);
  618. module_param(probe_eisa_isa, int, 0);
  619. module_param(force_dma32, int, 0);
  620. MODULE_AUTHOR("Achim Leubner");
  621. MODULE_LICENSE("GPL");
  622. /* ioctl interface */
  623. static struct file_operations gdth_fops = {
  624. .ioctl = gdth_ioctl,
  625. .open = gdth_open,
  626. .release = gdth_close,
  627. };
  628. #include "gdth_proc.h"
  629. #include "gdth_proc.c"
  630. /* notifier block to get a notify on system shutdown/halt/reboot */
  631. static struct notifier_block gdth_notifier = {
  632. gdth_halt, NULL, 0
  633. };
  634. static int notifier_disabled = 0;
  635. static void gdth_delay(int milliseconds)
  636. {
  637. if (milliseconds == 0) {
  638. udelay(1);
  639. } else {
  640. mdelay(milliseconds);
  641. }
  642. }
  643. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  644. {
  645. *cyls = size /HEADS/SECS;
  646. if (*cyls <= MAXCYLS) {
  647. *heads = HEADS;
  648. *secs = SECS;
  649. } else { /* too high for 64*32 */
  650. *cyls = size /MEDHEADS/MEDSECS;
  651. if (*cyls <= MAXCYLS) {
  652. *heads = MEDHEADS;
  653. *secs = MEDSECS;
  654. } else { /* too high for 127*63 */
  655. *cyls = size /BIGHEADS/BIGSECS;
  656. *heads = BIGHEADS;
  657. *secs = BIGSECS;
  658. }
  659. }
  660. }
  661. /* controller search and initialization functions */
  662. static int __init gdth_search_eisa(ushort eisa_adr)
  663. {
  664. ulong32 id;
  665. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  666. id = inl(eisa_adr+ID0REG);
  667. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  668. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  669. return 0; /* not EISA configured */
  670. return 1;
  671. }
  672. if (id == GDT3_ID) /* GDT3000 */
  673. return 1;
  674. return 0;
  675. }
  676. static int __init gdth_search_isa(ulong32 bios_adr)
  677. {
  678. void __iomem *addr;
  679. ulong32 id;
  680. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  681. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  682. id = gdth_readl(addr);
  683. iounmap(addr);
  684. if (id == GDT2_ID) /* GDT2000 */
  685. return 1;
  686. }
  687. return 0;
  688. }
  689. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  690. {
  691. ushort device, cnt;
  692. TRACE(("gdth_search_pci()\n"));
  693. cnt = 0;
  694. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  695. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  696. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  697. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  698. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  699. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  700. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  701. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  702. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  703. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  704. PCI_DEVICE_ID_INTEL_SRC);
  705. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  706. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  707. return cnt;
  708. }
  709. /* Vortex only makes RAID controllers.
  710. * We do not really want to specify all 550 ids here, so wildcard match.
  711. */
  712. static struct pci_device_id gdthtable[] __attribute_used__ = {
  713. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  714. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  715. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  716. {0}
  717. };
  718. MODULE_DEVICE_TABLE(pci,gdthtable);
  719. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  720. ushort vendor, ushort device)
  721. {
  722. ulong base0, base1, base2;
  723. struct pci_dev *pdev;
  724. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  725. *cnt, vendor, device));
  726. pdev = NULL;
  727. while ((pdev = pci_find_device(vendor, device, pdev))
  728. != NULL) {
  729. if (pci_enable_device(pdev))
  730. continue;
  731. if (*cnt >= MAXHA)
  732. return;
  733. /* GDT PCI controller found, resources are already in pdev */
  734. pcistr[*cnt].pdev = pdev;
  735. pcistr[*cnt].vendor_id = vendor;
  736. pcistr[*cnt].device_id = device;
  737. pcistr[*cnt].subdevice_id = pdev->subsystem_device;
  738. pcistr[*cnt].bus = pdev->bus->number;
  739. pcistr[*cnt].device_fn = pdev->devfn;
  740. pcistr[*cnt].irq = pdev->irq;
  741. base0 = pci_resource_flags(pdev, 0);
  742. base1 = pci_resource_flags(pdev, 1);
  743. base2 = pci_resource_flags(pdev, 2);
  744. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  745. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  746. if (!(base0 & IORESOURCE_MEM))
  747. continue;
  748. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  749. } else { /* GDT6110, GDT6120, .. */
  750. if (!(base0 & IORESOURCE_MEM) ||
  751. !(base2 & IORESOURCE_MEM) ||
  752. !(base1 & IORESOURCE_IO))
  753. continue;
  754. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  755. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  756. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  757. }
  758. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  759. pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
  760. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  761. (*cnt)++;
  762. }
  763. }
  764. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  765. {
  766. gdth_pci_str temp;
  767. int i, changed;
  768. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  769. if (cnt == 0)
  770. return;
  771. do {
  772. changed = FALSE;
  773. for (i = 0; i < cnt-1; ++i) {
  774. if (!reverse_scan) {
  775. if ((pcistr[i].bus > pcistr[i+1].bus) ||
  776. (pcistr[i].bus == pcistr[i+1].bus &&
  777. PCI_SLOT(pcistr[i].device_fn) >
  778. PCI_SLOT(pcistr[i+1].device_fn))) {
  779. temp = pcistr[i];
  780. pcistr[i] = pcistr[i+1];
  781. pcistr[i+1] = temp;
  782. changed = TRUE;
  783. }
  784. } else {
  785. if ((pcistr[i].bus < pcistr[i+1].bus) ||
  786. (pcistr[i].bus == pcistr[i+1].bus &&
  787. PCI_SLOT(pcistr[i].device_fn) <
  788. PCI_SLOT(pcistr[i+1].device_fn))) {
  789. temp = pcistr[i];
  790. pcistr[i] = pcistr[i+1];
  791. pcistr[i+1] = temp;
  792. changed = TRUE;
  793. }
  794. }
  795. }
  796. } while (changed);
  797. }
  798. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  799. {
  800. ulong32 retries,id;
  801. unchar prot_ver,eisacf,i,irq_found;
  802. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  803. /* disable board interrupts, deinitialize services */
  804. outb(0xff,eisa_adr+EDOORREG);
  805. outb(0x00,eisa_adr+EDENABREG);
  806. outb(0x00,eisa_adr+EINTENABREG);
  807. outb(0xff,eisa_adr+LDOORREG);
  808. retries = INIT_RETRIES;
  809. gdth_delay(20);
  810. while (inb(eisa_adr+EDOORREG) != 0xff) {
  811. if (--retries == 0) {
  812. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  813. return 0;
  814. }
  815. gdth_delay(1);
  816. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  817. }
  818. prot_ver = inb(eisa_adr+MAILBOXREG);
  819. outb(0xff,eisa_adr+EDOORREG);
  820. if (prot_ver != PROTOCOL_VERSION) {
  821. printk("GDT-EISA: Illegal protocol version\n");
  822. return 0;
  823. }
  824. ha->bmic = eisa_adr;
  825. ha->brd_phys = (ulong32)eisa_adr >> 12;
  826. outl(0,eisa_adr+MAILBOXREG);
  827. outl(0,eisa_adr+MAILBOXREG+4);
  828. outl(0,eisa_adr+MAILBOXREG+8);
  829. outl(0,eisa_adr+MAILBOXREG+12);
  830. /* detect IRQ */
  831. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  832. ha->oem_id = OEM_ID_ICP;
  833. ha->type = GDT_EISA;
  834. ha->stype = id;
  835. outl(1,eisa_adr+MAILBOXREG+8);
  836. outb(0xfe,eisa_adr+LDOORREG);
  837. retries = INIT_RETRIES;
  838. gdth_delay(20);
  839. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  840. if (--retries == 0) {
  841. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  842. return 0;
  843. }
  844. gdth_delay(1);
  845. }
  846. ha->irq = inb(eisa_adr+MAILBOXREG);
  847. outb(0xff,eisa_adr+EDOORREG);
  848. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  849. /* check the result */
  850. if (ha->irq == 0) {
  851. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  852. for (i = 0, irq_found = FALSE;
  853. i < MAXHA && irq[i] != 0xff; ++i) {
  854. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  855. irq_found = TRUE;
  856. break;
  857. }
  858. }
  859. if (irq_found) {
  860. ha->irq = irq[i];
  861. irq[i] = 0;
  862. printk("GDT-EISA: Can not detect controller IRQ,\n");
  863. printk("Use IRQ setting from command line (IRQ = %d)\n",
  864. ha->irq);
  865. } else {
  866. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  867. printk("the controller BIOS or use command line parameters\n");
  868. return 0;
  869. }
  870. }
  871. } else {
  872. eisacf = inb(eisa_adr+EISAREG) & 7;
  873. if (eisacf > 4) /* level triggered */
  874. eisacf -= 4;
  875. ha->irq = gdth_irq_tab[eisacf];
  876. ha->oem_id = OEM_ID_ICP;
  877. ha->type = GDT_EISA;
  878. ha->stype = id;
  879. }
  880. ha->dma64_support = 0;
  881. return 1;
  882. }
  883. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  884. {
  885. register gdt2_dpram_str __iomem *dp2_ptr;
  886. int i;
  887. unchar irq_drq,prot_ver;
  888. ulong32 retries;
  889. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  890. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  891. if (ha->brd == NULL) {
  892. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  893. return 0;
  894. }
  895. dp2_ptr = ha->brd;
  896. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  897. /* reset interface area */
  898. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  899. if (gdth_readl(&dp2_ptr->u) != 0) {
  900. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  901. iounmap(ha->brd);
  902. return 0;
  903. }
  904. /* disable board interrupts, read DRQ and IRQ */
  905. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  906. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  907. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  908. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  909. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  910. for (i=0; i<3; ++i) {
  911. if ((irq_drq & 1)==0)
  912. break;
  913. irq_drq >>= 1;
  914. }
  915. ha->drq = gdth_drq_tab[i];
  916. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  917. for (i=1; i<5; ++i) {
  918. if ((irq_drq & 1)==0)
  919. break;
  920. irq_drq >>= 1;
  921. }
  922. ha->irq = gdth_irq_tab[i];
  923. /* deinitialize services */
  924. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  925. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  926. gdth_writeb(0, &dp2_ptr->io.event);
  927. retries = INIT_RETRIES;
  928. gdth_delay(20);
  929. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  930. if (--retries == 0) {
  931. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  932. iounmap(ha->brd);
  933. return 0;
  934. }
  935. gdth_delay(1);
  936. }
  937. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  938. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  939. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  940. if (prot_ver != PROTOCOL_VERSION) {
  941. printk("GDT-ISA: Illegal protocol version\n");
  942. iounmap(ha->brd);
  943. return 0;
  944. }
  945. ha->oem_id = OEM_ID_ICP;
  946. ha->type = GDT_ISA;
  947. ha->ic_all_size = sizeof(dp2_ptr->u);
  948. ha->stype= GDT2_ID;
  949. ha->brd_phys = bios_adr >> 4;
  950. /* special request to controller BIOS */
  951. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  952. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  953. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  954. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  955. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  956. gdth_writeb(0, &dp2_ptr->io.event);
  957. retries = INIT_RETRIES;
  958. gdth_delay(20);
  959. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  960. if (--retries == 0) {
  961. printk("GDT-ISA: Initialization error\n");
  962. iounmap(ha->brd);
  963. return 0;
  964. }
  965. gdth_delay(1);
  966. }
  967. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  968. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  969. ha->dma64_support = 0;
  970. return 1;
  971. }
  972. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  973. {
  974. register gdt6_dpram_str __iomem *dp6_ptr;
  975. register gdt6c_dpram_str __iomem *dp6c_ptr;
  976. register gdt6m_dpram_str __iomem *dp6m_ptr;
  977. ulong32 retries;
  978. unchar prot_ver;
  979. ushort command;
  980. int i, found = FALSE;
  981. TRACE(("gdth_init_pci()\n"));
  982. if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
  983. ha->oem_id = OEM_ID_INTEL;
  984. else
  985. ha->oem_id = OEM_ID_ICP;
  986. ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
  987. ha->stype = (ulong32)pcistr->device_id;
  988. ha->subdevice_id = pcistr->subdevice_id;
  989. ha->irq = pcistr->irq;
  990. ha->pdev = pcistr->pdev;
  991. if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  992. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  993. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  994. if (ha->brd == NULL) {
  995. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  996. return 0;
  997. }
  998. /* check and reset interface area */
  999. dp6_ptr = ha->brd;
  1000. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1001. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1002. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1003. pcistr->dpmem);
  1004. found = FALSE;
  1005. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1006. iounmap(ha->brd);
  1007. ha->brd = ioremap(i, sizeof(ushort));
  1008. if (ha->brd == NULL) {
  1009. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1010. return 0;
  1011. }
  1012. if (gdth_readw(ha->brd) != 0xffff) {
  1013. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1014. continue;
  1015. }
  1016. iounmap(ha->brd);
  1017. pci_write_config_dword(pcistr->pdev,
  1018. PCI_BASE_ADDRESS_0, i);
  1019. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1020. if (ha->brd == NULL) {
  1021. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1022. return 0;
  1023. }
  1024. dp6_ptr = ha->brd;
  1025. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1026. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1027. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1028. found = TRUE;
  1029. break;
  1030. }
  1031. }
  1032. if (!found) {
  1033. printk("GDT-PCI: No free address found!\n");
  1034. iounmap(ha->brd);
  1035. return 0;
  1036. }
  1037. }
  1038. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1039. if (gdth_readl(&dp6_ptr->u) != 0) {
  1040. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1041. iounmap(ha->brd);
  1042. return 0;
  1043. }
  1044. /* disable board interrupts, deinit services */
  1045. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1046. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1047. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1048. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1049. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1050. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1051. gdth_writeb(0, &dp6_ptr->io.event);
  1052. retries = INIT_RETRIES;
  1053. gdth_delay(20);
  1054. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1055. if (--retries == 0) {
  1056. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1057. iounmap(ha->brd);
  1058. return 0;
  1059. }
  1060. gdth_delay(1);
  1061. }
  1062. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1063. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1064. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1065. if (prot_ver != PROTOCOL_VERSION) {
  1066. printk("GDT-PCI: Illegal protocol version\n");
  1067. iounmap(ha->brd);
  1068. return 0;
  1069. }
  1070. ha->type = GDT_PCI;
  1071. ha->ic_all_size = sizeof(dp6_ptr->u);
  1072. /* special command to controller BIOS */
  1073. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1074. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1075. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1076. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1077. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1078. gdth_writeb(0, &dp6_ptr->io.event);
  1079. retries = INIT_RETRIES;
  1080. gdth_delay(20);
  1081. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1082. if (--retries == 0) {
  1083. printk("GDT-PCI: Initialization error\n");
  1084. iounmap(ha->brd);
  1085. return 0;
  1086. }
  1087. gdth_delay(1);
  1088. }
  1089. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1090. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1091. ha->dma64_support = 0;
  1092. } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1093. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1094. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1095. pcistr->dpmem,ha->irq));
  1096. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1097. if (ha->brd == NULL) {
  1098. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1099. iounmap(ha->brd);
  1100. return 0;
  1101. }
  1102. /* check and reset interface area */
  1103. dp6c_ptr = ha->brd;
  1104. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1105. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1106. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1107. pcistr->dpmem);
  1108. found = FALSE;
  1109. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1110. iounmap(ha->brd);
  1111. ha->brd = ioremap(i, sizeof(ushort));
  1112. if (ha->brd == NULL) {
  1113. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1114. return 0;
  1115. }
  1116. if (gdth_readw(ha->brd) != 0xffff) {
  1117. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1118. continue;
  1119. }
  1120. iounmap(ha->brd);
  1121. pci_write_config_dword(pcistr->pdev,
  1122. PCI_BASE_ADDRESS_2, i);
  1123. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1124. if (ha->brd == NULL) {
  1125. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1126. return 0;
  1127. }
  1128. dp6c_ptr = ha->brd;
  1129. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1130. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1131. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1132. found = TRUE;
  1133. break;
  1134. }
  1135. }
  1136. if (!found) {
  1137. printk("GDT-PCI: No free address found!\n");
  1138. iounmap(ha->brd);
  1139. return 0;
  1140. }
  1141. }
  1142. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1143. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1144. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1145. iounmap(ha->brd);
  1146. return 0;
  1147. }
  1148. /* disable board interrupts, deinit services */
  1149. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1150. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1151. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1152. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1153. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1154. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1155. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1156. retries = INIT_RETRIES;
  1157. gdth_delay(20);
  1158. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1159. if (--retries == 0) {
  1160. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1161. iounmap(ha->brd);
  1162. return 0;
  1163. }
  1164. gdth_delay(1);
  1165. }
  1166. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1167. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1168. if (prot_ver != PROTOCOL_VERSION) {
  1169. printk("GDT-PCI: Illegal protocol version\n");
  1170. iounmap(ha->brd);
  1171. return 0;
  1172. }
  1173. ha->type = GDT_PCINEW;
  1174. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1175. /* special command to controller BIOS */
  1176. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1177. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1178. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1179. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1180. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1181. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1182. retries = INIT_RETRIES;
  1183. gdth_delay(20);
  1184. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1185. if (--retries == 0) {
  1186. printk("GDT-PCI: Initialization error\n");
  1187. iounmap(ha->brd);
  1188. return 0;
  1189. }
  1190. gdth_delay(1);
  1191. }
  1192. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1193. ha->dma64_support = 0;
  1194. } else { /* MPR */
  1195. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1196. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1197. if (ha->brd == NULL) {
  1198. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1199. return 0;
  1200. }
  1201. /* manipulate config. space to enable DPMEM, start RP controller */
  1202. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1203. command |= 6;
  1204. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1205. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1206. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1207. i = 0xFEFF0001UL;
  1208. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1209. gdth_delay(1);
  1210. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1211. pci_resource_start(pcistr->pdev, 8));
  1212. dp6m_ptr = ha->brd;
  1213. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1214. * Aditional check needed for Xscale based RAID controllers */
  1215. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1216. gdth_delay(1);
  1217. /* check and reset interface area */
  1218. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1219. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1220. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1221. pcistr->dpmem);
  1222. found = FALSE;
  1223. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1224. iounmap(ha->brd);
  1225. ha->brd = ioremap(i, sizeof(ushort));
  1226. if (ha->brd == NULL) {
  1227. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1228. return 0;
  1229. }
  1230. if (gdth_readw(ha->brd) != 0xffff) {
  1231. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1232. continue;
  1233. }
  1234. iounmap(ha->brd);
  1235. pci_write_config_dword(pcistr->pdev,
  1236. PCI_BASE_ADDRESS_0, i);
  1237. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1238. if (ha->brd == NULL) {
  1239. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1240. return 0;
  1241. }
  1242. dp6m_ptr = ha->brd;
  1243. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1244. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1245. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1246. found = TRUE;
  1247. break;
  1248. }
  1249. }
  1250. if (!found) {
  1251. printk("GDT-PCI: No free address found!\n");
  1252. iounmap(ha->brd);
  1253. return 0;
  1254. }
  1255. }
  1256. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1257. /* disable board interrupts, deinit services */
  1258. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1259. &dp6m_ptr->i960r.edoor_en_reg);
  1260. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1261. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1262. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1263. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1264. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1265. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1266. retries = INIT_RETRIES;
  1267. gdth_delay(20);
  1268. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1269. if (--retries == 0) {
  1270. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1271. iounmap(ha->brd);
  1272. return 0;
  1273. }
  1274. gdth_delay(1);
  1275. }
  1276. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1277. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1278. if (prot_ver != PROTOCOL_VERSION) {
  1279. printk("GDT-PCI: Illegal protocol version\n");
  1280. iounmap(ha->brd);
  1281. return 0;
  1282. }
  1283. ha->type = GDT_PCIMPR;
  1284. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1285. /* special command to controller BIOS */
  1286. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1287. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1288. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1289. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1290. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1291. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1292. retries = INIT_RETRIES;
  1293. gdth_delay(20);
  1294. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1295. if (--retries == 0) {
  1296. printk("GDT-PCI: Initialization error\n");
  1297. iounmap(ha->brd);
  1298. return 0;
  1299. }
  1300. gdth_delay(1);
  1301. }
  1302. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1303. /* read FW version to detect 64-bit DMA support */
  1304. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1305. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1306. retries = INIT_RETRIES;
  1307. gdth_delay(20);
  1308. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1309. if (--retries == 0) {
  1310. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1311. iounmap(ha->brd);
  1312. return 0;
  1313. }
  1314. gdth_delay(1);
  1315. }
  1316. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1317. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1318. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1319. ha->dma64_support = 0;
  1320. else
  1321. ha->dma64_support = 1;
  1322. }
  1323. return 1;
  1324. }
  1325. /* controller protocol functions */
  1326. static void __init gdth_enable_int(int hanum)
  1327. {
  1328. gdth_ha_str *ha;
  1329. ulong flags;
  1330. gdt2_dpram_str __iomem *dp2_ptr;
  1331. gdt6_dpram_str __iomem *dp6_ptr;
  1332. gdt6m_dpram_str __iomem *dp6m_ptr;
  1333. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1334. ha = HADATA(gdth_ctr_tab[hanum]);
  1335. spin_lock_irqsave(&ha->smp_lock, flags);
  1336. if (ha->type == GDT_EISA) {
  1337. outb(0xff, ha->bmic + EDOORREG);
  1338. outb(0xff, ha->bmic + EDENABREG);
  1339. outb(0x01, ha->bmic + EINTENABREG);
  1340. } else if (ha->type == GDT_ISA) {
  1341. dp2_ptr = ha->brd;
  1342. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1343. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1344. gdth_writeb(1, &dp2_ptr->io.irqen);
  1345. } else if (ha->type == GDT_PCI) {
  1346. dp6_ptr = ha->brd;
  1347. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1348. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1349. gdth_writeb(1, &dp6_ptr->io.irqen);
  1350. } else if (ha->type == GDT_PCINEW) {
  1351. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1352. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1353. } else if (ha->type == GDT_PCIMPR) {
  1354. dp6m_ptr = ha->brd;
  1355. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1356. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1357. &dp6m_ptr->i960r.edoor_en_reg);
  1358. }
  1359. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1360. }
  1361. static int gdth_get_status(unchar *pIStatus,int irq)
  1362. {
  1363. register gdth_ha_str *ha;
  1364. int i;
  1365. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1366. irq,gdth_ctr_count));
  1367. *pIStatus = 0;
  1368. for (i=0; i<gdth_ctr_count; ++i) {
  1369. ha = HADATA(gdth_ctr_tab[i]);
  1370. if (ha->irq != (unchar)irq) /* check IRQ */
  1371. continue;
  1372. if (ha->type == GDT_EISA)
  1373. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1374. else if (ha->type == GDT_ISA)
  1375. *pIStatus =
  1376. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1377. else if (ha->type == GDT_PCI)
  1378. *pIStatus =
  1379. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1380. else if (ha->type == GDT_PCINEW)
  1381. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1382. else if (ha->type == GDT_PCIMPR)
  1383. *pIStatus =
  1384. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1385. if (*pIStatus)
  1386. return i; /* board found */
  1387. }
  1388. return -1;
  1389. }
  1390. static int gdth_test_busy(int hanum)
  1391. {
  1392. register gdth_ha_str *ha;
  1393. register int gdtsema0 = 0;
  1394. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1395. ha = HADATA(gdth_ctr_tab[hanum]);
  1396. if (ha->type == GDT_EISA)
  1397. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1398. else if (ha->type == GDT_ISA)
  1399. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1400. else if (ha->type == GDT_PCI)
  1401. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1402. else if (ha->type == GDT_PCINEW)
  1403. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1404. else if (ha->type == GDT_PCIMPR)
  1405. gdtsema0 =
  1406. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1407. return (gdtsema0 & 1);
  1408. }
  1409. static int gdth_get_cmd_index(int hanum)
  1410. {
  1411. register gdth_ha_str *ha;
  1412. int i;
  1413. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1414. ha = HADATA(gdth_ctr_tab[hanum]);
  1415. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1416. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1417. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1418. ha->cmd_tab[i].service = ha->pccb->Service;
  1419. ha->pccb->CommandIndex = (ulong32)i+2;
  1420. return (i+2);
  1421. }
  1422. }
  1423. return 0;
  1424. }
  1425. static void gdth_set_sema0(int hanum)
  1426. {
  1427. register gdth_ha_str *ha;
  1428. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1429. ha = HADATA(gdth_ctr_tab[hanum]);
  1430. if (ha->type == GDT_EISA) {
  1431. outb(1, ha->bmic + SEMA0REG);
  1432. } else if (ha->type == GDT_ISA) {
  1433. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1434. } else if (ha->type == GDT_PCI) {
  1435. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1436. } else if (ha->type == GDT_PCINEW) {
  1437. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1438. } else if (ha->type == GDT_PCIMPR) {
  1439. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1440. }
  1441. }
  1442. static void gdth_copy_command(int hanum)
  1443. {
  1444. register gdth_ha_str *ha;
  1445. register gdth_cmd_str *cmd_ptr;
  1446. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1447. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1448. gdt6_dpram_str __iomem *dp6_ptr;
  1449. gdt2_dpram_str __iomem *dp2_ptr;
  1450. ushort cp_count,dp_offset,cmd_no;
  1451. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1452. ha = HADATA(gdth_ctr_tab[hanum]);
  1453. cp_count = ha->cmd_len;
  1454. dp_offset= ha->cmd_offs_dpmem;
  1455. cmd_no = ha->cmd_cnt;
  1456. cmd_ptr = ha->pccb;
  1457. ++ha->cmd_cnt;
  1458. if (ha->type == GDT_EISA)
  1459. return; /* no DPMEM, no copy */
  1460. /* set cpcount dword aligned */
  1461. if (cp_count & 3)
  1462. cp_count += (4 - (cp_count & 3));
  1463. ha->cmd_offs_dpmem += cp_count;
  1464. /* set offset and service, copy command to DPMEM */
  1465. if (ha->type == GDT_ISA) {
  1466. dp2_ptr = ha->brd;
  1467. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1468. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1469. gdth_writew((ushort)cmd_ptr->Service,
  1470. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1471. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1472. } else if (ha->type == GDT_PCI) {
  1473. dp6_ptr = ha->brd;
  1474. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1475. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1476. gdth_writew((ushort)cmd_ptr->Service,
  1477. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1478. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1479. } else if (ha->type == GDT_PCINEW) {
  1480. dp6c_ptr = ha->brd;
  1481. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1482. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1483. gdth_writew((ushort)cmd_ptr->Service,
  1484. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1485. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1486. } else if (ha->type == GDT_PCIMPR) {
  1487. dp6m_ptr = ha->brd;
  1488. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1489. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1490. gdth_writew((ushort)cmd_ptr->Service,
  1491. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1492. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1493. }
  1494. }
  1495. static void gdth_release_event(int hanum)
  1496. {
  1497. register gdth_ha_str *ha;
  1498. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1499. ha = HADATA(gdth_ctr_tab[hanum]);
  1500. #ifdef GDTH_STATISTICS
  1501. {
  1502. ulong32 i,j;
  1503. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1504. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1505. ++i;
  1506. }
  1507. if (max_index < i) {
  1508. max_index = i;
  1509. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1510. }
  1511. }
  1512. #endif
  1513. if (ha->pccb->OpCode == GDT_INIT)
  1514. ha->pccb->Service |= 0x80;
  1515. if (ha->type == GDT_EISA) {
  1516. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1517. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1518. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1519. } else if (ha->type == GDT_ISA) {
  1520. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1521. } else if (ha->type == GDT_PCI) {
  1522. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1523. } else if (ha->type == GDT_PCINEW) {
  1524. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1525. } else if (ha->type == GDT_PCIMPR) {
  1526. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1527. }
  1528. }
  1529. static int gdth_wait(int hanum,int index,ulong32 time)
  1530. {
  1531. gdth_ha_str *ha;
  1532. int answer_found = FALSE;
  1533. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1534. ha = HADATA(gdth_ctr_tab[hanum]);
  1535. if (index == 0)
  1536. return 1; /* no wait required */
  1537. gdth_from_wait = TRUE;
  1538. do {
  1539. gdth_interrupt((int)ha->irq,ha,NULL);
  1540. if (wait_hanum==hanum && wait_index==index) {
  1541. answer_found = TRUE;
  1542. break;
  1543. }
  1544. gdth_delay(1);
  1545. } while (--time);
  1546. gdth_from_wait = FALSE;
  1547. while (gdth_test_busy(hanum))
  1548. gdth_delay(0);
  1549. return (answer_found);
  1550. }
  1551. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1552. ulong64 p2,ulong64 p3)
  1553. {
  1554. register gdth_ha_str *ha;
  1555. register gdth_cmd_str *cmd_ptr;
  1556. int retries,index;
  1557. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1558. ha = HADATA(gdth_ctr_tab[hanum]);
  1559. cmd_ptr = ha->pccb;
  1560. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1561. /* make command */
  1562. for (retries = INIT_RETRIES;;) {
  1563. cmd_ptr->Service = service;
  1564. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1565. if (!(index=gdth_get_cmd_index(hanum))) {
  1566. TRACE(("GDT: No free command index found\n"));
  1567. return 0;
  1568. }
  1569. gdth_set_sema0(hanum);
  1570. cmd_ptr->OpCode = opcode;
  1571. cmd_ptr->BoardNode = LOCALBOARD;
  1572. if (service == CACHESERVICE) {
  1573. if (opcode == GDT_IOCTL) {
  1574. cmd_ptr->u.ioctl.subfunc = p1;
  1575. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1576. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1577. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1578. } else {
  1579. if (ha->cache_feat & GDT_64BIT) {
  1580. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1581. cmd_ptr->u.cache64.BlockNo = p2;
  1582. } else {
  1583. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1584. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1585. }
  1586. }
  1587. } else if (service == SCSIRAWSERVICE) {
  1588. if (ha->raw_feat & GDT_64BIT) {
  1589. cmd_ptr->u.raw64.direction = p1;
  1590. cmd_ptr->u.raw64.bus = (unchar)p2;
  1591. cmd_ptr->u.raw64.target = (unchar)p3;
  1592. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1593. } else {
  1594. cmd_ptr->u.raw.direction = p1;
  1595. cmd_ptr->u.raw.bus = (unchar)p2;
  1596. cmd_ptr->u.raw.target = (unchar)p3;
  1597. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1598. }
  1599. } else if (service == SCREENSERVICE) {
  1600. if (opcode == GDT_REALTIME) {
  1601. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1602. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1603. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1604. }
  1605. }
  1606. ha->cmd_len = sizeof(gdth_cmd_str);
  1607. ha->cmd_offs_dpmem = 0;
  1608. ha->cmd_cnt = 0;
  1609. gdth_copy_command(hanum);
  1610. gdth_release_event(hanum);
  1611. gdth_delay(20);
  1612. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1613. printk("GDT: Initialization error (timeout service %d)\n",service);
  1614. return 0;
  1615. }
  1616. if (ha->status != S_BSY || --retries == 0)
  1617. break;
  1618. gdth_delay(1);
  1619. }
  1620. return (ha->status != S_OK ? 0:1);
  1621. }
  1622. /* search for devices */
  1623. static int __init gdth_search_drives(int hanum)
  1624. {
  1625. register gdth_ha_str *ha;
  1626. ushort cdev_cnt, i;
  1627. int ok;
  1628. ulong32 bus_no, drv_cnt, drv_no, j;
  1629. gdth_getch_str *chn;
  1630. gdth_drlist_str *drl;
  1631. gdth_iochan_str *ioc;
  1632. gdth_raw_iochan_str *iocr;
  1633. gdth_arcdl_str *alst;
  1634. gdth_alist_str *alst2;
  1635. gdth_oem_str_ioctl *oemstr;
  1636. #ifdef INT_COAL
  1637. gdth_perf_modes *pmod;
  1638. #endif
  1639. #ifdef GDTH_RTC
  1640. unchar rtc[12];
  1641. ulong flags;
  1642. #endif
  1643. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1644. ha = HADATA(gdth_ctr_tab[hanum]);
  1645. ok = 0;
  1646. /* initialize controller services, at first: screen service */
  1647. ha->screen_feat = 0;
  1648. if (!force_dma32) {
  1649. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1650. if (ok)
  1651. ha->screen_feat = GDT_64BIT;
  1652. }
  1653. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1654. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1655. if (!ok) {
  1656. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1657. hanum, ha->status);
  1658. return 0;
  1659. }
  1660. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1661. #ifdef GDTH_RTC
  1662. /* read realtime clock info, send to controller */
  1663. /* 1. wait for the falling edge of update flag */
  1664. spin_lock_irqsave(&rtc_lock, flags);
  1665. for (j = 0; j < 1000000; ++j)
  1666. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1667. break;
  1668. for (j = 0; j < 1000000; ++j)
  1669. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1670. break;
  1671. /* 2. read info */
  1672. do {
  1673. for (j = 0; j < 12; ++j)
  1674. rtc[j] = CMOS_READ(j);
  1675. } while (rtc[0] != CMOS_READ(0));
  1676. spin_lock_irqrestore(&rtc_lock, flags);
  1677. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1678. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1679. /* 3. send to controller firmware */
  1680. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1681. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1682. #endif
  1683. /* unfreeze all IOs */
  1684. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1685. /* initialize cache service */
  1686. ha->cache_feat = 0;
  1687. if (!force_dma32) {
  1688. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1689. if (ok)
  1690. ha->cache_feat = GDT_64BIT;
  1691. }
  1692. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1693. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1694. if (!ok) {
  1695. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1696. hanum, ha->status);
  1697. return 0;
  1698. }
  1699. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1700. cdev_cnt = (ushort)ha->info;
  1701. ha->fw_vers = ha->service;
  1702. #ifdef INT_COAL
  1703. if (ha->type == GDT_PCIMPR) {
  1704. /* set perf. modes */
  1705. pmod = (gdth_perf_modes *)ha->pscratch;
  1706. pmod->version = 1;
  1707. pmod->st_mode = 1; /* enable one status buffer */
  1708. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1709. pmod->st_buff_indx1 = COALINDEX;
  1710. pmod->st_buff_addr2 = 0;
  1711. pmod->st_buff_u_addr2 = 0;
  1712. pmod->st_buff_indx2 = 0;
  1713. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1714. pmod->cmd_mode = 0; // disable all cmd buffers
  1715. pmod->cmd_buff_addr1 = 0;
  1716. pmod->cmd_buff_u_addr1 = 0;
  1717. pmod->cmd_buff_indx1 = 0;
  1718. pmod->cmd_buff_addr2 = 0;
  1719. pmod->cmd_buff_u_addr2 = 0;
  1720. pmod->cmd_buff_indx2 = 0;
  1721. pmod->cmd_buff_size = 0;
  1722. pmod->reserved1 = 0;
  1723. pmod->reserved2 = 0;
  1724. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1725. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1726. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1727. }
  1728. }
  1729. #endif
  1730. /* detect number of buses - try new IOCTL */
  1731. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1732. iocr->hdr.version = 0xffffffff;
  1733. iocr->hdr.list_entries = MAXBUS;
  1734. iocr->hdr.first_chan = 0;
  1735. iocr->hdr.last_chan = MAXBUS-1;
  1736. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1737. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1738. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1739. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1740. ha->bus_cnt = iocr->hdr.chan_count;
  1741. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1742. if (iocr->list[bus_no].proc_id < MAXID)
  1743. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1744. else
  1745. ha->bus_id[bus_no] = 0xff;
  1746. }
  1747. } else {
  1748. /* old method */
  1749. chn = (gdth_getch_str *)ha->pscratch;
  1750. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1751. chn->channel_no = bus_no;
  1752. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1753. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1754. IO_CHANNEL | INVALID_CHANNEL,
  1755. sizeof(gdth_getch_str))) {
  1756. if (bus_no == 0) {
  1757. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1758. hanum, ha->status);
  1759. return 0;
  1760. }
  1761. break;
  1762. }
  1763. if (chn->siop_id < MAXID)
  1764. ha->bus_id[bus_no] = chn->siop_id;
  1765. else
  1766. ha->bus_id[bus_no] = 0xff;
  1767. }
  1768. ha->bus_cnt = (unchar)bus_no;
  1769. }
  1770. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1771. /* read cache configuration */
  1772. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1773. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1774. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1775. hanum, ha->status);
  1776. return 0;
  1777. }
  1778. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1779. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1780. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1781. ha->cpar.write_back,ha->cpar.block_size));
  1782. /* read board info and features */
  1783. ha->more_proc = FALSE;
  1784. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1785. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1786. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1787. sizeof(gdth_binfo_str));
  1788. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1789. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1790. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1791. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1792. ha->more_proc = TRUE;
  1793. }
  1794. } else {
  1795. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1796. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1797. }
  1798. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1799. /* read more informations */
  1800. if (ha->more_proc) {
  1801. /* physical drives, channel addresses */
  1802. ioc = (gdth_iochan_str *)ha->pscratch;
  1803. ioc->hdr.version = 0xffffffff;
  1804. ioc->hdr.list_entries = MAXBUS;
  1805. ioc->hdr.first_chan = 0;
  1806. ioc->hdr.last_chan = MAXBUS-1;
  1807. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1808. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1809. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1810. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1811. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1812. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1813. }
  1814. } else {
  1815. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1816. ha->raw[bus_no].address = IO_CHANNEL;
  1817. ha->raw[bus_no].local_no = bus_no;
  1818. }
  1819. }
  1820. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1821. chn = (gdth_getch_str *)ha->pscratch;
  1822. chn->channel_no = ha->raw[bus_no].local_no;
  1823. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1824. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1825. ha->raw[bus_no].address | INVALID_CHANNEL,
  1826. sizeof(gdth_getch_str))) {
  1827. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1828. TRACE2(("Channel %d: %d phys. drives\n",
  1829. bus_no,chn->drive_cnt));
  1830. }
  1831. if (ha->raw[bus_no].pdev_cnt > 0) {
  1832. drl = (gdth_drlist_str *)ha->pscratch;
  1833. drl->sc_no = ha->raw[bus_no].local_no;
  1834. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1835. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1836. SCSI_DR_LIST | L_CTRL_PATTERN,
  1837. ha->raw[bus_no].address | INVALID_CHANNEL,
  1838. sizeof(gdth_drlist_str))) {
  1839. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1840. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1841. } else {
  1842. ha->raw[bus_no].pdev_cnt = 0;
  1843. }
  1844. }
  1845. }
  1846. /* logical drives */
  1847. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1848. INVALID_CHANNEL,sizeof(ulong32))) {
  1849. drv_cnt = *(ulong32 *)ha->pscratch;
  1850. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1851. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1852. for (j = 0; j < drv_cnt; ++j) {
  1853. drv_no = ((ulong32 *)ha->pscratch)[j];
  1854. if (drv_no < MAX_LDRIVES) {
  1855. ha->hdr[drv_no].is_logdrv = TRUE;
  1856. TRACE2(("Drive %d is log. drive\n",drv_no));
  1857. }
  1858. }
  1859. }
  1860. alst = (gdth_arcdl_str *)ha->pscratch;
  1861. alst->entries_avail = MAX_LDRIVES;
  1862. alst->first_entry = 0;
  1863. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1864. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1865. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1866. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1867. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1868. for (j = 0; j < alst->entries_init; ++j) {
  1869. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1870. ha->hdr[j].is_master = alst->list[j].is_master;
  1871. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1872. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1873. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1874. }
  1875. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1876. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1877. 0, 35 * sizeof(gdth_alist_str))) {
  1878. for (j = 0; j < 35; ++j) {
  1879. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1880. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1881. ha->hdr[j].is_master = alst2->is_master;
  1882. ha->hdr[j].is_parity = alst2->is_parity;
  1883. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1884. ha->hdr[j].master_no = alst2->cd_handle;
  1885. }
  1886. }
  1887. }
  1888. }
  1889. /* initialize raw service */
  1890. ha->raw_feat = 0;
  1891. if (!force_dma32) {
  1892. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1893. if (ok)
  1894. ha->raw_feat = GDT_64BIT;
  1895. }
  1896. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1897. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1898. if (!ok) {
  1899. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  1900. hanum, ha->status);
  1901. return 0;
  1902. }
  1903. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  1904. /* set/get features raw service (scatter/gather) */
  1905. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  1906. 0,0)) {
  1907. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  1908. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  1909. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  1910. ha->info));
  1911. ha->raw_feat |= (ushort)ha->info;
  1912. }
  1913. }
  1914. /* set/get features cache service (equal to raw service) */
  1915. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  1916. SCATTER_GATHER,0)) {
  1917. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  1918. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  1919. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  1920. ha->info));
  1921. ha->cache_feat |= (ushort)ha->info;
  1922. }
  1923. }
  1924. /* reserve drives for raw service */
  1925. if (reserve_mode != 0) {
  1926. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  1927. reserve_mode == 1 ? 1 : 3, 0, 0);
  1928. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  1929. ha->status));
  1930. }
  1931. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  1932. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  1933. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  1934. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  1935. reserve_list[i], reserve_list[i+1],
  1936. reserve_list[i+2], reserve_list[i+3]));
  1937. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  1938. reserve_list[i+1], reserve_list[i+2] |
  1939. (reserve_list[i+3] << 8))) {
  1940. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  1941. hanum, ha->status);
  1942. }
  1943. }
  1944. }
  1945. /* Determine OEM string using IOCTL */
  1946. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  1947. oemstr->params.ctl_version = 0x01;
  1948. oemstr->params.buffer_size = sizeof(oemstr->text);
  1949. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1950. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  1951. sizeof(gdth_oem_str_ioctl))) {
  1952. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  1953. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  1954. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  1955. /* Save the Host Drive inquiry data */
  1956. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  1957. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  1958. sizeof(ha->oem_name));
  1959. #else
  1960. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  1961. ha->oem_name[7] = '\0';
  1962. #endif
  1963. } else {
  1964. /* Old method, based on PCI ID */
  1965. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  1966. printk("GDT-HA %d: Name: %s\n",
  1967. hanum,ha->binfo.type_string);
  1968. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  1969. if (ha->oem_id == OEM_ID_INTEL)
  1970. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  1971. else
  1972. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  1973. #else
  1974. if (ha->oem_id == OEM_ID_INTEL)
  1975. strcpy(ha->oem_name,"Intel ");
  1976. else
  1977. strcpy(ha->oem_name,"ICP ");
  1978. #endif
  1979. }
  1980. /* scanning for host drives */
  1981. for (i = 0; i < cdev_cnt; ++i)
  1982. gdth_analyse_hdrive(hanum,i);
  1983. TRACE(("gdth_search_drives() OK\n"));
  1984. return 1;
  1985. }
  1986. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  1987. {
  1988. register gdth_ha_str *ha;
  1989. ulong32 drv_cyls;
  1990. int drv_hds, drv_secs;
  1991. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  1992. if (hdrive >= MAX_HDRIVES)
  1993. return 0;
  1994. ha = HADATA(gdth_ctr_tab[hanum]);
  1995. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  1996. return 0;
  1997. ha->hdr[hdrive].present = TRUE;
  1998. ha->hdr[hdrive].size = ha->info;
  1999. /* evaluate mapping (sectors per head, heads per cylinder) */
  2000. ha->hdr[hdrive].size &= ~SECS32;
  2001. if (ha->info2 == 0) {
  2002. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2003. } else {
  2004. drv_hds = ha->info2 & 0xff;
  2005. drv_secs = (ha->info2 >> 8) & 0xff;
  2006. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2007. }
  2008. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2009. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2010. /* round size */
  2011. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2012. if (ha->cache_feat & GDT_64BIT) {
  2013. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2014. && ha->info2 != 0) {
  2015. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2016. }
  2017. }
  2018. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2019. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2020. /* get informations about device */
  2021. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2022. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2023. hdrive,ha->info));
  2024. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2025. }
  2026. /* cluster info */
  2027. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2028. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2029. hdrive,ha->info));
  2030. if (!shared_access)
  2031. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2032. }
  2033. /* R/W attributes */
  2034. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2035. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2036. hdrive,ha->info));
  2037. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2038. }
  2039. return 1;
  2040. }
  2041. /* command queueing/sending functions */
  2042. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2043. {
  2044. register gdth_ha_str *ha;
  2045. register Scsi_Cmnd *pscp;
  2046. register Scsi_Cmnd *nscp;
  2047. ulong flags;
  2048. unchar b, t;
  2049. TRACE(("gdth_putq() priority %d\n",priority));
  2050. ha = HADATA(gdth_ctr_tab[hanum]);
  2051. spin_lock_irqsave(&ha->smp_lock, flags);
  2052. scp->SCp.this_residual = (int)priority;
  2053. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  2054. t = scp->device->id;
  2055. if (priority >= DEFAULT_PRI) {
  2056. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2057. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock)) {
  2058. TRACE2(("gdth_putq(): locked IO -> update_timeout()\n"));
  2059. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2060. }
  2061. }
  2062. if (ha->req_first==NULL) {
  2063. ha->req_first = scp; /* queue was empty */
  2064. scp->SCp.ptr = NULL;
  2065. } else { /* queue not empty */
  2066. pscp = ha->req_first;
  2067. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2068. /* priority: 0-highest,..,0xff-lowest */
  2069. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2070. pscp = nscp;
  2071. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2072. }
  2073. pscp->SCp.ptr = (char *)scp;
  2074. scp->SCp.ptr = (char *)nscp;
  2075. }
  2076. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2077. #ifdef GDTH_STATISTICS
  2078. flags = 0;
  2079. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2080. ++flags;
  2081. if (max_rq < flags) {
  2082. max_rq = flags;
  2083. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2084. }
  2085. #endif
  2086. }
  2087. static void gdth_next(int hanum)
  2088. {
  2089. register gdth_ha_str *ha;
  2090. register Scsi_Cmnd *pscp;
  2091. register Scsi_Cmnd *nscp;
  2092. unchar b, t, l, firsttime;
  2093. unchar this_cmd, next_cmd;
  2094. ulong flags = 0;
  2095. int cmd_index;
  2096. TRACE(("gdth_next() hanum %d\n",hanum));
  2097. ha = HADATA(gdth_ctr_tab[hanum]);
  2098. if (!gdth_polling)
  2099. spin_lock_irqsave(&ha->smp_lock, flags);
  2100. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2101. this_cmd = firsttime = TRUE;
  2102. next_cmd = gdth_polling ? FALSE:TRUE;
  2103. cmd_index = 0;
  2104. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2105. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2106. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2107. b = virt_ctr ? NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2108. t = nscp->device->id;
  2109. l = nscp->device->lun;
  2110. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2111. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2112. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2113. continue;
  2114. }
  2115. if (firsttime) {
  2116. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2117. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2118. if (!gdth_polling) {
  2119. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2120. return;
  2121. }
  2122. while (gdth_test_busy(hanum))
  2123. gdth_delay(1);
  2124. }
  2125. firsttime = FALSE;
  2126. }
  2127. if (nscp->done != gdth_scsi_done || nscp->cmnd[0] != 0xff) {
  2128. if (nscp->SCp.phase == -1) {
  2129. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2130. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2131. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2132. b, t, l));
  2133. /* TEST_UNIT_READY -> set scan mode */
  2134. if ((ha->scan_mode & 0x0f) == 0) {
  2135. if (b == 0 && t == 0 && l == 0) {
  2136. ha->scan_mode |= 1;
  2137. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2138. }
  2139. } else if ((ha->scan_mode & 0x0f) == 1) {
  2140. if (b == 0 && ((t == 0 && l == 1) ||
  2141. (t == 1 && l == 0))) {
  2142. nscp->SCp.sent_command = GDT_SCAN_START;
  2143. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2144. | SCSIRAWSERVICE;
  2145. ha->scan_mode = 0x12;
  2146. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2147. ha->scan_mode));
  2148. } else {
  2149. ha->scan_mode &= 0x10;
  2150. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2151. }
  2152. } else if (ha->scan_mode == 0x12) {
  2153. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2154. nscp->SCp.phase = SCSIRAWSERVICE;
  2155. nscp->SCp.sent_command = GDT_SCAN_END;
  2156. ha->scan_mode &= 0x10;
  2157. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2158. ha->scan_mode));
  2159. }
  2160. }
  2161. }
  2162. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2163. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2164. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2165. /* always GDT_CLUST_INFO! */
  2166. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2167. }
  2168. }
  2169. }
  2170. if (nscp->SCp.sent_command != -1) {
  2171. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2172. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2173. this_cmd = FALSE;
  2174. next_cmd = FALSE;
  2175. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2176. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2177. this_cmd = FALSE;
  2178. next_cmd = FALSE;
  2179. } else {
  2180. memset((char*)nscp->sense_buffer,0,16);
  2181. nscp->sense_buffer[0] = 0x70;
  2182. nscp->sense_buffer[2] = NOT_READY;
  2183. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2184. if (!nscp->SCp.have_data_in)
  2185. nscp->SCp.have_data_in++;
  2186. else
  2187. nscp->scsi_done(nscp);
  2188. }
  2189. } else if (nscp->done == gdth_scsi_done && nscp->cmnd[0] == 0xff) {
  2190. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2191. this_cmd = FALSE;
  2192. next_cmd = FALSE;
  2193. } else if (b != ha->virt_bus) {
  2194. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2195. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2196. this_cmd = FALSE;
  2197. else
  2198. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2199. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2200. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2201. nscp->cmnd[0], b, t, l));
  2202. nscp->result = DID_BAD_TARGET << 16;
  2203. if (!nscp->SCp.have_data_in)
  2204. nscp->SCp.have_data_in++;
  2205. else
  2206. nscp->scsi_done(nscp);
  2207. } else {
  2208. switch (nscp->cmnd[0]) {
  2209. case TEST_UNIT_READY:
  2210. case INQUIRY:
  2211. case REQUEST_SENSE:
  2212. case READ_CAPACITY:
  2213. case VERIFY:
  2214. case START_STOP:
  2215. case MODE_SENSE:
  2216. case SERVICE_ACTION_IN:
  2217. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2218. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2219. nscp->cmnd[4],nscp->cmnd[5]));
  2220. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2221. /* return UNIT_ATTENTION */
  2222. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2223. nscp->cmnd[0], t));
  2224. ha->hdr[t].media_changed = FALSE;
  2225. memset((char*)nscp->sense_buffer,0,16);
  2226. nscp->sense_buffer[0] = 0x70;
  2227. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2228. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2229. if (!nscp->SCp.have_data_in)
  2230. nscp->SCp.have_data_in++;
  2231. else
  2232. nscp->scsi_done(nscp);
  2233. } else if (gdth_internal_cache_cmd(hanum,nscp))
  2234. nscp->scsi_done(nscp);
  2235. break;
  2236. case ALLOW_MEDIUM_REMOVAL:
  2237. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2238. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2239. nscp->cmnd[4],nscp->cmnd[5]));
  2240. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2241. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2242. nscp->result = DID_OK << 16;
  2243. nscp->sense_buffer[0] = 0;
  2244. if (!nscp->SCp.have_data_in)
  2245. nscp->SCp.have_data_in++;
  2246. else
  2247. nscp->scsi_done(nscp);
  2248. } else {
  2249. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2250. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2251. nscp->cmnd[4],nscp->cmnd[3]));
  2252. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2253. this_cmd = FALSE;
  2254. }
  2255. break;
  2256. case RESERVE:
  2257. case RELEASE:
  2258. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2259. "RESERVE" : "RELEASE"));
  2260. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2261. this_cmd = FALSE;
  2262. break;
  2263. case READ_6:
  2264. case WRITE_6:
  2265. case READ_10:
  2266. case WRITE_10:
  2267. case READ_16:
  2268. case WRITE_16:
  2269. if (ha->hdr[t].media_changed) {
  2270. /* return UNIT_ATTENTION */
  2271. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2272. nscp->cmnd[0], t));
  2273. ha->hdr[t].media_changed = FALSE;
  2274. memset((char*)nscp->sense_buffer,0,16);
  2275. nscp->sense_buffer[0] = 0x70;
  2276. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2277. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2278. if (!nscp->SCp.have_data_in)
  2279. nscp->SCp.have_data_in++;
  2280. else
  2281. nscp->scsi_done(nscp);
  2282. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2283. this_cmd = FALSE;
  2284. break;
  2285. default:
  2286. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2287. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2288. nscp->cmnd[4],nscp->cmnd[5]));
  2289. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2290. hanum, nscp->cmnd[0]);
  2291. nscp->result = DID_ABORT << 16;
  2292. if (!nscp->SCp.have_data_in)
  2293. nscp->SCp.have_data_in++;
  2294. else
  2295. nscp->scsi_done(nscp);
  2296. break;
  2297. }
  2298. }
  2299. if (!this_cmd)
  2300. break;
  2301. if (nscp == ha->req_first)
  2302. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2303. else
  2304. pscp->SCp.ptr = nscp->SCp.ptr;
  2305. if (!next_cmd)
  2306. break;
  2307. }
  2308. if (ha->cmd_cnt > 0) {
  2309. gdth_release_event(hanum);
  2310. }
  2311. if (!gdth_polling)
  2312. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2313. if (gdth_polling && ha->cmd_cnt > 0) {
  2314. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2315. printk("GDT-HA %d: Command %d timed out !\n",
  2316. hanum,cmd_index);
  2317. }
  2318. }
  2319. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2320. char *buffer,ushort count)
  2321. {
  2322. ushort cpcount,i;
  2323. ushort cpsum,cpnow;
  2324. struct scatterlist *sl;
  2325. gdth_ha_str *ha;
  2326. char *address;
  2327. cpcount = count<=(ushort)scp->bufflen ? count:(ushort)scp->bufflen;
  2328. ha = HADATA(gdth_ctr_tab[hanum]);
  2329. if (scp->use_sg) {
  2330. sl = (struct scatterlist *)scp->request_buffer;
  2331. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2332. unsigned long flags;
  2333. cpnow = (ushort)sl->length;
  2334. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2335. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2336. if (cpsum+cpnow > cpcount)
  2337. cpnow = cpcount - cpsum;
  2338. cpsum += cpnow;
  2339. if (!sl->page) {
  2340. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2341. hanum);
  2342. return;
  2343. }
  2344. local_irq_save(flags);
  2345. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2346. memcpy(address,buffer,cpnow);
  2347. flush_dcache_page(sl->page);
  2348. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2349. local_irq_restore(flags);
  2350. if (cpsum == cpcount)
  2351. break;
  2352. buffer += cpnow;
  2353. }
  2354. } else {
  2355. TRACE(("copy_internal() count %d\n",cpcount));
  2356. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2357. }
  2358. }
  2359. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2360. {
  2361. register gdth_ha_str *ha;
  2362. unchar t;
  2363. gdth_inq_data inq;
  2364. gdth_rdcap_data rdc;
  2365. gdth_sense_data sd;
  2366. gdth_modep_data mpd;
  2367. ha = HADATA(gdth_ctr_tab[hanum]);
  2368. t = scp->device->id;
  2369. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2370. scp->cmnd[0],t));
  2371. scp->result = DID_OK << 16;
  2372. scp->sense_buffer[0] = 0;
  2373. switch (scp->cmnd[0]) {
  2374. case TEST_UNIT_READY:
  2375. case VERIFY:
  2376. case START_STOP:
  2377. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2378. break;
  2379. case INQUIRY:
  2380. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2381. t,ha->hdr[t].devtype));
  2382. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2383. /* you can here set all disks to removable, if you want to do
  2384. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2385. inq.modif_rmb = 0x00;
  2386. if ((ha->hdr[t].devtype & 1) ||
  2387. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2388. inq.modif_rmb = 0x80;
  2389. inq.version = 2;
  2390. inq.resp_aenc = 2;
  2391. inq.add_length= 32;
  2392. strcpy(inq.vendor,ha->oem_name);
  2393. sprintf(inq.product,"Host Drive #%02d",t);
  2394. strcpy(inq.revision," ");
  2395. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2396. break;
  2397. case REQUEST_SENSE:
  2398. TRACE2(("Request sense hdrive %d\n",t));
  2399. sd.errorcode = 0x70;
  2400. sd.segno = 0x00;
  2401. sd.key = NO_SENSE;
  2402. sd.info = 0;
  2403. sd.add_length= 0;
  2404. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2405. break;
  2406. case MODE_SENSE:
  2407. TRACE2(("Mode sense hdrive %d\n",t));
  2408. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2409. mpd.hd.data_length = sizeof(gdth_modep_data);
  2410. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2411. mpd.hd.bd_length = sizeof(mpd.bd);
  2412. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2413. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2414. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2415. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2416. break;
  2417. case READ_CAPACITY:
  2418. TRACE2(("Read capacity hdrive %d\n",t));
  2419. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2420. rdc.last_block_no = 0xffffffff;
  2421. else
  2422. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2423. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2424. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2425. break;
  2426. case SERVICE_ACTION_IN:
  2427. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2428. (ha->cache_feat & GDT_64BIT)) {
  2429. gdth_rdcap16_data rdc16;
  2430. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2431. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2432. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2433. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2434. } else {
  2435. scp->result = DID_ABORT << 16;
  2436. }
  2437. break;
  2438. default:
  2439. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2440. break;
  2441. }
  2442. if (!scp->SCp.have_data_in)
  2443. scp->SCp.have_data_in++;
  2444. else
  2445. return 1;
  2446. return 0;
  2447. }
  2448. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2449. {
  2450. register gdth_ha_str *ha;
  2451. register gdth_cmd_str *cmdp;
  2452. struct scatterlist *sl;
  2453. ulong32 cnt, blockcnt;
  2454. ulong64 no, blockno;
  2455. dma_addr_t phys_addr;
  2456. int i, cmd_index, read_write, sgcnt, mode64;
  2457. struct page *page;
  2458. ulong offset;
  2459. ha = HADATA(gdth_ctr_tab[hanum]);
  2460. cmdp = ha->pccb;
  2461. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2462. scp->cmnd[0],scp->cmd_len,hdrive));
  2463. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2464. return 0;
  2465. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2466. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2467. not required, should not occur due to error return on
  2468. READ_CAPACITY_16 */
  2469. cmdp->Service = CACHESERVICE;
  2470. cmdp->RequestBuffer = scp;
  2471. /* search free command index */
  2472. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2473. TRACE(("GDT: No free command index found\n"));
  2474. return 0;
  2475. }
  2476. /* if it's the first command, set command semaphore */
  2477. if (ha->cmd_cnt == 0)
  2478. gdth_set_sema0(hanum);
  2479. /* fill command */
  2480. read_write = 0;
  2481. if (scp->SCp.sent_command != -1)
  2482. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2483. else if (scp->cmnd[0] == RESERVE)
  2484. cmdp->OpCode = GDT_RESERVE_DRV;
  2485. else if (scp->cmnd[0] == RELEASE)
  2486. cmdp->OpCode = GDT_RELEASE_DRV;
  2487. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2488. if (scp->cmnd[4] & 1) /* prevent ? */
  2489. cmdp->OpCode = GDT_MOUNT;
  2490. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2491. cmdp->OpCode = GDT_UNMOUNT;
  2492. else
  2493. cmdp->OpCode = GDT_FLUSH;
  2494. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2495. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2496. ) {
  2497. read_write = 1;
  2498. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2499. (ha->cache_feat & GDT_WR_THROUGH)))
  2500. cmdp->OpCode = GDT_WRITE_THR;
  2501. else
  2502. cmdp->OpCode = GDT_WRITE;
  2503. } else {
  2504. read_write = 2;
  2505. cmdp->OpCode = GDT_READ;
  2506. }
  2507. cmdp->BoardNode = LOCALBOARD;
  2508. if (mode64) {
  2509. cmdp->u.cache64.DeviceNo = hdrive;
  2510. cmdp->u.cache64.BlockNo = 1;
  2511. cmdp->u.cache64.sg_canz = 0;
  2512. } else {
  2513. cmdp->u.cache.DeviceNo = hdrive;
  2514. cmdp->u.cache.BlockNo = 1;
  2515. cmdp->u.cache.sg_canz = 0;
  2516. }
  2517. if (read_write) {
  2518. if (scp->cmd_len == 16) {
  2519. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2520. blockno = be64_to_cpu(no);
  2521. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2522. blockcnt = be32_to_cpu(cnt);
  2523. } else if (scp->cmd_len == 10) {
  2524. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2525. blockno = be32_to_cpu(no);
  2526. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2527. blockcnt = be16_to_cpu(cnt);
  2528. } else {
  2529. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2530. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2531. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2532. }
  2533. if (mode64) {
  2534. cmdp->u.cache64.BlockNo = blockno;
  2535. cmdp->u.cache64.BlockCnt = blockcnt;
  2536. } else {
  2537. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2538. cmdp->u.cache.BlockCnt = blockcnt;
  2539. }
  2540. if (scp->use_sg) {
  2541. sl = (struct scatterlist *)scp->request_buffer;
  2542. sgcnt = scp->use_sg;
  2543. scp->SCp.Status = GDTH_MAP_SG;
  2544. scp->SCp.Message = (read_write == 1 ?
  2545. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2546. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2547. if (mode64) {
  2548. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2549. cmdp->u.cache64.sg_canz = sgcnt;
  2550. for (i=0; i<sgcnt; ++i,++sl) {
  2551. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2552. #ifdef GDTH_DMA_STATISTICS
  2553. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2554. ha->dma64_cnt++;
  2555. else
  2556. ha->dma32_cnt++;
  2557. #endif
  2558. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2559. }
  2560. } else {
  2561. cmdp->u.cache.DestAddr= 0xffffffff;
  2562. cmdp->u.cache.sg_canz = sgcnt;
  2563. for (i=0; i<sgcnt; ++i,++sl) {
  2564. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2565. #ifdef GDTH_DMA_STATISTICS
  2566. ha->dma32_cnt++;
  2567. #endif
  2568. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2569. }
  2570. }
  2571. #ifdef GDTH_STATISTICS
  2572. if (max_sg < (ulong32)sgcnt) {
  2573. max_sg = (ulong32)sgcnt;
  2574. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2575. }
  2576. #endif
  2577. } else if (scp->request_bufflen) {
  2578. scp->SCp.Status = GDTH_MAP_SINGLE;
  2579. scp->SCp.Message = (read_write == 1 ?
  2580. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2581. page = virt_to_page(scp->request_buffer);
  2582. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2583. phys_addr = pci_map_page(ha->pdev,page,offset,
  2584. scp->request_bufflen,scp->SCp.Message);
  2585. scp->SCp.dma_handle = phys_addr;
  2586. if (mode64) {
  2587. if (ha->cache_feat & SCATTER_GATHER) {
  2588. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2589. cmdp->u.cache64.sg_canz = 1;
  2590. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2591. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2592. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2593. } else {
  2594. cmdp->u.cache64.DestAddr = phys_addr;
  2595. cmdp->u.cache64.sg_canz= 0;
  2596. }
  2597. } else {
  2598. if (ha->cache_feat & SCATTER_GATHER) {
  2599. cmdp->u.cache.DestAddr = 0xffffffff;
  2600. cmdp->u.cache.sg_canz = 1;
  2601. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2602. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2603. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2604. } else {
  2605. cmdp->u.cache.DestAddr = phys_addr;
  2606. cmdp->u.cache.sg_canz= 0;
  2607. }
  2608. }
  2609. }
  2610. }
  2611. /* evaluate command size, check space */
  2612. if (mode64) {
  2613. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2614. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2615. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2616. cmdp->u.cache64.sg_lst[0].sg_len));
  2617. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2618. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2619. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2620. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2621. } else {
  2622. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2623. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2624. cmdp->u.cache.sg_lst[0].sg_ptr,
  2625. cmdp->u.cache.sg_lst[0].sg_len));
  2626. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2627. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2628. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2629. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2630. }
  2631. if (ha->cmd_len & 3)
  2632. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2633. if (ha->cmd_cnt > 0) {
  2634. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2635. ha->ic_all_size) {
  2636. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2637. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2638. return 0;
  2639. }
  2640. }
  2641. /* copy command */
  2642. gdth_copy_command(hanum);
  2643. return cmd_index;
  2644. }
  2645. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2646. {
  2647. register gdth_ha_str *ha;
  2648. register gdth_cmd_str *cmdp;
  2649. struct scatterlist *sl;
  2650. ushort i;
  2651. dma_addr_t phys_addr, sense_paddr;
  2652. int cmd_index, sgcnt, mode64;
  2653. unchar t,l;
  2654. struct page *page;
  2655. ulong offset;
  2656. ha = HADATA(gdth_ctr_tab[hanum]);
  2657. t = scp->device->id;
  2658. l = scp->device->lun;
  2659. cmdp = ha->pccb;
  2660. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2661. scp->cmnd[0],b,t,l));
  2662. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2663. return 0;
  2664. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2665. cmdp->Service = SCSIRAWSERVICE;
  2666. cmdp->RequestBuffer = scp;
  2667. /* search free command index */
  2668. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2669. TRACE(("GDT: No free command index found\n"));
  2670. return 0;
  2671. }
  2672. /* if it's the first command, set command semaphore */
  2673. if (ha->cmd_cnt == 0)
  2674. gdth_set_sema0(hanum);
  2675. /* fill command */
  2676. if (scp->SCp.sent_command != -1) {
  2677. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2678. cmdp->BoardNode = LOCALBOARD;
  2679. if (mode64) {
  2680. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2681. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2682. cmdp->OpCode, cmdp->u.raw64.direction));
  2683. /* evaluate command size */
  2684. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2685. } else {
  2686. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2687. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2688. cmdp->OpCode, cmdp->u.raw.direction));
  2689. /* evaluate command size */
  2690. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2691. }
  2692. } else {
  2693. page = virt_to_page(scp->sense_buffer);
  2694. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2695. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2696. 16,PCI_DMA_FROMDEVICE);
  2697. scp->SCp.buffer = (struct scatterlist *)((ulong32)sense_paddr);
  2698. /* high part, if 64bit */
  2699. scp->host_scribble = (char *)(ulong32)((ulong64)sense_paddr >> 32);
  2700. cmdp->OpCode = GDT_WRITE; /* always */
  2701. cmdp->BoardNode = LOCALBOARD;
  2702. if (mode64) {
  2703. cmdp->u.raw64.reserved = 0;
  2704. cmdp->u.raw64.mdisc_time = 0;
  2705. cmdp->u.raw64.mcon_time = 0;
  2706. cmdp->u.raw64.clen = scp->cmd_len;
  2707. cmdp->u.raw64.target = t;
  2708. cmdp->u.raw64.lun = l;
  2709. cmdp->u.raw64.bus = b;
  2710. cmdp->u.raw64.priority = 0;
  2711. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2712. cmdp->u.raw64.sense_len = 16;
  2713. cmdp->u.raw64.sense_data = sense_paddr;
  2714. cmdp->u.raw64.direction =
  2715. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2716. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2717. } else {
  2718. cmdp->u.raw.reserved = 0;
  2719. cmdp->u.raw.mdisc_time = 0;
  2720. cmdp->u.raw.mcon_time = 0;
  2721. cmdp->u.raw.clen = scp->cmd_len;
  2722. cmdp->u.raw.target = t;
  2723. cmdp->u.raw.lun = l;
  2724. cmdp->u.raw.bus = b;
  2725. cmdp->u.raw.priority = 0;
  2726. cmdp->u.raw.link_p = 0;
  2727. cmdp->u.raw.sdlen = scp->request_bufflen;
  2728. cmdp->u.raw.sense_len = 16;
  2729. cmdp->u.raw.sense_data = sense_paddr;
  2730. cmdp->u.raw.direction =
  2731. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2732. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2733. }
  2734. if (scp->use_sg) {
  2735. sl = (struct scatterlist *)scp->request_buffer;
  2736. sgcnt = scp->use_sg;
  2737. scp->SCp.Status = GDTH_MAP_SG;
  2738. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2739. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2740. if (mode64) {
  2741. cmdp->u.raw64.sdata = (ulong64)-1;
  2742. cmdp->u.raw64.sg_ranz = sgcnt;
  2743. for (i=0; i<sgcnt; ++i,++sl) {
  2744. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2745. #ifdef GDTH_DMA_STATISTICS
  2746. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2747. ha->dma64_cnt++;
  2748. else
  2749. ha->dma32_cnt++;
  2750. #endif
  2751. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2752. }
  2753. } else {
  2754. cmdp->u.raw.sdata = 0xffffffff;
  2755. cmdp->u.raw.sg_ranz = sgcnt;
  2756. for (i=0; i<sgcnt; ++i,++sl) {
  2757. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2758. #ifdef GDTH_DMA_STATISTICS
  2759. ha->dma32_cnt++;
  2760. #endif
  2761. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2762. }
  2763. }
  2764. #ifdef GDTH_STATISTICS
  2765. if (max_sg < sgcnt) {
  2766. max_sg = sgcnt;
  2767. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2768. }
  2769. #endif
  2770. } else {
  2771. scp->SCp.Status = GDTH_MAP_SINGLE;
  2772. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2773. page = virt_to_page(scp->request_buffer);
  2774. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2775. phys_addr = pci_map_page(ha->pdev,page,offset,
  2776. scp->request_bufflen,scp->SCp.Message);
  2777. scp->SCp.dma_handle = phys_addr;
  2778. if (mode64) {
  2779. if (ha->raw_feat & SCATTER_GATHER) {
  2780. cmdp->u.raw64.sdata = (ulong64)-1;
  2781. cmdp->u.raw64.sg_ranz= 1;
  2782. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2783. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2784. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2785. } else {
  2786. cmdp->u.raw64.sdata = phys_addr;
  2787. cmdp->u.raw64.sg_ranz= 0;
  2788. }
  2789. } else {
  2790. if (ha->raw_feat & SCATTER_GATHER) {
  2791. cmdp->u.raw.sdata = 0xffffffff;
  2792. cmdp->u.raw.sg_ranz= 1;
  2793. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2794. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2795. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2796. } else {
  2797. cmdp->u.raw.sdata = phys_addr;
  2798. cmdp->u.raw.sg_ranz= 0;
  2799. }
  2800. }
  2801. }
  2802. if (mode64) {
  2803. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2804. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2805. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2806. cmdp->u.raw64.sg_lst[0].sg_len));
  2807. /* evaluate command size */
  2808. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2809. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2810. } else {
  2811. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2812. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2813. cmdp->u.raw.sg_lst[0].sg_ptr,
  2814. cmdp->u.raw.sg_lst[0].sg_len));
  2815. /* evaluate command size */
  2816. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2817. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2818. }
  2819. }
  2820. /* check space */
  2821. if (ha->cmd_len & 3)
  2822. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2823. if (ha->cmd_cnt > 0) {
  2824. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2825. ha->ic_all_size) {
  2826. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2827. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2828. return 0;
  2829. }
  2830. }
  2831. /* copy command */
  2832. gdth_copy_command(hanum);
  2833. return cmd_index;
  2834. }
  2835. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2836. {
  2837. register gdth_ha_str *ha;
  2838. register gdth_cmd_str *cmdp;
  2839. int cmd_index;
  2840. ha = HADATA(gdth_ctr_tab[hanum]);
  2841. cmdp= ha->pccb;
  2842. TRACE2(("gdth_special_cmd(): "));
  2843. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2844. return 0;
  2845. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2846. cmdp->RequestBuffer = scp;
  2847. /* search free command index */
  2848. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2849. TRACE(("GDT: No free command index found\n"));
  2850. return 0;
  2851. }
  2852. /* if it's the first command, set command semaphore */
  2853. if (ha->cmd_cnt == 0)
  2854. gdth_set_sema0(hanum);
  2855. /* evaluate command size, check space */
  2856. if (cmdp->OpCode == GDT_IOCTL) {
  2857. TRACE2(("IOCTL\n"));
  2858. ha->cmd_len =
  2859. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2860. } else if (cmdp->Service == CACHESERVICE) {
  2861. TRACE2(("cache command %d\n",cmdp->OpCode));
  2862. if (ha->cache_feat & GDT_64BIT)
  2863. ha->cmd_len =
  2864. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2865. else
  2866. ha->cmd_len =
  2867. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2868. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2869. TRACE2(("raw command %d\n",cmdp->OpCode));
  2870. if (ha->raw_feat & GDT_64BIT)
  2871. ha->cmd_len =
  2872. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2873. else
  2874. ha->cmd_len =
  2875. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2876. }
  2877. if (ha->cmd_len & 3)
  2878. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2879. if (ha->cmd_cnt > 0) {
  2880. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2881. ha->ic_all_size) {
  2882. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2883. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2884. return 0;
  2885. }
  2886. }
  2887. /* copy command */
  2888. gdth_copy_command(hanum);
  2889. return cmd_index;
  2890. }
  2891. /* Controller event handling functions */
  2892. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  2893. ushort idx, gdth_evt_data *evt)
  2894. {
  2895. gdth_evt_str *e;
  2896. struct timeval tv;
  2897. /* no GDTH_LOCK_HA() ! */
  2898. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  2899. if (source == 0) /* no source -> no event */
  2900. return NULL;
  2901. if (ebuffer[elastidx].event_source == source &&
  2902. ebuffer[elastidx].event_idx == idx &&
  2903. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  2904. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  2905. (char *)&evt->eu, evt->size)) ||
  2906. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  2907. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  2908. (char *)&evt->event_string)))) {
  2909. e = &ebuffer[elastidx];
  2910. do_gettimeofday(&tv);
  2911. e->last_stamp = tv.tv_sec;
  2912. ++e->same_count;
  2913. } else {
  2914. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  2915. ++elastidx;
  2916. if (elastidx == MAX_EVENTS)
  2917. elastidx = 0;
  2918. if (elastidx == eoldidx) { /* reached mark ? */
  2919. ++eoldidx;
  2920. if (eoldidx == MAX_EVENTS)
  2921. eoldidx = 0;
  2922. }
  2923. }
  2924. e = &ebuffer[elastidx];
  2925. e->event_source = source;
  2926. e->event_idx = idx;
  2927. do_gettimeofday(&tv);
  2928. e->first_stamp = e->last_stamp = tv.tv_sec;
  2929. e->same_count = 1;
  2930. e->event_data = *evt;
  2931. e->application = 0;
  2932. }
  2933. return e;
  2934. }
  2935. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  2936. {
  2937. gdth_evt_str *e;
  2938. int eindex;
  2939. ulong flags;
  2940. TRACE2(("gdth_read_event() handle %d\n", handle));
  2941. spin_lock_irqsave(&ha->smp_lock, flags);
  2942. if (handle == -1)
  2943. eindex = eoldidx;
  2944. else
  2945. eindex = handle;
  2946. estr->event_source = 0;
  2947. if (eindex >= MAX_EVENTS) {
  2948. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2949. return eindex;
  2950. }
  2951. e = &ebuffer[eindex];
  2952. if (e->event_source != 0) {
  2953. if (eindex != elastidx) {
  2954. if (++eindex == MAX_EVENTS)
  2955. eindex = 0;
  2956. } else {
  2957. eindex = -1;
  2958. }
  2959. memcpy(estr, e, sizeof(gdth_evt_str));
  2960. }
  2961. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2962. return eindex;
  2963. }
  2964. static void gdth_readapp_event(gdth_ha_str *ha,
  2965. unchar application, gdth_evt_str *estr)
  2966. {
  2967. gdth_evt_str *e;
  2968. int eindex;
  2969. ulong flags;
  2970. unchar found = FALSE;
  2971. TRACE2(("gdth_readapp_event() app. %d\n", application));
  2972. spin_lock_irqsave(&ha->smp_lock, flags);
  2973. eindex = eoldidx;
  2974. for (;;) {
  2975. e = &ebuffer[eindex];
  2976. if (e->event_source == 0)
  2977. break;
  2978. if ((e->application & application) == 0) {
  2979. e->application |= application;
  2980. found = TRUE;
  2981. break;
  2982. }
  2983. if (eindex == elastidx)
  2984. break;
  2985. if (++eindex == MAX_EVENTS)
  2986. eindex = 0;
  2987. }
  2988. if (found)
  2989. memcpy(estr, e, sizeof(gdth_evt_str));
  2990. else
  2991. estr->event_source = 0;
  2992. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2993. }
  2994. static void gdth_clear_events(void)
  2995. {
  2996. TRACE(("gdth_clear_events()"));
  2997. eoldidx = elastidx = 0;
  2998. ebuffer[0].event_source = 0;
  2999. }
  3000. /* SCSI interface functions */
  3001. static irqreturn_t gdth_interrupt(int irq,void *dev_id,struct pt_regs *regs)
  3002. {
  3003. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3004. register gdth_ha_str *ha;
  3005. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3006. gdt6_dpram_str __iomem *dp6_ptr;
  3007. gdt2_dpram_str __iomem *dp2_ptr;
  3008. Scsi_Cmnd *scp;
  3009. int hanum, rval, i;
  3010. unchar IStatus;
  3011. ushort Service;
  3012. ulong flags = 0;
  3013. #ifdef INT_COAL
  3014. int coalesced = FALSE;
  3015. int next = FALSE;
  3016. gdth_coal_status *pcs = NULL;
  3017. int act_int_coal = 0;
  3018. #endif
  3019. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3020. /* if polling and not from gdth_wait() -> return */
  3021. if (gdth_polling) {
  3022. if (!gdth_from_wait) {
  3023. return IRQ_HANDLED;
  3024. }
  3025. }
  3026. if (!gdth_polling)
  3027. spin_lock_irqsave(&ha2->smp_lock, flags);
  3028. wait_index = 0;
  3029. /* search controller */
  3030. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3031. /* spurious interrupt */
  3032. if (!gdth_polling)
  3033. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3034. return IRQ_HANDLED;
  3035. }
  3036. ha = HADATA(gdth_ctr_tab[hanum]);
  3037. #ifdef GDTH_STATISTICS
  3038. ++act_ints;
  3039. #endif
  3040. #ifdef INT_COAL
  3041. /* See if the fw is returning coalesced status */
  3042. if (IStatus == COALINDEX) {
  3043. /* Coalesced status. Setup the initial status
  3044. buffer pointer and flags */
  3045. pcs = ha->coal_stat;
  3046. coalesced = TRUE;
  3047. next = TRUE;
  3048. }
  3049. do {
  3050. if (coalesced) {
  3051. /* For coalesced requests all status
  3052. information is found in the status buffer */
  3053. IStatus = (unchar)(pcs->status & 0xff);
  3054. }
  3055. #endif
  3056. if (ha->type == GDT_EISA) {
  3057. if (IStatus & 0x80) { /* error flag */
  3058. IStatus &= ~0x80;
  3059. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3060. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3061. } else /* no error */
  3062. ha->status = S_OK;
  3063. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3064. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3065. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3066. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3067. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3068. } else if (ha->type == GDT_ISA) {
  3069. dp2_ptr = ha->brd;
  3070. if (IStatus & 0x80) { /* error flag */
  3071. IStatus &= ~0x80;
  3072. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3073. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3074. } else /* no error */
  3075. ha->status = S_OK;
  3076. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3077. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3078. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3079. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3080. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3081. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3082. } else if (ha->type == GDT_PCI) {
  3083. dp6_ptr = ha->brd;
  3084. if (IStatus & 0x80) { /* error flag */
  3085. IStatus &= ~0x80;
  3086. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3087. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3088. } else /* no error */
  3089. ha->status = S_OK;
  3090. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3091. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3092. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3093. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3094. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3095. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3096. } else if (ha->type == GDT_PCINEW) {
  3097. if (IStatus & 0x80) { /* error flag */
  3098. IStatus &= ~0x80;
  3099. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3100. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3101. } else
  3102. ha->status = S_OK;
  3103. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3104. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3105. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3106. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3107. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3108. } else if (ha->type == GDT_PCIMPR) {
  3109. dp6m_ptr = ha->brd;
  3110. if (IStatus & 0x80) { /* error flag */
  3111. IStatus &= ~0x80;
  3112. #ifdef INT_COAL
  3113. if (coalesced)
  3114. ha->status = pcs->ext_status && 0xffff;
  3115. else
  3116. #endif
  3117. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3118. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3119. } else /* no error */
  3120. ha->status = S_OK;
  3121. #ifdef INT_COAL
  3122. /* get information */
  3123. if (coalesced) {
  3124. ha->info = pcs->info0;
  3125. ha->info2 = pcs->info1;
  3126. ha->service = (pcs->ext_status >> 16) && 0xffff;
  3127. } else
  3128. #endif
  3129. {
  3130. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3131. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3132. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3133. }
  3134. /* event string */
  3135. if (IStatus == ASYNCINDEX) {
  3136. if (ha->service != SCREENSERVICE &&
  3137. (ha->fw_vers & 0xff) >= 0x1a) {
  3138. ha->dvr.severity = gdth_readb
  3139. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3140. for (i = 0; i < 256; ++i) {
  3141. ha->dvr.event_string[i] = gdth_readb
  3142. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3143. if (ha->dvr.event_string[i] == 0)
  3144. break;
  3145. }
  3146. }
  3147. }
  3148. #ifdef INT_COAL
  3149. /* Make sure that non coalesced interrupts get cleared
  3150. before being handled by gdth_async_event/gdth_sync_event */
  3151. if (!coalesced)
  3152. #endif
  3153. {
  3154. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3155. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3156. }
  3157. } else {
  3158. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3159. if (!gdth_polling)
  3160. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3161. return IRQ_HANDLED;
  3162. }
  3163. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3164. IStatus,ha->status,ha->info));
  3165. if (gdth_from_wait) {
  3166. wait_hanum = hanum;
  3167. wait_index = (int)IStatus;
  3168. }
  3169. if (IStatus == ASYNCINDEX) {
  3170. TRACE2(("gdth_interrupt() async. event\n"));
  3171. gdth_async_event(hanum);
  3172. if (!gdth_polling)
  3173. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3174. gdth_next(hanum);
  3175. return IRQ_HANDLED;
  3176. }
  3177. if (IStatus == SPEZINDEX) {
  3178. TRACE2(("Service unknown or not initialized !\n"));
  3179. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3180. ha->dvr.eu.driver.ionode = hanum;
  3181. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3182. if (!gdth_polling)
  3183. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3184. return IRQ_HANDLED;
  3185. }
  3186. scp = ha->cmd_tab[IStatus-2].cmnd;
  3187. Service = ha->cmd_tab[IStatus-2].service;
  3188. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3189. if (scp == UNUSED_CMND) {
  3190. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3191. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3192. ha->dvr.eu.driver.ionode = hanum;
  3193. ha->dvr.eu.driver.index = IStatus;
  3194. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3195. if (!gdth_polling)
  3196. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3197. return IRQ_HANDLED;
  3198. }
  3199. if (scp == INTERNAL_CMND) {
  3200. TRACE(("gdth_interrupt() answer to internal command\n"));
  3201. if (!gdth_polling)
  3202. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3203. return IRQ_HANDLED;
  3204. }
  3205. TRACE(("gdth_interrupt() sync. status\n"));
  3206. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3207. if (!gdth_polling)
  3208. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3209. if (rval == 2) {
  3210. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3211. } else if (rval == 1) {
  3212. scp->scsi_done(scp);
  3213. }
  3214. #ifdef INT_COAL
  3215. if (coalesced) {
  3216. /* go to the next status in the status buffer */
  3217. ++pcs;
  3218. #ifdef GDTH_STATISTICS
  3219. ++act_int_coal;
  3220. if (act_int_coal > max_int_coal) {
  3221. max_int_coal = act_int_coal;
  3222. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3223. }
  3224. #endif
  3225. /* see if there is another status */
  3226. if (pcs->status == 0)
  3227. /* Stop the coalesce loop */
  3228. next = FALSE;
  3229. }
  3230. } while (next);
  3231. /* coalescing only for new GDT_PCIMPR controllers available */
  3232. if (ha->type == GDT_PCIMPR && coalesced) {
  3233. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3234. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3235. }
  3236. #endif
  3237. gdth_next(hanum);
  3238. return IRQ_HANDLED;
  3239. }
  3240. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3241. {
  3242. register gdth_ha_str *ha;
  3243. gdth_msg_str *msg;
  3244. gdth_cmd_str *cmdp;
  3245. unchar b, t;
  3246. ha = HADATA(gdth_ctr_tab[hanum]);
  3247. cmdp = ha->pccb;
  3248. TRACE(("gdth_sync_event() serv %d status %d\n",
  3249. service,ha->status));
  3250. if (service == SCREENSERVICE) {
  3251. msg = ha->pmsg;
  3252. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3253. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3254. if (msg->msg_len > MSGLEN+1)
  3255. msg->msg_len = MSGLEN+1;
  3256. if (msg->msg_len)
  3257. if (!(msg->msg_answer && msg->msg_ext)) {
  3258. msg->msg_text[msg->msg_len] = '\0';
  3259. printk("%s",msg->msg_text);
  3260. }
  3261. if (msg->msg_ext && !msg->msg_answer) {
  3262. while (gdth_test_busy(hanum))
  3263. gdth_delay(0);
  3264. cmdp->Service = SCREENSERVICE;
  3265. cmdp->RequestBuffer = SCREEN_CMND;
  3266. gdth_get_cmd_index(hanum);
  3267. gdth_set_sema0(hanum);
  3268. cmdp->OpCode = GDT_READ;
  3269. cmdp->BoardNode = LOCALBOARD;
  3270. cmdp->u.screen.reserved = 0;
  3271. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3272. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3273. ha->cmd_offs_dpmem = 0;
  3274. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3275. + sizeof(ulong64);
  3276. ha->cmd_cnt = 0;
  3277. gdth_copy_command(hanum);
  3278. gdth_release_event(hanum);
  3279. return 0;
  3280. }
  3281. if (msg->msg_answer && msg->msg_alen) {
  3282. /* default answers (getchar() not possible) */
  3283. if (msg->msg_alen == 1) {
  3284. msg->msg_alen = 0;
  3285. msg->msg_len = 1;
  3286. msg->msg_text[0] = 0;
  3287. } else {
  3288. msg->msg_alen -= 2;
  3289. msg->msg_len = 2;
  3290. msg->msg_text[0] = 1;
  3291. msg->msg_text[1] = 0;
  3292. }
  3293. msg->msg_ext = 0;
  3294. msg->msg_answer = 0;
  3295. while (gdth_test_busy(hanum))
  3296. gdth_delay(0);
  3297. cmdp->Service = SCREENSERVICE;
  3298. cmdp->RequestBuffer = SCREEN_CMND;
  3299. gdth_get_cmd_index(hanum);
  3300. gdth_set_sema0(hanum);
  3301. cmdp->OpCode = GDT_WRITE;
  3302. cmdp->BoardNode = LOCALBOARD;
  3303. cmdp->u.screen.reserved = 0;
  3304. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3305. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3306. ha->cmd_offs_dpmem = 0;
  3307. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3308. + sizeof(ulong64);
  3309. ha->cmd_cnt = 0;
  3310. gdth_copy_command(hanum);
  3311. gdth_release_event(hanum);
  3312. return 0;
  3313. }
  3314. printk("\n");
  3315. } else {
  3316. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3317. t = scp->device->id;
  3318. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3319. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3320. }
  3321. /* cache or raw service */
  3322. if (ha->status == S_BSY) {
  3323. TRACE2(("Controller busy -> retry !\n"));
  3324. if (scp->SCp.sent_command == GDT_MOUNT)
  3325. scp->SCp.sent_command = GDT_CLUST_INFO;
  3326. /* retry */
  3327. return 2;
  3328. }
  3329. if (scp->SCp.Status == GDTH_MAP_SG)
  3330. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3331. scp->use_sg,scp->SCp.Message);
  3332. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3333. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3334. scp->request_bufflen,scp->SCp.Message);
  3335. if (scp->SCp.buffer) {
  3336. dma_addr_t addr;
  3337. addr = (dma_addr_t)(ulong32)scp->SCp.buffer;
  3338. if (scp->host_scribble)
  3339. addr += (dma_addr_t)((ulong64)(ulong32)scp->host_scribble << 32);
  3340. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3341. }
  3342. if (ha->status == S_OK) {
  3343. scp->SCp.Status = S_OK;
  3344. scp->SCp.Message = ha->info;
  3345. if (scp->SCp.sent_command != -1) {
  3346. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3347. scp->SCp.sent_command));
  3348. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3349. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3350. ha->hdr[t].cluster_type = (unchar)ha->info;
  3351. if (!(ha->hdr[t].cluster_type &
  3352. CLUSTER_MOUNTED)) {
  3353. /* NOT MOUNTED -> MOUNT */
  3354. scp->SCp.sent_command = GDT_MOUNT;
  3355. if (ha->hdr[t].cluster_type &
  3356. CLUSTER_RESERVED) {
  3357. /* cluster drive RESERVED (on the other node) */
  3358. scp->SCp.phase = -2; /* reservation conflict */
  3359. }
  3360. } else {
  3361. scp->SCp.sent_command = -1;
  3362. }
  3363. } else {
  3364. if (scp->SCp.sent_command == GDT_MOUNT) {
  3365. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3366. ha->hdr[t].media_changed = TRUE;
  3367. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3368. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3369. ha->hdr[t].media_changed = TRUE;
  3370. }
  3371. scp->SCp.sent_command = -1;
  3372. }
  3373. /* retry */
  3374. scp->SCp.this_residual = HIGH_PRI;
  3375. return 2;
  3376. } else {
  3377. /* RESERVE/RELEASE ? */
  3378. if (scp->cmnd[0] == RESERVE) {
  3379. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3380. } else if (scp->cmnd[0] == RELEASE) {
  3381. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3382. }
  3383. scp->result = DID_OK << 16;
  3384. scp->sense_buffer[0] = 0;
  3385. }
  3386. } else {
  3387. scp->SCp.Status = ha->status;
  3388. scp->SCp.Message = ha->info;
  3389. if (scp->SCp.sent_command != -1) {
  3390. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3391. scp->SCp.sent_command, ha->status));
  3392. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3393. scp->SCp.sent_command == GDT_SCAN_END) {
  3394. scp->SCp.sent_command = -1;
  3395. /* retry */
  3396. scp->SCp.this_residual = HIGH_PRI;
  3397. return 2;
  3398. }
  3399. memset((char*)scp->sense_buffer,0,16);
  3400. scp->sense_buffer[0] = 0x70;
  3401. scp->sense_buffer[2] = NOT_READY;
  3402. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3403. } else if (service == CACHESERVICE) {
  3404. if (ha->status == S_CACHE_UNKNOWN &&
  3405. (ha->hdr[t].cluster_type &
  3406. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3407. /* bus reset -> force GDT_CLUST_INFO */
  3408. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3409. }
  3410. memset((char*)scp->sense_buffer,0,16);
  3411. if (ha->status == (ushort)S_CACHE_RESERV) {
  3412. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3413. } else {
  3414. scp->sense_buffer[0] = 0x70;
  3415. scp->sense_buffer[2] = NOT_READY;
  3416. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3417. }
  3418. if (scp->done != gdth_scsi_done) {
  3419. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3420. ha->dvr.eu.sync.ionode = hanum;
  3421. ha->dvr.eu.sync.service = service;
  3422. ha->dvr.eu.sync.status = ha->status;
  3423. ha->dvr.eu.sync.info = ha->info;
  3424. ha->dvr.eu.sync.hostdrive = t;
  3425. if (ha->status >= 0x8000)
  3426. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3427. else
  3428. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3429. }
  3430. } else {
  3431. /* sense buffer filled from controller firmware (DMA) */
  3432. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3433. scp->result = DID_BAD_TARGET << 16;
  3434. } else {
  3435. scp->result = (DID_OK << 16) | ha->info;
  3436. }
  3437. }
  3438. }
  3439. if (!scp->SCp.have_data_in)
  3440. scp->SCp.have_data_in++;
  3441. else
  3442. return 1;
  3443. }
  3444. return 0;
  3445. }
  3446. static char *async_cache_tab[] = {
  3447. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3448. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3449. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3450. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3451. /* 2*/ "\005\000\002\006\004"
  3452. "GDT HA %u, Host Drive %lu not ready",
  3453. /* 3*/ "\005\000\002\006\004"
  3454. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3455. /* 4*/ "\005\000\002\006\004"
  3456. "GDT HA %u, mirror update on Host Drive %lu failed",
  3457. /* 5*/ "\005\000\002\006\004"
  3458. "GDT HA %u, Mirror Drive %lu failed",
  3459. /* 6*/ "\005\000\002\006\004"
  3460. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3461. /* 7*/ "\005\000\002\006\004"
  3462. "GDT HA %u, Host Drive %lu write protected",
  3463. /* 8*/ "\005\000\002\006\004"
  3464. "GDT HA %u, media changed in Host Drive %lu",
  3465. /* 9*/ "\005\000\002\006\004"
  3466. "GDT HA %u, Host Drive %lu is offline",
  3467. /*10*/ "\005\000\002\006\004"
  3468. "GDT HA %u, media change of Mirror Drive %lu",
  3469. /*11*/ "\005\000\002\006\004"
  3470. "GDT HA %u, Mirror Drive %lu is write protected",
  3471. /*12*/ "\005\000\002\006\004"
  3472. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3473. /*13*/ "\007\000\002\006\002\010\002"
  3474. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3475. /*14*/ "\005\000\002\006\002"
  3476. "GDT HA %u, Array Drive %u: FAIL state entered",
  3477. /*15*/ "\005\000\002\006\002"
  3478. "GDT HA %u, Array Drive %u: error",
  3479. /*16*/ "\007\000\002\006\002\010\002"
  3480. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3481. /*17*/ "\005\000\002\006\002"
  3482. "GDT HA %u, Array Drive %u: parity build failed",
  3483. /*18*/ "\005\000\002\006\002"
  3484. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3485. /*19*/ "\005\000\002\010\002"
  3486. "GDT HA %u, Test of Hot Fix %u failed",
  3487. /*20*/ "\005\000\002\006\002"
  3488. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3489. /*21*/ "\005\000\002\006\002"
  3490. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3491. /*22*/ "\007\000\002\006\002\010\002"
  3492. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3493. /*23*/ "\005\000\002\006\002"
  3494. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3495. /*24*/ "\005\000\002\010\002"
  3496. "GDT HA %u, mirror update on Cache Drive %u completed",
  3497. /*25*/ "\005\000\002\010\002"
  3498. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3499. /*26*/ "\005\000\002\006\002"
  3500. "GDT HA %u, Array Drive %u: drive rebuild started",
  3501. /*27*/ "\005\000\002\012\001"
  3502. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3503. /*28*/ "\005\000\002\012\001"
  3504. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3505. /*29*/ "\007\000\002\012\001\013\001"
  3506. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3507. /*30*/ "\007\000\002\012\001\013\001"
  3508. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3509. /*31*/ "\007\000\002\012\001\013\001"
  3510. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3511. /*32*/ "\007\000\002\012\001\013\001"
  3512. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3513. /*33*/ "\007\000\002\012\001\013\001"
  3514. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3515. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3516. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3517. /*35*/ "\007\000\002\012\001\013\001"
  3518. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3519. /*36*/ "\007\000\002\012\001\013\001"
  3520. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3521. /*37*/ "\007\000\002\012\001\006\004"
  3522. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3523. /*38*/ "\007\000\002\012\001\013\001"
  3524. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3525. /*39*/ "\007\000\002\012\001\013\001"
  3526. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3527. /*40*/ "\007\000\002\012\001\013\001"
  3528. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3529. /*41*/ "\007\000\002\012\001\013\001"
  3530. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3531. /*42*/ "\005\000\002\006\002"
  3532. "GDT HA %u, Array Drive %u: drive build started",
  3533. /*43*/ "\003\000\002"
  3534. "GDT HA %u, DRAM parity error detected",
  3535. /*44*/ "\005\000\002\006\002"
  3536. "GDT HA %u, Mirror Drive %u: update started",
  3537. /*45*/ "\007\000\002\006\002\010\002"
  3538. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3539. /*46*/ "\005\000\002\006\002"
  3540. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3541. /*47*/ "\005\000\002\006\002"
  3542. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3543. /*48*/ "\005\000\002\006\002"
  3544. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3545. /*49*/ "\005\000\002\006\002"
  3546. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3547. /*50*/ "\007\000\002\012\001\013\001"
  3548. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3549. /*51*/ "\005\000\002\006\002"
  3550. "GDT HA %u, Array Drive %u: expand started",
  3551. /*52*/ "\005\000\002\006\002"
  3552. "GDT HA %u, Array Drive %u: expand finished successfully",
  3553. /*53*/ "\005\000\002\006\002"
  3554. "GDT HA %u, Array Drive %u: expand failed",
  3555. /*54*/ "\003\000\002"
  3556. "GDT HA %u, CPU temperature critical",
  3557. /*55*/ "\003\000\002"
  3558. "GDT HA %u, CPU temperature OK",
  3559. /*56*/ "\005\000\002\006\004"
  3560. "GDT HA %u, Host drive %lu created",
  3561. /*57*/ "\005\000\002\006\002"
  3562. "GDT HA %u, Array Drive %u: expand restarted",
  3563. /*58*/ "\005\000\002\006\002"
  3564. "GDT HA %u, Array Drive %u: expand stopped",
  3565. /*59*/ "\005\000\002\010\002"
  3566. "GDT HA %u, Mirror Drive %u: drive build quited",
  3567. /*60*/ "\005\000\002\006\002"
  3568. "GDT HA %u, Array Drive %u: parity build quited",
  3569. /*61*/ "\005\000\002\006\002"
  3570. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3571. /*62*/ "\005\000\002\006\002"
  3572. "GDT HA %u, Array Drive %u: parity verify started",
  3573. /*63*/ "\005\000\002\006\002"
  3574. "GDT HA %u, Array Drive %u: parity verify done",
  3575. /*64*/ "\005\000\002\006\002"
  3576. "GDT HA %u, Array Drive %u: parity verify failed",
  3577. /*65*/ "\005\000\002\006\002"
  3578. "GDT HA %u, Array Drive %u: parity error detected",
  3579. /*66*/ "\005\000\002\006\002"
  3580. "GDT HA %u, Array Drive %u: parity verify quited",
  3581. /*67*/ "\005\000\002\006\002"
  3582. "GDT HA %u, Host Drive %u reserved",
  3583. /*68*/ "\005\000\002\006\002"
  3584. "GDT HA %u, Host Drive %u mounted and released",
  3585. /*69*/ "\005\000\002\006\002"
  3586. "GDT HA %u, Host Drive %u released",
  3587. /*70*/ "\003\000\002"
  3588. "GDT HA %u, DRAM error detected and corrected with ECC",
  3589. /*71*/ "\003\000\002"
  3590. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3591. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3592. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3593. /*73*/ "\005\000\002\006\002"
  3594. "GDT HA %u, Host drive %u resetted locally",
  3595. /*74*/ "\005\000\002\006\002"
  3596. "GDT HA %u, Host drive %u resetted remotely",
  3597. /*75*/ "\003\000\002"
  3598. "GDT HA %u, async. status 75 unknown",
  3599. };
  3600. static int gdth_async_event(int hanum)
  3601. {
  3602. gdth_ha_str *ha;
  3603. gdth_cmd_str *cmdp;
  3604. int cmd_index;
  3605. ha = HADATA(gdth_ctr_tab[hanum]);
  3606. cmdp= ha->pccb;
  3607. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3608. hanum,ha->service));
  3609. if (ha->service == SCREENSERVICE) {
  3610. if (ha->status == MSG_REQUEST) {
  3611. while (gdth_test_busy(hanum))
  3612. gdth_delay(0);
  3613. cmdp->Service = SCREENSERVICE;
  3614. cmdp->RequestBuffer = SCREEN_CMND;
  3615. cmd_index = gdth_get_cmd_index(hanum);
  3616. gdth_set_sema0(hanum);
  3617. cmdp->OpCode = GDT_READ;
  3618. cmdp->BoardNode = LOCALBOARD;
  3619. cmdp->u.screen.reserved = 0;
  3620. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3621. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3622. ha->cmd_offs_dpmem = 0;
  3623. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3624. + sizeof(ulong64);
  3625. ha->cmd_cnt = 0;
  3626. gdth_copy_command(hanum);
  3627. if (ha->type == GDT_EISA)
  3628. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3629. else if (ha->type == GDT_ISA)
  3630. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3631. else
  3632. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3633. (ushort)((ha->brd_phys>>3)&0x1f));
  3634. gdth_release_event(hanum);
  3635. }
  3636. } else {
  3637. if (ha->type == GDT_PCIMPR &&
  3638. (ha->fw_vers & 0xff) >= 0x1a) {
  3639. ha->dvr.size = 0;
  3640. ha->dvr.eu.async.ionode = hanum;
  3641. ha->dvr.eu.async.status = ha->status;
  3642. /* severity and event_string already set! */
  3643. } else {
  3644. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3645. ha->dvr.eu.async.ionode = hanum;
  3646. ha->dvr.eu.async.service = ha->service;
  3647. ha->dvr.eu.async.status = ha->status;
  3648. ha->dvr.eu.async.info = ha->info;
  3649. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3650. }
  3651. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3652. gdth_log_event( &ha->dvr, NULL );
  3653. /* new host drive from expand? */
  3654. if (ha->service == CACHESERVICE && ha->status == 56) {
  3655. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3656. (ushort)ha->info));
  3657. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3658. }
  3659. }
  3660. return 1;
  3661. }
  3662. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3663. {
  3664. gdth_stackframe stack;
  3665. char *f = NULL;
  3666. int i,j;
  3667. TRACE2(("gdth_log_event()\n"));
  3668. if (dvr->size == 0) {
  3669. if (buffer == NULL) {
  3670. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3671. } else {
  3672. sprintf(buffer,"Adapter %d: %s\n",
  3673. dvr->eu.async.ionode,dvr->event_string);
  3674. }
  3675. } else if (dvr->eu.async.service == CACHESERVICE &&
  3676. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3677. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3678. dvr->eu.async.status));
  3679. f = async_cache_tab[dvr->eu.async.status];
  3680. /* i: parameter to push, j: stack element to fill */
  3681. for (j=0,i=1; i < f[0]; i+=2) {
  3682. switch (f[i+1]) {
  3683. case 4:
  3684. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3685. break;
  3686. case 2:
  3687. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3688. break;
  3689. case 1:
  3690. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3691. break;
  3692. default:
  3693. break;
  3694. }
  3695. }
  3696. if (buffer == NULL) {
  3697. printk(&f[(int)f[0]],stack);
  3698. printk("\n");
  3699. } else {
  3700. sprintf(buffer,&f[(int)f[0]],stack);
  3701. }
  3702. } else {
  3703. if (buffer == NULL) {
  3704. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3705. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3706. } else {
  3707. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3708. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3709. }
  3710. }
  3711. }
  3712. #ifdef GDTH_STATISTICS
  3713. static void gdth_timeout(ulong data)
  3714. {
  3715. ulong32 i;
  3716. Scsi_Cmnd *nscp;
  3717. gdth_ha_str *ha;
  3718. ulong flags;
  3719. int hanum = 0;
  3720. ha = HADATA(gdth_ctr_tab[hanum]);
  3721. spin_lock_irqsave(&ha->smp_lock, flags);
  3722. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3723. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3724. ++act_stats;
  3725. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3726. ++act_rq;
  3727. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3728. act_ints, act_ios, act_stats, act_rq));
  3729. act_ints = act_ios = 0;
  3730. gdth_timer.expires = jiffies + 30 * HZ;
  3731. add_timer(&gdth_timer);
  3732. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3733. }
  3734. #endif
  3735. static void __init internal_setup(char *str,int *ints)
  3736. {
  3737. int i, argc;
  3738. char *cur_str, *argv;
  3739. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3740. str ? str:"NULL", ints ? ints[0]:0));
  3741. /* read irq[] from ints[] */
  3742. if (ints) {
  3743. argc = ints[0];
  3744. if (argc > 0) {
  3745. if (argc > MAXHA)
  3746. argc = MAXHA;
  3747. for (i = 0; i < argc; ++i)
  3748. irq[i] = ints[i+1];
  3749. }
  3750. }
  3751. /* analyse string */
  3752. argv = str;
  3753. while (argv && (cur_str = strchr(argv, ':'))) {
  3754. int val = 0, c = *++cur_str;
  3755. if (c == 'n' || c == 'N')
  3756. val = 0;
  3757. else if (c == 'y' || c == 'Y')
  3758. val = 1;
  3759. else
  3760. val = (int)simple_strtoul(cur_str, NULL, 0);
  3761. if (!strncmp(argv, "disable:", 8))
  3762. disable = val;
  3763. else if (!strncmp(argv, "reserve_mode:", 13))
  3764. reserve_mode = val;
  3765. else if (!strncmp(argv, "reverse_scan:", 13))
  3766. reverse_scan = val;
  3767. else if (!strncmp(argv, "hdr_channel:", 12))
  3768. hdr_channel = val;
  3769. else if (!strncmp(argv, "max_ids:", 8))
  3770. max_ids = val;
  3771. else if (!strncmp(argv, "rescan:", 7))
  3772. rescan = val;
  3773. else if (!strncmp(argv, "virt_ctr:", 9))
  3774. virt_ctr = val;
  3775. else if (!strncmp(argv, "shared_access:", 14))
  3776. shared_access = val;
  3777. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3778. probe_eisa_isa = val;
  3779. else if (!strncmp(argv, "reserve_list:", 13)) {
  3780. reserve_list[0] = val;
  3781. for (i = 1; i < MAX_RES_ARGS; i++) {
  3782. cur_str = strchr(cur_str, ',');
  3783. if (!cur_str)
  3784. break;
  3785. if (!isdigit((int)*++cur_str)) {
  3786. --cur_str;
  3787. break;
  3788. }
  3789. reserve_list[i] =
  3790. (int)simple_strtoul(cur_str, NULL, 0);
  3791. }
  3792. if (!cur_str)
  3793. break;
  3794. argv = ++cur_str;
  3795. continue;
  3796. }
  3797. if ((argv = strchr(argv, ',')))
  3798. ++argv;
  3799. }
  3800. }
  3801. int __init option_setup(char *str)
  3802. {
  3803. int ints[MAXHA];
  3804. char *cur = str;
  3805. int i = 1;
  3806. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3807. while (cur && isdigit(*cur) && i <= MAXHA) {
  3808. ints[i++] = simple_strtoul(cur, NULL, 0);
  3809. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3810. }
  3811. ints[0] = i - 1;
  3812. internal_setup(cur, ints);
  3813. return 1;
  3814. }
  3815. static int __init gdth_detect(struct scsi_host_template *shtp)
  3816. {
  3817. struct Scsi_Host *shp;
  3818. gdth_pci_str pcistr[MAXHA];
  3819. gdth_ha_str *ha;
  3820. ulong32 isa_bios;
  3821. ushort eisa_slot;
  3822. int i,hanum,cnt,ctr,err;
  3823. unchar b;
  3824. #ifdef DEBUG_GDTH
  3825. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3826. DebugState);
  3827. printk(" Destination of debugging information: ");
  3828. #ifdef __SERIAL__
  3829. #ifdef __COM2__
  3830. printk("Serial port COM2\n");
  3831. #else
  3832. printk("Serial port COM1\n");
  3833. #endif
  3834. #else
  3835. printk("Console\n");
  3836. #endif
  3837. gdth_delay(3000);
  3838. #endif
  3839. TRACE(("gdth_detect()\n"));
  3840. if (disable) {
  3841. printk("GDT-HA: Controller driver disabled from command line !\n");
  3842. return 0;
  3843. }
  3844. printk("GDT-HA: Storage RAID Controller Driver. Version: %s \n",GDTH_VERSION_STR);
  3845. /* initializations */
  3846. gdth_polling = TRUE; b = 0;
  3847. gdth_clear_events();
  3848. /* As default we do not probe for EISA or ISA controllers */
  3849. if (probe_eisa_isa) {
  3850. /* scanning for controllers, at first: ISA controller */
  3851. for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
  3852. dma_addr_t scratch_dma_handle;
  3853. scratch_dma_handle = 0;
  3854. if (gdth_ctr_count >= MAXHA)
  3855. break;
  3856. if (gdth_search_isa(isa_bios)) { /* controller found */
  3857. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3858. if (shp == NULL)
  3859. continue;
  3860. ha = HADATA(shp);
  3861. if (!gdth_init_isa(isa_bios,ha)) {
  3862. scsi_unregister(shp);
  3863. continue;
  3864. }
  3865. #ifdef __ia64__
  3866. break;
  3867. #else
  3868. /* controller found and initialized */
  3869. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  3870. isa_bios,ha->irq,ha->drq);
  3871. if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
  3872. printk("GDT-ISA: Unable to allocate IRQ\n");
  3873. scsi_unregister(shp);
  3874. continue;
  3875. }
  3876. if (request_dma(ha->drq,"gdth")) {
  3877. printk("GDT-ISA: Unable to allocate DMA channel\n");
  3878. free_irq(ha->irq,ha);
  3879. scsi_unregister(shp);
  3880. continue;
  3881. }
  3882. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  3883. enable_dma(ha->drq);
  3884. shp->unchecked_isa_dma = 1;
  3885. shp->irq = ha->irq;
  3886. shp->dma_channel = ha->drq;
  3887. hanum = gdth_ctr_count;
  3888. gdth_ctr_tab[gdth_ctr_count++] = shp;
  3889. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3890. NUMDATA(shp)->hanum = (ushort)hanum;
  3891. NUMDATA(shp)->busnum= 0;
  3892. ha->pccb = CMDDATA(shp);
  3893. ha->ccb_phys = 0L;
  3894. ha->pdev = NULL;
  3895. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  3896. &scratch_dma_handle);
  3897. ha->scratch_phys = scratch_dma_handle;
  3898. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  3899. &scratch_dma_handle);
  3900. ha->msg_phys = scratch_dma_handle;
  3901. #ifdef INT_COAL
  3902. ha->coal_stat = (gdth_coal_status *)
  3903. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3904. MAXOFFSETS, &scratch_dma_handle);
  3905. ha->coal_stat_phys = scratch_dma_handle;
  3906. #endif
  3907. ha->scratch_busy = FALSE;
  3908. ha->req_first = NULL;
  3909. ha->tid_cnt = MAX_HDRIVES;
  3910. if (max_ids > 0 && max_ids < ha->tid_cnt)
  3911. ha->tid_cnt = max_ids;
  3912. for (i=0; i<GDTH_MAXCMDS; ++i)
  3913. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  3914. ha->scan_mode = rescan ? 0x10 : 0;
  3915. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  3916. !gdth_search_drives(hanum)) {
  3917. printk("GDT-ISA: Error during device scan\n");
  3918. --gdth_ctr_count;
  3919. --gdth_ctr_vcount;
  3920. #ifdef INT_COAL
  3921. if (ha->coal_stat)
  3922. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  3923. MAXOFFSETS, ha->coal_stat,
  3924. ha->coal_stat_phys);
  3925. #endif
  3926. if (ha->pscratch)
  3927. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  3928. ha->pscratch, ha->scratch_phys);
  3929. if (ha->pmsg)
  3930. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  3931. ha->pmsg, ha->msg_phys);
  3932. free_irq(ha->irq,ha);
  3933. scsi_unregister(shp);
  3934. continue;
  3935. }
  3936. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  3937. hdr_channel = ha->bus_cnt;
  3938. ha->virt_bus = hdr_channel;
  3939. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  3940. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  3941. shp->highmem_io = 0;
  3942. #endif
  3943. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  3944. shp->max_cmd_len = 16;
  3945. shp->max_id = ha->tid_cnt;
  3946. shp->max_lun = MAXLUN;
  3947. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  3948. if (virt_ctr) {
  3949. virt_ctr = 1;
  3950. /* register addit. SCSI channels as virtual controllers */
  3951. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  3952. shp = scsi_register(shtp,sizeof(gdth_num_str));
  3953. shp->unchecked_isa_dma = 1;
  3954. shp->irq = ha->irq;
  3955. shp->dma_channel = ha->drq;
  3956. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3957. NUMDATA(shp)->hanum = (ushort)hanum;
  3958. NUMDATA(shp)->busnum = b;
  3959. }
  3960. }
  3961. spin_lock_init(&ha->smp_lock);
  3962. gdth_enable_int(hanum);
  3963. #endif /* !__ia64__ */
  3964. }
  3965. }
  3966. /* scanning for EISA controllers */
  3967. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  3968. dma_addr_t scratch_dma_handle;
  3969. scratch_dma_handle = 0;
  3970. if (gdth_ctr_count >= MAXHA)
  3971. break;
  3972. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  3973. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3974. if (shp == NULL)
  3975. continue;
  3976. ha = HADATA(shp);
  3977. if (!gdth_init_eisa(eisa_slot,ha)) {
  3978. scsi_unregister(shp);
  3979. continue;
  3980. }
  3981. /* controller found and initialized */
  3982. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  3983. eisa_slot>>12,ha->irq);
  3984. if (request_irq(ha->irq,gdth_interrupt,SA_INTERRUPT,"gdth",ha)) {
  3985. printk("GDT-EISA: Unable to allocate IRQ\n");
  3986. scsi_unregister(shp);
  3987. continue;
  3988. }
  3989. shp->unchecked_isa_dma = 0;
  3990. shp->irq = ha->irq;
  3991. shp->dma_channel = 0xff;
  3992. hanum = gdth_ctr_count;
  3993. gdth_ctr_tab[gdth_ctr_count++] = shp;
  3994. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  3995. NUMDATA(shp)->hanum = (ushort)hanum;
  3996. NUMDATA(shp)->busnum= 0;
  3997. TRACE2(("EISA detect Bus 0: hanum %d\n",
  3998. NUMDATA(shp)->hanum));
  3999. ha->pccb = CMDDATA(shp);
  4000. ha->ccb_phys = 0L;
  4001. ha->pdev = NULL;
  4002. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4003. &scratch_dma_handle);
  4004. ha->scratch_phys = scratch_dma_handle;
  4005. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4006. &scratch_dma_handle);
  4007. ha->msg_phys = scratch_dma_handle;
  4008. #ifdef INT_COAL
  4009. ha->coal_stat = (gdth_coal_status *)
  4010. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4011. MAXOFFSETS, &scratch_dma_handle);
  4012. ha->coal_stat_phys = scratch_dma_handle;
  4013. #endif
  4014. ha->ccb_phys =
  4015. pci_map_single(ha->pdev,ha->pccb,
  4016. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4017. ha->scratch_busy = FALSE;
  4018. ha->req_first = NULL;
  4019. ha->tid_cnt = MAX_HDRIVES;
  4020. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4021. ha->tid_cnt = max_ids;
  4022. for (i=0; i<GDTH_MAXCMDS; ++i)
  4023. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4024. ha->scan_mode = rescan ? 0x10 : 0;
  4025. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4026. !gdth_search_drives(hanum)) {
  4027. printk("GDT-EISA: Error during device scan\n");
  4028. --gdth_ctr_count;
  4029. --gdth_ctr_vcount;
  4030. #ifdef INT_COAL
  4031. if (ha->coal_stat)
  4032. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4033. MAXOFFSETS, ha->coal_stat,
  4034. ha->coal_stat_phys);
  4035. #endif
  4036. if (ha->pscratch)
  4037. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4038. ha->pscratch, ha->scratch_phys);
  4039. if (ha->pmsg)
  4040. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4041. ha->pmsg, ha->msg_phys);
  4042. if (ha->ccb_phys)
  4043. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4044. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4045. free_irq(ha->irq,ha);
  4046. scsi_unregister(shp);
  4047. continue;
  4048. }
  4049. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4050. hdr_channel = ha->bus_cnt;
  4051. ha->virt_bus = hdr_channel;
  4052. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4053. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4054. shp->highmem_io = 0;
  4055. #endif
  4056. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4057. shp->max_cmd_len = 16;
  4058. shp->max_id = ha->tid_cnt;
  4059. shp->max_lun = MAXLUN;
  4060. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4061. if (virt_ctr) {
  4062. virt_ctr = 1;
  4063. /* register addit. SCSI channels as virtual controllers */
  4064. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4065. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4066. shp->unchecked_isa_dma = 0;
  4067. shp->irq = ha->irq;
  4068. shp->dma_channel = 0xff;
  4069. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4070. NUMDATA(shp)->hanum = (ushort)hanum;
  4071. NUMDATA(shp)->busnum = b;
  4072. }
  4073. }
  4074. spin_lock_init(&ha->smp_lock);
  4075. gdth_enable_int(hanum);
  4076. }
  4077. }
  4078. }
  4079. /* scanning for PCI controllers */
  4080. cnt = gdth_search_pci(pcistr);
  4081. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4082. gdth_sort_pci(pcistr,cnt);
  4083. for (ctr = 0; ctr < cnt; ++ctr) {
  4084. dma_addr_t scratch_dma_handle;
  4085. scratch_dma_handle = 0;
  4086. if (gdth_ctr_count >= MAXHA)
  4087. break;
  4088. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4089. if (shp == NULL)
  4090. continue;
  4091. ha = HADATA(shp);
  4092. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4093. scsi_unregister(shp);
  4094. continue;
  4095. }
  4096. /* controller found and initialized */
  4097. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4098. pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
  4099. if (request_irq(ha->irq, gdth_interrupt,
  4100. SA_INTERRUPT|SA_SHIRQ, "gdth", ha))
  4101. {
  4102. printk("GDT-PCI: Unable to allocate IRQ\n");
  4103. scsi_unregister(shp);
  4104. continue;
  4105. }
  4106. shp->unchecked_isa_dma = 0;
  4107. shp->irq = ha->irq;
  4108. shp->dma_channel = 0xff;
  4109. hanum = gdth_ctr_count;
  4110. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4111. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4112. NUMDATA(shp)->hanum = (ushort)hanum;
  4113. NUMDATA(shp)->busnum= 0;
  4114. ha->pccb = CMDDATA(shp);
  4115. ha->ccb_phys = 0L;
  4116. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4117. &scratch_dma_handle);
  4118. ha->scratch_phys = scratch_dma_handle;
  4119. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4120. &scratch_dma_handle);
  4121. ha->msg_phys = scratch_dma_handle;
  4122. #ifdef INT_COAL
  4123. ha->coal_stat = (gdth_coal_status *)
  4124. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4125. MAXOFFSETS, &scratch_dma_handle);
  4126. ha->coal_stat_phys = scratch_dma_handle;
  4127. #endif
  4128. ha->scratch_busy = FALSE;
  4129. ha->req_first = NULL;
  4130. ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
  4131. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4132. ha->tid_cnt = max_ids;
  4133. for (i=0; i<GDTH_MAXCMDS; ++i)
  4134. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4135. ha->scan_mode = rescan ? 0x10 : 0;
  4136. err = FALSE;
  4137. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4138. !gdth_search_drives(hanum)) {
  4139. err = TRUE;
  4140. } else {
  4141. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4142. hdr_channel = ha->bus_cnt;
  4143. ha->virt_bus = hdr_channel;
  4144. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4145. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4146. #endif
  4147. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4148. /* 64-bit DMA only supported from FW >= x.43 */
  4149. (!ha->dma64_support)) {
  4150. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4151. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4152. err = TRUE;
  4153. }
  4154. } else {
  4155. shp->max_cmd_len = 16;
  4156. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4157. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4158. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4159. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4160. err = TRUE;
  4161. }
  4162. }
  4163. }
  4164. if (err) {
  4165. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4166. --gdth_ctr_count;
  4167. --gdth_ctr_vcount;
  4168. #ifdef INT_COAL
  4169. if (ha->coal_stat)
  4170. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4171. MAXOFFSETS, ha->coal_stat,
  4172. ha->coal_stat_phys);
  4173. #endif
  4174. if (ha->pscratch)
  4175. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4176. ha->pscratch, ha->scratch_phys);
  4177. if (ha->pmsg)
  4178. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4179. ha->pmsg, ha->msg_phys);
  4180. free_irq(ha->irq,ha);
  4181. scsi_unregister(shp);
  4182. continue;
  4183. }
  4184. shp->max_id = ha->tid_cnt;
  4185. shp->max_lun = MAXLUN;
  4186. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4187. if (virt_ctr) {
  4188. virt_ctr = 1;
  4189. /* register addit. SCSI channels as virtual controllers */
  4190. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4191. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4192. shp->unchecked_isa_dma = 0;
  4193. shp->irq = ha->irq;
  4194. shp->dma_channel = 0xff;
  4195. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4196. NUMDATA(shp)->hanum = (ushort)hanum;
  4197. NUMDATA(shp)->busnum = b;
  4198. }
  4199. }
  4200. spin_lock_init(&ha->smp_lock);
  4201. gdth_enable_int(hanum);
  4202. }
  4203. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4204. if (gdth_ctr_count > 0) {
  4205. #ifdef GDTH_STATISTICS
  4206. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4207. init_timer(&gdth_timer);
  4208. gdth_timer.expires = jiffies + HZ;
  4209. gdth_timer.data = 0L;
  4210. gdth_timer.function = gdth_timeout;
  4211. add_timer(&gdth_timer);
  4212. #endif
  4213. major = register_chrdev(0,"gdth",&gdth_fops);
  4214. notifier_disabled = 0;
  4215. register_reboot_notifier(&gdth_notifier);
  4216. }
  4217. gdth_polling = FALSE;
  4218. return gdth_ctr_vcount;
  4219. }
  4220. static int gdth_release(struct Scsi_Host *shp)
  4221. {
  4222. int hanum;
  4223. gdth_ha_str *ha;
  4224. TRACE2(("gdth_release()\n"));
  4225. if (NUMDATA(shp)->busnum == 0) {
  4226. hanum = NUMDATA(shp)->hanum;
  4227. ha = HADATA(gdth_ctr_tab[hanum]);
  4228. if (ha->sdev) {
  4229. scsi_free_host_dev(ha->sdev);
  4230. ha->sdev = NULL;
  4231. }
  4232. gdth_flush(hanum);
  4233. if (shp->irq) {
  4234. free_irq(shp->irq,ha);
  4235. }
  4236. #ifndef __ia64__
  4237. if (shp->dma_channel != 0xff) {
  4238. free_dma(shp->dma_channel);
  4239. }
  4240. #endif
  4241. #ifdef INT_COAL
  4242. if (ha->coal_stat)
  4243. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4244. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4245. #endif
  4246. if (ha->pscratch)
  4247. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4248. ha->pscratch, ha->scratch_phys);
  4249. if (ha->pmsg)
  4250. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4251. ha->pmsg, ha->msg_phys);
  4252. if (ha->ccb_phys)
  4253. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4254. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4255. gdth_ctr_released++;
  4256. TRACE2(("gdth_release(): HA %d of %d\n",
  4257. gdth_ctr_released, gdth_ctr_count));
  4258. if (gdth_ctr_released == gdth_ctr_count) {
  4259. #ifdef GDTH_STATISTICS
  4260. del_timer(&gdth_timer);
  4261. #endif
  4262. unregister_chrdev(major,"gdth");
  4263. unregister_reboot_notifier(&gdth_notifier);
  4264. }
  4265. }
  4266. scsi_unregister(shp);
  4267. return 0;
  4268. }
  4269. static const char *gdth_ctr_name(int hanum)
  4270. {
  4271. gdth_ha_str *ha;
  4272. TRACE2(("gdth_ctr_name()\n"));
  4273. ha = HADATA(gdth_ctr_tab[hanum]);
  4274. if (ha->type == GDT_EISA) {
  4275. switch (ha->stype) {
  4276. case GDT3_ID:
  4277. return("GDT3000/3020");
  4278. case GDT3A_ID:
  4279. return("GDT3000A/3020A/3050A");
  4280. case GDT3B_ID:
  4281. return("GDT3000B/3010A");
  4282. }
  4283. } else if (ha->type == GDT_ISA) {
  4284. return("GDT2000/2020");
  4285. } else if (ha->type == GDT_PCI) {
  4286. switch (ha->stype) {
  4287. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4288. return("GDT6000/6020/6050");
  4289. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4290. return("GDT6000B/6010");
  4291. }
  4292. }
  4293. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4294. return("");
  4295. }
  4296. static const char *gdth_info(struct Scsi_Host *shp)
  4297. {
  4298. int hanum;
  4299. gdth_ha_str *ha;
  4300. TRACE2(("gdth_info()\n"));
  4301. hanum = NUMDATA(shp)->hanum;
  4302. ha = HADATA(gdth_ctr_tab[hanum]);
  4303. return ((const char *)ha->binfo.type_string);
  4304. }
  4305. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4306. {
  4307. int i, hanum;
  4308. gdth_ha_str *ha;
  4309. ulong flags;
  4310. Scsi_Cmnd *cmnd;
  4311. unchar b;
  4312. TRACE2(("gdth_eh_bus_reset()\n"));
  4313. hanum = NUMDATA(scp->device->host)->hanum;
  4314. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4315. ha = HADATA(gdth_ctr_tab[hanum]);
  4316. /* clear command tab */
  4317. spin_lock_irqsave(&ha->smp_lock, flags);
  4318. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4319. cmnd = ha->cmd_tab[i].cmnd;
  4320. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4321. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4322. }
  4323. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4324. if (b == ha->virt_bus) {
  4325. /* host drives */
  4326. for (i = 0; i < MAX_HDRIVES; ++i) {
  4327. if (ha->hdr[i].present) {
  4328. spin_lock_irqsave(&ha->smp_lock, flags);
  4329. gdth_polling = TRUE;
  4330. while (gdth_test_busy(hanum))
  4331. gdth_delay(0);
  4332. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4333. GDT_CLUST_RESET, i, 0, 0))
  4334. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4335. gdth_polling = FALSE;
  4336. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4337. }
  4338. }
  4339. } else {
  4340. /* raw devices */
  4341. spin_lock_irqsave(&ha->smp_lock, flags);
  4342. for (i = 0; i < MAXID; ++i)
  4343. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4344. gdth_polling = TRUE;
  4345. while (gdth_test_busy(hanum))
  4346. gdth_delay(0);
  4347. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4348. BUS_L2P(ha,b), 0, 0);
  4349. gdth_polling = FALSE;
  4350. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4351. }
  4352. return SUCCESS;
  4353. }
  4354. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4355. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4356. #else
  4357. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4358. #endif
  4359. {
  4360. unchar b, t;
  4361. int hanum;
  4362. gdth_ha_str *ha;
  4363. struct scsi_device *sd;
  4364. unsigned capacity;
  4365. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4366. sd = sdev;
  4367. capacity = cap;
  4368. #else
  4369. sd = disk->device;
  4370. capacity = disk->capacity;
  4371. #endif
  4372. hanum = NUMDATA(sd->host)->hanum;
  4373. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4374. t = sd->id;
  4375. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4376. ha = HADATA(gdth_ctr_tab[hanum]);
  4377. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4378. /* raw device or host drive without mapping information */
  4379. TRACE2(("Evaluate mapping\n"));
  4380. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4381. } else {
  4382. ip[0] = ha->hdr[t].heads;
  4383. ip[1] = ha->hdr[t].secs;
  4384. ip[2] = capacity / ip[0] / ip[1];
  4385. }
  4386. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4387. ip[0],ip[1],ip[2]));
  4388. return 0;
  4389. }
  4390. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
  4391. {
  4392. int hanum;
  4393. int priority;
  4394. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4395. scp->scsi_done = (void *)done;
  4396. scp->SCp.have_data_in = 1;
  4397. scp->SCp.phase = -1;
  4398. scp->SCp.sent_command = -1;
  4399. scp->SCp.Status = GDTH_MAP_NONE;
  4400. scp->SCp.buffer = (struct scatterlist *)NULL;
  4401. hanum = NUMDATA(scp->device->host)->hanum;
  4402. #ifdef GDTH_STATISTICS
  4403. ++act_ios;
  4404. #endif
  4405. priority = DEFAULT_PRI;
  4406. if (scp->done == gdth_scsi_done)
  4407. priority = scp->SCp.this_residual;
  4408. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4409. gdth_putq( hanum, scp, priority );
  4410. gdth_next( hanum );
  4411. return 0;
  4412. }
  4413. static int gdth_open(struct inode *inode, struct file *filep)
  4414. {
  4415. gdth_ha_str *ha;
  4416. int i;
  4417. for (i = 0; i < gdth_ctr_count; i++) {
  4418. ha = HADATA(gdth_ctr_tab[i]);
  4419. if (!ha->sdev)
  4420. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4421. }
  4422. TRACE(("gdth_open()\n"));
  4423. return 0;
  4424. }
  4425. static int gdth_close(struct inode *inode, struct file *filep)
  4426. {
  4427. TRACE(("gdth_close()\n"));
  4428. return 0;
  4429. }
  4430. static int ioc_event(void __user *arg)
  4431. {
  4432. gdth_ioctl_event evt;
  4433. gdth_ha_str *ha;
  4434. ulong flags;
  4435. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4436. evt.ionode >= gdth_ctr_count)
  4437. return -EFAULT;
  4438. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4439. if (evt.erase == 0xff) {
  4440. if (evt.event.event_source == ES_TEST)
  4441. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4442. else if (evt.event.event_source == ES_DRIVER)
  4443. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4444. else if (evt.event.event_source == ES_SYNC)
  4445. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4446. else
  4447. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4448. spin_lock_irqsave(&ha->smp_lock, flags);
  4449. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4450. &evt.event.event_data);
  4451. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4452. } else if (evt.erase == 0xfe) {
  4453. gdth_clear_events();
  4454. } else if (evt.erase == 0) {
  4455. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4456. } else {
  4457. gdth_readapp_event(ha, evt.erase, &evt.event);
  4458. }
  4459. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4460. return -EFAULT;
  4461. return 0;
  4462. }
  4463. static int ioc_lockdrv(void __user *arg)
  4464. {
  4465. gdth_ioctl_lockdrv ldrv;
  4466. unchar i, j;
  4467. ulong flags;
  4468. gdth_ha_str *ha;
  4469. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4470. ldrv.ionode >= gdth_ctr_count)
  4471. return -EFAULT;
  4472. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4473. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4474. j = ldrv.drives[i];
  4475. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4476. continue;
  4477. if (ldrv.lock) {
  4478. spin_lock_irqsave(&ha->smp_lock, flags);
  4479. ha->hdr[j].lock = 1;
  4480. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4481. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4482. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4483. } else {
  4484. spin_lock_irqsave(&ha->smp_lock, flags);
  4485. ha->hdr[j].lock = 0;
  4486. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4487. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4488. gdth_next(ldrv.ionode);
  4489. }
  4490. }
  4491. return 0;
  4492. }
  4493. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4494. {
  4495. gdth_ioctl_reset res;
  4496. gdth_cmd_str cmd;
  4497. int hanum;
  4498. gdth_ha_str *ha;
  4499. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4500. Scsi_Request *srp;
  4501. #else
  4502. Scsi_Cmnd *scp;
  4503. #endif
  4504. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4505. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4506. return -EFAULT;
  4507. hanum = res.ionode;
  4508. ha = HADATA(gdth_ctr_tab[hanum]);
  4509. if (!ha->hdr[res.number].present)
  4510. return 0;
  4511. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4512. cmd.Service = CACHESERVICE;
  4513. cmd.OpCode = GDT_CLUST_RESET;
  4514. if (ha->cache_feat & GDT_64BIT)
  4515. cmd.u.cache64.DeviceNo = res.number;
  4516. else
  4517. cmd.u.cache.DeviceNo = res.number;
  4518. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4519. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4520. if (!srp)
  4521. return -ENOMEM;
  4522. srp->sr_cmd_len = 12;
  4523. srp->sr_use_sg = 0;
  4524. gdth_do_req(srp, &cmd, cmnd, 30);
  4525. res.status = (ushort)srp->sr_command->SCp.Status;
  4526. scsi_release_request(srp);
  4527. #else
  4528. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4529. if (!scp)
  4530. return -ENOMEM;
  4531. scp->cmd_len = 12;
  4532. scp->use_sg = 0;
  4533. gdth_do_cmd(scp, &cmd, cmnd, 30);
  4534. res.status = (ushort)scp->SCp.Status;
  4535. scsi_release_command(scp);
  4536. #endif
  4537. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4538. return -EFAULT;
  4539. return 0;
  4540. }
  4541. static int ioc_general(void __user *arg, char *cmnd)
  4542. {
  4543. gdth_ioctl_general gen;
  4544. char *buf = NULL;
  4545. ulong64 paddr;
  4546. int hanum;
  4547. gdth_ha_str *ha;
  4548. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4549. Scsi_Request *srp;
  4550. #else
  4551. Scsi_Cmnd *scp;
  4552. #endif
  4553. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4554. gen.ionode >= gdth_ctr_count)
  4555. return -EFAULT;
  4556. hanum = gen.ionode;
  4557. ha = HADATA(gdth_ctr_tab[hanum]);
  4558. if (gen.data_len + gen.sense_len != 0) {
  4559. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4560. FALSE, &paddr)))
  4561. return -EFAULT;
  4562. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4563. gen.data_len + gen.sense_len)) {
  4564. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4565. return -EFAULT;
  4566. }
  4567. if (gen.command.OpCode == GDT_IOCTL) {
  4568. gen.command.u.ioctl.p_param = paddr;
  4569. } else if (gen.command.Service == CACHESERVICE) {
  4570. if (ha->cache_feat & GDT_64BIT) {
  4571. /* copy elements from 32-bit IOCTL structure */
  4572. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4573. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4574. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4575. /* addresses */
  4576. if (ha->cache_feat & SCATTER_GATHER) {
  4577. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4578. gen.command.u.cache64.sg_canz = 1;
  4579. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4580. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4581. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4582. } else {
  4583. gen.command.u.cache64.DestAddr = paddr;
  4584. gen.command.u.cache64.sg_canz = 0;
  4585. }
  4586. } else {
  4587. if (ha->cache_feat & SCATTER_GATHER) {
  4588. gen.command.u.cache.DestAddr = 0xffffffff;
  4589. gen.command.u.cache.sg_canz = 1;
  4590. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4591. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4592. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4593. } else {
  4594. gen.command.u.cache.DestAddr = paddr;
  4595. gen.command.u.cache.sg_canz = 0;
  4596. }
  4597. }
  4598. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4599. if (ha->raw_feat & GDT_64BIT) {
  4600. /* copy elements from 32-bit IOCTL structure */
  4601. char cmd[16];
  4602. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4603. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4604. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4605. gen.command.u.raw64.target = gen.command.u.raw.target;
  4606. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4607. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4608. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4609. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4610. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4611. /* addresses */
  4612. if (ha->raw_feat & SCATTER_GATHER) {
  4613. gen.command.u.raw64.sdata = (ulong64)-1;
  4614. gen.command.u.raw64.sg_ranz = 1;
  4615. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4616. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4617. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4618. } else {
  4619. gen.command.u.raw64.sdata = paddr;
  4620. gen.command.u.raw64.sg_ranz = 0;
  4621. }
  4622. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4623. } else {
  4624. if (ha->raw_feat & SCATTER_GATHER) {
  4625. gen.command.u.raw.sdata = 0xffffffff;
  4626. gen.command.u.raw.sg_ranz = 1;
  4627. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4628. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4629. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4630. } else {
  4631. gen.command.u.raw.sdata = paddr;
  4632. gen.command.u.raw.sg_ranz = 0;
  4633. }
  4634. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4635. }
  4636. } else {
  4637. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4638. return -EFAULT;
  4639. }
  4640. }
  4641. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4642. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4643. if (!srp)
  4644. return -ENOMEM;
  4645. srp->sr_cmd_len = 12;
  4646. srp->sr_use_sg = 0;
  4647. gdth_do_req(srp, &gen.command, cmnd, gen.timeout);
  4648. gen.status = srp->sr_command->SCp.Status;
  4649. gen.info = srp->sr_command->SCp.Message;
  4650. scsi_release_request(srp);
  4651. #else
  4652. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4653. if (!scp)
  4654. return -ENOMEM;
  4655. scp->cmd_len = 12;
  4656. scp->use_sg = 0;
  4657. gdth_do_cmd(scp, &gen.command, cmnd, gen.timeout);
  4658. gen.status = scp->SCp.Status;
  4659. gen.info = scp->SCp.Message;
  4660. scsi_release_command(scp);
  4661. #endif
  4662. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4663. gen.data_len + gen.sense_len)) {
  4664. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4665. return -EFAULT;
  4666. }
  4667. if (copy_to_user(arg, &gen,
  4668. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4669. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4670. return -EFAULT;
  4671. }
  4672. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4673. return 0;
  4674. }
  4675. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4676. {
  4677. gdth_ioctl_rescan *rsc;
  4678. gdth_cmd_str *cmd;
  4679. gdth_ha_str *ha;
  4680. unchar i;
  4681. int hanum, rc = -ENOMEM;
  4682. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4683. Scsi_Request *srp;
  4684. #else
  4685. Scsi_Cmnd *scp;
  4686. #endif
  4687. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4688. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4689. if (!rsc || !cmd)
  4690. goto free_fail;
  4691. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4692. rsc->ionode >= gdth_ctr_count) {
  4693. rc = -EFAULT;
  4694. goto free_fail;
  4695. }
  4696. hanum = rsc->ionode;
  4697. ha = HADATA(gdth_ctr_tab[hanum]);
  4698. memset(cmd, 0, sizeof(gdth_cmd_str));
  4699. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4700. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4701. if (!srp)
  4702. goto free_fail;
  4703. srp->sr_cmd_len = 12;
  4704. srp->sr_use_sg = 0;
  4705. #else
  4706. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4707. if (!scp)
  4708. goto free_fail;
  4709. scp->cmd_len = 12;
  4710. scp->use_sg = 0;
  4711. #endif
  4712. for (i = 0; i < MAX_HDRIVES; ++i) {
  4713. if (!ha->hdr[i].present) {
  4714. rsc->hdr_list[i].bus = 0xff;
  4715. continue;
  4716. }
  4717. rsc->hdr_list[i].bus = ha->virt_bus;
  4718. rsc->hdr_list[i].target = i;
  4719. rsc->hdr_list[i].lun = 0;
  4720. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4721. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4722. cmd->Service = CACHESERVICE;
  4723. cmd->OpCode = GDT_CLUST_INFO;
  4724. if (ha->cache_feat & GDT_64BIT)
  4725. cmd->u.cache64.DeviceNo = i;
  4726. else
  4727. cmd->u.cache.DeviceNo = i;
  4728. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4729. gdth_do_req(srp, cmd, cmnd, 30);
  4730. if (srp->sr_command->SCp.Status == S_OK)
  4731. rsc->hdr_list[i].cluster_type = srp->sr_command->SCp.Message;
  4732. #else
  4733. gdth_do_cmd(scp, cmd, cmnd, 30);
  4734. if (scp->SCp.Status == S_OK)
  4735. rsc->hdr_list[i].cluster_type = scp->SCp.Message;
  4736. #endif
  4737. }
  4738. }
  4739. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4740. scsi_release_request(srp);
  4741. #else
  4742. scsi_release_command(scp);
  4743. #endif
  4744. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4745. rc = -EFAULT;
  4746. else
  4747. rc = 0;
  4748. free_fail:
  4749. kfree(rsc);
  4750. kfree(cmd);
  4751. return rc;
  4752. }
  4753. static int ioc_rescan(void __user *arg, char *cmnd)
  4754. {
  4755. gdth_ioctl_rescan *rsc;
  4756. gdth_cmd_str *cmd;
  4757. ushort i, status, hdr_cnt;
  4758. ulong32 info;
  4759. int hanum, cyls, hds, secs;
  4760. int rc = -ENOMEM;
  4761. ulong flags;
  4762. gdth_ha_str *ha;
  4763. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4764. Scsi_Request *srp;
  4765. #else
  4766. Scsi_Cmnd *scp;
  4767. #endif
  4768. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4769. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4770. if (!cmd || !rsc)
  4771. goto free_fail;
  4772. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4773. rsc->ionode >= gdth_ctr_count) {
  4774. rc = -EFAULT;
  4775. goto free_fail;
  4776. }
  4777. hanum = rsc->ionode;
  4778. ha = HADATA(gdth_ctr_tab[hanum]);
  4779. memset(cmd, 0, sizeof(gdth_cmd_str));
  4780. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4781. srp = scsi_allocate_request(ha->sdev, GFP_KERNEL);
  4782. if (!srp)
  4783. goto free_fail;
  4784. srp->sr_cmd_len = 12;
  4785. srp->sr_use_sg = 0;
  4786. #else
  4787. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4788. if (!scp)
  4789. goto free_fail;
  4790. scp->cmd_len = 12;
  4791. scp->use_sg = 0;
  4792. #endif
  4793. if (rsc->flag == 0) {
  4794. /* old method: re-init. cache service */
  4795. cmd->Service = CACHESERVICE;
  4796. if (ha->cache_feat & GDT_64BIT) {
  4797. cmd->OpCode = GDT_X_INIT_HOST;
  4798. cmd->u.cache64.DeviceNo = LINUX_OS;
  4799. } else {
  4800. cmd->OpCode = GDT_INIT;
  4801. cmd->u.cache.DeviceNo = LINUX_OS;
  4802. }
  4803. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4804. gdth_do_req(srp, cmd, cmnd, 30);
  4805. status = (ushort)srp->sr_command->SCp.Status;
  4806. info = (ulong32)srp->sr_command->SCp.Message;
  4807. #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0)
  4808. gdth_do_cmd(scp, cmd, cmnd, 30);
  4809. status = (ushort)scp->SCp.Status;
  4810. info = (ulong32)scp->SCp.Message;
  4811. #else
  4812. gdth_do_cmd(&scp, cmd, cmnd, 30);
  4813. status = (ushort)scp.SCp.Status;
  4814. info = (ulong32)scp.SCp.Message;
  4815. #endif
  4816. i = 0;
  4817. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4818. } else {
  4819. i = rsc->hdr_no;
  4820. hdr_cnt = i + 1;
  4821. }
  4822. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4823. cmd->Service = CACHESERVICE;
  4824. cmd->OpCode = GDT_INFO;
  4825. if (ha->cache_feat & GDT_64BIT)
  4826. cmd->u.cache64.DeviceNo = i;
  4827. else
  4828. cmd->u.cache.DeviceNo = i;
  4829. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4830. gdth_do_req(srp, cmd, cmnd, 30);
  4831. status = (ushort)srp->sr_command->SCp.Status;
  4832. info = (ulong32)srp->sr_command->SCp.Message;
  4833. #else
  4834. gdth_do_cmd(scp, cmd, cmnd, 30);
  4835. status = (ushort)scp->SCp.Status;
  4836. info = (ulong32)scp->SCp.Message;
  4837. #endif
  4838. spin_lock_irqsave(&ha->smp_lock, flags);
  4839. rsc->hdr_list[i].bus = ha->virt_bus;
  4840. rsc->hdr_list[i].target = i;
  4841. rsc->hdr_list[i].lun = 0;
  4842. if (status != S_OK) {
  4843. ha->hdr[i].present = FALSE;
  4844. } else {
  4845. ha->hdr[i].present = TRUE;
  4846. ha->hdr[i].size = info;
  4847. /* evaluate mapping */
  4848. ha->hdr[i].size &= ~SECS32;
  4849. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4850. ha->hdr[i].heads = hds;
  4851. ha->hdr[i].secs = secs;
  4852. /* round size */
  4853. ha->hdr[i].size = cyls * hds * secs;
  4854. }
  4855. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4856. if (status != S_OK)
  4857. continue;
  4858. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4859. /* but we need ha->info2, not yet stored in scp->SCp */
  4860. /* devtype, cluster info, R/W attribs */
  4861. cmd->Service = CACHESERVICE;
  4862. cmd->OpCode = GDT_DEVTYPE;
  4863. if (ha->cache_feat & GDT_64BIT)
  4864. cmd->u.cache64.DeviceNo = i;
  4865. else
  4866. cmd->u.cache.DeviceNo = i;
  4867. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4868. gdth_do_req(srp, cmd, cmnd, 30);
  4869. status = (ushort)srp->sr_command->SCp.Status;
  4870. info = (ulong32)srp->sr_command->SCp.Message;
  4871. #else
  4872. gdth_do_cmd(scp, cmd, cmnd, 30);
  4873. status = (ushort)scp->SCp.Status;
  4874. info = (ulong32)scp->SCp.Message;
  4875. #endif
  4876. spin_lock_irqsave(&ha->smp_lock, flags);
  4877. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4878. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4879. cmd->Service = CACHESERVICE;
  4880. cmd->OpCode = GDT_CLUST_INFO;
  4881. if (ha->cache_feat & GDT_64BIT)
  4882. cmd->u.cache64.DeviceNo = i;
  4883. else
  4884. cmd->u.cache.DeviceNo = i;
  4885. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4886. gdth_do_req(srp, cmd, cmnd, 30);
  4887. status = (ushort)srp->sr_command->SCp.Status;
  4888. info = (ulong32)srp->sr_command->SCp.Message;
  4889. #else
  4890. gdth_do_cmd(scp, cmd, cmnd, 30);
  4891. status = (ushort)scp->SCp.Status;
  4892. info = (ulong32)scp->SCp.Message;
  4893. #endif
  4894. spin_lock_irqsave(&ha->smp_lock, flags);
  4895. ha->hdr[i].cluster_type =
  4896. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4897. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4898. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4899. cmd->Service = CACHESERVICE;
  4900. cmd->OpCode = GDT_RW_ATTRIBS;
  4901. if (ha->cache_feat & GDT_64BIT)
  4902. cmd->u.cache64.DeviceNo = i;
  4903. else
  4904. cmd->u.cache.DeviceNo = i;
  4905. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4906. gdth_do_req(srp, cmd, cmnd, 30);
  4907. status = (ushort)srp->sr_command->SCp.Status;
  4908. info = (ulong32)srp->sr_command->SCp.Message;
  4909. #else
  4910. gdth_do_cmd(scp, cmd, cmnd, 30);
  4911. status = (ushort)scp->SCp.Status;
  4912. info = (ulong32)scp->SCp.Message;
  4913. #endif
  4914. spin_lock_irqsave(&ha->smp_lock, flags);
  4915. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4916. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4917. }
  4918. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4919. scsi_release_request(srp);
  4920. #else
  4921. scsi_release_command(scp);
  4922. #endif
  4923. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4924. rc = -EFAULT;
  4925. else
  4926. rc = 0;
  4927. free_fail:
  4928. kfree(rsc);
  4929. kfree(cmd);
  4930. return rc;
  4931. }
  4932. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4933. unsigned int cmd, unsigned long arg)
  4934. {
  4935. gdth_ha_str *ha;
  4936. Scsi_Cmnd *scp;
  4937. ulong flags;
  4938. char cmnd[MAX_COMMAND_SIZE];
  4939. void __user *argp = (void __user *)arg;
  4940. memset(cmnd, 0xff, 12);
  4941. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4942. switch (cmd) {
  4943. case GDTIOCTL_CTRCNT:
  4944. {
  4945. int cnt = gdth_ctr_count;
  4946. if (put_user(cnt, (int __user *)argp))
  4947. return -EFAULT;
  4948. break;
  4949. }
  4950. case GDTIOCTL_DRVERS:
  4951. {
  4952. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4953. if (put_user(ver, (int __user *)argp))
  4954. return -EFAULT;
  4955. break;
  4956. }
  4957. case GDTIOCTL_OSVERS:
  4958. {
  4959. gdth_ioctl_osvers osv;
  4960. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4961. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4962. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4963. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4964. return -EFAULT;
  4965. break;
  4966. }
  4967. case GDTIOCTL_CTRTYPE:
  4968. {
  4969. gdth_ioctl_ctrtype ctrt;
  4970. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4971. ctrt.ionode >= gdth_ctr_count)
  4972. return -EFAULT;
  4973. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4974. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4975. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4976. } else {
  4977. if (ha->type != GDT_PCIMPR) {
  4978. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4979. } else {
  4980. ctrt.type =
  4981. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4982. if (ha->stype >= 0x300)
  4983. ctrt.ext_type = 0x6000 | ha->subdevice_id;
  4984. else
  4985. ctrt.ext_type = 0x6000 | ha->stype;
  4986. }
  4987. ctrt.device_id = ha->stype;
  4988. ctrt.sub_device_id = ha->subdevice_id;
  4989. }
  4990. ctrt.info = ha->brd_phys;
  4991. ctrt.oem_id = ha->oem_id;
  4992. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4993. return -EFAULT;
  4994. break;
  4995. }
  4996. case GDTIOCTL_GENERAL:
  4997. return ioc_general(argp, cmnd);
  4998. case GDTIOCTL_EVENT:
  4999. return ioc_event(argp);
  5000. case GDTIOCTL_LOCKDRV:
  5001. return ioc_lockdrv(argp);
  5002. case GDTIOCTL_LOCKCHN:
  5003. {
  5004. gdth_ioctl_lockchn lchn;
  5005. unchar i, j;
  5006. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  5007. lchn.ionode >= gdth_ctr_count)
  5008. return -EFAULT;
  5009. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  5010. i = lchn.channel;
  5011. if (i < ha->bus_cnt) {
  5012. if (lchn.lock) {
  5013. spin_lock_irqsave(&ha->smp_lock, flags);
  5014. ha->raw[i].lock = 1;
  5015. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5016. for (j = 0; j < ha->tid_cnt; ++j) {
  5017. gdth_wait_completion(lchn.ionode, i, j);
  5018. gdth_stop_timeout(lchn.ionode, i, j);
  5019. }
  5020. } else {
  5021. spin_lock_irqsave(&ha->smp_lock, flags);
  5022. ha->raw[i].lock = 0;
  5023. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5024. for (j = 0; j < ha->tid_cnt; ++j) {
  5025. gdth_start_timeout(lchn.ionode, i, j);
  5026. gdth_next(lchn.ionode);
  5027. }
  5028. }
  5029. }
  5030. break;
  5031. }
  5032. case GDTIOCTL_RESCAN:
  5033. return ioc_rescan(argp, cmnd);
  5034. case GDTIOCTL_HDRLIST:
  5035. return ioc_hdrlist(argp, cmnd);
  5036. case GDTIOCTL_RESET_BUS:
  5037. {
  5038. gdth_ioctl_reset res;
  5039. int hanum, rval;
  5040. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  5041. res.ionode >= gdth_ctr_count)
  5042. return -EFAULT;
  5043. hanum = res.ionode;
  5044. ha = HADATA(gdth_ctr_tab[hanum]);
  5045. /* Because we need a Scsi_Cmnd struct., we make a scsi_allocate device also for kernels >=2.6.x */
  5046. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5047. scp = scsi_get_command(ha->sdev, GFP_KERNEL);
  5048. if (!scp)
  5049. return -ENOMEM;
  5050. scp->cmd_len = 12;
  5051. scp->use_sg = 0;
  5052. scp->device->channel = virt_ctr ? 0 : res.number;
  5053. rval = gdth_eh_bus_reset(scp);
  5054. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5055. scsi_put_command(scp);
  5056. #else
  5057. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  5058. if (!scp)
  5059. return -ENOMEM;
  5060. scp->cmd_len = 12;
  5061. scp->use_sg = 0;
  5062. scp->channel = virt_ctr ? 0 : res.number;
  5063. rval = gdth_eh_bus_reset(scp);
  5064. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5065. scsi_release_command(scp);
  5066. #endif
  5067. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  5068. return -EFAULT;
  5069. break;
  5070. }
  5071. case GDTIOCTL_RESET_DRV:
  5072. return ioc_resetdrv(argp, cmnd);
  5073. default:
  5074. break;
  5075. }
  5076. return 0;
  5077. }
  5078. /* flush routine */
  5079. static void gdth_flush(int hanum)
  5080. {
  5081. int i;
  5082. gdth_ha_str *ha;
  5083. gdth_cmd_str gdtcmd;
  5084. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5085. Scsi_Request *srp;
  5086. #else
  5087. Scsi_Cmnd *scp;
  5088. #endif
  5089. struct scsi_device *sdev;
  5090. char cmnd[MAX_COMMAND_SIZE];
  5091. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5092. TRACE2(("gdth_flush() hanum %d\n",hanum));
  5093. ha = HADATA(gdth_ctr_tab[hanum]);
  5094. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5095. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5096. srp = scsi_allocate_request(sdev, GFP_KERNEL);
  5097. if (!srp)
  5098. return;
  5099. srp->sr_cmd_len = 12;
  5100. srp->sr_use_sg = 0;
  5101. #else
  5102. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5103. scp = scsi_allocate_device(sdev, 1, FALSE);
  5104. if (!scp)
  5105. return;
  5106. scp->cmd_len = 12;
  5107. scp->use_sg = 0;
  5108. #endif
  5109. for (i = 0; i < MAX_HDRIVES; ++i) {
  5110. if (ha->hdr[i].present) {
  5111. gdtcmd.BoardNode = LOCALBOARD;
  5112. gdtcmd.Service = CACHESERVICE;
  5113. gdtcmd.OpCode = GDT_FLUSH;
  5114. if (ha->cache_feat & GDT_64BIT) {
  5115. gdtcmd.u.cache64.DeviceNo = i;
  5116. gdtcmd.u.cache64.BlockNo = 1;
  5117. gdtcmd.u.cache64.sg_canz = 0;
  5118. } else {
  5119. gdtcmd.u.cache.DeviceNo = i;
  5120. gdtcmd.u.cache.BlockNo = 1;
  5121. gdtcmd.u.cache.sg_canz = 0;
  5122. }
  5123. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  5124. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5125. gdth_do_req(srp, &gdtcmd, cmnd, 30);
  5126. #else
  5127. gdth_do_cmd(scp, &gdtcmd, cmnd, 30);
  5128. #endif
  5129. }
  5130. }
  5131. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5132. scsi_release_request(srp);
  5133. scsi_free_host_dev(sdev);
  5134. #else
  5135. scsi_release_command(scp);
  5136. scsi_free_host_dev(sdev);
  5137. #endif
  5138. }
  5139. /* shutdown routine */
  5140. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  5141. {
  5142. int hanum;
  5143. #ifndef __alpha__
  5144. gdth_cmd_str gdtcmd;
  5145. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5146. Scsi_Request *srp;
  5147. struct scsi_device *sdev;
  5148. #else
  5149. Scsi_Cmnd *scp;
  5150. struct scsi_device *sdev;
  5151. #endif
  5152. char cmnd[MAX_COMMAND_SIZE];
  5153. #endif
  5154. if (notifier_disabled)
  5155. return NOTIFY_OK;
  5156. TRACE2(("gdth_halt() event %d\n",(int)event));
  5157. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5158. return NOTIFY_DONE;
  5159. notifier_disabled = 1;
  5160. printk("GDT-HA: Flushing all host drives .. ");
  5161. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5162. gdth_flush(hanum);
  5163. #ifndef __alpha__
  5164. /* controller reset */
  5165. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5166. gdtcmd.BoardNode = LOCALBOARD;
  5167. gdtcmd.Service = CACHESERVICE;
  5168. gdtcmd.OpCode = GDT_RESET;
  5169. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5170. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5171. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5172. srp = scsi_allocate_request(sdev, GFP_KERNEL);
  5173. if (!srp) {
  5174. unregister_reboot_notifier(&gdth_notifier);
  5175. return NOTIFY_OK;
  5176. }
  5177. srp->sr_cmd_len = 12;
  5178. srp->sr_use_sg = 0;
  5179. gdth_do_req(srp, &gdtcmd, cmnd, 10);
  5180. scsi_release_request(srp);
  5181. scsi_free_host_dev(sdev);
  5182. #else
  5183. sdev = scsi_get_host_dev(gdth_ctr_tab[hanum]);
  5184. scp = scsi_allocate_device(sdev, 1, FALSE);
  5185. if (!scp) {
  5186. unregister_reboot_notifier(&gdth_notifier);
  5187. return NOTIFY_OK;
  5188. }
  5189. scp->cmd_len = 12;
  5190. scp->use_sg = 0;
  5191. gdth_do_cmd(scp, &gdtcmd, cmnd, 10);
  5192. scsi_release_command(scp);
  5193. scsi_free_host_dev(sdev);
  5194. #endif
  5195. #endif
  5196. }
  5197. printk("Done.\n");
  5198. #ifdef GDTH_STATISTICS
  5199. del_timer(&gdth_timer);
  5200. #endif
  5201. return NOTIFY_OK;
  5202. }
  5203. static struct scsi_host_template driver_template = {
  5204. .proc_name = "gdth",
  5205. .proc_info = gdth_proc_info,
  5206. .name = "GDT SCSI Disk Array Controller",
  5207. .detect = gdth_detect,
  5208. .release = gdth_release,
  5209. .info = gdth_info,
  5210. .queuecommand = gdth_queuecommand,
  5211. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5212. .bios_param = gdth_bios_param,
  5213. .can_queue = GDTH_MAXCMDS,
  5214. .this_id = -1,
  5215. .sg_tablesize = GDTH_MAXSG,
  5216. .cmd_per_lun = GDTH_MAXC_P_L,
  5217. .unchecked_isa_dma = 1,
  5218. .use_clustering = ENABLE_CLUSTERING,
  5219. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5220. .use_new_eh_code = 1,
  5221. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5222. .highmem_io = 1,
  5223. #endif
  5224. #endif
  5225. };
  5226. #include "scsi_module.c"
  5227. #ifndef MODULE
  5228. __setup("gdth=", option_setup);
  5229. #endif