i82092.c 18 KB

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  1. /*
  2. * Driver for Intel I82092AA PCI-PCMCIA bridge.
  3. *
  4. * (C) 2001 Red Hat, Inc.
  5. *
  6. * Author: Arjan Van De Ven <arjanv@redhat.com>
  7. * Loosly based on i82365.c from the pcmcia-cs package
  8. *
  9. * $Id: i82092aa.c,v 1.2 2001/10/23 14:43:34 arjanv Exp $
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/module.h>
  13. #include <linux/pci.h>
  14. #include <linux/init.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/device.h>
  18. #include <pcmcia/cs_types.h>
  19. #include <pcmcia/ss.h>
  20. #include <pcmcia/cs.h>
  21. #include <asm/system.h>
  22. #include <asm/io.h>
  23. #include "i82092aa.h"
  24. #include "i82365.h"
  25. MODULE_LICENSE("GPL");
  26. /* PCI core routines */
  27. static struct pci_device_id i82092aa_pci_ids[] = {
  28. {
  29. .vendor = PCI_VENDOR_ID_INTEL,
  30. .device = PCI_DEVICE_ID_INTEL_82092AA_0,
  31. .subvendor = PCI_ANY_ID,
  32. .subdevice = PCI_ANY_ID,
  33. },
  34. {}
  35. };
  36. MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
  37. static int i82092aa_socket_suspend (struct pci_dev *dev, pm_message_t state)
  38. {
  39. return pcmcia_socket_dev_suspend(&dev->dev, state);
  40. }
  41. static int i82092aa_socket_resume (struct pci_dev *dev)
  42. {
  43. return pcmcia_socket_dev_resume(&dev->dev);
  44. }
  45. static struct pci_driver i82092aa_pci_drv = {
  46. .name = "i82092aa",
  47. .id_table = i82092aa_pci_ids,
  48. .probe = i82092aa_pci_probe,
  49. .remove = __devexit_p(i82092aa_pci_remove),
  50. .suspend = i82092aa_socket_suspend,
  51. .resume = i82092aa_socket_resume,
  52. };
  53. /* the pccard structure and its functions */
  54. static struct pccard_operations i82092aa_operations = {
  55. .init = i82092aa_init,
  56. .get_status = i82092aa_get_status,
  57. .set_socket = i82092aa_set_socket,
  58. .set_io_map = i82092aa_set_io_map,
  59. .set_mem_map = i82092aa_set_mem_map,
  60. };
  61. /* The card can do upto 4 sockets, allocate a structure for each of them */
  62. struct socket_info {
  63. int number;
  64. int card_state; /* 0 = no socket,
  65. 1 = empty socket,
  66. 2 = card but not initialized,
  67. 3 = operational card */
  68. kio_addr_t io_base; /* base io address of the socket */
  69. struct pcmcia_socket socket;
  70. struct pci_dev *dev; /* The PCI device for the socket */
  71. };
  72. #define MAX_SOCKETS 4
  73. static struct socket_info sockets[MAX_SOCKETS];
  74. static int socket_count; /* shortcut */
  75. static int __devinit i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  76. {
  77. unsigned char configbyte;
  78. int i, ret;
  79. enter("i82092aa_pci_probe");
  80. if ((ret = pci_enable_device(dev)))
  81. return ret;
  82. pci_read_config_byte(dev, 0x40, &configbyte); /* PCI Configuration Control */
  83. switch(configbyte&6) {
  84. case 0:
  85. socket_count = 2;
  86. break;
  87. case 2:
  88. socket_count = 1;
  89. break;
  90. case 4:
  91. case 6:
  92. socket_count = 4;
  93. break;
  94. default:
  95. printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n");
  96. ret = -EIO;
  97. goto err_out_disable;
  98. }
  99. printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count);
  100. if (!request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
  101. ret = -EBUSY;
  102. goto err_out_disable;
  103. }
  104. for (i = 0;i<socket_count;i++) {
  105. sockets[i].card_state = 1; /* 1 = present but empty */
  106. sockets[i].io_base = pci_resource_start(dev, 0);
  107. sockets[i].socket.features |= SS_CAP_PCCARD;
  108. sockets[i].socket.map_size = 0x1000;
  109. sockets[i].socket.irq_mask = 0;
  110. sockets[i].socket.pci_irq = dev->irq;
  111. sockets[i].socket.owner = THIS_MODULE;
  112. sockets[i].number = i;
  113. if (card_present(i)) {
  114. sockets[i].card_state = 3;
  115. dprintk(KERN_DEBUG "i82092aa: slot %i is occupied\n",i);
  116. } else {
  117. dprintk(KERN_DEBUG "i82092aa: slot %i is vacant\n",i);
  118. }
  119. }
  120. /* Now, specifiy that all interrupts are to be done as PCI interrupts */
  121. configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */
  122. pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */
  123. /* Register the interrupt handler */
  124. dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq);
  125. if ((ret = request_irq(dev->irq, i82092aa_interrupt, SA_SHIRQ, "i82092aa", i82092aa_interrupt))) {
  126. printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq);
  127. goto err_out_free_res;
  128. }
  129. pci_set_drvdata(dev, &sockets[i].socket);
  130. for (i = 0; i<socket_count; i++) {
  131. sockets[i].socket.dev.dev = &dev->dev;
  132. sockets[i].socket.ops = &i82092aa_operations;
  133. sockets[i].socket.resource_ops = &pccard_nonstatic_ops;
  134. ret = pcmcia_register_socket(&sockets[i].socket);
  135. if (ret) {
  136. goto err_out_free_sockets;
  137. }
  138. }
  139. leave("i82092aa_pci_probe");
  140. return 0;
  141. err_out_free_sockets:
  142. if (i) {
  143. for (i--;i>=0;i--) {
  144. pcmcia_unregister_socket(&sockets[i].socket);
  145. }
  146. }
  147. free_irq(dev->irq, i82092aa_interrupt);
  148. err_out_free_res:
  149. release_region(pci_resource_start(dev, 0), 2);
  150. err_out_disable:
  151. pci_disable_device(dev);
  152. return ret;
  153. }
  154. static void __devexit i82092aa_pci_remove(struct pci_dev *dev)
  155. {
  156. struct pcmcia_socket *socket = pci_get_drvdata(dev);
  157. enter("i82092aa_pci_remove");
  158. free_irq(dev->irq, i82092aa_interrupt);
  159. if (socket)
  160. pcmcia_unregister_socket(socket);
  161. leave("i82092aa_pci_remove");
  162. }
  163. static DEFINE_SPINLOCK(port_lock);
  164. /* basic value read/write functions */
  165. static unsigned char indirect_read(int socket, unsigned short reg)
  166. {
  167. unsigned short int port;
  168. unsigned char val;
  169. unsigned long flags;
  170. spin_lock_irqsave(&port_lock,flags);
  171. reg += socket * 0x40;
  172. port = sockets[socket].io_base;
  173. outb(reg,port);
  174. val = inb(port+1);
  175. spin_unlock_irqrestore(&port_lock,flags);
  176. return val;
  177. }
  178. #if 0
  179. static unsigned short indirect_read16(int socket, unsigned short reg)
  180. {
  181. unsigned short int port;
  182. unsigned short tmp;
  183. unsigned long flags;
  184. spin_lock_irqsave(&port_lock,flags);
  185. reg = reg + socket * 0x40;
  186. port = sockets[socket].io_base;
  187. outb(reg,port);
  188. tmp = inb(port+1);
  189. reg++;
  190. outb(reg,port);
  191. tmp = tmp | (inb(port+1)<<8);
  192. spin_unlock_irqrestore(&port_lock,flags);
  193. return tmp;
  194. }
  195. #endif
  196. static void indirect_write(int socket, unsigned short reg, unsigned char value)
  197. {
  198. unsigned short int port;
  199. unsigned long flags;
  200. spin_lock_irqsave(&port_lock,flags);
  201. reg = reg + socket * 0x40;
  202. port = sockets[socket].io_base;
  203. outb(reg,port);
  204. outb(value,port+1);
  205. spin_unlock_irqrestore(&port_lock,flags);
  206. }
  207. static void indirect_setbit(int socket, unsigned short reg, unsigned char mask)
  208. {
  209. unsigned short int port;
  210. unsigned char val;
  211. unsigned long flags;
  212. spin_lock_irqsave(&port_lock,flags);
  213. reg = reg + socket * 0x40;
  214. port = sockets[socket].io_base;
  215. outb(reg,port);
  216. val = inb(port+1);
  217. val |= mask;
  218. outb(reg,port);
  219. outb(val,port+1);
  220. spin_unlock_irqrestore(&port_lock,flags);
  221. }
  222. static void indirect_resetbit(int socket, unsigned short reg, unsigned char mask)
  223. {
  224. unsigned short int port;
  225. unsigned char val;
  226. unsigned long flags;
  227. spin_lock_irqsave(&port_lock,flags);
  228. reg = reg + socket * 0x40;
  229. port = sockets[socket].io_base;
  230. outb(reg,port);
  231. val = inb(port+1);
  232. val &= ~mask;
  233. outb(reg,port);
  234. outb(val,port+1);
  235. spin_unlock_irqrestore(&port_lock,flags);
  236. }
  237. static void indirect_write16(int socket, unsigned short reg, unsigned short value)
  238. {
  239. unsigned short int port;
  240. unsigned char val;
  241. unsigned long flags;
  242. spin_lock_irqsave(&port_lock,flags);
  243. reg = reg + socket * 0x40;
  244. port = sockets[socket].io_base;
  245. outb(reg,port);
  246. val = value & 255;
  247. outb(val,port+1);
  248. reg++;
  249. outb(reg,port);
  250. val = value>>8;
  251. outb(val,port+1);
  252. spin_unlock_irqrestore(&port_lock,flags);
  253. }
  254. /* simple helper functions */
  255. /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
  256. static int cycle_time = 120;
  257. static int to_cycles(int ns)
  258. {
  259. if (cycle_time!=0)
  260. return ns/cycle_time;
  261. else
  262. return 0;
  263. }
  264. /* Interrupt handler functionality */
  265. static irqreturn_t i82092aa_interrupt(int irq, void *dev, struct pt_regs *regs)
  266. {
  267. int i;
  268. int loopcount = 0;
  269. int handled = 0;
  270. unsigned int events, active=0;
  271. /* enter("i82092aa_interrupt");*/
  272. while (1) {
  273. loopcount++;
  274. if (loopcount>20) {
  275. printk(KERN_ERR "i82092aa: infinite eventloop in interrupt \n");
  276. break;
  277. }
  278. active = 0;
  279. for (i=0;i<socket_count;i++) {
  280. int csc;
  281. if (sockets[i].card_state==0) /* Inactive socket, should not happen */
  282. continue;
  283. csc = indirect_read(i,I365_CSC); /* card status change register */
  284. if (csc==0) /* no events on this socket */
  285. continue;
  286. handled = 1;
  287. events = 0;
  288. if (csc & I365_CSC_DETECT) {
  289. events |= SS_DETECT;
  290. printk("Card detected in socket %i!\n",i);
  291. }
  292. if (indirect_read(i,I365_INTCTL) & I365_PC_IOCARD) {
  293. /* For IO/CARDS, bit 0 means "read the card" */
  294. events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
  295. } else {
  296. /* Check for battery/ready events */
  297. events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
  298. events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
  299. events |= (csc & I365_CSC_READY) ? SS_READY : 0;
  300. }
  301. if (events) {
  302. pcmcia_parse_events(&sockets[i].socket, events);
  303. }
  304. active |= events;
  305. }
  306. if (active==0) /* no more events to handle */
  307. break;
  308. }
  309. return IRQ_RETVAL(handled);
  310. /* leave("i82092aa_interrupt");*/
  311. }
  312. /* socket functions */
  313. static int card_present(int socketno)
  314. {
  315. unsigned int val;
  316. enter("card_present");
  317. if ((socketno<0) || (socketno >= MAX_SOCKETS))
  318. return 0;
  319. if (sockets[socketno].io_base == 0)
  320. return 0;
  321. val = indirect_read(socketno, 1); /* Interface status register */
  322. if ((val&12)==12) {
  323. leave("card_present 1");
  324. return 1;
  325. }
  326. leave("card_present 0");
  327. return 0;
  328. }
  329. static void set_bridge_state(int sock)
  330. {
  331. enter("set_bridge_state");
  332. indirect_write(sock, I365_GBLCTL,0x00);
  333. indirect_write(sock, I365_GENCTL,0x00);
  334. indirect_setbit(sock, I365_INTCTL,0x08);
  335. leave("set_bridge_state");
  336. }
  337. static int i82092aa_init(struct pcmcia_socket *sock)
  338. {
  339. int i;
  340. struct resource res = { .start = 0, .end = 0x0fff };
  341. pccard_io_map io = { 0, 0, 0, 0, 1 };
  342. pccard_mem_map mem = { .res = &res, };
  343. enter("i82092aa_init");
  344. for (i = 0; i < 2; i++) {
  345. io.map = i;
  346. i82092aa_set_io_map(sock, &io);
  347. }
  348. for (i = 0; i < 5; i++) {
  349. mem.map = i;
  350. i82092aa_set_mem_map(sock, &mem);
  351. }
  352. leave("i82092aa_init");
  353. return 0;
  354. }
  355. static int i82092aa_get_status(struct pcmcia_socket *socket, u_int *value)
  356. {
  357. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  358. unsigned int status;
  359. enter("i82092aa_get_status");
  360. status = indirect_read(sock,I365_STATUS); /* Interface Status Register */
  361. *value = 0;
  362. if ((status & I365_CS_DETECT) == I365_CS_DETECT) {
  363. *value |= SS_DETECT;
  364. }
  365. /* IO cards have a different meaning of bits 0,1 */
  366. /* Also notice the inverse-logic on the bits */
  367. if (indirect_read(sock, I365_INTCTL) & I365_PC_IOCARD) {
  368. /* IO card */
  369. if (!(status & I365_CS_STSCHG))
  370. *value |= SS_STSCHG;
  371. } else { /* non I/O card */
  372. if (!(status & I365_CS_BVD1))
  373. *value |= SS_BATDEAD;
  374. if (!(status & I365_CS_BVD2))
  375. *value |= SS_BATWARN;
  376. }
  377. if (status & I365_CS_WRPROT)
  378. (*value) |= SS_WRPROT; /* card is write protected */
  379. if (status & I365_CS_READY)
  380. (*value) |= SS_READY; /* card is not busy */
  381. if (status & I365_CS_POWERON)
  382. (*value) |= SS_POWERON; /* power is applied to the card */
  383. leave("i82092aa_get_status");
  384. return 0;
  385. }
  386. static int i82092aa_set_socket(struct pcmcia_socket *socket, socket_state_t *state)
  387. {
  388. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  389. unsigned char reg;
  390. enter("i82092aa_set_socket");
  391. /* First, set the global controller options */
  392. set_bridge_state(sock);
  393. /* Values for the IGENC register */
  394. reg = 0;
  395. if (!(state->flags & SS_RESET)) /* The reset bit has "inverse" logic */
  396. reg = reg | I365_PC_RESET;
  397. if (state->flags & SS_IOCARD)
  398. reg = reg | I365_PC_IOCARD;
  399. indirect_write(sock,I365_INTCTL,reg); /* IGENC, Interrupt and General Control Register */
  400. /* Power registers */
  401. reg = I365_PWR_NORESET; /* default: disable resetdrv on resume */
  402. if (state->flags & SS_PWR_AUTO) {
  403. printk("Auto power\n");
  404. reg |= I365_PWR_AUTO; /* automatic power mngmnt */
  405. }
  406. if (state->flags & SS_OUTPUT_ENA) {
  407. printk("Power Enabled \n");
  408. reg |= I365_PWR_OUT; /* enable power */
  409. }
  410. switch (state->Vcc) {
  411. case 0:
  412. break;
  413. case 50:
  414. printk("setting voltage to Vcc to 5V on socket %i\n",sock);
  415. reg |= I365_VCC_5V;
  416. break;
  417. default:
  418. printk("i82092aa: i82092aa_set_socket called with invalid VCC power value: %i ", state->Vcc);
  419. leave("i82092aa_set_socket");
  420. return -EINVAL;
  421. }
  422. switch (state->Vpp) {
  423. case 0:
  424. printk("not setting Vpp on socket %i\n",sock);
  425. break;
  426. case 50:
  427. printk("setting Vpp to 5.0 for socket %i\n",sock);
  428. reg |= I365_VPP1_5V | I365_VPP2_5V;
  429. break;
  430. case 120:
  431. printk("setting Vpp to 12.0\n");
  432. reg |= I365_VPP1_12V | I365_VPP2_12V;
  433. break;
  434. default:
  435. printk("i82092aa: i82092aa_set_socket called with invalid VPP power value: %i ", state->Vcc);
  436. leave("i82092aa_set_socket");
  437. return -EINVAL;
  438. }
  439. if (reg != indirect_read(sock,I365_POWER)) /* only write if changed */
  440. indirect_write(sock,I365_POWER,reg);
  441. /* Enable specific interrupt events */
  442. reg = 0x00;
  443. if (state->csc_mask & SS_DETECT) {
  444. reg |= I365_CSC_DETECT;
  445. }
  446. if (state->flags & SS_IOCARD) {
  447. if (state->csc_mask & SS_STSCHG)
  448. reg |= I365_CSC_STSCHG;
  449. } else {
  450. if (state->csc_mask & SS_BATDEAD)
  451. reg |= I365_CSC_BVD1;
  452. if (state->csc_mask & SS_BATWARN)
  453. reg |= I365_CSC_BVD2;
  454. if (state->csc_mask & SS_READY)
  455. reg |= I365_CSC_READY;
  456. }
  457. /* now write the value and clear the (probably bogus) pending stuff by doing a dummy read*/
  458. indirect_write(sock,I365_CSCINT,reg);
  459. (void)indirect_read(sock,I365_CSC);
  460. leave("i82092aa_set_socket");
  461. return 0;
  462. }
  463. static int i82092aa_set_io_map(struct pcmcia_socket *socket, struct pccard_io_map *io)
  464. {
  465. unsigned int sock = container_of(socket, struct socket_info, socket)->number;
  466. unsigned char map, ioctl;
  467. enter("i82092aa_set_io_map");
  468. map = io->map;
  469. /* Check error conditions */
  470. if (map > 1) {
  471. leave("i82092aa_set_io_map with invalid map");
  472. return -EINVAL;
  473. }
  474. if ((io->start > 0xffff) || (io->stop > 0xffff) || (io->stop < io->start)){
  475. leave("i82092aa_set_io_map with invalid io");
  476. return -EINVAL;
  477. }
  478. /* Turn off the window before changing anything */
  479. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_IO(map))
  480. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_IO(map));
  481. /* printk("set_io_map: Setting range to %x - %x \n",io->start,io->stop); */
  482. /* write the new values */
  483. indirect_write16(sock,I365_IO(map)+I365_W_START,io->start);
  484. indirect_write16(sock,I365_IO(map)+I365_W_STOP,io->stop);
  485. ioctl = indirect_read(sock,I365_IOCTL) & ~I365_IOCTL_MASK(map);
  486. if (io->flags & (MAP_16BIT|MAP_AUTOSZ))
  487. ioctl |= I365_IOCTL_16BIT(map);
  488. indirect_write(sock,I365_IOCTL,ioctl);
  489. /* Turn the window back on if needed */
  490. if (io->flags & MAP_ACTIVE)
  491. indirect_setbit(sock,I365_ADDRWIN,I365_ENA_IO(map));
  492. leave("i82092aa_set_io_map");
  493. return 0;
  494. }
  495. static int i82092aa_set_mem_map(struct pcmcia_socket *socket, struct pccard_mem_map *mem)
  496. {
  497. struct socket_info *sock_info = container_of(socket, struct socket_info, socket);
  498. unsigned int sock = sock_info->number;
  499. struct pci_bus_region region;
  500. unsigned short base, i;
  501. unsigned char map;
  502. enter("i82092aa_set_mem_map");
  503. pcibios_resource_to_bus(sock_info->dev, &region, mem->res);
  504. map = mem->map;
  505. if (map > 4) {
  506. leave("i82092aa_set_mem_map: invalid map");
  507. return -EINVAL;
  508. }
  509. if ( (mem->card_start > 0x3ffffff) || (region.start > region.end) ||
  510. (mem->speed > 1000) ) {
  511. leave("i82092aa_set_mem_map: invalid address / speed");
  512. printk("invalid mem map for socket %i : %lx to %lx with a start of %x \n",sock,region.start, region.end, mem->card_start);
  513. return -EINVAL;
  514. }
  515. /* Turn off the window before changing anything */
  516. if (indirect_read(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
  517. indirect_resetbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  518. /* printk("set_mem_map: Setting map %i range to %x - %x on socket %i, speed is %i, active = %i \n",map, region.start,region.end,sock,mem->speed,mem->flags & MAP_ACTIVE); */
  519. /* write the start address */
  520. base = I365_MEM(map);
  521. i = (region.start >> 12) & 0x0fff;
  522. if (mem->flags & MAP_16BIT)
  523. i |= I365_MEM_16BIT;
  524. if (mem->flags & MAP_0WS)
  525. i |= I365_MEM_0WS;
  526. indirect_write16(sock,base+I365_W_START,i);
  527. /* write the stop address */
  528. i= (region.end >> 12) & 0x0fff;
  529. switch (to_cycles(mem->speed)) {
  530. case 0:
  531. break;
  532. case 1:
  533. i |= I365_MEM_WS0;
  534. break;
  535. case 2:
  536. i |= I365_MEM_WS1;
  537. break;
  538. default:
  539. i |= I365_MEM_WS1 | I365_MEM_WS0;
  540. break;
  541. }
  542. indirect_write16(sock,base+I365_W_STOP,i);
  543. /* card start */
  544. i = ((mem->card_start - region.start) >> 12) & 0x3fff;
  545. if (mem->flags & MAP_WRPROT)
  546. i |= I365_MEM_WRPROT;
  547. if (mem->flags & MAP_ATTRIB) {
  548. /* printk("requesting attribute memory for socket %i\n",sock);*/
  549. i |= I365_MEM_REG;
  550. } else {
  551. /* printk("requesting normal memory for socket %i\n",sock);*/
  552. }
  553. indirect_write16(sock,base+I365_W_OFF,i);
  554. /* Enable the window if necessary */
  555. if (mem->flags & MAP_ACTIVE)
  556. indirect_setbit(sock, I365_ADDRWIN, I365_ENA_MEM(map));
  557. leave("i82092aa_set_mem_map");
  558. return 0;
  559. }
  560. static int i82092aa_module_init(void)
  561. {
  562. enter("i82092aa_module_init");
  563. pci_register_driver(&i82092aa_pci_drv);
  564. leave("i82092aa_module_init");
  565. return 0;
  566. }
  567. static void i82092aa_module_exit(void)
  568. {
  569. enter("i82092aa_module_exit");
  570. pci_unregister_driver(&i82092aa_pci_drv);
  571. if (sockets[0].io_base>0)
  572. release_region(sockets[0].io_base, 2);
  573. leave("i82092aa_module_exit");
  574. }
  575. module_init(i82092aa_module_init);
  576. module_exit(i82092aa_module_exit);