islpci_dev.c 26 KB

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  1. /*
  2. *
  3. * Copyright (C) 2002 Intersil Americas Inc.
  4. * Copyright (C) 2003 Herbert Valerio Riedel <hvr@gnu.org>
  5. * Copyright (C) 2003 Luis R. Rodriguez <mcgrof@ruslug.rutgers.edu>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/netdevice.h>
  23. #include <linux/pci.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/delay.h>
  26. #include <linux/if_arp.h>
  27. #include <asm/io.h>
  28. #include "prismcompat.h"
  29. #include "isl_38xx.h"
  30. #include "isl_ioctl.h"
  31. #include "islpci_dev.h"
  32. #include "islpci_mgt.h"
  33. #include "islpci_eth.h"
  34. #include "oid_mgt.h"
  35. #define ISL3877_IMAGE_FILE "isl3877"
  36. #define ISL3886_IMAGE_FILE "isl3886"
  37. #define ISL3890_IMAGE_FILE "isl3890"
  38. static int prism54_bring_down(islpci_private *);
  39. static int islpci_alloc_memory(islpci_private *);
  40. static struct net_device_stats *islpci_statistics(struct net_device *);
  41. /* Temporary dummy MAC address to use until firmware is loaded.
  42. * The idea there is that some tools (such as nameif) may query
  43. * the MAC address before the netdev is 'open'. By using a valid
  44. * OUI prefix, they can process the netdev properly.
  45. * Of course, this is not the final/real MAC address. It doesn't
  46. * matter, as you are suppose to be able to change it anytime via
  47. * ndev->set_mac_address. Jean II */
  48. static const unsigned char dummy_mac[6] = { 0x00, 0x30, 0xB4, 0x00, 0x00, 0x00 };
  49. static int
  50. isl_upload_firmware(islpci_private *priv)
  51. {
  52. u32 reg, rc;
  53. void __iomem *device_base = priv->device_base;
  54. /* clear the RAMBoot and the Reset bit */
  55. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  56. reg &= ~ISL38XX_CTRL_STAT_RESET;
  57. reg &= ~ISL38XX_CTRL_STAT_RAMBOOT;
  58. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  59. wmb();
  60. udelay(ISL38XX_WRITEIO_DELAY);
  61. /* set the Reset bit without reading the register ! */
  62. reg |= ISL38XX_CTRL_STAT_RESET;
  63. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  64. wmb();
  65. udelay(ISL38XX_WRITEIO_DELAY);
  66. /* clear the Reset bit */
  67. reg &= ~ISL38XX_CTRL_STAT_RESET;
  68. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  69. wmb();
  70. /* wait a while for the device to reboot */
  71. mdelay(50);
  72. {
  73. const struct firmware *fw_entry = NULL;
  74. long fw_len;
  75. const u32 *fw_ptr;
  76. rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV);
  77. if (rc) {
  78. printk(KERN_ERR
  79. "%s: request_firmware() failed for '%s'\n",
  80. "prism54", priv->firmware);
  81. return rc;
  82. }
  83. /* prepare the Direct Memory Base register */
  84. reg = ISL38XX_DEV_FIRMWARE_ADDRES;
  85. fw_ptr = (u32 *) fw_entry->data;
  86. fw_len = fw_entry->size;
  87. if (fw_len % 4) {
  88. printk(KERN_ERR
  89. "%s: firmware '%s' size is not multiple of 32bit, aborting!\n",
  90. "prism54", priv->firmware);
  91. release_firmware(fw_entry);
  92. return -EILSEQ; /* Illegal byte sequence */;
  93. }
  94. while (fw_len > 0) {
  95. long _fw_len =
  96. (fw_len >
  97. ISL38XX_MEMORY_WINDOW_SIZE) ?
  98. ISL38XX_MEMORY_WINDOW_SIZE : fw_len;
  99. u32 __iomem *dev_fw_ptr = device_base + ISL38XX_DIRECT_MEM_WIN;
  100. /* set the cards base address for writting the data */
  101. isl38xx_w32_flush(device_base, reg,
  102. ISL38XX_DIR_MEM_BASE_REG);
  103. wmb(); /* be paranoid */
  104. /* increment the write address for next iteration */
  105. reg += _fw_len;
  106. fw_len -= _fw_len;
  107. /* write the data to the Direct Memory Window 32bit-wise */
  108. /* memcpy_toio() doesn't guarantee 32bit writes :-| */
  109. while (_fw_len > 0) {
  110. /* use non-swapping writel() */
  111. __raw_writel(*fw_ptr, dev_fw_ptr);
  112. fw_ptr++, dev_fw_ptr++;
  113. _fw_len -= 4;
  114. }
  115. /* flush PCI posting */
  116. (void) readl(device_base + ISL38XX_PCI_POSTING_FLUSH);
  117. wmb(); /* be paranoid again */
  118. BUG_ON(_fw_len != 0);
  119. }
  120. BUG_ON(fw_len != 0);
  121. /* Firmware version is at offset 40 (also for "newmac") */
  122. printk(KERN_DEBUG "%s: firmware version: %.8s\n",
  123. priv->ndev->name, fw_entry->data + 40);
  124. release_firmware(fw_entry);
  125. }
  126. /* now reset the device
  127. * clear the Reset & ClkRun bit, set the RAMBoot bit */
  128. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  129. reg &= ~ISL38XX_CTRL_STAT_CLKRUN;
  130. reg &= ~ISL38XX_CTRL_STAT_RESET;
  131. reg |= ISL38XX_CTRL_STAT_RAMBOOT;
  132. isl38xx_w32_flush(device_base, reg, ISL38XX_CTRL_STAT_REG);
  133. wmb();
  134. udelay(ISL38XX_WRITEIO_DELAY);
  135. /* set the reset bit latches the host override and RAMBoot bits
  136. * into the device for operation when the reset bit is reset */
  137. reg |= ISL38XX_CTRL_STAT_RESET;
  138. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  139. /* don't do flush PCI posting here! */
  140. wmb();
  141. udelay(ISL38XX_WRITEIO_DELAY);
  142. /* clear the reset bit should start the whole circus */
  143. reg &= ~ISL38XX_CTRL_STAT_RESET;
  144. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  145. /* don't do flush PCI posting here! */
  146. wmb();
  147. udelay(ISL38XX_WRITEIO_DELAY);
  148. return 0;
  149. }
  150. /******************************************************************************
  151. Device Interrupt Handler
  152. ******************************************************************************/
  153. irqreturn_t
  154. islpci_interrupt(int irq, void *config, struct pt_regs *regs)
  155. {
  156. u32 reg;
  157. islpci_private *priv = config;
  158. struct net_device *ndev = priv->ndev;
  159. void __iomem *device = priv->device_base;
  160. int powerstate = ISL38XX_PSM_POWERSAVE_STATE;
  161. /* lock the interrupt handler */
  162. spin_lock(&priv->slock);
  163. /* received an interrupt request on a shared IRQ line
  164. * first check whether the device is in sleep mode */
  165. reg = readl(device + ISL38XX_CTRL_STAT_REG);
  166. if (reg & ISL38XX_CTRL_STAT_SLEEPMODE)
  167. /* device is in sleep mode, IRQ was generated by someone else */
  168. {
  169. #if VERBOSE > SHOW_ERROR_MESSAGES
  170. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  171. #endif
  172. spin_unlock(&priv->slock);
  173. return IRQ_NONE;
  174. }
  175. /* check whether there is any source of interrupt on the device */
  176. reg = readl(device + ISL38XX_INT_IDENT_REG);
  177. /* also check the contents of the Interrupt Enable Register, because this
  178. * will filter out interrupt sources from other devices on the same irq ! */
  179. reg &= readl(device + ISL38XX_INT_EN_REG);
  180. reg &= ISL38XX_INT_SOURCES;
  181. if (reg != 0) {
  182. if (islpci_get_state(priv) != PRV_STATE_SLEEP)
  183. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  184. /* reset the request bits in the Identification register */
  185. isl38xx_w32_flush(device, reg, ISL38XX_INT_ACK_REG);
  186. #if VERBOSE > SHOW_ERROR_MESSAGES
  187. DEBUG(SHOW_FUNCTION_CALLS,
  188. "IRQ: Identification register 0x%p 0x%x \n", device, reg);
  189. #endif
  190. /* check for each bit in the register separately */
  191. if (reg & ISL38XX_INT_IDENT_UPDATE) {
  192. #if VERBOSE > SHOW_ERROR_MESSAGES
  193. /* Queue has been updated */
  194. DEBUG(SHOW_TRACING, "IRQ: Update flag \n");
  195. DEBUG(SHOW_QUEUE_INDEXES,
  196. "CB drv Qs: [%i][%i][%i][%i][%i][%i]\n",
  197. le32_to_cpu(priv->control_block->
  198. driver_curr_frag[0]),
  199. le32_to_cpu(priv->control_block->
  200. driver_curr_frag[1]),
  201. le32_to_cpu(priv->control_block->
  202. driver_curr_frag[2]),
  203. le32_to_cpu(priv->control_block->
  204. driver_curr_frag[3]),
  205. le32_to_cpu(priv->control_block->
  206. driver_curr_frag[4]),
  207. le32_to_cpu(priv->control_block->
  208. driver_curr_frag[5])
  209. );
  210. DEBUG(SHOW_QUEUE_INDEXES,
  211. "CB dev Qs: [%i][%i][%i][%i][%i][%i]\n",
  212. le32_to_cpu(priv->control_block->
  213. device_curr_frag[0]),
  214. le32_to_cpu(priv->control_block->
  215. device_curr_frag[1]),
  216. le32_to_cpu(priv->control_block->
  217. device_curr_frag[2]),
  218. le32_to_cpu(priv->control_block->
  219. device_curr_frag[3]),
  220. le32_to_cpu(priv->control_block->
  221. device_curr_frag[4]),
  222. le32_to_cpu(priv->control_block->
  223. device_curr_frag[5])
  224. );
  225. #endif
  226. /* cleanup the data low transmit queue */
  227. islpci_eth_cleanup_transmit(priv, priv->control_block);
  228. /* device is in active state, update the
  229. * powerstate flag if necessary */
  230. powerstate = ISL38XX_PSM_ACTIVE_STATE;
  231. /* check all three queues in priority order
  232. * call the PIMFOR receive function until the
  233. * queue is empty */
  234. if (isl38xx_in_queue(priv->control_block,
  235. ISL38XX_CB_RX_MGMTQ) != 0) {
  236. #if VERBOSE > SHOW_ERROR_MESSAGES
  237. DEBUG(SHOW_TRACING,
  238. "Received frame in Management Queue\n");
  239. #endif
  240. islpci_mgt_receive(ndev);
  241. islpci_mgt_cleanup_transmit(ndev);
  242. /* Refill slots in receive queue */
  243. islpci_mgmt_rx_fill(ndev);
  244. /* no need to trigger the device, next
  245. islpci_mgt_transaction does it */
  246. }
  247. while (isl38xx_in_queue(priv->control_block,
  248. ISL38XX_CB_RX_DATA_LQ) != 0) {
  249. #if VERBOSE > SHOW_ERROR_MESSAGES
  250. DEBUG(SHOW_TRACING,
  251. "Received frame in Data Low Queue \n");
  252. #endif
  253. islpci_eth_receive(priv);
  254. }
  255. /* check whether the data transmit queues were full */
  256. if (priv->data_low_tx_full) {
  257. /* check whether the transmit is not full anymore */
  258. if (ISL38XX_CB_TX_QSIZE -
  259. isl38xx_in_queue(priv->control_block,
  260. ISL38XX_CB_TX_DATA_LQ) >=
  261. ISL38XX_MIN_QTHRESHOLD) {
  262. /* nope, the driver is ready for more network frames */
  263. netif_wake_queue(priv->ndev);
  264. /* reset the full flag */
  265. priv->data_low_tx_full = 0;
  266. }
  267. }
  268. }
  269. if (reg & ISL38XX_INT_IDENT_INIT) {
  270. /* Device has been initialized */
  271. #if VERBOSE > SHOW_ERROR_MESSAGES
  272. DEBUG(SHOW_TRACING,
  273. "IRQ: Init flag, device initialized \n");
  274. #endif
  275. wake_up(&priv->reset_done);
  276. }
  277. if (reg & ISL38XX_INT_IDENT_SLEEP) {
  278. /* Device intends to move to powersave state */
  279. #if VERBOSE > SHOW_ERROR_MESSAGES
  280. DEBUG(SHOW_TRACING, "IRQ: Sleep flag \n");
  281. #endif
  282. isl38xx_handle_sleep_request(priv->control_block,
  283. &powerstate,
  284. priv->device_base);
  285. }
  286. if (reg & ISL38XX_INT_IDENT_WAKEUP) {
  287. /* Device has been woken up to active state */
  288. #if VERBOSE > SHOW_ERROR_MESSAGES
  289. DEBUG(SHOW_TRACING, "IRQ: Wakeup flag \n");
  290. #endif
  291. isl38xx_handle_wakeup(priv->control_block,
  292. &powerstate, priv->device_base);
  293. }
  294. } else {
  295. #if VERBOSE > SHOW_ERROR_MESSAGES
  296. DEBUG(SHOW_TRACING, "Assuming someone else called the IRQ\n");
  297. #endif
  298. spin_unlock(&priv->slock);
  299. return IRQ_NONE;
  300. }
  301. /* sleep -> ready */
  302. if (islpci_get_state(priv) == PRV_STATE_SLEEP
  303. && powerstate == ISL38XX_PSM_ACTIVE_STATE)
  304. islpci_set_state(priv, PRV_STATE_READY);
  305. /* !sleep -> sleep */
  306. if (islpci_get_state(priv) != PRV_STATE_SLEEP
  307. && powerstate == ISL38XX_PSM_POWERSAVE_STATE)
  308. islpci_set_state(priv, PRV_STATE_SLEEP);
  309. /* unlock the interrupt handler */
  310. spin_unlock(&priv->slock);
  311. return IRQ_HANDLED;
  312. }
  313. /******************************************************************************
  314. Network Interface Control & Statistical functions
  315. ******************************************************************************/
  316. static int
  317. islpci_open(struct net_device *ndev)
  318. {
  319. u32 rc;
  320. islpci_private *priv = netdev_priv(ndev);
  321. /* reset data structures, upload firmware and reset device */
  322. rc = islpci_reset(priv,1);
  323. if (rc) {
  324. prism54_bring_down(priv);
  325. return rc; /* Returns informative message */
  326. }
  327. netif_start_queue(ndev);
  328. /* netif_mark_up( ndev ); */
  329. return 0;
  330. }
  331. static int
  332. islpci_close(struct net_device *ndev)
  333. {
  334. islpci_private *priv = netdev_priv(ndev);
  335. printk(KERN_DEBUG "%s: islpci_close ()\n", ndev->name);
  336. netif_stop_queue(ndev);
  337. return prism54_bring_down(priv);
  338. }
  339. static int
  340. prism54_bring_down(islpci_private *priv)
  341. {
  342. void __iomem *device_base = priv->device_base;
  343. u32 reg;
  344. /* we are going to shutdown the device */
  345. islpci_set_state(priv, PRV_STATE_PREBOOT);
  346. /* disable all device interrupts in case they weren't */
  347. isl38xx_disable_interrupts(priv->device_base);
  348. /* For safety reasons, we may want to ensure that no DMA transfer is
  349. * currently in progress by emptying the TX and RX queues. */
  350. /* wait until interrupts have finished executing on other CPUs */
  351. synchronize_irq(priv->pdev->irq);
  352. reg = readl(device_base + ISL38XX_CTRL_STAT_REG);
  353. reg &= ~(ISL38XX_CTRL_STAT_RESET | ISL38XX_CTRL_STAT_RAMBOOT);
  354. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  355. wmb();
  356. udelay(ISL38XX_WRITEIO_DELAY);
  357. reg |= ISL38XX_CTRL_STAT_RESET;
  358. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  359. wmb();
  360. udelay(ISL38XX_WRITEIO_DELAY);
  361. /* clear the Reset bit */
  362. reg &= ~ISL38XX_CTRL_STAT_RESET;
  363. writel(reg, device_base + ISL38XX_CTRL_STAT_REG);
  364. wmb();
  365. /* wait a while for the device to reset */
  366. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  367. return 0;
  368. }
  369. static int
  370. islpci_upload_fw(islpci_private *priv)
  371. {
  372. islpci_state_t old_state;
  373. u32 rc;
  374. old_state = islpci_set_state(priv, PRV_STATE_BOOT);
  375. printk(KERN_DEBUG "%s: uploading firmware...\n", priv->ndev->name);
  376. rc = isl_upload_firmware(priv);
  377. if (rc) {
  378. /* error uploading the firmware */
  379. printk(KERN_ERR "%s: could not upload firmware ('%s')\n",
  380. priv->ndev->name, priv->firmware);
  381. islpci_set_state(priv, old_state);
  382. return rc;
  383. }
  384. printk(KERN_DEBUG "%s: firmware upload complete\n",
  385. priv->ndev->name);
  386. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  387. return 0;
  388. }
  389. static int
  390. islpci_reset_if(islpci_private *priv)
  391. {
  392. long remaining;
  393. int result = -ETIME;
  394. int count;
  395. DEFINE_WAIT(wait);
  396. prepare_to_wait(&priv->reset_done, &wait, TASK_UNINTERRUPTIBLE);
  397. /* now the last step is to reset the interface */
  398. isl38xx_interface_reset(priv->device_base, priv->device_host_address);
  399. islpci_set_state(priv, PRV_STATE_PREINIT);
  400. for(count = 0; count < 2 && result; count++) {
  401. /* The software reset acknowledge needs about 220 msec here.
  402. * Be conservative and wait for up to one second. */
  403. remaining = schedule_timeout_uninterruptible(HZ);
  404. if(remaining > 0) {
  405. result = 0;
  406. break;
  407. }
  408. /* If we're here it's because our IRQ hasn't yet gone through.
  409. * Retry a bit more...
  410. */
  411. printk(KERN_ERR "%s: no 'reset complete' IRQ seen - retrying\n",
  412. priv->ndev->name);
  413. }
  414. finish_wait(&priv->reset_done, &wait);
  415. if (result) {
  416. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  417. return result;
  418. }
  419. islpci_set_state(priv, PRV_STATE_INIT);
  420. /* Now that the device is 100% up, let's allow
  421. * for the other interrupts --
  422. * NOTE: this is not *yet* true since we've only allowed the
  423. * INIT interrupt on the IRQ line. We can perhaps poll
  424. * the IRQ line until we know for sure the reset went through */
  425. isl38xx_enable_common_interrupts(priv->device_base);
  426. down_write(&priv->mib_sem);
  427. result = mgt_commit(priv);
  428. if (result) {
  429. printk(KERN_ERR "%s: interface reset failure\n", priv->ndev->name);
  430. up_write(&priv->mib_sem);
  431. return result;
  432. }
  433. up_write(&priv->mib_sem);
  434. islpci_set_state(priv, PRV_STATE_READY);
  435. printk(KERN_DEBUG "%s: interface reset complete\n", priv->ndev->name);
  436. return 0;
  437. }
  438. int
  439. islpci_reset(islpci_private *priv, int reload_firmware)
  440. {
  441. isl38xx_control_block *cb = /* volatile not needed */
  442. (isl38xx_control_block *) priv->control_block;
  443. unsigned counter;
  444. int rc;
  445. if (reload_firmware)
  446. islpci_set_state(priv, PRV_STATE_PREBOOT);
  447. else
  448. islpci_set_state(priv, PRV_STATE_POSTBOOT);
  449. printk(KERN_DEBUG "%s: resetting device...\n", priv->ndev->name);
  450. /* disable all device interrupts in case they weren't */
  451. isl38xx_disable_interrupts(priv->device_base);
  452. /* flush all management queues */
  453. priv->index_mgmt_tx = 0;
  454. priv->index_mgmt_rx = 0;
  455. /* clear the indexes in the frame pointer */
  456. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  457. cb->driver_curr_frag[counter] = cpu_to_le32(0);
  458. cb->device_curr_frag[counter] = cpu_to_le32(0);
  459. }
  460. /* reset the mgmt receive queue */
  461. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  462. isl38xx_fragment *frag = &cb->rx_data_mgmt[counter];
  463. frag->size = cpu_to_le16(MGMT_FRAME_SIZE);
  464. frag->flags = 0;
  465. frag->address = cpu_to_le32(priv->mgmt_rx[counter].pci_addr);
  466. }
  467. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  468. cb->rx_data_low[counter].address =
  469. cpu_to_le32((u32) priv->pci_map_rx_address[counter]);
  470. }
  471. /* since the receive queues are filled with empty fragments, now we can
  472. * set the corresponding indexes in the Control Block */
  473. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_DATA_LQ] =
  474. cpu_to_le32(ISL38XX_CB_RX_QSIZE);
  475. priv->control_block->driver_curr_frag[ISL38XX_CB_RX_MGMTQ] =
  476. cpu_to_le32(ISL38XX_CB_MGMT_QSIZE);
  477. /* reset the remaining real index registers and full flags */
  478. priv->free_data_rx = 0;
  479. priv->free_data_tx = 0;
  480. priv->data_low_tx_full = 0;
  481. if (reload_firmware) { /* Should we load the firmware ? */
  482. /* now that the data structures are cleaned up, upload
  483. * firmware and reset interface */
  484. rc = islpci_upload_fw(priv);
  485. if (rc) {
  486. printk(KERN_ERR "%s: islpci_reset: failure\n",
  487. priv->ndev->name);
  488. return rc;
  489. }
  490. }
  491. /* finally reset interface */
  492. rc = islpci_reset_if(priv);
  493. if (rc)
  494. printk(KERN_ERR "prism54: Your card/socket may be faulty, or IRQ line too busy :(\n");
  495. return rc;
  496. }
  497. static struct net_device_stats *
  498. islpci_statistics(struct net_device *ndev)
  499. {
  500. islpci_private *priv = netdev_priv(ndev);
  501. #if VERBOSE > SHOW_ERROR_MESSAGES
  502. DEBUG(SHOW_FUNCTION_CALLS, "islpci_statistics\n");
  503. #endif
  504. return &priv->statistics;
  505. }
  506. /******************************************************************************
  507. Network device configuration functions
  508. ******************************************************************************/
  509. static int
  510. islpci_alloc_memory(islpci_private *priv)
  511. {
  512. int counter;
  513. #if VERBOSE > SHOW_ERROR_MESSAGES
  514. printk(KERN_DEBUG "islpci_alloc_memory\n");
  515. #endif
  516. /* remap the PCI device base address to accessable */
  517. if (!(priv->device_base =
  518. ioremap(pci_resource_start(priv->pdev, 0),
  519. ISL38XX_PCI_MEM_SIZE))) {
  520. /* error in remapping the PCI device memory address range */
  521. printk(KERN_ERR "PCI memory remapping failed \n");
  522. return -1;
  523. }
  524. /* memory layout for consistent DMA region:
  525. *
  526. * Area 1: Control Block for the device interface
  527. * Area 2: Power Save Mode Buffer for temporary frame storage. Be aware that
  528. * the number of supported stations in the AP determines the minimal
  529. * size of the buffer !
  530. */
  531. /* perform the allocation */
  532. priv->driver_mem_address = pci_alloc_consistent(priv->pdev,
  533. HOST_MEM_BLOCK,
  534. &priv->
  535. device_host_address);
  536. if (!priv->driver_mem_address) {
  537. /* error allocating the block of PCI memory */
  538. printk(KERN_ERR "%s: could not allocate DMA memory, aborting!",
  539. "prism54");
  540. return -1;
  541. }
  542. /* assign the Control Block to the first address of the allocated area */
  543. priv->control_block =
  544. (isl38xx_control_block *) priv->driver_mem_address;
  545. /* set the Power Save Buffer pointer directly behind the CB */
  546. priv->device_psm_buffer =
  547. priv->device_host_address + CONTROL_BLOCK_SIZE;
  548. /* make sure all buffer pointers are initialized */
  549. for (counter = 0; counter < ISL38XX_CB_QCOUNT; counter++) {
  550. priv->control_block->driver_curr_frag[counter] = cpu_to_le32(0);
  551. priv->control_block->device_curr_frag[counter] = cpu_to_le32(0);
  552. }
  553. priv->index_mgmt_rx = 0;
  554. memset(priv->mgmt_rx, 0, sizeof(priv->mgmt_rx));
  555. memset(priv->mgmt_tx, 0, sizeof(priv->mgmt_tx));
  556. /* allocate rx queue for management frames */
  557. if (islpci_mgmt_rx_fill(priv->ndev) < 0)
  558. goto out_free;
  559. /* now get the data rx skb's */
  560. memset(priv->data_low_rx, 0, sizeof (priv->data_low_rx));
  561. memset(priv->pci_map_rx_address, 0, sizeof (priv->pci_map_rx_address));
  562. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  563. struct sk_buff *skb;
  564. /* allocate an sk_buff for received data frames storage
  565. * each frame on receive size consists of 1 fragment
  566. * include any required allignment operations */
  567. if (!(skb = dev_alloc_skb(MAX_FRAGMENT_SIZE_RX + 2))) {
  568. /* error allocating an sk_buff structure elements */
  569. printk(KERN_ERR "Error allocating skb.\n");
  570. skb = NULL;
  571. goto out_free;
  572. }
  573. skb_reserve(skb, (4 - (long) skb->data) & 0x03);
  574. /* add the new allocated sk_buff to the buffer array */
  575. priv->data_low_rx[counter] = skb;
  576. /* map the allocated skb data area to pci */
  577. priv->pci_map_rx_address[counter] =
  578. pci_map_single(priv->pdev, (void *) skb->data,
  579. MAX_FRAGMENT_SIZE_RX + 2,
  580. PCI_DMA_FROMDEVICE);
  581. if (!priv->pci_map_rx_address[counter]) {
  582. /* error mapping the buffer to device
  583. accessable memory address */
  584. printk(KERN_ERR "failed to map skb DMA'able\n");
  585. goto out_free;
  586. }
  587. }
  588. prism54_acl_init(&priv->acl);
  589. prism54_wpa_ie_init(priv);
  590. if (mgt_init(priv))
  591. goto out_free;
  592. return 0;
  593. out_free:
  594. islpci_free_memory(priv);
  595. return -1;
  596. }
  597. int
  598. islpci_free_memory(islpci_private *priv)
  599. {
  600. int counter;
  601. if (priv->device_base)
  602. iounmap(priv->device_base);
  603. priv->device_base = NULL;
  604. /* free consistent DMA area... */
  605. if (priv->driver_mem_address)
  606. pci_free_consistent(priv->pdev, HOST_MEM_BLOCK,
  607. priv->driver_mem_address,
  608. priv->device_host_address);
  609. /* clear some dangling pointers */
  610. priv->driver_mem_address = NULL;
  611. priv->device_host_address = 0;
  612. priv->device_psm_buffer = 0;
  613. priv->control_block = NULL;
  614. /* clean up mgmt rx buffers */
  615. for (counter = 0; counter < ISL38XX_CB_MGMT_QSIZE; counter++) {
  616. struct islpci_membuf *buf = &priv->mgmt_rx[counter];
  617. if (buf->pci_addr)
  618. pci_unmap_single(priv->pdev, buf->pci_addr,
  619. buf->size, PCI_DMA_FROMDEVICE);
  620. buf->pci_addr = 0;
  621. kfree(buf->mem);
  622. buf->size = 0;
  623. buf->mem = NULL;
  624. }
  625. /* clean up data rx buffers */
  626. for (counter = 0; counter < ISL38XX_CB_RX_QSIZE; counter++) {
  627. if (priv->pci_map_rx_address[counter])
  628. pci_unmap_single(priv->pdev,
  629. priv->pci_map_rx_address[counter],
  630. MAX_FRAGMENT_SIZE_RX + 2,
  631. PCI_DMA_FROMDEVICE);
  632. priv->pci_map_rx_address[counter] = 0;
  633. if (priv->data_low_rx[counter])
  634. dev_kfree_skb(priv->data_low_rx[counter]);
  635. priv->data_low_rx[counter] = NULL;
  636. }
  637. /* Free the acces control list and the WPA list */
  638. prism54_acl_clean(&priv->acl);
  639. prism54_wpa_ie_clean(priv);
  640. mgt_clean(priv);
  641. return 0;
  642. }
  643. #if 0
  644. static void
  645. islpci_set_multicast_list(struct net_device *dev)
  646. {
  647. /* put device into promisc mode and let network layer handle it */
  648. }
  649. #endif
  650. struct net_device *
  651. islpci_setup(struct pci_dev *pdev)
  652. {
  653. islpci_private *priv;
  654. struct net_device *ndev = alloc_etherdev(sizeof (islpci_private));
  655. if (!ndev)
  656. return ndev;
  657. SET_MODULE_OWNER(ndev);
  658. pci_set_drvdata(pdev, ndev);
  659. #if defined(SET_NETDEV_DEV)
  660. SET_NETDEV_DEV(ndev, &pdev->dev);
  661. #endif
  662. /* setup the structure members */
  663. ndev->base_addr = pci_resource_start(pdev, 0);
  664. ndev->irq = pdev->irq;
  665. /* initialize the function pointers */
  666. ndev->open = &islpci_open;
  667. ndev->stop = &islpci_close;
  668. ndev->get_stats = &islpci_statistics;
  669. ndev->do_ioctl = &prism54_ioctl;
  670. ndev->wireless_handlers =
  671. (struct iw_handler_def *) &prism54_handler_def;
  672. ndev->hard_start_xmit = &islpci_eth_transmit;
  673. /* ndev->set_multicast_list = &islpci_set_multicast_list; */
  674. ndev->addr_len = ETH_ALEN;
  675. ndev->set_mac_address = &prism54_set_mac_address;
  676. /* Get a non-zero dummy MAC address for nameif. Jean II */
  677. memcpy(ndev->dev_addr, dummy_mac, 6);
  678. #ifdef HAVE_TX_TIMEOUT
  679. ndev->watchdog_timeo = ISLPCI_TX_TIMEOUT;
  680. ndev->tx_timeout = &islpci_eth_tx_timeout;
  681. #endif
  682. /* allocate a private device structure to the network device */
  683. priv = netdev_priv(ndev);
  684. priv->ndev = ndev;
  685. priv->pdev = pdev;
  686. priv->monitor_type = ARPHRD_IEEE80211;
  687. priv->ndev->type = (priv->iw_mode == IW_MODE_MONITOR) ?
  688. priv->monitor_type : ARPHRD_ETHER;
  689. /* Add pointers to enable iwspy support. */
  690. priv->wireless_data.spy_data = &priv->spy_data;
  691. ndev->wireless_data = &priv->wireless_data;
  692. /* save the start and end address of the PCI memory area */
  693. ndev->mem_start = (unsigned long) priv->device_base;
  694. ndev->mem_end = ndev->mem_start + ISL38XX_PCI_MEM_SIZE;
  695. #if VERBOSE > SHOW_ERROR_MESSAGES
  696. DEBUG(SHOW_TRACING, "PCI Memory remapped to 0x%p\n", priv->device_base);
  697. #endif
  698. init_waitqueue_head(&priv->reset_done);
  699. /* init the queue read locks, process wait counter */
  700. sema_init(&priv->mgmt_sem, 1);
  701. priv->mgmt_received = NULL;
  702. init_waitqueue_head(&priv->mgmt_wqueue);
  703. sema_init(&priv->stats_sem, 1);
  704. spin_lock_init(&priv->slock);
  705. /* init state machine with off#1 state */
  706. priv->state = PRV_STATE_OFF;
  707. priv->state_off = 1;
  708. /* initialize workqueue's */
  709. INIT_WORK(&priv->stats_work,
  710. (void (*)(void *)) prism54_update_stats, priv);
  711. priv->stats_timestamp = 0;
  712. INIT_WORK(&priv->reset_task, islpci_do_reset_and_wake, priv);
  713. priv->reset_task_pending = 0;
  714. /* allocate various memory areas */
  715. if (islpci_alloc_memory(priv))
  716. goto do_free_netdev;
  717. /* select the firmware file depending on the device id */
  718. switch (pdev->device) {
  719. case 0x3877:
  720. strcpy(priv->firmware, ISL3877_IMAGE_FILE);
  721. break;
  722. case 0x3886:
  723. strcpy(priv->firmware, ISL3886_IMAGE_FILE);
  724. break;
  725. default:
  726. strcpy(priv->firmware, ISL3890_IMAGE_FILE);
  727. break;
  728. }
  729. if (register_netdev(ndev)) {
  730. DEBUG(SHOW_ERROR_MESSAGES,
  731. "ERROR: register_netdev() failed \n");
  732. goto do_islpci_free_memory;
  733. }
  734. return ndev;
  735. do_islpci_free_memory:
  736. islpci_free_memory(priv);
  737. do_free_netdev:
  738. pci_set_drvdata(pdev, NULL);
  739. free_netdev(ndev);
  740. priv = NULL;
  741. return NULL;
  742. }
  743. islpci_state_t
  744. islpci_set_state(islpci_private *priv, islpci_state_t new_state)
  745. {
  746. islpci_state_t old_state;
  747. /* lock */
  748. old_state = priv->state;
  749. /* this means either a race condition or some serious error in
  750. * the driver code */
  751. switch (new_state) {
  752. case PRV_STATE_OFF:
  753. priv->state_off++;
  754. default:
  755. priv->state = new_state;
  756. break;
  757. case PRV_STATE_PREBOOT:
  758. /* there are actually many off-states, enumerated by
  759. * state_off */
  760. if (old_state == PRV_STATE_OFF)
  761. priv->state_off--;
  762. /* only if hw_unavailable is zero now it means we either
  763. * were in off#1 state, or came here from
  764. * somewhere else */
  765. if (!priv->state_off)
  766. priv->state = new_state;
  767. break;
  768. };
  769. #if 0
  770. printk(KERN_DEBUG "%s: state transition %d -> %d (off#%d)\n",
  771. priv->ndev->name, old_state, new_state, priv->state_off);
  772. #endif
  773. /* invariants */
  774. BUG_ON(priv->state_off < 0);
  775. BUG_ON(priv->state_off && (priv->state != PRV_STATE_OFF));
  776. BUG_ON(!priv->state_off && (priv->state == PRV_STATE_OFF));
  777. /* unlock */
  778. return old_state;
  779. }