lmc_media.c 34 KB

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  1. /* $Id: lmc_media.c,v 1.13 2000/04/11 05:25:26 asj Exp $ */
  2. #include <linux/config.h>
  3. #include <linux/kernel.h>
  4. #include <linux/string.h>
  5. #include <linux/timer.h>
  6. #include <linux/ptrace.h>
  7. #include <linux/errno.h>
  8. #include <linux/ioport.h>
  9. #include <linux/slab.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/pci.h>
  12. #include <linux/in.h>
  13. #include <linux/if_arp.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/skbuff.h>
  17. #include <linux/inet.h>
  18. #include <linux/bitops.h>
  19. #include <net/syncppp.h>
  20. #include <asm/processor.h> /* Processor type for cache alignment. */
  21. #include <asm/io.h>
  22. #include <asm/dma.h>
  23. #include <asm/uaccess.h>
  24. #include "lmc.h"
  25. #include "lmc_var.h"
  26. #include "lmc_ioctl.h"
  27. #include "lmc_debug.h"
  28. #define CONFIG_LMC_IGNORE_HARDWARE_HANDSHAKE 1
  29. /*
  30. * Copyright (c) 1997-2000 LAN Media Corporation (LMC)
  31. * All rights reserved. www.lanmedia.com
  32. *
  33. * This code is written by:
  34. * Andrew Stanley-Jones (asj@cban.com)
  35. * Rob Braun (bbraun@vix.com),
  36. * Michael Graff (explorer@vix.com) and
  37. * Matt Thomas (matt@3am-software.com).
  38. *
  39. * This software may be used and distributed according to the terms
  40. * of the GNU General Public License version 2, incorporated herein by reference.
  41. */
  42. /*
  43. * protocol independent method.
  44. */
  45. static void lmc_set_protocol (lmc_softc_t * const, lmc_ctl_t *);
  46. /*
  47. * media independent methods to check on media status, link, light LEDs,
  48. * etc.
  49. */
  50. static void lmc_ds3_init (lmc_softc_t * const);
  51. static void lmc_ds3_default (lmc_softc_t * const);
  52. static void lmc_ds3_set_status (lmc_softc_t * const, lmc_ctl_t *);
  53. static void lmc_ds3_set_100ft (lmc_softc_t * const, int);
  54. static int lmc_ds3_get_link_status (lmc_softc_t * const);
  55. static void lmc_ds3_set_crc_length (lmc_softc_t * const, int);
  56. static void lmc_ds3_set_scram (lmc_softc_t * const, int);
  57. static void lmc_ds3_watchdog (lmc_softc_t * const);
  58. static void lmc_hssi_init (lmc_softc_t * const);
  59. static void lmc_hssi_default (lmc_softc_t * const);
  60. static void lmc_hssi_set_status (lmc_softc_t * const, lmc_ctl_t *);
  61. static void lmc_hssi_set_clock (lmc_softc_t * const, int);
  62. static int lmc_hssi_get_link_status (lmc_softc_t * const);
  63. static void lmc_hssi_set_link_status (lmc_softc_t * const, int);
  64. static void lmc_hssi_set_crc_length (lmc_softc_t * const, int);
  65. static void lmc_hssi_watchdog (lmc_softc_t * const);
  66. static void lmc_ssi_init (lmc_softc_t * const);
  67. static void lmc_ssi_default (lmc_softc_t * const);
  68. static void lmc_ssi_set_status (lmc_softc_t * const, lmc_ctl_t *);
  69. static void lmc_ssi_set_clock (lmc_softc_t * const, int);
  70. static void lmc_ssi_set_speed (lmc_softc_t * const, lmc_ctl_t *);
  71. static int lmc_ssi_get_link_status (lmc_softc_t * const);
  72. static void lmc_ssi_set_link_status (lmc_softc_t * const, int);
  73. static void lmc_ssi_set_crc_length (lmc_softc_t * const, int);
  74. static void lmc_ssi_watchdog (lmc_softc_t * const);
  75. static void lmc_t1_init (lmc_softc_t * const);
  76. static void lmc_t1_default (lmc_softc_t * const);
  77. static void lmc_t1_set_status (lmc_softc_t * const, lmc_ctl_t *);
  78. static int lmc_t1_get_link_status (lmc_softc_t * const);
  79. static void lmc_t1_set_circuit_type (lmc_softc_t * const, int);
  80. static void lmc_t1_set_crc_length (lmc_softc_t * const, int);
  81. static void lmc_t1_set_clock (lmc_softc_t * const, int);
  82. static void lmc_t1_watchdog (lmc_softc_t * const);
  83. static void lmc_dummy_set_1 (lmc_softc_t * const, int);
  84. static void lmc_dummy_set2_1 (lmc_softc_t * const, lmc_ctl_t *);
  85. static inline void write_av9110_bit (lmc_softc_t *, int);
  86. static void write_av9110 (lmc_softc_t *, u_int32_t, u_int32_t, u_int32_t,
  87. u_int32_t, u_int32_t);
  88. lmc_media_t lmc_ds3_media = {
  89. lmc_ds3_init, /* special media init stuff */
  90. lmc_ds3_default, /* reset to default state */
  91. lmc_ds3_set_status, /* reset status to state provided */
  92. lmc_dummy_set_1, /* set clock source */
  93. lmc_dummy_set2_1, /* set line speed */
  94. lmc_ds3_set_100ft, /* set cable length */
  95. lmc_ds3_set_scram, /* set scrambler */
  96. lmc_ds3_get_link_status, /* get link status */
  97. lmc_dummy_set_1, /* set link status */
  98. lmc_ds3_set_crc_length, /* set CRC length */
  99. lmc_dummy_set_1, /* set T1 or E1 circuit type */
  100. lmc_ds3_watchdog
  101. };
  102. lmc_media_t lmc_hssi_media = {
  103. lmc_hssi_init, /* special media init stuff */
  104. lmc_hssi_default, /* reset to default state */
  105. lmc_hssi_set_status, /* reset status to state provided */
  106. lmc_hssi_set_clock, /* set clock source */
  107. lmc_dummy_set2_1, /* set line speed */
  108. lmc_dummy_set_1, /* set cable length */
  109. lmc_dummy_set_1, /* set scrambler */
  110. lmc_hssi_get_link_status, /* get link status */
  111. lmc_hssi_set_link_status, /* set link status */
  112. lmc_hssi_set_crc_length, /* set CRC length */
  113. lmc_dummy_set_1, /* set T1 or E1 circuit type */
  114. lmc_hssi_watchdog
  115. };
  116. lmc_media_t lmc_ssi_media = { lmc_ssi_init, /* special media init stuff */
  117. lmc_ssi_default, /* reset to default state */
  118. lmc_ssi_set_status, /* reset status to state provided */
  119. lmc_ssi_set_clock, /* set clock source */
  120. lmc_ssi_set_speed, /* set line speed */
  121. lmc_dummy_set_1, /* set cable length */
  122. lmc_dummy_set_1, /* set scrambler */
  123. lmc_ssi_get_link_status, /* get link status */
  124. lmc_ssi_set_link_status, /* set link status */
  125. lmc_ssi_set_crc_length, /* set CRC length */
  126. lmc_dummy_set_1, /* set T1 or E1 circuit type */
  127. lmc_ssi_watchdog
  128. };
  129. lmc_media_t lmc_t1_media = {
  130. lmc_t1_init, /* special media init stuff */
  131. lmc_t1_default, /* reset to default state */
  132. lmc_t1_set_status, /* reset status to state provided */
  133. lmc_t1_set_clock, /* set clock source */
  134. lmc_dummy_set2_1, /* set line speed */
  135. lmc_dummy_set_1, /* set cable length */
  136. lmc_dummy_set_1, /* set scrambler */
  137. lmc_t1_get_link_status, /* get link status */
  138. lmc_dummy_set_1, /* set link status */
  139. lmc_t1_set_crc_length, /* set CRC length */
  140. lmc_t1_set_circuit_type, /* set T1 or E1 circuit type */
  141. lmc_t1_watchdog
  142. };
  143. static void
  144. lmc_dummy_set_1 (lmc_softc_t * const sc, int a)
  145. {
  146. }
  147. static void
  148. lmc_dummy_set2_1 (lmc_softc_t * const sc, lmc_ctl_t * a)
  149. {
  150. }
  151. /*
  152. * HSSI methods
  153. */
  154. static void
  155. lmc_hssi_init (lmc_softc_t * const sc)
  156. {
  157. sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5200;
  158. lmc_gpio_mkoutput (sc, LMC_GEP_HSSI_CLOCK);
  159. }
  160. static void
  161. lmc_hssi_default (lmc_softc_t * const sc)
  162. {
  163. sc->lmc_miireg16 = LMC_MII16_LED_ALL;
  164. sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
  165. sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
  166. sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
  167. }
  168. /*
  169. * Given a user provided state, set ourselves up to match it. This will
  170. * always reset the card if needed.
  171. */
  172. static void
  173. lmc_hssi_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
  174. {
  175. if (ctl == NULL)
  176. {
  177. sc->lmc_media->set_clock_source (sc, sc->ictl.clock_source);
  178. lmc_set_protocol (sc, NULL);
  179. return;
  180. }
  181. /*
  182. * check for change in clock source
  183. */
  184. if (ctl->clock_source && !sc->ictl.clock_source)
  185. {
  186. sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_INT);
  187. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_INT;
  188. }
  189. else if (!ctl->clock_source && sc->ictl.clock_source)
  190. {
  191. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  192. sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
  193. }
  194. lmc_set_protocol (sc, ctl);
  195. }
  196. /*
  197. * 1 == internal, 0 == external
  198. */
  199. static void
  200. lmc_hssi_set_clock (lmc_softc_t * const sc, int ie)
  201. {
  202. int old;
  203. old = sc->ictl.clock_source;
  204. if (ie == LMC_CTL_CLOCK_SOURCE_EXT)
  205. {
  206. sc->lmc_gpio |= LMC_GEP_HSSI_CLOCK;
  207. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  208. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
  209. if(old != ie)
  210. printk (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS);
  211. }
  212. else
  213. {
  214. sc->lmc_gpio &= ~(LMC_GEP_HSSI_CLOCK);
  215. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  216. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
  217. if(old != ie)
  218. printk (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS);
  219. }
  220. }
  221. /*
  222. * return hardware link status.
  223. * 0 == link is down, 1 == link is up.
  224. */
  225. static int
  226. lmc_hssi_get_link_status (lmc_softc_t * const sc)
  227. {
  228. /*
  229. * We're using the same code as SSI since
  230. * they're practically the same
  231. */
  232. return lmc_ssi_get_link_status(sc);
  233. }
  234. static void
  235. lmc_hssi_set_link_status (lmc_softc_t * const sc, int state)
  236. {
  237. if (state == LMC_LINK_UP)
  238. sc->lmc_miireg16 |= LMC_MII16_HSSI_TA;
  239. else
  240. sc->lmc_miireg16 &= ~LMC_MII16_HSSI_TA;
  241. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  242. }
  243. /*
  244. * 0 == 16bit, 1 == 32bit
  245. */
  246. static void
  247. lmc_hssi_set_crc_length (lmc_softc_t * const sc, int state)
  248. {
  249. if (state == LMC_CTL_CRC_LENGTH_32)
  250. {
  251. /* 32 bit */
  252. sc->lmc_miireg16 |= LMC_MII16_HSSI_CRC;
  253. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
  254. }
  255. else
  256. {
  257. /* 16 bit */
  258. sc->lmc_miireg16 &= ~LMC_MII16_HSSI_CRC;
  259. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
  260. }
  261. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  262. }
  263. static void
  264. lmc_hssi_watchdog (lmc_softc_t * const sc)
  265. {
  266. /* HSSI is blank */
  267. }
  268. /*
  269. * DS3 methods
  270. */
  271. /*
  272. * Set cable length
  273. */
  274. static void
  275. lmc_ds3_set_100ft (lmc_softc_t * const sc, int ie)
  276. {
  277. if (ie == LMC_CTL_CABLE_LENGTH_GT_100FT)
  278. {
  279. sc->lmc_miireg16 &= ~LMC_MII16_DS3_ZERO;
  280. sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_GT_100FT;
  281. }
  282. else if (ie == LMC_CTL_CABLE_LENGTH_LT_100FT)
  283. {
  284. sc->lmc_miireg16 |= LMC_MII16_DS3_ZERO;
  285. sc->ictl.cable_length = LMC_CTL_CABLE_LENGTH_LT_100FT;
  286. }
  287. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  288. }
  289. static void
  290. lmc_ds3_default (lmc_softc_t * const sc)
  291. {
  292. sc->lmc_miireg16 = LMC_MII16_LED_ALL;
  293. sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
  294. sc->lmc_media->set_cable_length (sc, LMC_CTL_CABLE_LENGTH_LT_100FT);
  295. sc->lmc_media->set_scrambler (sc, LMC_CTL_OFF);
  296. sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
  297. }
  298. /*
  299. * Given a user provided state, set ourselves up to match it. This will
  300. * always reset the card if needed.
  301. */
  302. static void
  303. lmc_ds3_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
  304. {
  305. if (ctl == NULL)
  306. {
  307. sc->lmc_media->set_cable_length (sc, sc->ictl.cable_length);
  308. sc->lmc_media->set_scrambler (sc, sc->ictl.scrambler_onoff);
  309. lmc_set_protocol (sc, NULL);
  310. return;
  311. }
  312. /*
  313. * check for change in cable length setting
  314. */
  315. if (ctl->cable_length && !sc->ictl.cable_length)
  316. lmc_ds3_set_100ft (sc, LMC_CTL_CABLE_LENGTH_GT_100FT);
  317. else if (!ctl->cable_length && sc->ictl.cable_length)
  318. lmc_ds3_set_100ft (sc, LMC_CTL_CABLE_LENGTH_LT_100FT);
  319. /*
  320. * Check for change in scrambler setting (requires reset)
  321. */
  322. if (ctl->scrambler_onoff && !sc->ictl.scrambler_onoff)
  323. lmc_ds3_set_scram (sc, LMC_CTL_ON);
  324. else if (!ctl->scrambler_onoff && sc->ictl.scrambler_onoff)
  325. lmc_ds3_set_scram (sc, LMC_CTL_OFF);
  326. lmc_set_protocol (sc, ctl);
  327. }
  328. static void
  329. lmc_ds3_init (lmc_softc_t * const sc)
  330. {
  331. int i;
  332. sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC5245;
  333. /* writes zeros everywhere */
  334. for (i = 0; i < 21; i++)
  335. {
  336. lmc_mii_writereg (sc, 0, 17, i);
  337. lmc_mii_writereg (sc, 0, 18, 0);
  338. }
  339. /* set some essential bits */
  340. lmc_mii_writereg (sc, 0, 17, 1);
  341. lmc_mii_writereg (sc, 0, 18, 0x25); /* ser, xtx */
  342. lmc_mii_writereg (sc, 0, 17, 5);
  343. lmc_mii_writereg (sc, 0, 18, 0x80); /* emode */
  344. lmc_mii_writereg (sc, 0, 17, 14);
  345. lmc_mii_writereg (sc, 0, 18, 0x30); /* rcgen, tcgen */
  346. /* clear counters and latched bits */
  347. for (i = 0; i < 21; i++)
  348. {
  349. lmc_mii_writereg (sc, 0, 17, i);
  350. lmc_mii_readreg (sc, 0, 18);
  351. }
  352. }
  353. /*
  354. * 1 == DS3 payload scrambled, 0 == not scrambled
  355. */
  356. static void
  357. lmc_ds3_set_scram (lmc_softc_t * const sc, int ie)
  358. {
  359. if (ie == LMC_CTL_ON)
  360. {
  361. sc->lmc_miireg16 |= LMC_MII16_DS3_SCRAM;
  362. sc->ictl.scrambler_onoff = LMC_CTL_ON;
  363. }
  364. else
  365. {
  366. sc->lmc_miireg16 &= ~LMC_MII16_DS3_SCRAM;
  367. sc->ictl.scrambler_onoff = LMC_CTL_OFF;
  368. }
  369. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  370. }
  371. /*
  372. * return hardware link status.
  373. * 0 == link is down, 1 == link is up.
  374. */
  375. static int
  376. lmc_ds3_get_link_status (lmc_softc_t * const sc)
  377. {
  378. u_int16_t link_status, link_status_11;
  379. int ret = 1;
  380. lmc_mii_writereg (sc, 0, 17, 7);
  381. link_status = lmc_mii_readreg (sc, 0, 18);
  382. /* LMC5245 (DS3) & LMC1200 (DS1) LED definitions
  383. * led0 yellow = far-end adapter is in Red alarm condition
  384. * led1 blue = received an Alarm Indication signal
  385. * (upstream failure)
  386. * led2 Green = power to adapter, Gate Array loaded & driver
  387. * attached
  388. * led3 red = Loss of Signal (LOS) or out of frame (OOF)
  389. * conditions detected on T3 receive signal
  390. */
  391. lmc_led_on(sc, LMC_DS3_LED2);
  392. if ((link_status & LMC_FRAMER_REG0_DLOS) ||
  393. (link_status & LMC_FRAMER_REG0_OOFS)){
  394. ret = 0;
  395. if(sc->last_led_err[3] != 1){
  396. u16 r1;
  397. lmc_mii_writereg (sc, 0, 17, 01); /* Turn on Xbit error as our cisco does */
  398. r1 = lmc_mii_readreg (sc, 0, 18);
  399. r1 &= 0xfe;
  400. lmc_mii_writereg(sc, 0, 18, r1);
  401. printk(KERN_WARNING "%s: Red Alarm - Loss of Signal or Loss of Framing\n", sc->name);
  402. }
  403. lmc_led_on(sc, LMC_DS3_LED3); /* turn on red LED */
  404. sc->last_led_err[3] = 1;
  405. }
  406. else {
  407. lmc_led_off(sc, LMC_DS3_LED3); /* turn on red LED */
  408. if(sc->last_led_err[3] == 1){
  409. u16 r1;
  410. lmc_mii_writereg (sc, 0, 17, 01); /* Turn off Xbit error */
  411. r1 = lmc_mii_readreg (sc, 0, 18);
  412. r1 |= 0x01;
  413. lmc_mii_writereg(sc, 0, 18, r1);
  414. }
  415. sc->last_led_err[3] = 0;
  416. }
  417. lmc_mii_writereg(sc, 0, 17, 0x10);
  418. link_status_11 = lmc_mii_readreg(sc, 0, 18);
  419. if((link_status & LMC_FRAMER_REG0_AIS) ||
  420. (link_status_11 & LMC_FRAMER_REG10_XBIT)) {
  421. ret = 0;
  422. if(sc->last_led_err[0] != 1){
  423. printk(KERN_WARNING "%s: AIS Alarm or XBit Error\n", sc->name);
  424. printk(KERN_WARNING "%s: Remote end has loss of signal or framing\n", sc->name);
  425. }
  426. lmc_led_on(sc, LMC_DS3_LED0);
  427. sc->last_led_err[0] = 1;
  428. }
  429. else {
  430. lmc_led_off(sc, LMC_DS3_LED0);
  431. sc->last_led_err[0] = 0;
  432. }
  433. lmc_mii_writereg (sc, 0, 17, 9);
  434. link_status = lmc_mii_readreg (sc, 0, 18);
  435. if(link_status & LMC_FRAMER_REG9_RBLUE){
  436. ret = 0;
  437. if(sc->last_led_err[1] != 1){
  438. printk(KERN_WARNING "%s: Blue Alarm - Receiving all 1's\n", sc->name);
  439. }
  440. lmc_led_on(sc, LMC_DS3_LED1);
  441. sc->last_led_err[1] = 1;
  442. }
  443. else {
  444. lmc_led_off(sc, LMC_DS3_LED1);
  445. sc->last_led_err[1] = 0;
  446. }
  447. return ret;
  448. }
  449. /*
  450. * 0 == 16bit, 1 == 32bit
  451. */
  452. static void
  453. lmc_ds3_set_crc_length (lmc_softc_t * const sc, int state)
  454. {
  455. if (state == LMC_CTL_CRC_LENGTH_32)
  456. {
  457. /* 32 bit */
  458. sc->lmc_miireg16 |= LMC_MII16_DS3_CRC;
  459. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
  460. }
  461. else
  462. {
  463. /* 16 bit */
  464. sc->lmc_miireg16 &= ~LMC_MII16_DS3_CRC;
  465. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
  466. }
  467. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  468. }
  469. static void
  470. lmc_ds3_watchdog (lmc_softc_t * const sc)
  471. {
  472. }
  473. /*
  474. * SSI methods
  475. */
  476. static void
  477. lmc_ssi_init (lmc_softc_t * const sc)
  478. {
  479. u_int16_t mii17;
  480. int cable;
  481. sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1000;
  482. mii17 = lmc_mii_readreg (sc, 0, 17);
  483. cable = (mii17 & LMC_MII17_SSI_CABLE_MASK) >> LMC_MII17_SSI_CABLE_SHIFT;
  484. sc->ictl.cable_type = cable;
  485. lmc_gpio_mkoutput (sc, LMC_GEP_SSI_TXCLOCK);
  486. }
  487. static void
  488. lmc_ssi_default (lmc_softc_t * const sc)
  489. {
  490. sc->lmc_miireg16 = LMC_MII16_LED_ALL;
  491. /*
  492. * make TXCLOCK always be an output
  493. */
  494. lmc_gpio_mkoutput (sc, LMC_GEP_SSI_TXCLOCK);
  495. sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
  496. sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
  497. sc->lmc_media->set_speed (sc, NULL);
  498. sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
  499. }
  500. /*
  501. * Given a user provided state, set ourselves up to match it. This will
  502. * always reset the card if needed.
  503. */
  504. static void
  505. lmc_ssi_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
  506. {
  507. if (ctl == NULL)
  508. {
  509. sc->lmc_media->set_clock_source (sc, sc->ictl.clock_source);
  510. sc->lmc_media->set_speed (sc, &sc->ictl);
  511. lmc_set_protocol (sc, NULL);
  512. return;
  513. }
  514. /*
  515. * check for change in clock source
  516. */
  517. if (ctl->clock_source == LMC_CTL_CLOCK_SOURCE_INT
  518. && sc->ictl.clock_source == LMC_CTL_CLOCK_SOURCE_EXT)
  519. {
  520. sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_INT);
  521. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_INT;
  522. }
  523. else if (ctl->clock_source == LMC_CTL_CLOCK_SOURCE_EXT
  524. && sc->ictl.clock_source == LMC_CTL_CLOCK_SOURCE_INT)
  525. {
  526. sc->lmc_media->set_clock_source (sc, LMC_CTL_CLOCK_SOURCE_EXT);
  527. sc->lmc_timing = LMC_CTL_CLOCK_SOURCE_EXT;
  528. }
  529. if (ctl->clock_rate != sc->ictl.clock_rate)
  530. sc->lmc_media->set_speed (sc, ctl);
  531. lmc_set_protocol (sc, ctl);
  532. }
  533. /*
  534. * 1 == internal, 0 == external
  535. */
  536. static void
  537. lmc_ssi_set_clock (lmc_softc_t * const sc, int ie)
  538. {
  539. int old;
  540. old = ie;
  541. if (ie == LMC_CTL_CLOCK_SOURCE_EXT)
  542. {
  543. sc->lmc_gpio &= ~(LMC_GEP_SSI_TXCLOCK);
  544. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  545. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
  546. if(ie != old)
  547. printk (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS);
  548. }
  549. else
  550. {
  551. sc->lmc_gpio |= LMC_GEP_SSI_TXCLOCK;
  552. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  553. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
  554. if(ie != old)
  555. printk (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS);
  556. }
  557. }
  558. static void
  559. lmc_ssi_set_speed (lmc_softc_t * const sc, lmc_ctl_t * ctl)
  560. {
  561. lmc_ctl_t *ictl = &sc->ictl;
  562. lmc_av9110_t *av;
  563. /* original settings for clock rate of:
  564. * 100 Khz (8,25,0,0,2) were incorrect
  565. * they should have been 80,125,1,3,3
  566. * There are 17 param combinations to produce this freq.
  567. * For 1.5 Mhz use 120,100,1,1,2 (226 param. combinations)
  568. */
  569. if (ctl == NULL)
  570. {
  571. av = &ictl->cardspec.ssi;
  572. ictl->clock_rate = 1500000;
  573. av->f = ictl->clock_rate;
  574. av->n = 120;
  575. av->m = 100;
  576. av->v = 1;
  577. av->x = 1;
  578. av->r = 2;
  579. write_av9110 (sc, av->n, av->m, av->v, av->x, av->r);
  580. return;
  581. }
  582. av = &ctl->cardspec.ssi;
  583. if (av->f == 0)
  584. return;
  585. ictl->clock_rate = av->f; /* really, this is the rate we are */
  586. ictl->cardspec.ssi = *av;
  587. write_av9110 (sc, av->n, av->m, av->v, av->x, av->r);
  588. }
  589. /*
  590. * return hardware link status.
  591. * 0 == link is down, 1 == link is up.
  592. */
  593. static int
  594. lmc_ssi_get_link_status (lmc_softc_t * const sc)
  595. {
  596. u_int16_t link_status;
  597. u_int32_t ticks;
  598. int ret = 1;
  599. int hw_hdsk = 1;
  600. /*
  601. * missing CTS? Hmm. If we require CTS on, we may never get the
  602. * link to come up, so omit it in this test.
  603. *
  604. * Also, it seems that with a loopback cable, DCD isn't asserted,
  605. * so just check for things like this:
  606. * DSR _must_ be asserted.
  607. * One of DCD or CTS must be asserted.
  608. */
  609. /* LMC 1000 (SSI) LED definitions
  610. * led0 Green = power to adapter, Gate Array loaded &
  611. * driver attached
  612. * led1 Green = DSR and DTR and RTS and CTS are set
  613. * led2 Green = Cable detected
  614. * led3 red = No timing is available from the
  615. * cable or the on-board frequency
  616. * generator.
  617. */
  618. link_status = lmc_mii_readreg (sc, 0, 16);
  619. /* Is the transmit clock still available */
  620. ticks = LMC_CSR_READ (sc, csr_gp_timer);
  621. ticks = 0x0000ffff - (ticks & 0x0000ffff);
  622. lmc_led_on (sc, LMC_MII16_LED0);
  623. /* ====== transmit clock determination ===== */
  624. if (sc->lmc_timing == LMC_CTL_CLOCK_SOURCE_INT) {
  625. lmc_led_off(sc, LMC_MII16_LED3);
  626. }
  627. else if (ticks == 0 ) { /* no clock found ? */
  628. ret = 0;
  629. if(sc->last_led_err[3] != 1){
  630. sc->stats.tx_lossOfClockCnt++;
  631. printk(KERN_WARNING "%s: Lost Clock, Link Down\n", sc->name);
  632. }
  633. sc->last_led_err[3] = 1;
  634. lmc_led_on (sc, LMC_MII16_LED3); /* turn ON red LED */
  635. }
  636. else {
  637. if(sc->last_led_err[3] == 1)
  638. printk(KERN_WARNING "%s: Clock Returned\n", sc->name);
  639. sc->last_led_err[3] = 0;
  640. lmc_led_off (sc, LMC_MII16_LED3); /* turn OFF red LED */
  641. }
  642. if ((link_status & LMC_MII16_SSI_DSR) == 0) { /* Also HSSI CA */
  643. ret = 0;
  644. hw_hdsk = 0;
  645. }
  646. #ifdef CONFIG_LMC_IGNORE_HARDWARE_HANDSHAKE
  647. if ((link_status & (LMC_MII16_SSI_CTS | LMC_MII16_SSI_DCD)) == 0){
  648. ret = 0;
  649. hw_hdsk = 0;
  650. }
  651. #endif
  652. if(hw_hdsk == 0){
  653. if(sc->last_led_err[1] != 1)
  654. printk(KERN_WARNING "%s: DSR not asserted\n", sc->name);
  655. sc->last_led_err[1] = 1;
  656. lmc_led_off(sc, LMC_MII16_LED1);
  657. }
  658. else {
  659. if(sc->last_led_err[1] != 0)
  660. printk(KERN_WARNING "%s: DSR now asserted\n", sc->name);
  661. sc->last_led_err[1] = 0;
  662. lmc_led_on(sc, LMC_MII16_LED1);
  663. }
  664. if(ret == 1) {
  665. lmc_led_on(sc, LMC_MII16_LED2); /* Over all good status? */
  666. }
  667. return ret;
  668. }
  669. static void
  670. lmc_ssi_set_link_status (lmc_softc_t * const sc, int state)
  671. {
  672. if (state == LMC_LINK_UP)
  673. {
  674. sc->lmc_miireg16 |= (LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS);
  675. printk (LMC_PRINTF_FMT ": asserting DTR and RTS\n", LMC_PRINTF_ARGS);
  676. }
  677. else
  678. {
  679. sc->lmc_miireg16 &= ~(LMC_MII16_SSI_DTR | LMC_MII16_SSI_RTS);
  680. printk (LMC_PRINTF_FMT ": deasserting DTR and RTS\n", LMC_PRINTF_ARGS);
  681. }
  682. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  683. }
  684. /*
  685. * 0 == 16bit, 1 == 32bit
  686. */
  687. static void
  688. lmc_ssi_set_crc_length (lmc_softc_t * const sc, int state)
  689. {
  690. if (state == LMC_CTL_CRC_LENGTH_32)
  691. {
  692. /* 32 bit */
  693. sc->lmc_miireg16 |= LMC_MII16_SSI_CRC;
  694. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
  695. sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4;
  696. }
  697. else
  698. {
  699. /* 16 bit */
  700. sc->lmc_miireg16 &= ~LMC_MII16_SSI_CRC;
  701. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
  702. sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2;
  703. }
  704. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  705. }
  706. /*
  707. * These are bits to program the ssi frequency generator
  708. */
  709. static inline void
  710. write_av9110_bit (lmc_softc_t * sc, int c)
  711. {
  712. /*
  713. * set the data bit as we need it.
  714. */
  715. sc->lmc_gpio &= ~(LMC_GEP_CLK);
  716. if (c & 0x01)
  717. sc->lmc_gpio |= LMC_GEP_DATA;
  718. else
  719. sc->lmc_gpio &= ~(LMC_GEP_DATA);
  720. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  721. /*
  722. * set the clock to high
  723. */
  724. sc->lmc_gpio |= LMC_GEP_CLK;
  725. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  726. /*
  727. * set the clock to low again.
  728. */
  729. sc->lmc_gpio &= ~(LMC_GEP_CLK);
  730. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  731. }
  732. static void
  733. write_av9110 (lmc_softc_t * sc, u_int32_t n, u_int32_t m, u_int32_t v,
  734. u_int32_t x, u_int32_t r)
  735. {
  736. int i;
  737. #if 0
  738. printk (LMC_PRINTF_FMT ": speed %u, %d %d %d %d %d\n",
  739. LMC_PRINTF_ARGS, sc->ictl.clock_rate, n, m, v, x, r);
  740. #endif
  741. sc->lmc_gpio |= LMC_GEP_SSI_GENERATOR;
  742. sc->lmc_gpio &= ~(LMC_GEP_DATA | LMC_GEP_CLK);
  743. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  744. /*
  745. * Set the TXCLOCK, GENERATOR, SERIAL, and SERIALCLK
  746. * as outputs.
  747. */
  748. lmc_gpio_mkoutput (sc, (LMC_GEP_DATA | LMC_GEP_CLK
  749. | LMC_GEP_SSI_GENERATOR));
  750. sc->lmc_gpio &= ~(LMC_GEP_SSI_GENERATOR);
  751. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  752. /*
  753. * a shifting we will go...
  754. */
  755. for (i = 0; i < 7; i++)
  756. write_av9110_bit (sc, n >> i);
  757. for (i = 0; i < 7; i++)
  758. write_av9110_bit (sc, m >> i);
  759. for (i = 0; i < 1; i++)
  760. write_av9110_bit (sc, v >> i);
  761. for (i = 0; i < 2; i++)
  762. write_av9110_bit (sc, x >> i);
  763. for (i = 0; i < 2; i++)
  764. write_av9110_bit (sc, r >> i);
  765. for (i = 0; i < 5; i++)
  766. write_av9110_bit (sc, 0x17 >> i);
  767. /*
  768. * stop driving serial-related signals
  769. */
  770. lmc_gpio_mkinput (sc,
  771. (LMC_GEP_DATA | LMC_GEP_CLK
  772. | LMC_GEP_SSI_GENERATOR));
  773. }
  774. static void
  775. lmc_ssi_watchdog (lmc_softc_t * const sc)
  776. {
  777. u_int16_t mii17;
  778. struct ssicsr2
  779. {
  780. unsigned short dtr:1, dsr:1, rts:1, cable:3, crc:1, led0:1, led1:1,
  781. led2:1, led3:1, fifo:1, ll:1, rl:1, tm:1, loop:1;
  782. };
  783. struct ssicsr2 *ssicsr;
  784. mii17 = lmc_mii_readreg (sc, 0, 17);
  785. ssicsr = (struct ssicsr2 *) &mii17;
  786. if (ssicsr->cable == 7)
  787. {
  788. lmc_led_off (sc, LMC_MII16_LED2);
  789. }
  790. else
  791. {
  792. lmc_led_on (sc, LMC_MII16_LED2);
  793. }
  794. }
  795. /*
  796. * T1 methods
  797. */
  798. /*
  799. * The framer regs are multiplexed through MII regs 17 & 18
  800. * write the register address to MII reg 17 and the * data to MII reg 18. */
  801. static void
  802. lmc_t1_write (lmc_softc_t * const sc, int a, int d)
  803. {
  804. lmc_mii_writereg (sc, 0, 17, a);
  805. lmc_mii_writereg (sc, 0, 18, d);
  806. }
  807. /* Save a warning
  808. static int
  809. lmc_t1_read (lmc_softc_t * const sc, int a)
  810. {
  811. lmc_mii_writereg (sc, 0, 17, a);
  812. return lmc_mii_readreg (sc, 0, 18);
  813. }
  814. */
  815. static void
  816. lmc_t1_init (lmc_softc_t * const sc)
  817. {
  818. u_int16_t mii16;
  819. int i;
  820. sc->ictl.cardtype = LMC_CTL_CARDTYPE_LMC1200;
  821. mii16 = lmc_mii_readreg (sc, 0, 16);
  822. /* reset 8370 */
  823. mii16 &= ~LMC_MII16_T1_RST;
  824. lmc_mii_writereg (sc, 0, 16, mii16 | LMC_MII16_T1_RST);
  825. lmc_mii_writereg (sc, 0, 16, mii16);
  826. /* set T1 or E1 line. Uses sc->lmcmii16 reg in function so update it */
  827. sc->lmc_miireg16 = mii16;
  828. lmc_t1_set_circuit_type(sc, LMC_CTL_CIRCUIT_TYPE_T1);
  829. mii16 = sc->lmc_miireg16;
  830. lmc_t1_write (sc, 0x01, 0x1B); /* CR0 - primary control */
  831. lmc_t1_write (sc, 0x02, 0x42); /* JAT_CR - jitter atten config */
  832. lmc_t1_write (sc, 0x14, 0x00); /* LOOP - loopback config */
  833. lmc_t1_write (sc, 0x15, 0x00); /* DL3_TS - external data link timeslot */
  834. lmc_t1_write (sc, 0x18, 0xFF); /* PIO - programmable I/O */
  835. lmc_t1_write (sc, 0x19, 0x30); /* POE - programmable OE */
  836. lmc_t1_write (sc, 0x1A, 0x0F); /* CMUX - clock input mux */
  837. lmc_t1_write (sc, 0x20, 0x41); /* LIU_CR - RX LIU config */
  838. lmc_t1_write (sc, 0x22, 0x76); /* RLIU_CR - RX LIU config */
  839. lmc_t1_write (sc, 0x40, 0x03); /* RCR0 - RX config */
  840. lmc_t1_write (sc, 0x45, 0x00); /* RALM - RX alarm config */
  841. lmc_t1_write (sc, 0x46, 0x05); /* LATCH - RX alarm/err/cntr latch */
  842. lmc_t1_write (sc, 0x68, 0x40); /* TLIU_CR - TX LIU config */
  843. lmc_t1_write (sc, 0x70, 0x0D); /* TCR0 - TX framer config */
  844. lmc_t1_write (sc, 0x71, 0x05); /* TCR1 - TX config */
  845. lmc_t1_write (sc, 0x72, 0x0B); /* TFRM - TX frame format */
  846. lmc_t1_write (sc, 0x73, 0x00); /* TERROR - TX error insert */
  847. lmc_t1_write (sc, 0x74, 0x00); /* TMAN - TX manual Sa/FEBE config */
  848. lmc_t1_write (sc, 0x75, 0x00); /* TALM - TX alarm signal config */
  849. lmc_t1_write (sc, 0x76, 0x00); /* TPATT - TX test pattern config */
  850. lmc_t1_write (sc, 0x77, 0x00); /* TLB - TX inband loopback config */
  851. lmc_t1_write (sc, 0x90, 0x05); /* CLAD_CR - clock rate adapter config */
  852. lmc_t1_write (sc, 0x91, 0x05); /* CSEL - clad freq sel */
  853. lmc_t1_write (sc, 0xA6, 0x00); /* DL1_CTL - DL1 control */
  854. lmc_t1_write (sc, 0xB1, 0x00); /* DL2_CTL - DL2 control */
  855. lmc_t1_write (sc, 0xD0, 0x47); /* SBI_CR - sys bus iface config */
  856. lmc_t1_write (sc, 0xD1, 0x70); /* RSB_CR - RX sys bus config */
  857. lmc_t1_write (sc, 0xD4, 0x30); /* TSB_CR - TX sys bus config */
  858. for (i = 0; i < 32; i++)
  859. {
  860. lmc_t1_write (sc, 0x0E0 + i, 0x00); /* SBCn - sys bus per-channel ctl */
  861. lmc_t1_write (sc, 0x100 + i, 0x00); /* TPCn - TX per-channel ctl */
  862. lmc_t1_write (sc, 0x180 + i, 0x00); /* RPCn - RX per-channel ctl */
  863. }
  864. for (i = 1; i < 25; i++)
  865. {
  866. lmc_t1_write (sc, 0x0E0 + i, 0x0D); /* SBCn - sys bus per-channel ctl */
  867. }
  868. mii16 |= LMC_MII16_T1_XOE;
  869. lmc_mii_writereg (sc, 0, 16, mii16);
  870. sc->lmc_miireg16 = mii16;
  871. }
  872. static void
  873. lmc_t1_default (lmc_softc_t * const sc)
  874. {
  875. sc->lmc_miireg16 = LMC_MII16_LED_ALL;
  876. sc->lmc_media->set_link_status (sc, LMC_LINK_DOWN);
  877. sc->lmc_media->set_circuit_type (sc, LMC_CTL_CIRCUIT_TYPE_T1);
  878. sc->lmc_media->set_crc_length (sc, LMC_CTL_CRC_LENGTH_16);
  879. /* Right now we can only clock from out internal source */
  880. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
  881. }
  882. /* * Given a user provided state, set ourselves up to match it. This will * always reset the card if needed.
  883. */
  884. static void
  885. lmc_t1_set_status (lmc_softc_t * const sc, lmc_ctl_t * ctl)
  886. {
  887. if (ctl == NULL)
  888. {
  889. sc->lmc_media->set_circuit_type (sc, sc->ictl.circuit_type);
  890. lmc_set_protocol (sc, NULL);
  891. return;
  892. }
  893. /*
  894. * check for change in circuit type */
  895. if (ctl->circuit_type == LMC_CTL_CIRCUIT_TYPE_T1
  896. && sc->ictl.circuit_type ==
  897. LMC_CTL_CIRCUIT_TYPE_E1) sc->lmc_media->set_circuit_type (sc,
  898. LMC_CTL_CIRCUIT_TYPE_E1);
  899. else if (ctl->circuit_type == LMC_CTL_CIRCUIT_TYPE_E1
  900. && sc->ictl.circuit_type == LMC_CTL_CIRCUIT_TYPE_T1)
  901. sc->lmc_media->set_circuit_type (sc, LMC_CTL_CIRCUIT_TYPE_T1);
  902. lmc_set_protocol (sc, ctl);
  903. }
  904. /*
  905. * return hardware link status.
  906. * 0 == link is down, 1 == link is up.
  907. */ static int
  908. lmc_t1_get_link_status (lmc_softc_t * const sc)
  909. {
  910. u_int16_t link_status;
  911. int ret = 1;
  912. /* LMC5245 (DS3) & LMC1200 (DS1) LED definitions
  913. * led0 yellow = far-end adapter is in Red alarm condition
  914. * led1 blue = received an Alarm Indication signal
  915. * (upstream failure)
  916. * led2 Green = power to adapter, Gate Array loaded & driver
  917. * attached
  918. * led3 red = Loss of Signal (LOS) or out of frame (OOF)
  919. * conditions detected on T3 receive signal
  920. */
  921. lmc_trace(sc->lmc_device, "lmc_t1_get_link_status in");
  922. lmc_led_on(sc, LMC_DS3_LED2);
  923. lmc_mii_writereg (sc, 0, 17, T1FRAMER_ALARM1_STATUS);
  924. link_status = lmc_mii_readreg (sc, 0, 18);
  925. if (link_status & T1F_RAIS) { /* turn on blue LED */
  926. ret = 0;
  927. if(sc->last_led_err[1] != 1){
  928. printk(KERN_WARNING "%s: Receive AIS/Blue Alarm. Far end in RED alarm\n", sc->name);
  929. }
  930. lmc_led_on(sc, LMC_DS3_LED1);
  931. sc->last_led_err[1] = 1;
  932. }
  933. else {
  934. if(sc->last_led_err[1] != 0){
  935. printk(KERN_WARNING "%s: End AIS/Blue Alarm\n", sc->name);
  936. }
  937. lmc_led_off (sc, LMC_DS3_LED1);
  938. sc->last_led_err[1] = 0;
  939. }
  940. /*
  941. * Yellow Alarm is nasty evil stuff, looks at data patterns
  942. * inside the channel and confuses it with HDLC framing
  943. * ignore all yellow alarms.
  944. *
  945. * Do listen to MultiFrame Yellow alarm which while implemented
  946. * different ways isn't in the channel and hence somewhat
  947. * more reliable
  948. */
  949. if (link_status & T1F_RMYEL) {
  950. ret = 0;
  951. if(sc->last_led_err[0] != 1){
  952. printk(KERN_WARNING "%s: Receive Yellow AIS Alarm\n", sc->name);
  953. }
  954. lmc_led_on(sc, LMC_DS3_LED0);
  955. sc->last_led_err[0] = 1;
  956. }
  957. else {
  958. if(sc->last_led_err[0] != 0){
  959. printk(KERN_WARNING "%s: End of Yellow AIS Alarm\n", sc->name);
  960. }
  961. lmc_led_off(sc, LMC_DS3_LED0);
  962. sc->last_led_err[0] = 0;
  963. }
  964. /*
  965. * Loss of signal and los of frame
  966. * Use the green bit to identify which one lit the led
  967. */
  968. if(link_status & T1F_RLOF){
  969. ret = 0;
  970. if(sc->last_led_err[3] != 1){
  971. printk(KERN_WARNING "%s: Local Red Alarm: Loss of Framing\n", sc->name);
  972. }
  973. lmc_led_on(sc, LMC_DS3_LED3);
  974. sc->last_led_err[3] = 1;
  975. }
  976. else {
  977. if(sc->last_led_err[3] != 0){
  978. printk(KERN_WARNING "%s: End Red Alarm (LOF)\n", sc->name);
  979. }
  980. if( ! (link_status & T1F_RLOS))
  981. lmc_led_off(sc, LMC_DS3_LED3);
  982. sc->last_led_err[3] = 0;
  983. }
  984. if(link_status & T1F_RLOS){
  985. ret = 0;
  986. if(sc->last_led_err[2] != 1){
  987. printk(KERN_WARNING "%s: Local Red Alarm: Loss of Signal\n", sc->name);
  988. }
  989. lmc_led_on(sc, LMC_DS3_LED3);
  990. sc->last_led_err[2] = 1;
  991. }
  992. else {
  993. if(sc->last_led_err[2] != 0){
  994. printk(KERN_WARNING "%s: End Red Alarm (LOS)\n", sc->name);
  995. }
  996. if( ! (link_status & T1F_RLOF))
  997. lmc_led_off(sc, LMC_DS3_LED3);
  998. sc->last_led_err[2] = 0;
  999. }
  1000. sc->lmc_xinfo.t1_alarm1_status = link_status;
  1001. lmc_mii_writereg (sc, 0, 17, T1FRAMER_ALARM2_STATUS);
  1002. sc->lmc_xinfo.t1_alarm2_status = lmc_mii_readreg (sc, 0, 18);
  1003. lmc_trace(sc->lmc_device, "lmc_t1_get_link_status out");
  1004. return ret;
  1005. }
  1006. /*
  1007. * 1 == T1 Circuit Type , 0 == E1 Circuit Type
  1008. */
  1009. static void
  1010. lmc_t1_set_circuit_type (lmc_softc_t * const sc, int ie)
  1011. {
  1012. if (ie == LMC_CTL_CIRCUIT_TYPE_T1) {
  1013. sc->lmc_miireg16 |= LMC_MII16_T1_Z;
  1014. sc->ictl.circuit_type = LMC_CTL_CIRCUIT_TYPE_T1;
  1015. printk(KERN_INFO "%s: In T1 Mode\n", sc->name);
  1016. }
  1017. else {
  1018. sc->lmc_miireg16 &= ~LMC_MII16_T1_Z;
  1019. sc->ictl.circuit_type = LMC_CTL_CIRCUIT_TYPE_E1;
  1020. printk(KERN_INFO "%s: In E1 Mode\n", sc->name);
  1021. }
  1022. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  1023. }
  1024. /*
  1025. * 0 == 16bit, 1 == 32bit */
  1026. static void
  1027. lmc_t1_set_crc_length (lmc_softc_t * const sc, int state)
  1028. {
  1029. if (state == LMC_CTL_CRC_LENGTH_32)
  1030. {
  1031. /* 32 bit */
  1032. sc->lmc_miireg16 |= LMC_MII16_T1_CRC;
  1033. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_32;
  1034. sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_4;
  1035. }
  1036. else
  1037. {
  1038. /* 16 bit */ sc->lmc_miireg16 &= ~LMC_MII16_T1_CRC;
  1039. sc->ictl.crc_length = LMC_CTL_CRC_LENGTH_16;
  1040. sc->lmc_crcSize = LMC_CTL_CRC_BYTESIZE_2;
  1041. }
  1042. lmc_mii_writereg (sc, 0, 16, sc->lmc_miireg16);
  1043. }
  1044. /*
  1045. * 1 == internal, 0 == external
  1046. */
  1047. static void
  1048. lmc_t1_set_clock (lmc_softc_t * const sc, int ie)
  1049. {
  1050. int old;
  1051. old = ie;
  1052. if (ie == LMC_CTL_CLOCK_SOURCE_EXT)
  1053. {
  1054. sc->lmc_gpio &= ~(LMC_GEP_SSI_TXCLOCK);
  1055. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  1056. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
  1057. if(old != ie)
  1058. printk (LMC_PRINTF_FMT ": clock external\n", LMC_PRINTF_ARGS);
  1059. }
  1060. else
  1061. {
  1062. sc->lmc_gpio |= LMC_GEP_SSI_TXCLOCK;
  1063. LMC_CSR_WRITE (sc, csr_gp, sc->lmc_gpio);
  1064. sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
  1065. if(old != ie)
  1066. printk (LMC_PRINTF_FMT ": clock internal\n", LMC_PRINTF_ARGS);
  1067. }
  1068. }
  1069. static void
  1070. lmc_t1_watchdog (lmc_softc_t * const sc)
  1071. {
  1072. }
  1073. static void
  1074. lmc_set_protocol (lmc_softc_t * const sc, lmc_ctl_t * ctl)
  1075. {
  1076. if (ctl == 0)
  1077. {
  1078. sc->ictl.keepalive_onoff = LMC_CTL_ON;
  1079. return;
  1080. }
  1081. }