typhoon.c 74 KB

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  1. /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
  2. /*
  3. Written 2002-2004 by David Dillow <dave@thedillows.org>
  4. Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
  5. Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
  6. This software may be used and distributed according to the terms of
  7. the GNU General Public License (GPL), incorporated herein by reference.
  8. Drivers based on or derived from this code fall under the GPL and must
  9. retain the authorship, copyright and license notice. This file is not
  10. a complete program and may only be used when the entire operating
  11. system is licensed under the GPL.
  12. This software is available on a public web site. It may enable
  13. cryptographic capabilities of the 3Com hardware, and may be
  14. exported from the United States under License Exception "TSU"
  15. pursuant to 15 C.F.R. Section 740.13(e).
  16. This work was funded by the National Library of Medicine under
  17. the Department of Energy project number 0274DD06D1 and NLM project
  18. number Y1-LM-2015-01.
  19. This driver is designed for the 3Com 3CR990 Family of cards with the
  20. 3XP Processor. It has been tested on x86 and sparc64.
  21. KNOWN ISSUES:
  22. *) The current firmware always strips the VLAN tag off, even if
  23. we tell it not to. You should filter VLANs at the switch
  24. as a workaround (good practice in any event) until we can
  25. get this fixed.
  26. *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  27. issue. Hopefully 3Com will fix it.
  28. *) Waiting for a command response takes 8ms due to non-preemptable
  29. polling. Only significant for getting stats and creating
  30. SAs, but an ugly wart never the less.
  31. TODO:
  32. *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  33. *) Add more support for ethtool (especially for NIC stats)
  34. *) Allow disabling of RX checksum offloading
  35. *) Fix MAC changing to work while the interface is up
  36. (Need to put commands on the TX ring, which changes
  37. the locking)
  38. *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  39. http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  40. */
  41. /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  42. * Setting to > 1518 effectively disables this feature.
  43. */
  44. static int rx_copybreak = 200;
  45. /* Should we use MMIO or Port IO?
  46. * 0: Port IO
  47. * 1: MMIO
  48. * 2: Try MMIO, fallback to Port IO
  49. */
  50. static unsigned int use_mmio = 2;
  51. /* end user-configurable values */
  52. /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  53. */
  54. static const int multicast_filter_limit = 32;
  55. /* Operational parameters that are set at compile time. */
  56. /* Keep the ring sizes a power of two for compile efficiency.
  57. * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  58. * Making the Tx ring too large decreases the effectiveness of channel
  59. * bonding and packet priority.
  60. * There are no ill effects from too-large receive rings.
  61. *
  62. * We don't currently use the Hi Tx ring so, don't make it very big.
  63. *
  64. * Beware that if we start using the Hi Tx ring, we will need to change
  65. * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  66. */
  67. #define TXHI_ENTRIES 2
  68. #define TXLO_ENTRIES 128
  69. #define RX_ENTRIES 32
  70. #define COMMAND_ENTRIES 16
  71. #define RESPONSE_ENTRIES 32
  72. #define COMMAND_RING_SIZE (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  73. #define RESPONSE_RING_SIZE (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  74. /* The 3XP will preload and remove 64 entries from the free buffer
  75. * list, and we need one entry to keep the ring from wrapping, so
  76. * to keep this a power of two, we use 128 entries.
  77. */
  78. #define RXFREE_ENTRIES 128
  79. #define RXENT_ENTRIES (RXFREE_ENTRIES - 1)
  80. /* Operational parameters that usually are not changed. */
  81. /* Time in jiffies before concluding the transmitter is hung. */
  82. #define TX_TIMEOUT (2*HZ)
  83. #define PKT_BUF_SZ 1536
  84. #define DRV_MODULE_NAME "typhoon"
  85. #define DRV_MODULE_VERSION "1.5.7"
  86. #define DRV_MODULE_RELDATE "05/01/07"
  87. #define PFX DRV_MODULE_NAME ": "
  88. #define ERR_PFX KERN_ERR PFX
  89. #include <linux/module.h>
  90. #include <linux/kernel.h>
  91. #include <linux/string.h>
  92. #include <linux/timer.h>
  93. #include <linux/errno.h>
  94. #include <linux/ioport.h>
  95. #include <linux/slab.h>
  96. #include <linux/interrupt.h>
  97. #include <linux/pci.h>
  98. #include <linux/netdevice.h>
  99. #include <linux/etherdevice.h>
  100. #include <linux/skbuff.h>
  101. #include <linux/init.h>
  102. #include <linux/delay.h>
  103. #include <linux/ethtool.h>
  104. #include <linux/if_vlan.h>
  105. #include <linux/crc32.h>
  106. #include <linux/bitops.h>
  107. #include <asm/processor.h>
  108. #include <asm/io.h>
  109. #include <asm/uaccess.h>
  110. #include <linux/in6.h>
  111. #include <asm/checksum.h>
  112. #include <linux/version.h>
  113. #include <linux/dma-mapping.h>
  114. #include "typhoon.h"
  115. #include "typhoon-firmware.h"
  116. static const char version[] __devinitdata =
  117. "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  118. MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
  119. MODULE_VERSION(DRV_MODULE_VERSION);
  120. MODULE_LICENSE("GPL");
  121. MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
  122. MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
  123. "the buffer given back to the NIC. Default "
  124. "is 200.");
  125. MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
  126. "Default is to try MMIO and fallback to PIO.");
  127. module_param(rx_copybreak, int, 0);
  128. module_param(use_mmio, int, 0);
  129. #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
  130. #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
  131. #undef NETIF_F_TSO
  132. #endif
  133. #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
  134. #error TX ring too small!
  135. #endif
  136. struct typhoon_card_info {
  137. char *name;
  138. int capabilities;
  139. };
  140. #define TYPHOON_CRYPTO_NONE 0x00
  141. #define TYPHOON_CRYPTO_DES 0x01
  142. #define TYPHOON_CRYPTO_3DES 0x02
  143. #define TYPHOON_CRYPTO_VARIABLE 0x04
  144. #define TYPHOON_FIBER 0x08
  145. #define TYPHOON_WAKEUP_NEEDS_RESET 0x10
  146. enum typhoon_cards {
  147. TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
  148. TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
  149. TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
  150. TYPHOON_FXM,
  151. };
  152. /* directly indexed by enum typhoon_cards, above */
  153. static const struct typhoon_card_info typhoon_card_info[] __devinitdata = {
  154. { "3Com Typhoon (3C990-TX)",
  155. TYPHOON_CRYPTO_NONE},
  156. { "3Com Typhoon (3CR990-TX-95)",
  157. TYPHOON_CRYPTO_DES},
  158. { "3Com Typhoon (3CR990-TX-97)",
  159. TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
  160. { "3Com Typhoon (3C990SVR)",
  161. TYPHOON_CRYPTO_NONE},
  162. { "3Com Typhoon (3CR990SVR95)",
  163. TYPHOON_CRYPTO_DES},
  164. { "3Com Typhoon (3CR990SVR97)",
  165. TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
  166. { "3Com Typhoon2 (3C990B-TX-M)",
  167. TYPHOON_CRYPTO_VARIABLE},
  168. { "3Com Typhoon2 (3C990BSVR)",
  169. TYPHOON_CRYPTO_VARIABLE},
  170. { "3Com Typhoon (3CR990-FX-95)",
  171. TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
  172. { "3Com Typhoon (3CR990-FX-97)",
  173. TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
  174. { "3Com Typhoon (3CR990-FX-95 Server)",
  175. TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
  176. { "3Com Typhoon (3CR990-FX-97 Server)",
  177. TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
  178. { "3Com Typhoon2 (3C990B-FX-97)",
  179. TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
  180. };
  181. /* Notes on the new subsystem numbering scheme:
  182. * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
  183. * bit 4 indicates if this card has secured firmware (we don't support it)
  184. * bit 8 indicates if this is a (0) copper or (1) fiber card
  185. * bits 12-16 indicate card type: (0) client and (1) server
  186. */
  187. static struct pci_device_id typhoon_pci_tbl[] = {
  188. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
  189. PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
  190. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
  191. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
  192. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
  193. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
  194. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
  195. PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
  196. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
  197. PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
  198. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
  199. PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
  200. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
  201. PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
  202. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
  203. PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
  204. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
  205. PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
  206. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
  207. PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
  208. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
  209. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
  210. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
  211. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
  212. { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
  213. PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
  214. { 0, }
  215. };
  216. MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
  217. /* Define the shared memory area
  218. * Align everything the 3XP will normally be using.
  219. * We'll need to move/align txHi if we start using that ring.
  220. */
  221. #define __3xp_aligned ____cacheline_aligned
  222. struct typhoon_shared {
  223. struct typhoon_interface iface;
  224. struct typhoon_indexes indexes __3xp_aligned;
  225. struct tx_desc txLo[TXLO_ENTRIES] __3xp_aligned;
  226. struct rx_desc rxLo[RX_ENTRIES] __3xp_aligned;
  227. struct rx_desc rxHi[RX_ENTRIES] __3xp_aligned;
  228. struct cmd_desc cmd[COMMAND_ENTRIES] __3xp_aligned;
  229. struct resp_desc resp[RESPONSE_ENTRIES] __3xp_aligned;
  230. struct rx_free rxBuff[RXFREE_ENTRIES] __3xp_aligned;
  231. u32 zeroWord;
  232. struct tx_desc txHi[TXHI_ENTRIES];
  233. } __attribute__ ((packed));
  234. struct rxbuff_ent {
  235. struct sk_buff *skb;
  236. dma_addr_t dma_addr;
  237. };
  238. struct typhoon {
  239. /* Tx cache line section */
  240. struct transmit_ring txLoRing ____cacheline_aligned;
  241. struct pci_dev * tx_pdev;
  242. void __iomem *tx_ioaddr;
  243. u32 txlo_dma_addr;
  244. /* Irq/Rx cache line section */
  245. void __iomem *ioaddr ____cacheline_aligned;
  246. struct typhoon_indexes *indexes;
  247. u8 awaiting_resp;
  248. u8 duplex;
  249. u8 speed;
  250. u8 card_state;
  251. struct basic_ring rxLoRing;
  252. struct pci_dev * pdev;
  253. struct net_device * dev;
  254. spinlock_t state_lock;
  255. struct vlan_group * vlgrp;
  256. struct basic_ring rxHiRing;
  257. struct basic_ring rxBuffRing;
  258. struct rxbuff_ent rxbuffers[RXENT_ENTRIES];
  259. /* general section */
  260. spinlock_t command_lock ____cacheline_aligned;
  261. struct basic_ring cmdRing;
  262. struct basic_ring respRing;
  263. struct net_device_stats stats;
  264. struct net_device_stats stats_saved;
  265. const char * name;
  266. struct typhoon_shared * shared;
  267. dma_addr_t shared_dma;
  268. u16 xcvr_select;
  269. u16 wol_events;
  270. u32 offload;
  271. /* unused stuff (future use) */
  272. int capabilities;
  273. struct transmit_ring txHiRing;
  274. };
  275. enum completion_wait_values {
  276. NoWait = 0, WaitNoSleep, WaitSleep,
  277. };
  278. /* These are the values for the typhoon.card_state variable.
  279. * These determine where the statistics will come from in get_stats().
  280. * The sleep image does not support the statistics we need.
  281. */
  282. enum state_values {
  283. Sleeping = 0, Running,
  284. };
  285. /* PCI writes are not guaranteed to be posted in order, but outstanding writes
  286. * cannot pass a read, so this forces current writes to post.
  287. */
  288. #define typhoon_post_pci_writes(x) \
  289. do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
  290. /* We'll wait up to six seconds for a reset, and half a second normally.
  291. */
  292. #define TYPHOON_UDELAY 50
  293. #define TYPHOON_RESET_TIMEOUT_SLEEP (6 * HZ)
  294. #define TYPHOON_RESET_TIMEOUT_NOSLEEP ((6 * 1000000) / TYPHOON_UDELAY)
  295. #define TYPHOON_WAIT_TIMEOUT ((1000000 / 2) / TYPHOON_UDELAY)
  296. #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 28)
  297. #define typhoon_synchronize_irq(x) synchronize_irq()
  298. #else
  299. #define typhoon_synchronize_irq(x) synchronize_irq(x)
  300. #endif
  301. #if defined(NETIF_F_TSO)
  302. #define skb_tso_size(x) (skb_shinfo(x)->tso_size)
  303. #define TSO_NUM_DESCRIPTORS 2
  304. #define TSO_OFFLOAD_ON TYPHOON_OFFLOAD_TCP_SEGMENT
  305. #else
  306. #define NETIF_F_TSO 0
  307. #define skb_tso_size(x) 0
  308. #define TSO_NUM_DESCRIPTORS 0
  309. #define TSO_OFFLOAD_ON 0
  310. #endif
  311. static inline void
  312. typhoon_inc_index(u32 *index, const int count, const int num_entries)
  313. {
  314. /* Increment a ring index -- we can use this for all rings execept
  315. * the Rx rings, as they use different size descriptors
  316. * otherwise, everything is the same size as a cmd_desc
  317. */
  318. *index += count * sizeof(struct cmd_desc);
  319. *index %= num_entries * sizeof(struct cmd_desc);
  320. }
  321. static inline void
  322. typhoon_inc_cmd_index(u32 *index, const int count)
  323. {
  324. typhoon_inc_index(index, count, COMMAND_ENTRIES);
  325. }
  326. static inline void
  327. typhoon_inc_resp_index(u32 *index, const int count)
  328. {
  329. typhoon_inc_index(index, count, RESPONSE_ENTRIES);
  330. }
  331. static inline void
  332. typhoon_inc_rxfree_index(u32 *index, const int count)
  333. {
  334. typhoon_inc_index(index, count, RXFREE_ENTRIES);
  335. }
  336. static inline void
  337. typhoon_inc_tx_index(u32 *index, const int count)
  338. {
  339. /* if we start using the Hi Tx ring, this needs updateing */
  340. typhoon_inc_index(index, count, TXLO_ENTRIES);
  341. }
  342. static inline void
  343. typhoon_inc_rx_index(u32 *index, const int count)
  344. {
  345. /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
  346. *index += count * sizeof(struct rx_desc);
  347. *index %= RX_ENTRIES * sizeof(struct rx_desc);
  348. }
  349. static int
  350. typhoon_reset(void __iomem *ioaddr, int wait_type)
  351. {
  352. int i, err = 0;
  353. int timeout;
  354. if(wait_type == WaitNoSleep)
  355. timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
  356. else
  357. timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
  358. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
  359. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
  360. iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
  361. typhoon_post_pci_writes(ioaddr);
  362. udelay(1);
  363. iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
  364. if(wait_type != NoWait) {
  365. for(i = 0; i < timeout; i++) {
  366. if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
  367. TYPHOON_STATUS_WAITING_FOR_HOST)
  368. goto out;
  369. if(wait_type == WaitSleep)
  370. schedule_timeout_uninterruptible(1);
  371. else
  372. udelay(TYPHOON_UDELAY);
  373. }
  374. err = -ETIMEDOUT;
  375. }
  376. out:
  377. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
  378. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
  379. /* The 3XP seems to need a little extra time to complete the load
  380. * of the sleep image before we can reliably boot it. Failure to
  381. * do this occasionally results in a hung adapter after boot in
  382. * typhoon_init_one() while trying to read the MAC address or
  383. * putting the card to sleep. 3Com's driver waits 5ms, but
  384. * that seems to be overkill. However, if we can sleep, we might
  385. * as well give it that much time. Otherwise, we'll give it 500us,
  386. * which should be enough (I've see it work well at 100us, but still
  387. * saw occasional problems.)
  388. */
  389. if(wait_type == WaitSleep)
  390. msleep(5);
  391. else
  392. udelay(500);
  393. return err;
  394. }
  395. static int
  396. typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
  397. {
  398. int i, err = 0;
  399. for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
  400. if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
  401. goto out;
  402. udelay(TYPHOON_UDELAY);
  403. }
  404. err = -ETIMEDOUT;
  405. out:
  406. return err;
  407. }
  408. static inline void
  409. typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
  410. {
  411. if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
  412. netif_carrier_off(dev);
  413. else
  414. netif_carrier_on(dev);
  415. }
  416. static inline void
  417. typhoon_hello(struct typhoon *tp)
  418. {
  419. struct basic_ring *ring = &tp->cmdRing;
  420. struct cmd_desc *cmd;
  421. /* We only get a hello request if we've not sent anything to the
  422. * card in a long while. If the lock is held, then we're in the
  423. * process of issuing a command, so we don't need to respond.
  424. */
  425. if(spin_trylock(&tp->command_lock)) {
  426. cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
  427. typhoon_inc_cmd_index(&ring->lastWrite, 1);
  428. INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
  429. smp_wmb();
  430. iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
  431. spin_unlock(&tp->command_lock);
  432. }
  433. }
  434. static int
  435. typhoon_process_response(struct typhoon *tp, int resp_size,
  436. struct resp_desc *resp_save)
  437. {
  438. struct typhoon_indexes *indexes = tp->indexes;
  439. struct resp_desc *resp;
  440. u8 *base = tp->respRing.ringBase;
  441. int count, len, wrap_len;
  442. u32 cleared;
  443. u32 ready;
  444. cleared = le32_to_cpu(indexes->respCleared);
  445. ready = le32_to_cpu(indexes->respReady);
  446. while(cleared != ready) {
  447. resp = (struct resp_desc *)(base + cleared);
  448. count = resp->numDesc + 1;
  449. if(resp_save && resp->seqNo) {
  450. if(count > resp_size) {
  451. resp_save->flags = TYPHOON_RESP_ERROR;
  452. goto cleanup;
  453. }
  454. wrap_len = 0;
  455. len = count * sizeof(*resp);
  456. if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
  457. wrap_len = cleared + len - RESPONSE_RING_SIZE;
  458. len = RESPONSE_RING_SIZE - cleared;
  459. }
  460. memcpy(resp_save, resp, len);
  461. if(unlikely(wrap_len)) {
  462. resp_save += len / sizeof(*resp);
  463. memcpy(resp_save, base, wrap_len);
  464. }
  465. resp_save = NULL;
  466. } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
  467. typhoon_media_status(tp->dev, resp);
  468. } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
  469. typhoon_hello(tp);
  470. } else {
  471. printk(KERN_ERR "%s: dumping unexpected response "
  472. "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
  473. tp->name, le16_to_cpu(resp->cmd),
  474. resp->numDesc, resp->flags,
  475. le16_to_cpu(resp->parm1),
  476. le32_to_cpu(resp->parm2),
  477. le32_to_cpu(resp->parm3));
  478. }
  479. cleanup:
  480. typhoon_inc_resp_index(&cleared, count);
  481. }
  482. indexes->respCleared = cpu_to_le32(cleared);
  483. wmb();
  484. return (resp_save == NULL);
  485. }
  486. static inline int
  487. typhoon_num_free(int lastWrite, int lastRead, int ringSize)
  488. {
  489. /* this works for all descriptors but rx_desc, as they are a
  490. * different size than the cmd_desc -- everyone else is the same
  491. */
  492. lastWrite /= sizeof(struct cmd_desc);
  493. lastRead /= sizeof(struct cmd_desc);
  494. return (ringSize + lastRead - lastWrite - 1) % ringSize;
  495. }
  496. static inline int
  497. typhoon_num_free_cmd(struct typhoon *tp)
  498. {
  499. int lastWrite = tp->cmdRing.lastWrite;
  500. int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
  501. return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
  502. }
  503. static inline int
  504. typhoon_num_free_resp(struct typhoon *tp)
  505. {
  506. int respReady = le32_to_cpu(tp->indexes->respReady);
  507. int respCleared = le32_to_cpu(tp->indexes->respCleared);
  508. return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
  509. }
  510. static inline int
  511. typhoon_num_free_tx(struct transmit_ring *ring)
  512. {
  513. /* if we start using the Hi Tx ring, this needs updating */
  514. return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
  515. }
  516. static int
  517. typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
  518. int num_resp, struct resp_desc *resp)
  519. {
  520. struct typhoon_indexes *indexes = tp->indexes;
  521. struct basic_ring *ring = &tp->cmdRing;
  522. struct resp_desc local_resp;
  523. int i, err = 0;
  524. int got_resp;
  525. int freeCmd, freeResp;
  526. int len, wrap_len;
  527. spin_lock(&tp->command_lock);
  528. freeCmd = typhoon_num_free_cmd(tp);
  529. freeResp = typhoon_num_free_resp(tp);
  530. if(freeCmd < num_cmd || freeResp < num_resp) {
  531. printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
  532. "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
  533. freeResp, num_resp);
  534. err = -ENOMEM;
  535. goto out;
  536. }
  537. if(cmd->flags & TYPHOON_CMD_RESPOND) {
  538. /* If we're expecting a response, but the caller hasn't given
  539. * us a place to put it, we'll provide one.
  540. */
  541. tp->awaiting_resp = 1;
  542. if(resp == NULL) {
  543. resp = &local_resp;
  544. num_resp = 1;
  545. }
  546. }
  547. wrap_len = 0;
  548. len = num_cmd * sizeof(*cmd);
  549. if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
  550. wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
  551. len = COMMAND_RING_SIZE - ring->lastWrite;
  552. }
  553. memcpy(ring->ringBase + ring->lastWrite, cmd, len);
  554. if(unlikely(wrap_len)) {
  555. struct cmd_desc *wrap_ptr = cmd;
  556. wrap_ptr += len / sizeof(*cmd);
  557. memcpy(ring->ringBase, wrap_ptr, wrap_len);
  558. }
  559. typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
  560. /* "I feel a presence... another warrior is on the the mesa."
  561. */
  562. wmb();
  563. iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
  564. typhoon_post_pci_writes(tp->ioaddr);
  565. if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
  566. goto out;
  567. /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
  568. * preempt or do anything other than take interrupts. So, don't
  569. * wait for a response unless you have to.
  570. *
  571. * I've thought about trying to sleep here, but we're called
  572. * from many contexts that don't allow that. Also, given the way
  573. * 3Com has implemented irq coalescing, we would likely timeout --
  574. * this has been observed in real life!
  575. *
  576. * The big killer is we have to wait to get stats from the card,
  577. * though we could go to a periodic refresh of those if we don't
  578. * mind them getting somewhat stale. The rest of the waiting
  579. * commands occur during open/close/suspend/resume, so they aren't
  580. * time critical. Creating SAs in the future will also have to
  581. * wait here.
  582. */
  583. got_resp = 0;
  584. for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
  585. if(indexes->respCleared != indexes->respReady)
  586. got_resp = typhoon_process_response(tp, num_resp,
  587. resp);
  588. udelay(TYPHOON_UDELAY);
  589. }
  590. if(!got_resp) {
  591. err = -ETIMEDOUT;
  592. goto out;
  593. }
  594. /* Collect the error response even if we don't care about the
  595. * rest of the response
  596. */
  597. if(resp->flags & TYPHOON_RESP_ERROR)
  598. err = -EIO;
  599. out:
  600. if(tp->awaiting_resp) {
  601. tp->awaiting_resp = 0;
  602. smp_wmb();
  603. /* Ugh. If a response was added to the ring between
  604. * the call to typhoon_process_response() and the clearing
  605. * of tp->awaiting_resp, we could have missed the interrupt
  606. * and it could hang in the ring an indeterminate amount of
  607. * time. So, check for it, and interrupt ourselves if this
  608. * is the case.
  609. */
  610. if(indexes->respCleared != indexes->respReady)
  611. iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
  612. }
  613. spin_unlock(&tp->command_lock);
  614. return err;
  615. }
  616. static void
  617. typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
  618. {
  619. struct typhoon *tp = netdev_priv(dev);
  620. struct cmd_desc xp_cmd;
  621. int err;
  622. spin_lock_bh(&tp->state_lock);
  623. if(!tp->vlgrp != !grp) {
  624. /* We've either been turned on for the first time, or we've
  625. * been turned off. Update the 3XP.
  626. */
  627. if(grp)
  628. tp->offload |= TYPHOON_OFFLOAD_VLAN;
  629. else
  630. tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
  631. /* If the interface is up, the runtime is running -- and we
  632. * must be up for the vlan core to call us.
  633. *
  634. * Do the command outside of the spin lock, as it is slow.
  635. */
  636. INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
  637. TYPHOON_CMD_SET_OFFLOAD_TASKS);
  638. xp_cmd.parm2 = tp->offload;
  639. xp_cmd.parm3 = tp->offload;
  640. spin_unlock_bh(&tp->state_lock);
  641. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  642. if(err < 0)
  643. printk("%s: vlan offload error %d\n", tp->name, -err);
  644. spin_lock_bh(&tp->state_lock);
  645. }
  646. /* now make the change visible */
  647. tp->vlgrp = grp;
  648. spin_unlock_bh(&tp->state_lock);
  649. }
  650. static void
  651. typhoon_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
  652. {
  653. struct typhoon *tp = netdev_priv(dev);
  654. spin_lock_bh(&tp->state_lock);
  655. if(tp->vlgrp)
  656. tp->vlgrp->vlan_devices[vid] = NULL;
  657. spin_unlock_bh(&tp->state_lock);
  658. }
  659. static inline void
  660. typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
  661. u32 ring_dma)
  662. {
  663. struct tcpopt_desc *tcpd;
  664. u32 tcpd_offset = ring_dma;
  665. tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
  666. tcpd_offset += txRing->lastWrite;
  667. tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
  668. typhoon_inc_tx_index(&txRing->lastWrite, 1);
  669. tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
  670. tcpd->numDesc = 1;
  671. tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
  672. tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
  673. tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
  674. tcpd->bytesTx = cpu_to_le32(skb->len);
  675. tcpd->status = 0;
  676. }
  677. static int
  678. typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
  679. {
  680. struct typhoon *tp = netdev_priv(dev);
  681. struct transmit_ring *txRing;
  682. struct tx_desc *txd, *first_txd;
  683. dma_addr_t skb_dma;
  684. int numDesc;
  685. /* we have two rings to choose from, but we only use txLo for now
  686. * If we start using the Hi ring as well, we'll need to update
  687. * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
  688. * and TXHI_ENTRIES to match, as well as update the TSO code below
  689. * to get the right DMA address
  690. */
  691. txRing = &tp->txLoRing;
  692. /* We need one descriptor for each fragment of the sk_buff, plus the
  693. * one for the ->data area of it.
  694. *
  695. * The docs say a maximum of 16 fragment descriptors per TCP option
  696. * descriptor, then make a new packet descriptor and option descriptor
  697. * for the next 16 fragments. The engineers say just an option
  698. * descriptor is needed. I've tested up to 26 fragments with a single
  699. * packet descriptor/option descriptor combo, so I use that for now.
  700. *
  701. * If problems develop with TSO, check this first.
  702. */
  703. numDesc = skb_shinfo(skb)->nr_frags + 1;
  704. if(skb_tso_size(skb))
  705. numDesc++;
  706. /* When checking for free space in the ring, we need to also
  707. * account for the initial Tx descriptor, and we always must leave
  708. * at least one descriptor unused in the ring so that it doesn't
  709. * wrap and look empty.
  710. *
  711. * The only time we should loop here is when we hit the race
  712. * between marking the queue awake and updating the cleared index.
  713. * Just loop and it will appear. This comes from the acenic driver.
  714. */
  715. while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
  716. smp_rmb();
  717. first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
  718. typhoon_inc_tx_index(&txRing->lastWrite, 1);
  719. first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
  720. first_txd->numDesc = 0;
  721. first_txd->len = 0;
  722. first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
  723. first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
  724. first_txd->processFlags = 0;
  725. if(skb->ip_summed == CHECKSUM_HW) {
  726. /* The 3XP will figure out if this is UDP/TCP */
  727. first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
  728. first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
  729. first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
  730. }
  731. if(vlan_tx_tag_present(skb)) {
  732. first_txd->processFlags |=
  733. TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
  734. first_txd->processFlags |=
  735. cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
  736. TYPHOON_TX_PF_VLAN_TAG_SHIFT);
  737. }
  738. if(skb_tso_size(skb)) {
  739. first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
  740. first_txd->numDesc++;
  741. typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
  742. }
  743. txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
  744. typhoon_inc_tx_index(&txRing->lastWrite, 1);
  745. /* No need to worry about padding packet -- the firmware pads
  746. * it with zeros to ETH_ZLEN for us.
  747. */
  748. if(skb_shinfo(skb)->nr_frags == 0) {
  749. skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
  750. PCI_DMA_TODEVICE);
  751. txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
  752. txd->len = cpu_to_le16(skb->len);
  753. txd->addr = cpu_to_le32(skb_dma);
  754. txd->addrHi = 0;
  755. first_txd->numDesc++;
  756. } else {
  757. int i, len;
  758. len = skb_headlen(skb);
  759. skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
  760. PCI_DMA_TODEVICE);
  761. txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
  762. txd->len = cpu_to_le16(len);
  763. txd->addr = cpu_to_le32(skb_dma);
  764. txd->addrHi = 0;
  765. first_txd->numDesc++;
  766. for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
  767. skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
  768. void *frag_addr;
  769. txd = (struct tx_desc *) (txRing->ringBase +
  770. txRing->lastWrite);
  771. typhoon_inc_tx_index(&txRing->lastWrite, 1);
  772. len = frag->size;
  773. frag_addr = (void *) page_address(frag->page) +
  774. frag->page_offset;
  775. skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
  776. PCI_DMA_TODEVICE);
  777. txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
  778. txd->len = cpu_to_le16(len);
  779. txd->addr = cpu_to_le32(skb_dma);
  780. txd->addrHi = 0;
  781. first_txd->numDesc++;
  782. }
  783. }
  784. /* Kick the 3XP
  785. */
  786. wmb();
  787. iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
  788. dev->trans_start = jiffies;
  789. /* If we don't have room to put the worst case packet on the
  790. * queue, then we must stop the queue. We need 2 extra
  791. * descriptors -- one to prevent ring wrap, and one for the
  792. * Tx header.
  793. */
  794. numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
  795. if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
  796. netif_stop_queue(dev);
  797. /* A Tx complete IRQ could have gotten inbetween, making
  798. * the ring free again. Only need to recheck here, since
  799. * Tx is serialized.
  800. */
  801. if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
  802. netif_wake_queue(dev);
  803. }
  804. return 0;
  805. }
  806. static void
  807. typhoon_set_rx_mode(struct net_device *dev)
  808. {
  809. struct typhoon *tp = netdev_priv(dev);
  810. struct cmd_desc xp_cmd;
  811. u32 mc_filter[2];
  812. u16 filter;
  813. filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
  814. if(dev->flags & IFF_PROMISC) {
  815. printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
  816. dev->name);
  817. filter |= TYPHOON_RX_FILTER_PROMISCOUS;
  818. } else if((dev->mc_count > multicast_filter_limit) ||
  819. (dev->flags & IFF_ALLMULTI)) {
  820. /* Too many to match, or accept all multicasts. */
  821. filter |= TYPHOON_RX_FILTER_ALL_MCAST;
  822. } else if(dev->mc_count) {
  823. struct dev_mc_list *mclist;
  824. int i;
  825. memset(mc_filter, 0, sizeof(mc_filter));
  826. for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  827. i++, mclist = mclist->next) {
  828. int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
  829. mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
  830. }
  831. INIT_COMMAND_NO_RESPONSE(&xp_cmd,
  832. TYPHOON_CMD_SET_MULTICAST_HASH);
  833. xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
  834. xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
  835. xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
  836. typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  837. filter |= TYPHOON_RX_FILTER_MCAST_HASH;
  838. }
  839. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
  840. xp_cmd.parm1 = filter;
  841. typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  842. }
  843. static int
  844. typhoon_do_get_stats(struct typhoon *tp)
  845. {
  846. struct net_device_stats *stats = &tp->stats;
  847. struct net_device_stats *saved = &tp->stats_saved;
  848. struct cmd_desc xp_cmd;
  849. struct resp_desc xp_resp[7];
  850. struct stats_resp *s = (struct stats_resp *) xp_resp;
  851. int err;
  852. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
  853. err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
  854. if(err < 0)
  855. return err;
  856. /* 3Com's Linux driver uses txMultipleCollisions as it's
  857. * collisions value, but there is some other collision info as well...
  858. *
  859. * The extra status reported would be a good candidate for
  860. * ethtool_ops->get_{strings,stats}()
  861. */
  862. stats->tx_packets = le32_to_cpu(s->txPackets);
  863. stats->tx_bytes = le32_to_cpu(s->txBytes);
  864. stats->tx_errors = le32_to_cpu(s->txCarrierLost);
  865. stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
  866. stats->collisions = le32_to_cpu(s->txMultipleCollisions);
  867. stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
  868. stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
  869. stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
  870. stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
  871. le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
  872. stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
  873. stats->rx_length_errors = le32_to_cpu(s->rxOversized);
  874. tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
  875. SPEED_100 : SPEED_10;
  876. tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
  877. DUPLEX_FULL : DUPLEX_HALF;
  878. /* add in the saved statistics
  879. */
  880. stats->tx_packets += saved->tx_packets;
  881. stats->tx_bytes += saved->tx_bytes;
  882. stats->tx_errors += saved->tx_errors;
  883. stats->collisions += saved->collisions;
  884. stats->rx_packets += saved->rx_packets;
  885. stats->rx_bytes += saved->rx_bytes;
  886. stats->rx_fifo_errors += saved->rx_fifo_errors;
  887. stats->rx_errors += saved->rx_errors;
  888. stats->rx_crc_errors += saved->rx_crc_errors;
  889. stats->rx_length_errors += saved->rx_length_errors;
  890. return 0;
  891. }
  892. static struct net_device_stats *
  893. typhoon_get_stats(struct net_device *dev)
  894. {
  895. struct typhoon *tp = netdev_priv(dev);
  896. struct net_device_stats *stats = &tp->stats;
  897. struct net_device_stats *saved = &tp->stats_saved;
  898. smp_rmb();
  899. if(tp->card_state == Sleeping)
  900. return saved;
  901. if(typhoon_do_get_stats(tp) < 0) {
  902. printk(KERN_ERR "%s: error getting stats\n", dev->name);
  903. return saved;
  904. }
  905. return stats;
  906. }
  907. static int
  908. typhoon_set_mac_address(struct net_device *dev, void *addr)
  909. {
  910. struct sockaddr *saddr = (struct sockaddr *) addr;
  911. if(netif_running(dev))
  912. return -EBUSY;
  913. memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
  914. return 0;
  915. }
  916. static void
  917. typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  918. {
  919. struct typhoon *tp = netdev_priv(dev);
  920. struct pci_dev *pci_dev = tp->pdev;
  921. struct cmd_desc xp_cmd;
  922. struct resp_desc xp_resp[3];
  923. smp_rmb();
  924. if(tp->card_state == Sleeping) {
  925. strcpy(info->fw_version, "Sleep image");
  926. } else {
  927. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
  928. if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
  929. strcpy(info->fw_version, "Unknown runtime");
  930. } else {
  931. u32 sleep_ver = xp_resp[0].parm2;
  932. snprintf(info->fw_version, 32, "%02x.%03x.%03x",
  933. sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
  934. sleep_ver & 0xfff);
  935. }
  936. }
  937. strcpy(info->driver, DRV_MODULE_NAME);
  938. strcpy(info->version, DRV_MODULE_VERSION);
  939. strcpy(info->bus_info, pci_name(pci_dev));
  940. }
  941. static int
  942. typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  943. {
  944. struct typhoon *tp = netdev_priv(dev);
  945. cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
  946. SUPPORTED_Autoneg;
  947. switch (tp->xcvr_select) {
  948. case TYPHOON_XCVR_10HALF:
  949. cmd->advertising = ADVERTISED_10baseT_Half;
  950. break;
  951. case TYPHOON_XCVR_10FULL:
  952. cmd->advertising = ADVERTISED_10baseT_Full;
  953. break;
  954. case TYPHOON_XCVR_100HALF:
  955. cmd->advertising = ADVERTISED_100baseT_Half;
  956. break;
  957. case TYPHOON_XCVR_100FULL:
  958. cmd->advertising = ADVERTISED_100baseT_Full;
  959. break;
  960. case TYPHOON_XCVR_AUTONEG:
  961. cmd->advertising = ADVERTISED_10baseT_Half |
  962. ADVERTISED_10baseT_Full |
  963. ADVERTISED_100baseT_Half |
  964. ADVERTISED_100baseT_Full |
  965. ADVERTISED_Autoneg;
  966. break;
  967. }
  968. if(tp->capabilities & TYPHOON_FIBER) {
  969. cmd->supported |= SUPPORTED_FIBRE;
  970. cmd->advertising |= ADVERTISED_FIBRE;
  971. cmd->port = PORT_FIBRE;
  972. } else {
  973. cmd->supported |= SUPPORTED_10baseT_Half |
  974. SUPPORTED_10baseT_Full |
  975. SUPPORTED_TP;
  976. cmd->advertising |= ADVERTISED_TP;
  977. cmd->port = PORT_TP;
  978. }
  979. /* need to get stats to make these link speed/duplex valid */
  980. typhoon_do_get_stats(tp);
  981. cmd->speed = tp->speed;
  982. cmd->duplex = tp->duplex;
  983. cmd->phy_address = 0;
  984. cmd->transceiver = XCVR_INTERNAL;
  985. if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
  986. cmd->autoneg = AUTONEG_ENABLE;
  987. else
  988. cmd->autoneg = AUTONEG_DISABLE;
  989. cmd->maxtxpkt = 1;
  990. cmd->maxrxpkt = 1;
  991. return 0;
  992. }
  993. static int
  994. typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  995. {
  996. struct typhoon *tp = netdev_priv(dev);
  997. struct cmd_desc xp_cmd;
  998. int xcvr;
  999. int err;
  1000. err = -EINVAL;
  1001. if(cmd->autoneg == AUTONEG_ENABLE) {
  1002. xcvr = TYPHOON_XCVR_AUTONEG;
  1003. } else {
  1004. if(cmd->duplex == DUPLEX_HALF) {
  1005. if(cmd->speed == SPEED_10)
  1006. xcvr = TYPHOON_XCVR_10HALF;
  1007. else if(cmd->speed == SPEED_100)
  1008. xcvr = TYPHOON_XCVR_100HALF;
  1009. else
  1010. goto out;
  1011. } else if(cmd->duplex == DUPLEX_FULL) {
  1012. if(cmd->speed == SPEED_10)
  1013. xcvr = TYPHOON_XCVR_10FULL;
  1014. else if(cmd->speed == SPEED_100)
  1015. xcvr = TYPHOON_XCVR_100FULL;
  1016. else
  1017. goto out;
  1018. } else
  1019. goto out;
  1020. }
  1021. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
  1022. xp_cmd.parm1 = cpu_to_le16(xcvr);
  1023. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1024. if(err < 0)
  1025. goto out;
  1026. tp->xcvr_select = xcvr;
  1027. if(cmd->autoneg == AUTONEG_ENABLE) {
  1028. tp->speed = 0xff; /* invalid */
  1029. tp->duplex = 0xff; /* invalid */
  1030. } else {
  1031. tp->speed = cmd->speed;
  1032. tp->duplex = cmd->duplex;
  1033. }
  1034. out:
  1035. return err;
  1036. }
  1037. static void
  1038. typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1039. {
  1040. struct typhoon *tp = netdev_priv(dev);
  1041. wol->supported = WAKE_PHY | WAKE_MAGIC;
  1042. wol->wolopts = 0;
  1043. if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
  1044. wol->wolopts |= WAKE_PHY;
  1045. if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
  1046. wol->wolopts |= WAKE_MAGIC;
  1047. memset(&wol->sopass, 0, sizeof(wol->sopass));
  1048. }
  1049. static int
  1050. typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  1051. {
  1052. struct typhoon *tp = netdev_priv(dev);
  1053. if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
  1054. return -EINVAL;
  1055. tp->wol_events = 0;
  1056. if(wol->wolopts & WAKE_PHY)
  1057. tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
  1058. if(wol->wolopts & WAKE_MAGIC)
  1059. tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
  1060. return 0;
  1061. }
  1062. static u32
  1063. typhoon_get_rx_csum(struct net_device *dev)
  1064. {
  1065. /* For now, we don't allow turning off RX checksums.
  1066. */
  1067. return 1;
  1068. }
  1069. static void
  1070. typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
  1071. {
  1072. ering->rx_max_pending = RXENT_ENTRIES;
  1073. ering->rx_mini_max_pending = 0;
  1074. ering->rx_jumbo_max_pending = 0;
  1075. ering->tx_max_pending = TXLO_ENTRIES - 1;
  1076. ering->rx_pending = RXENT_ENTRIES;
  1077. ering->rx_mini_pending = 0;
  1078. ering->rx_jumbo_pending = 0;
  1079. ering->tx_pending = TXLO_ENTRIES - 1;
  1080. }
  1081. static struct ethtool_ops typhoon_ethtool_ops = {
  1082. .get_settings = typhoon_get_settings,
  1083. .set_settings = typhoon_set_settings,
  1084. .get_drvinfo = typhoon_get_drvinfo,
  1085. .get_wol = typhoon_get_wol,
  1086. .set_wol = typhoon_set_wol,
  1087. .get_link = ethtool_op_get_link,
  1088. .get_rx_csum = typhoon_get_rx_csum,
  1089. .get_tx_csum = ethtool_op_get_tx_csum,
  1090. .set_tx_csum = ethtool_op_set_tx_csum,
  1091. .get_sg = ethtool_op_get_sg,
  1092. .set_sg = ethtool_op_set_sg,
  1093. .get_tso = ethtool_op_get_tso,
  1094. .set_tso = ethtool_op_set_tso,
  1095. .get_ringparam = typhoon_get_ringparam,
  1096. };
  1097. static int
  1098. typhoon_wait_interrupt(void __iomem *ioaddr)
  1099. {
  1100. int i, err = 0;
  1101. for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
  1102. if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
  1103. TYPHOON_INTR_BOOTCMD)
  1104. goto out;
  1105. udelay(TYPHOON_UDELAY);
  1106. }
  1107. err = -ETIMEDOUT;
  1108. out:
  1109. iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
  1110. return err;
  1111. }
  1112. #define shared_offset(x) offsetof(struct typhoon_shared, x)
  1113. static void
  1114. typhoon_init_interface(struct typhoon *tp)
  1115. {
  1116. struct typhoon_interface *iface = &tp->shared->iface;
  1117. dma_addr_t shared_dma;
  1118. memset(tp->shared, 0, sizeof(struct typhoon_shared));
  1119. /* The *Hi members of iface are all init'd to zero by the memset().
  1120. */
  1121. shared_dma = tp->shared_dma + shared_offset(indexes);
  1122. iface->ringIndex = cpu_to_le32(shared_dma);
  1123. shared_dma = tp->shared_dma + shared_offset(txLo);
  1124. iface->txLoAddr = cpu_to_le32(shared_dma);
  1125. iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
  1126. shared_dma = tp->shared_dma + shared_offset(txHi);
  1127. iface->txHiAddr = cpu_to_le32(shared_dma);
  1128. iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
  1129. shared_dma = tp->shared_dma + shared_offset(rxBuff);
  1130. iface->rxBuffAddr = cpu_to_le32(shared_dma);
  1131. iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
  1132. sizeof(struct rx_free));
  1133. shared_dma = tp->shared_dma + shared_offset(rxLo);
  1134. iface->rxLoAddr = cpu_to_le32(shared_dma);
  1135. iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
  1136. shared_dma = tp->shared_dma + shared_offset(rxHi);
  1137. iface->rxHiAddr = cpu_to_le32(shared_dma);
  1138. iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
  1139. shared_dma = tp->shared_dma + shared_offset(cmd);
  1140. iface->cmdAddr = cpu_to_le32(shared_dma);
  1141. iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
  1142. shared_dma = tp->shared_dma + shared_offset(resp);
  1143. iface->respAddr = cpu_to_le32(shared_dma);
  1144. iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
  1145. shared_dma = tp->shared_dma + shared_offset(zeroWord);
  1146. iface->zeroAddr = cpu_to_le32(shared_dma);
  1147. tp->indexes = &tp->shared->indexes;
  1148. tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
  1149. tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
  1150. tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
  1151. tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
  1152. tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
  1153. tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
  1154. tp->respRing.ringBase = (u8 *) tp->shared->resp;
  1155. tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
  1156. tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
  1157. tp->txlo_dma_addr = iface->txLoAddr;
  1158. tp->card_state = Sleeping;
  1159. smp_wmb();
  1160. tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
  1161. tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
  1162. spin_lock_init(&tp->command_lock);
  1163. spin_lock_init(&tp->state_lock);
  1164. }
  1165. static void
  1166. typhoon_init_rings(struct typhoon *tp)
  1167. {
  1168. memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
  1169. tp->txLoRing.lastWrite = 0;
  1170. tp->txHiRing.lastWrite = 0;
  1171. tp->rxLoRing.lastWrite = 0;
  1172. tp->rxHiRing.lastWrite = 0;
  1173. tp->rxBuffRing.lastWrite = 0;
  1174. tp->cmdRing.lastWrite = 0;
  1175. tp->cmdRing.lastWrite = 0;
  1176. tp->txLoRing.lastRead = 0;
  1177. tp->txHiRing.lastRead = 0;
  1178. }
  1179. static int
  1180. typhoon_download_firmware(struct typhoon *tp)
  1181. {
  1182. void __iomem *ioaddr = tp->ioaddr;
  1183. struct pci_dev *pdev = tp->pdev;
  1184. struct typhoon_file_header *fHdr;
  1185. struct typhoon_section_header *sHdr;
  1186. u8 *image_data;
  1187. void *dpage;
  1188. dma_addr_t dpage_dma;
  1189. unsigned int csum;
  1190. u32 irqEnabled;
  1191. u32 irqMasked;
  1192. u32 numSections;
  1193. u32 section_len;
  1194. u32 len;
  1195. u32 load_addr;
  1196. u32 hmac;
  1197. int i;
  1198. int err;
  1199. err = -EINVAL;
  1200. fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
  1201. image_data = (u8 *) fHdr;
  1202. if(memcmp(fHdr->tag, "TYPHOON", 8)) {
  1203. printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
  1204. goto err_out;
  1205. }
  1206. /* Cannot just map the firmware image using pci_map_single() as
  1207. * the firmware is part of the kernel/module image, so we allocate
  1208. * some consistent memory to copy the sections into, as it is simpler,
  1209. * and short-lived. If we ever split out and require a userland
  1210. * firmware loader, then we can revisit this.
  1211. */
  1212. err = -ENOMEM;
  1213. dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
  1214. if(!dpage) {
  1215. printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
  1216. goto err_out;
  1217. }
  1218. irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
  1219. iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
  1220. ioaddr + TYPHOON_REG_INTR_ENABLE);
  1221. irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
  1222. iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
  1223. ioaddr + TYPHOON_REG_INTR_MASK);
  1224. err = -ETIMEDOUT;
  1225. if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
  1226. printk(KERN_ERR "%s: card ready timeout\n", tp->name);
  1227. goto err_out_irq;
  1228. }
  1229. numSections = le32_to_cpu(fHdr->numSections);
  1230. load_addr = le32_to_cpu(fHdr->startAddr);
  1231. iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
  1232. iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
  1233. hmac = le32_to_cpu(fHdr->hmacDigest[0]);
  1234. iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
  1235. hmac = le32_to_cpu(fHdr->hmacDigest[1]);
  1236. iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
  1237. hmac = le32_to_cpu(fHdr->hmacDigest[2]);
  1238. iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
  1239. hmac = le32_to_cpu(fHdr->hmacDigest[3]);
  1240. iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
  1241. hmac = le32_to_cpu(fHdr->hmacDigest[4]);
  1242. iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
  1243. typhoon_post_pci_writes(ioaddr);
  1244. iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
  1245. image_data += sizeof(struct typhoon_file_header);
  1246. /* The ioread32() in typhoon_wait_interrupt() will force the
  1247. * last write to the command register to post, so
  1248. * we don't need a typhoon_post_pci_writes() after it.
  1249. */
  1250. for(i = 0; i < numSections; i++) {
  1251. sHdr = (struct typhoon_section_header *) image_data;
  1252. image_data += sizeof(struct typhoon_section_header);
  1253. load_addr = le32_to_cpu(sHdr->startAddr);
  1254. section_len = le32_to_cpu(sHdr->len);
  1255. while(section_len) {
  1256. len = min_t(u32, section_len, PAGE_SIZE);
  1257. if(typhoon_wait_interrupt(ioaddr) < 0 ||
  1258. ioread32(ioaddr + TYPHOON_REG_STATUS) !=
  1259. TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
  1260. printk(KERN_ERR "%s: segment ready timeout\n",
  1261. tp->name);
  1262. goto err_out_irq;
  1263. }
  1264. /* Do an pseudo IPv4 checksum on the data -- first
  1265. * need to convert each u16 to cpu order before
  1266. * summing. Fortunately, due to the properties of
  1267. * the checksum, we can do this once, at the end.
  1268. */
  1269. csum = csum_partial_copy_nocheck(image_data, dpage,
  1270. len, 0);
  1271. csum = csum_fold(csum);
  1272. csum = le16_to_cpu(csum);
  1273. iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
  1274. iowrite32(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
  1275. iowrite32(load_addr,
  1276. ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
  1277. iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
  1278. iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
  1279. typhoon_post_pci_writes(ioaddr);
  1280. iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
  1281. ioaddr + TYPHOON_REG_COMMAND);
  1282. image_data += len;
  1283. load_addr += len;
  1284. section_len -= len;
  1285. }
  1286. }
  1287. if(typhoon_wait_interrupt(ioaddr) < 0 ||
  1288. ioread32(ioaddr + TYPHOON_REG_STATUS) !=
  1289. TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
  1290. printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
  1291. goto err_out_irq;
  1292. }
  1293. iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
  1294. if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
  1295. printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
  1296. tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
  1297. goto err_out_irq;
  1298. }
  1299. err = 0;
  1300. err_out_irq:
  1301. iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
  1302. iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
  1303. pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
  1304. err_out:
  1305. return err;
  1306. }
  1307. static int
  1308. typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
  1309. {
  1310. void __iomem *ioaddr = tp->ioaddr;
  1311. if(typhoon_wait_status(ioaddr, initial_status) < 0) {
  1312. printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
  1313. goto out_timeout;
  1314. }
  1315. iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
  1316. iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
  1317. typhoon_post_pci_writes(ioaddr);
  1318. iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
  1319. ioaddr + TYPHOON_REG_COMMAND);
  1320. if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
  1321. printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
  1322. tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
  1323. goto out_timeout;
  1324. }
  1325. /* Clear the Transmit and Command ready registers
  1326. */
  1327. iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
  1328. iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
  1329. iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
  1330. typhoon_post_pci_writes(ioaddr);
  1331. iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
  1332. return 0;
  1333. out_timeout:
  1334. return -ETIMEDOUT;
  1335. }
  1336. static u32
  1337. typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
  1338. volatile u32 * index)
  1339. {
  1340. u32 lastRead = txRing->lastRead;
  1341. struct tx_desc *tx;
  1342. dma_addr_t skb_dma;
  1343. int dma_len;
  1344. int type;
  1345. while(lastRead != le32_to_cpu(*index)) {
  1346. tx = (struct tx_desc *) (txRing->ringBase + lastRead);
  1347. type = tx->flags & TYPHOON_TYPE_MASK;
  1348. if(type == TYPHOON_TX_DESC) {
  1349. /* This tx_desc describes a packet.
  1350. */
  1351. unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
  1352. struct sk_buff *skb = (struct sk_buff *) ptr;
  1353. dev_kfree_skb_irq(skb);
  1354. } else if(type == TYPHOON_FRAG_DESC) {
  1355. /* This tx_desc describes a memory mapping. Free it.
  1356. */
  1357. skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
  1358. dma_len = le16_to_cpu(tx->len);
  1359. pci_unmap_single(tp->pdev, skb_dma, dma_len,
  1360. PCI_DMA_TODEVICE);
  1361. }
  1362. tx->flags = 0;
  1363. typhoon_inc_tx_index(&lastRead, 1);
  1364. }
  1365. return lastRead;
  1366. }
  1367. static void
  1368. typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
  1369. volatile u32 * index)
  1370. {
  1371. u32 lastRead;
  1372. int numDesc = MAX_SKB_FRAGS + 1;
  1373. /* This will need changing if we start to use the Hi Tx ring. */
  1374. lastRead = typhoon_clean_tx(tp, txRing, index);
  1375. if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
  1376. lastRead, TXLO_ENTRIES) > (numDesc + 2))
  1377. netif_wake_queue(tp->dev);
  1378. txRing->lastRead = lastRead;
  1379. smp_wmb();
  1380. }
  1381. static void
  1382. typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
  1383. {
  1384. struct typhoon_indexes *indexes = tp->indexes;
  1385. struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
  1386. struct basic_ring *ring = &tp->rxBuffRing;
  1387. struct rx_free *r;
  1388. if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
  1389. indexes->rxBuffCleared) {
  1390. /* no room in ring, just drop the skb
  1391. */
  1392. dev_kfree_skb_any(rxb->skb);
  1393. rxb->skb = NULL;
  1394. return;
  1395. }
  1396. r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
  1397. typhoon_inc_rxfree_index(&ring->lastWrite, 1);
  1398. r->virtAddr = idx;
  1399. r->physAddr = cpu_to_le32(rxb->dma_addr);
  1400. /* Tell the card about it */
  1401. wmb();
  1402. indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
  1403. }
  1404. static int
  1405. typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
  1406. {
  1407. struct typhoon_indexes *indexes = tp->indexes;
  1408. struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
  1409. struct basic_ring *ring = &tp->rxBuffRing;
  1410. struct rx_free *r;
  1411. struct sk_buff *skb;
  1412. dma_addr_t dma_addr;
  1413. rxb->skb = NULL;
  1414. if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
  1415. indexes->rxBuffCleared)
  1416. return -ENOMEM;
  1417. skb = dev_alloc_skb(PKT_BUF_SZ);
  1418. if(!skb)
  1419. return -ENOMEM;
  1420. #if 0
  1421. /* Please, 3com, fix the firmware to allow DMA to a unaligned
  1422. * address! Pretty please?
  1423. */
  1424. skb_reserve(skb, 2);
  1425. #endif
  1426. skb->dev = tp->dev;
  1427. dma_addr = pci_map_single(tp->pdev, skb->data,
  1428. PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
  1429. /* Since no card does 64 bit DAC, the high bits will never
  1430. * change from zero.
  1431. */
  1432. r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
  1433. typhoon_inc_rxfree_index(&ring->lastWrite, 1);
  1434. r->virtAddr = idx;
  1435. r->physAddr = cpu_to_le32(dma_addr);
  1436. rxb->skb = skb;
  1437. rxb->dma_addr = dma_addr;
  1438. /* Tell the card about it */
  1439. wmb();
  1440. indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
  1441. return 0;
  1442. }
  1443. static int
  1444. typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
  1445. volatile u32 * cleared, int budget)
  1446. {
  1447. struct rx_desc *rx;
  1448. struct sk_buff *skb, *new_skb;
  1449. struct rxbuff_ent *rxb;
  1450. dma_addr_t dma_addr;
  1451. u32 local_ready;
  1452. u32 rxaddr;
  1453. int pkt_len;
  1454. u32 idx;
  1455. u32 csum_bits;
  1456. int received;
  1457. received = 0;
  1458. local_ready = le32_to_cpu(*ready);
  1459. rxaddr = le32_to_cpu(*cleared);
  1460. while(rxaddr != local_ready && budget > 0) {
  1461. rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
  1462. idx = rx->addr;
  1463. rxb = &tp->rxbuffers[idx];
  1464. skb = rxb->skb;
  1465. dma_addr = rxb->dma_addr;
  1466. typhoon_inc_rx_index(&rxaddr, 1);
  1467. if(rx->flags & TYPHOON_RX_ERROR) {
  1468. typhoon_recycle_rx_skb(tp, idx);
  1469. continue;
  1470. }
  1471. pkt_len = le16_to_cpu(rx->frameLen);
  1472. if(pkt_len < rx_copybreak &&
  1473. (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
  1474. new_skb->dev = tp->dev;
  1475. skb_reserve(new_skb, 2);
  1476. pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
  1477. PKT_BUF_SZ,
  1478. PCI_DMA_FROMDEVICE);
  1479. eth_copy_and_sum(new_skb, skb->data, pkt_len, 0);
  1480. pci_dma_sync_single_for_device(tp->pdev, dma_addr,
  1481. PKT_BUF_SZ,
  1482. PCI_DMA_FROMDEVICE);
  1483. skb_put(new_skb, pkt_len);
  1484. typhoon_recycle_rx_skb(tp, idx);
  1485. } else {
  1486. new_skb = skb;
  1487. skb_put(new_skb, pkt_len);
  1488. pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
  1489. PCI_DMA_FROMDEVICE);
  1490. typhoon_alloc_rx_skb(tp, idx);
  1491. }
  1492. new_skb->protocol = eth_type_trans(new_skb, tp->dev);
  1493. csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
  1494. TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
  1495. if(csum_bits ==
  1496. (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
  1497. || csum_bits ==
  1498. (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
  1499. new_skb->ip_summed = CHECKSUM_UNNECESSARY;
  1500. } else
  1501. new_skb->ip_summed = CHECKSUM_NONE;
  1502. spin_lock(&tp->state_lock);
  1503. if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
  1504. vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
  1505. ntohl(rx->vlanTag) & 0xffff);
  1506. else
  1507. netif_receive_skb(new_skb);
  1508. spin_unlock(&tp->state_lock);
  1509. tp->dev->last_rx = jiffies;
  1510. received++;
  1511. budget--;
  1512. }
  1513. *cleared = cpu_to_le32(rxaddr);
  1514. return received;
  1515. }
  1516. static void
  1517. typhoon_fill_free_ring(struct typhoon *tp)
  1518. {
  1519. u32 i;
  1520. for(i = 0; i < RXENT_ENTRIES; i++) {
  1521. struct rxbuff_ent *rxb = &tp->rxbuffers[i];
  1522. if(rxb->skb)
  1523. continue;
  1524. if(typhoon_alloc_rx_skb(tp, i) < 0)
  1525. break;
  1526. }
  1527. }
  1528. static int
  1529. typhoon_poll(struct net_device *dev, int *total_budget)
  1530. {
  1531. struct typhoon *tp = netdev_priv(dev);
  1532. struct typhoon_indexes *indexes = tp->indexes;
  1533. int orig_budget = *total_budget;
  1534. int budget, work_done, done;
  1535. rmb();
  1536. if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
  1537. typhoon_process_response(tp, 0, NULL);
  1538. if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
  1539. typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
  1540. if(orig_budget > dev->quota)
  1541. orig_budget = dev->quota;
  1542. budget = orig_budget;
  1543. work_done = 0;
  1544. done = 1;
  1545. if(indexes->rxHiCleared != indexes->rxHiReady) {
  1546. work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
  1547. &indexes->rxHiCleared, budget);
  1548. budget -= work_done;
  1549. }
  1550. if(indexes->rxLoCleared != indexes->rxLoReady) {
  1551. work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
  1552. &indexes->rxLoCleared, budget);
  1553. }
  1554. if(work_done) {
  1555. *total_budget -= work_done;
  1556. dev->quota -= work_done;
  1557. if(work_done >= orig_budget)
  1558. done = 0;
  1559. }
  1560. if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
  1561. /* rxBuff ring is empty, try to fill it. */
  1562. typhoon_fill_free_ring(tp);
  1563. }
  1564. if(done) {
  1565. netif_rx_complete(dev);
  1566. iowrite32(TYPHOON_INTR_NONE,
  1567. tp->ioaddr + TYPHOON_REG_INTR_MASK);
  1568. typhoon_post_pci_writes(tp->ioaddr);
  1569. }
  1570. return (done ? 0 : 1);
  1571. }
  1572. static irqreturn_t
  1573. typhoon_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
  1574. {
  1575. struct net_device *dev = (struct net_device *) dev_instance;
  1576. struct typhoon *tp = dev->priv;
  1577. void __iomem *ioaddr = tp->ioaddr;
  1578. u32 intr_status;
  1579. intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
  1580. if(!(intr_status & TYPHOON_INTR_HOST_INT))
  1581. return IRQ_NONE;
  1582. iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
  1583. if(netif_rx_schedule_prep(dev)) {
  1584. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
  1585. typhoon_post_pci_writes(ioaddr);
  1586. __netif_rx_schedule(dev);
  1587. } else {
  1588. printk(KERN_ERR "%s: Error, poll already scheduled\n",
  1589. dev->name);
  1590. }
  1591. return IRQ_HANDLED;
  1592. }
  1593. static void
  1594. typhoon_free_rx_rings(struct typhoon *tp)
  1595. {
  1596. u32 i;
  1597. for(i = 0; i < RXENT_ENTRIES; i++) {
  1598. struct rxbuff_ent *rxb = &tp->rxbuffers[i];
  1599. if(rxb->skb) {
  1600. pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
  1601. PCI_DMA_FROMDEVICE);
  1602. dev_kfree_skb(rxb->skb);
  1603. rxb->skb = NULL;
  1604. }
  1605. }
  1606. }
  1607. static int
  1608. typhoon_sleep(struct typhoon *tp, pci_power_t state, u16 events)
  1609. {
  1610. struct pci_dev *pdev = tp->pdev;
  1611. void __iomem *ioaddr = tp->ioaddr;
  1612. struct cmd_desc xp_cmd;
  1613. int err;
  1614. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
  1615. xp_cmd.parm1 = events;
  1616. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1617. if(err < 0) {
  1618. printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
  1619. tp->name, err);
  1620. return err;
  1621. }
  1622. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
  1623. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1624. if(err < 0) {
  1625. printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
  1626. tp->name, err);
  1627. return err;
  1628. }
  1629. if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
  1630. return -ETIMEDOUT;
  1631. /* Since we cannot monitor the status of the link while sleeping,
  1632. * tell the world it went away.
  1633. */
  1634. netif_carrier_off(tp->dev);
  1635. pci_enable_wake(tp->pdev, state, 1);
  1636. pci_disable_device(pdev);
  1637. return pci_set_power_state(pdev, state);
  1638. }
  1639. static int
  1640. typhoon_wakeup(struct typhoon *tp, int wait_type)
  1641. {
  1642. struct pci_dev *pdev = tp->pdev;
  1643. void __iomem *ioaddr = tp->ioaddr;
  1644. pci_set_power_state(pdev, PCI_D0);
  1645. pci_restore_state(pdev);
  1646. /* Post 2.x.x versions of the Sleep Image require a reset before
  1647. * we can download the Runtime Image. But let's not make users of
  1648. * the old firmware pay for the reset.
  1649. */
  1650. iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
  1651. if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
  1652. (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
  1653. return typhoon_reset(ioaddr, wait_type);
  1654. return 0;
  1655. }
  1656. static int
  1657. typhoon_start_runtime(struct typhoon *tp)
  1658. {
  1659. struct net_device *dev = tp->dev;
  1660. void __iomem *ioaddr = tp->ioaddr;
  1661. struct cmd_desc xp_cmd;
  1662. int err;
  1663. typhoon_init_rings(tp);
  1664. typhoon_fill_free_ring(tp);
  1665. err = typhoon_download_firmware(tp);
  1666. if(err < 0) {
  1667. printk("%s: cannot load runtime on 3XP\n", tp->name);
  1668. goto error_out;
  1669. }
  1670. if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
  1671. printk("%s: cannot boot 3XP\n", tp->name);
  1672. err = -EIO;
  1673. goto error_out;
  1674. }
  1675. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
  1676. xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
  1677. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1678. if(err < 0)
  1679. goto error_out;
  1680. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
  1681. xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
  1682. xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
  1683. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1684. if(err < 0)
  1685. goto error_out;
  1686. /* Disable IRQ coalescing -- we can reenable it when 3Com gives
  1687. * us some more information on how to control it.
  1688. */
  1689. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
  1690. xp_cmd.parm1 = 0;
  1691. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1692. if(err < 0)
  1693. goto error_out;
  1694. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
  1695. xp_cmd.parm1 = tp->xcvr_select;
  1696. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1697. if(err < 0)
  1698. goto error_out;
  1699. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
  1700. xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
  1701. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1702. if(err < 0)
  1703. goto error_out;
  1704. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
  1705. spin_lock_bh(&tp->state_lock);
  1706. xp_cmd.parm2 = tp->offload;
  1707. xp_cmd.parm3 = tp->offload;
  1708. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1709. spin_unlock_bh(&tp->state_lock);
  1710. if(err < 0)
  1711. goto error_out;
  1712. typhoon_set_rx_mode(dev);
  1713. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
  1714. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1715. if(err < 0)
  1716. goto error_out;
  1717. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
  1718. err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1719. if(err < 0)
  1720. goto error_out;
  1721. tp->card_state = Running;
  1722. smp_wmb();
  1723. iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
  1724. iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
  1725. typhoon_post_pci_writes(ioaddr);
  1726. return 0;
  1727. error_out:
  1728. typhoon_reset(ioaddr, WaitNoSleep);
  1729. typhoon_free_rx_rings(tp);
  1730. typhoon_init_rings(tp);
  1731. return err;
  1732. }
  1733. static int
  1734. typhoon_stop_runtime(struct typhoon *tp, int wait_type)
  1735. {
  1736. struct typhoon_indexes *indexes = tp->indexes;
  1737. struct transmit_ring *txLo = &tp->txLoRing;
  1738. void __iomem *ioaddr = tp->ioaddr;
  1739. struct cmd_desc xp_cmd;
  1740. int i;
  1741. /* Disable interrupts early, since we can't schedule a poll
  1742. * when called with !netif_running(). This will be posted
  1743. * when we force the posting of the command.
  1744. */
  1745. iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
  1746. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
  1747. typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1748. /* Wait 1/2 sec for any outstanding transmits to occur
  1749. * We'll cleanup after the reset if this times out.
  1750. */
  1751. for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
  1752. if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
  1753. break;
  1754. udelay(TYPHOON_UDELAY);
  1755. }
  1756. if(i == TYPHOON_WAIT_TIMEOUT)
  1757. printk(KERN_ERR
  1758. "%s: halt timed out waiting for Tx to complete\n",
  1759. tp->name);
  1760. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
  1761. typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1762. /* save the statistics so when we bring the interface up again,
  1763. * the values reported to userspace are correct.
  1764. */
  1765. tp->card_state = Sleeping;
  1766. smp_wmb();
  1767. typhoon_do_get_stats(tp);
  1768. memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
  1769. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
  1770. typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
  1771. if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
  1772. printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
  1773. tp->name);
  1774. if(typhoon_reset(ioaddr, wait_type) < 0) {
  1775. printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
  1776. return -ETIMEDOUT;
  1777. }
  1778. /* cleanup any outstanding Tx packets */
  1779. if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
  1780. indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
  1781. typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
  1782. }
  1783. return 0;
  1784. }
  1785. static void
  1786. typhoon_tx_timeout(struct net_device *dev)
  1787. {
  1788. struct typhoon *tp = netdev_priv(dev);
  1789. if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
  1790. printk(KERN_WARNING "%s: could not reset in tx timeout\n",
  1791. dev->name);
  1792. goto truely_dead;
  1793. }
  1794. /* If we ever start using the Hi ring, it will need cleaning too */
  1795. typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
  1796. typhoon_free_rx_rings(tp);
  1797. if(typhoon_start_runtime(tp) < 0) {
  1798. printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
  1799. dev->name);
  1800. goto truely_dead;
  1801. }
  1802. netif_wake_queue(dev);
  1803. return;
  1804. truely_dead:
  1805. /* Reset the hardware, and turn off carrier to avoid more timeouts */
  1806. typhoon_reset(tp->ioaddr, NoWait);
  1807. netif_carrier_off(dev);
  1808. }
  1809. static int
  1810. typhoon_open(struct net_device *dev)
  1811. {
  1812. struct typhoon *tp = netdev_priv(dev);
  1813. int err;
  1814. err = typhoon_wakeup(tp, WaitSleep);
  1815. if(err < 0) {
  1816. printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
  1817. goto out_sleep;
  1818. }
  1819. err = request_irq(dev->irq, &typhoon_interrupt, SA_SHIRQ,
  1820. dev->name, dev);
  1821. if(err < 0)
  1822. goto out_sleep;
  1823. err = typhoon_start_runtime(tp);
  1824. if(err < 0)
  1825. goto out_irq;
  1826. netif_start_queue(dev);
  1827. return 0;
  1828. out_irq:
  1829. free_irq(dev->irq, dev);
  1830. out_sleep:
  1831. if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
  1832. printk(KERN_ERR "%s: unable to reboot into sleep img\n",
  1833. dev->name);
  1834. typhoon_reset(tp->ioaddr, NoWait);
  1835. goto out;
  1836. }
  1837. if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
  1838. printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
  1839. out:
  1840. return err;
  1841. }
  1842. static int
  1843. typhoon_close(struct net_device *dev)
  1844. {
  1845. struct typhoon *tp = netdev_priv(dev);
  1846. netif_stop_queue(dev);
  1847. if(typhoon_stop_runtime(tp, WaitSleep) < 0)
  1848. printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
  1849. /* Make sure there is no irq handler running on a different CPU. */
  1850. typhoon_synchronize_irq(dev->irq);
  1851. free_irq(dev->irq, dev);
  1852. typhoon_free_rx_rings(tp);
  1853. typhoon_init_rings(tp);
  1854. if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
  1855. printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
  1856. if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
  1857. printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
  1858. return 0;
  1859. }
  1860. #ifdef CONFIG_PM
  1861. static int
  1862. typhoon_resume(struct pci_dev *pdev)
  1863. {
  1864. struct net_device *dev = pci_get_drvdata(pdev);
  1865. struct typhoon *tp = netdev_priv(dev);
  1866. /* If we're down, resume when we are upped.
  1867. */
  1868. if(!netif_running(dev))
  1869. return 0;
  1870. if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
  1871. printk(KERN_ERR "%s: critical: could not wake up in resume\n",
  1872. dev->name);
  1873. goto reset;
  1874. }
  1875. if(typhoon_start_runtime(tp) < 0) {
  1876. printk(KERN_ERR "%s: critical: could not start runtime in "
  1877. "resume\n", dev->name);
  1878. goto reset;
  1879. }
  1880. netif_device_attach(dev);
  1881. netif_start_queue(dev);
  1882. return 0;
  1883. reset:
  1884. typhoon_reset(tp->ioaddr, NoWait);
  1885. return -EBUSY;
  1886. }
  1887. static int
  1888. typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
  1889. {
  1890. struct net_device *dev = pci_get_drvdata(pdev);
  1891. struct typhoon *tp = netdev_priv(dev);
  1892. struct cmd_desc xp_cmd;
  1893. /* If we're down, we're already suspended.
  1894. */
  1895. if(!netif_running(dev))
  1896. return 0;
  1897. spin_lock_bh(&tp->state_lock);
  1898. if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
  1899. spin_unlock_bh(&tp->state_lock);
  1900. printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
  1901. dev->name);
  1902. return -EBUSY;
  1903. }
  1904. spin_unlock_bh(&tp->state_lock);
  1905. netif_device_detach(dev);
  1906. if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
  1907. printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
  1908. goto need_resume;
  1909. }
  1910. typhoon_free_rx_rings(tp);
  1911. typhoon_init_rings(tp);
  1912. if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
  1913. printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
  1914. goto need_resume;
  1915. }
  1916. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
  1917. xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
  1918. xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
  1919. if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
  1920. printk(KERN_ERR "%s: unable to set mac address in suspend\n",
  1921. dev->name);
  1922. goto need_resume;
  1923. }
  1924. INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
  1925. xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
  1926. if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
  1927. printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
  1928. dev->name);
  1929. goto need_resume;
  1930. }
  1931. if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
  1932. printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
  1933. goto need_resume;
  1934. }
  1935. return 0;
  1936. need_resume:
  1937. typhoon_resume(pdev);
  1938. return -EBUSY;
  1939. }
  1940. static int
  1941. typhoon_enable_wake(struct pci_dev *pdev, pci_power_t state, int enable)
  1942. {
  1943. return pci_enable_wake(pdev, state, enable);
  1944. }
  1945. #endif
  1946. static int __devinit
  1947. typhoon_test_mmio(struct pci_dev *pdev)
  1948. {
  1949. void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
  1950. int mode = 0;
  1951. u32 val;
  1952. if(!ioaddr)
  1953. goto out;
  1954. if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
  1955. TYPHOON_STATUS_WAITING_FOR_HOST)
  1956. goto out_unmap;
  1957. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
  1958. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
  1959. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
  1960. /* Ok, see if we can change our interrupt status register by
  1961. * sending ourselves an interrupt. If so, then MMIO works.
  1962. * The 50usec delay is arbitrary -- it could probably be smaller.
  1963. */
  1964. val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
  1965. if((val & TYPHOON_INTR_SELF) == 0) {
  1966. iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
  1967. ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
  1968. udelay(50);
  1969. val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
  1970. if(val & TYPHOON_INTR_SELF)
  1971. mode = 1;
  1972. }
  1973. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
  1974. iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
  1975. iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
  1976. ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
  1977. out_unmap:
  1978. pci_iounmap(pdev, ioaddr);
  1979. out:
  1980. if(!mode)
  1981. printk(KERN_INFO PFX "falling back to port IO\n");
  1982. return mode;
  1983. }
  1984. static int __devinit
  1985. typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  1986. {
  1987. static int did_version = 0;
  1988. struct net_device *dev;
  1989. struct typhoon *tp;
  1990. int card_id = (int) ent->driver_data;
  1991. void __iomem *ioaddr;
  1992. void *shared;
  1993. dma_addr_t shared_dma;
  1994. struct cmd_desc xp_cmd;
  1995. struct resp_desc xp_resp[3];
  1996. int i;
  1997. int err = 0;
  1998. if(!did_version++)
  1999. printk(KERN_INFO "%s", version);
  2000. dev = alloc_etherdev(sizeof(*tp));
  2001. if(dev == NULL) {
  2002. printk(ERR_PFX "%s: unable to alloc new net device\n",
  2003. pci_name(pdev));
  2004. err = -ENOMEM;
  2005. goto error_out;
  2006. }
  2007. SET_MODULE_OWNER(dev);
  2008. SET_NETDEV_DEV(dev, &pdev->dev);
  2009. err = pci_enable_device(pdev);
  2010. if(err < 0) {
  2011. printk(ERR_PFX "%s: unable to enable device\n",
  2012. pci_name(pdev));
  2013. goto error_out_dev;
  2014. }
  2015. err = pci_set_mwi(pdev);
  2016. if(err < 0) {
  2017. printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
  2018. goto error_out_disable;
  2019. }
  2020. err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
  2021. if(err < 0) {
  2022. printk(ERR_PFX "%s: No usable DMA configuration\n",
  2023. pci_name(pdev));
  2024. goto error_out_mwi;
  2025. }
  2026. /* sanity checks on IO and MMIO BARs
  2027. */
  2028. if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
  2029. printk(ERR_PFX
  2030. "%s: region #1 not a PCI IO resource, aborting\n",
  2031. pci_name(pdev));
  2032. err = -ENODEV;
  2033. goto error_out_mwi;
  2034. }
  2035. if(pci_resource_len(pdev, 0) < 128) {
  2036. printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
  2037. pci_name(pdev));
  2038. err = -ENODEV;
  2039. goto error_out_mwi;
  2040. }
  2041. if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
  2042. printk(ERR_PFX
  2043. "%s: region #1 not a PCI MMIO resource, aborting\n",
  2044. pci_name(pdev));
  2045. err = -ENODEV;
  2046. goto error_out_mwi;
  2047. }
  2048. if(pci_resource_len(pdev, 1) < 128) {
  2049. printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
  2050. pci_name(pdev));
  2051. err = -ENODEV;
  2052. goto error_out_mwi;
  2053. }
  2054. err = pci_request_regions(pdev, "typhoon");
  2055. if(err < 0) {
  2056. printk(ERR_PFX "%s: could not request regions\n",
  2057. pci_name(pdev));
  2058. goto error_out_mwi;
  2059. }
  2060. /* map our registers
  2061. */
  2062. if(use_mmio != 0 && use_mmio != 1)
  2063. use_mmio = typhoon_test_mmio(pdev);
  2064. ioaddr = pci_iomap(pdev, use_mmio, 128);
  2065. if (!ioaddr) {
  2066. printk(ERR_PFX "%s: cannot remap registers, aborting\n",
  2067. pci_name(pdev));
  2068. err = -EIO;
  2069. goto error_out_regions;
  2070. }
  2071. /* allocate pci dma space for rx and tx descriptor rings
  2072. */
  2073. shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
  2074. &shared_dma);
  2075. if(!shared) {
  2076. printk(ERR_PFX "%s: could not allocate DMA memory\n",
  2077. pci_name(pdev));
  2078. err = -ENOMEM;
  2079. goto error_out_remap;
  2080. }
  2081. dev->irq = pdev->irq;
  2082. tp = netdev_priv(dev);
  2083. tp->shared = (struct typhoon_shared *) shared;
  2084. tp->shared_dma = shared_dma;
  2085. tp->pdev = pdev;
  2086. tp->tx_pdev = pdev;
  2087. tp->ioaddr = ioaddr;
  2088. tp->tx_ioaddr = ioaddr;
  2089. tp->dev = dev;
  2090. /* Init sequence:
  2091. * 1) Reset the adapter to clear any bad juju
  2092. * 2) Reload the sleep image
  2093. * 3) Boot the sleep image
  2094. * 4) Get the hardware address.
  2095. * 5) Put the card to sleep.
  2096. */
  2097. if (typhoon_reset(ioaddr, WaitSleep) < 0) {
  2098. printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
  2099. err = -EIO;
  2100. goto error_out_dma;
  2101. }
  2102. /* Now that we've reset the 3XP and are sure it's not going to
  2103. * write all over memory, enable bus mastering, and save our
  2104. * state for resuming after a suspend.
  2105. */
  2106. pci_set_master(pdev);
  2107. pci_save_state(pdev);
  2108. /* dev->name is not valid until we register, but we need to
  2109. * use some common routines to initialize the card. So that those
  2110. * routines print the right name, we keep our oun pointer to the name
  2111. */
  2112. tp->name = pci_name(pdev);
  2113. typhoon_init_interface(tp);
  2114. typhoon_init_rings(tp);
  2115. if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
  2116. printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
  2117. pci_name(pdev));
  2118. err = -EIO;
  2119. goto error_out_reset;
  2120. }
  2121. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
  2122. if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
  2123. printk(ERR_PFX "%s: cannot read MAC address\n",
  2124. pci_name(pdev));
  2125. err = -EIO;
  2126. goto error_out_reset;
  2127. }
  2128. *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
  2129. *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
  2130. if(!is_valid_ether_addr(dev->dev_addr)) {
  2131. printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
  2132. "aborting\n", pci_name(pdev));
  2133. goto error_out_reset;
  2134. }
  2135. /* Read the Sleep Image version last, so the response is valid
  2136. * later when we print out the version reported.
  2137. */
  2138. INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
  2139. if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
  2140. printk(ERR_PFX "%s: Could not get Sleep Image version\n",
  2141. pci_name(pdev));
  2142. goto error_out_reset;
  2143. }
  2144. tp->capabilities = typhoon_card_info[card_id].capabilities;
  2145. tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
  2146. /* Typhoon 1.0 Sleep Images return one response descriptor to the
  2147. * READ_VERSIONS command. Those versions are OK after waking up
  2148. * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
  2149. * seem to need a little extra help to get started. Since we don't
  2150. * know how to nudge it along, just kick it.
  2151. */
  2152. if(xp_resp[0].numDesc != 0)
  2153. tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
  2154. if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
  2155. printk(ERR_PFX "%s: cannot put adapter to sleep\n",
  2156. pci_name(pdev));
  2157. err = -EIO;
  2158. goto error_out_reset;
  2159. }
  2160. /* The chip-specific entries in the device structure. */
  2161. dev->open = typhoon_open;
  2162. dev->hard_start_xmit = typhoon_start_tx;
  2163. dev->stop = typhoon_close;
  2164. dev->set_multicast_list = typhoon_set_rx_mode;
  2165. dev->tx_timeout = typhoon_tx_timeout;
  2166. dev->poll = typhoon_poll;
  2167. dev->weight = 16;
  2168. dev->watchdog_timeo = TX_TIMEOUT;
  2169. dev->get_stats = typhoon_get_stats;
  2170. dev->set_mac_address = typhoon_set_mac_address;
  2171. dev->vlan_rx_register = typhoon_vlan_rx_register;
  2172. dev->vlan_rx_kill_vid = typhoon_vlan_rx_kill_vid;
  2173. SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
  2174. /* We can handle scatter gather, up to 16 entries, and
  2175. * we can do IP checksumming (only version 4, doh...)
  2176. */
  2177. dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
  2178. dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  2179. dev->features |= NETIF_F_TSO;
  2180. if(register_netdev(dev) < 0)
  2181. goto error_out_reset;
  2182. /* fixup our local name */
  2183. tp->name = dev->name;
  2184. pci_set_drvdata(pdev, dev);
  2185. printk(KERN_INFO "%s: %s at %s 0x%lx, ",
  2186. dev->name, typhoon_card_info[card_id].name,
  2187. use_mmio ? "MMIO" : "IO", pci_resource_start(pdev, use_mmio));
  2188. for(i = 0; i < 5; i++)
  2189. printk("%2.2x:", dev->dev_addr[i]);
  2190. printk("%2.2x\n", dev->dev_addr[i]);
  2191. /* xp_resp still contains the response to the READ_VERSIONS command.
  2192. * For debugging, let the user know what version he has.
  2193. */
  2194. if(xp_resp[0].numDesc == 0) {
  2195. /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
  2196. * of version is Month/Day of build.
  2197. */
  2198. u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
  2199. printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
  2200. "%02u/%02u/2000\n", dev->name, monthday >> 8,
  2201. monthday & 0xff);
  2202. } else if(xp_resp[0].numDesc == 2) {
  2203. /* This is the Typhoon 1.1+ type Sleep Image
  2204. */
  2205. u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
  2206. u8 *ver_string = (u8 *) &xp_resp[1];
  2207. ver_string[25] = 0;
  2208. printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
  2209. "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
  2210. (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
  2211. ver_string);
  2212. } else {
  2213. printk(KERN_WARNING "%s: Unknown Sleep Image version "
  2214. "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
  2215. le32_to_cpu(xp_resp[0].parm2));
  2216. }
  2217. return 0;
  2218. error_out_reset:
  2219. typhoon_reset(ioaddr, NoWait);
  2220. error_out_dma:
  2221. pci_free_consistent(pdev, sizeof(struct typhoon_shared),
  2222. shared, shared_dma);
  2223. error_out_remap:
  2224. pci_iounmap(pdev, ioaddr);
  2225. error_out_regions:
  2226. pci_release_regions(pdev);
  2227. error_out_mwi:
  2228. pci_clear_mwi(pdev);
  2229. error_out_disable:
  2230. pci_disable_device(pdev);
  2231. error_out_dev:
  2232. free_netdev(dev);
  2233. error_out:
  2234. return err;
  2235. }
  2236. static void __devexit
  2237. typhoon_remove_one(struct pci_dev *pdev)
  2238. {
  2239. struct net_device *dev = pci_get_drvdata(pdev);
  2240. struct typhoon *tp = netdev_priv(dev);
  2241. unregister_netdev(dev);
  2242. pci_set_power_state(pdev, PCI_D0);
  2243. pci_restore_state(pdev);
  2244. typhoon_reset(tp->ioaddr, NoWait);
  2245. pci_iounmap(pdev, tp->ioaddr);
  2246. pci_free_consistent(pdev, sizeof(struct typhoon_shared),
  2247. tp->shared, tp->shared_dma);
  2248. pci_release_regions(pdev);
  2249. pci_clear_mwi(pdev);
  2250. pci_disable_device(pdev);
  2251. pci_set_drvdata(pdev, NULL);
  2252. free_netdev(dev);
  2253. }
  2254. static struct pci_driver typhoon_driver = {
  2255. .name = DRV_MODULE_NAME,
  2256. .id_table = typhoon_pci_tbl,
  2257. .probe = typhoon_init_one,
  2258. .remove = __devexit_p(typhoon_remove_one),
  2259. #ifdef CONFIG_PM
  2260. .suspend = typhoon_suspend,
  2261. .resume = typhoon_resume,
  2262. .enable_wake = typhoon_enable_wake,
  2263. #endif
  2264. };
  2265. static int __init
  2266. typhoon_init(void)
  2267. {
  2268. return pci_module_init(&typhoon_driver);
  2269. }
  2270. static void __exit
  2271. typhoon_cleanup(void)
  2272. {
  2273. pci_unregister_driver(&typhoon_driver);
  2274. }
  2275. module_init(typhoon_init);
  2276. module_exit(typhoon_cleanup);