ixgb_osdep.h 2.7 KB

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  1. /*******************************************************************************
  2. Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
  3. This program is free software; you can redistribute it and/or modify it
  4. under the terms of the GNU General Public License as published by the Free
  5. Software Foundation; either version 2 of the License, or (at your option)
  6. any later version.
  7. This program is distributed in the hope that it will be useful, but WITHOUT
  8. ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  9. FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  10. more details.
  11. You should have received a copy of the GNU General Public License along with
  12. this program; if not, write to the Free Software Foundation, Inc., 59
  13. Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  14. The full GNU General Public License is included in this distribution in the
  15. file called LICENSE.
  16. Contact Information:
  17. Linux NICS <linux.nics@intel.com>
  18. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  19. *******************************************************************************/
  20. /* glue for the OS independent part of ixgb
  21. * includes register access macros
  22. */
  23. #ifndef _IXGB_OSDEP_H_
  24. #define _IXGB_OSDEP_H_
  25. #include <linux/types.h>
  26. #include <linux/pci.h>
  27. #include <linux/delay.h>
  28. #include <asm/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/sched.h>
  31. #ifndef msec_delay
  32. #define msec_delay(x) do { if(in_interrupt()) { \
  33. /* Don't mdelay in interrupt context! */ \
  34. BUG(); \
  35. } else { \
  36. msleep(x); \
  37. } } while(0)
  38. #endif
  39. #define PCI_COMMAND_REGISTER PCI_COMMAND
  40. #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
  41. typedef enum {
  42. #undef FALSE
  43. FALSE = 0,
  44. #undef TRUE
  45. TRUE = 1
  46. } boolean_t;
  47. #undef ASSERT
  48. #define ASSERT(x) if(!(x)) BUG()
  49. #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
  50. #ifdef DBG
  51. #define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
  52. #define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
  53. #else
  54. #define DEBUGOUT(S)
  55. #define DEBUGOUT1(S, A...)
  56. #endif
  57. #define DEBUGFUNC(F) DEBUGOUT(F)
  58. #define DEBUGOUT2 DEBUGOUT1
  59. #define DEBUGOUT3 DEBUGOUT2
  60. #define DEBUGOUT7 DEBUGOUT3
  61. #define IXGB_WRITE_REG(a, reg, value) ( \
  62. writel((value), ((a)->hw_addr + IXGB_##reg)))
  63. #define IXGB_READ_REG(a, reg) ( \
  64. readl((a)->hw_addr + IXGB_##reg))
  65. #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \
  66. writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
  67. #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
  68. readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
  69. #define IXGB_WRITE_FLUSH(a) IXGB_READ_REG(a, STATUS)
  70. #define IXGB_MEMCPY memcpy
  71. #endif /* _IXGB_OSDEP_H_ */