dl2k.c 50 KB

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  1. /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
  2. /*
  3. Copyright (c) 2001, 2002 by D-Link Corporation
  4. Written by Edward Peng.<edward_peng@dlink.com.tw>
  5. Created 03-May-2001, base on Linux' sundance.c.
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. */
  11. /*
  12. Rev Date Description
  13. ==========================================================================
  14. 0.01 2001/05/03 Created DL2000-based linux driver
  15. 0.02 2001/05/21 Added VLAN and hardware checksum support.
  16. 1.00 2001/06/26 Added jumbo frame support.
  17. 1.01 2001/08/21 Added two parameters, rx_coalesce and rx_timeout.
  18. 1.02 2001/10/08 Supported fiber media.
  19. Added flow control parameters.
  20. 1.03 2001/10/12 Changed the default media to 1000mbps_fd for
  21. the fiber devices.
  22. 1.04 2001/11/08 Fixed Tx stopped when tx very busy.
  23. 1.05 2001/11/22 Fixed Tx stopped when unidirectional tx busy.
  24. 1.06 2001/12/13 Fixed disconnect bug at 10Mbps mode.
  25. Fixed tx_full flag incorrect.
  26. Added tx_coalesce paramter.
  27. 1.07 2002/01/03 Fixed miscount of RX frame error.
  28. 1.08 2002/01/17 Fixed the multicast bug.
  29. 1.09 2002/03/07 Move rx-poll-now to re-fill loop.
  30. Added rio_timer() to watch rx buffers.
  31. 1.10 2002/04/16 Fixed miscount of carrier error.
  32. 1.11 2002/05/23 Added ISR schedule scheme
  33. Fixed miscount of rx frame error for DGE-550SX.
  34. Fixed VLAN bug.
  35. 1.12 2002/06/13 Lock tx_coalesce=1 on 10/100Mbps mode.
  36. 1.13 2002/08/13 1. Fix disconnection (many tx:carrier/rx:frame
  37. errs) with some mainboards.
  38. 2. Use definition "DRV_NAME" "DRV_VERSION"
  39. "DRV_RELDATE" for flexibility.
  40. 1.14 2002/08/14 Support ethtool.
  41. 1.15 2002/08/27 Changed the default media to Auto-Negotiation
  42. for the fiber devices.
  43. 1.16 2002/09/04 More power down time for fiber devices auto-
  44. negotiation.
  45. Fix disconnect bug after ifup and ifdown.
  46. 1.17 2002/10/03 Fix RMON statistics overflow.
  47. Always use I/O mapping to access eeprom,
  48. avoid system freezing with some chipsets.
  49. */
  50. #define DRV_NAME "D-Link DL2000-based linux driver"
  51. #define DRV_VERSION "v1.17b"
  52. #define DRV_RELDATE "2006/03/10"
  53. #include "dl2k.h"
  54. static char version[] __devinitdata =
  55. KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
  56. #define MAX_UNITS 8
  57. static int mtu[MAX_UNITS];
  58. static int vlan[MAX_UNITS];
  59. static int jumbo[MAX_UNITS];
  60. static char *media[MAX_UNITS];
  61. static int tx_flow=-1;
  62. static int rx_flow=-1;
  63. static int copy_thresh;
  64. static int rx_coalesce=10; /* Rx frame count each interrupt */
  65. static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
  66. static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
  67. MODULE_AUTHOR ("Edward Peng");
  68. MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
  69. MODULE_LICENSE("GPL");
  70. module_param_array(mtu, int, NULL, 0);
  71. module_param_array(media, charp, NULL, 0);
  72. module_param_array(vlan, int, NULL, 0);
  73. module_param_array(jumbo, int, NULL, 0);
  74. module_param(tx_flow, int, 0);
  75. module_param(rx_flow, int, 0);
  76. module_param(copy_thresh, int, 0);
  77. module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
  78. module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
  79. module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
  80. /* Enable the default interrupts */
  81. #define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
  82. UpdateStats | LinkEvent)
  83. #define EnableInt() \
  84. writew(DEFAULT_INTR, ioaddr + IntEnable)
  85. static const int max_intrloop = 50;
  86. static const int multicast_filter_limit = 0x40;
  87. static int rio_open (struct net_device *dev);
  88. static void rio_timer (unsigned long data);
  89. static void rio_tx_timeout (struct net_device *dev);
  90. static void alloc_list (struct net_device *dev);
  91. static int start_xmit (struct sk_buff *skb, struct net_device *dev);
  92. static irqreturn_t rio_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
  93. static void rio_free_tx (struct net_device *dev, int irq);
  94. static void tx_error (struct net_device *dev, int tx_status);
  95. static int receive_packet (struct net_device *dev);
  96. static void rio_error (struct net_device *dev, int int_status);
  97. static int change_mtu (struct net_device *dev, int new_mtu);
  98. static void set_multicast (struct net_device *dev);
  99. static struct net_device_stats *get_stats (struct net_device *dev);
  100. static int clear_stats (struct net_device *dev);
  101. static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  102. static int rio_close (struct net_device *dev);
  103. static int find_miiphy (struct net_device *dev);
  104. static int parse_eeprom (struct net_device *dev);
  105. static int read_eeprom (long ioaddr, int eep_addr);
  106. static int mii_wait_link (struct net_device *dev, int wait);
  107. static int mii_set_media (struct net_device *dev);
  108. static int mii_get_media (struct net_device *dev);
  109. static int mii_set_media_pcs (struct net_device *dev);
  110. static int mii_get_media_pcs (struct net_device *dev);
  111. static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
  112. static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
  113. u16 data);
  114. static struct ethtool_ops ethtool_ops;
  115. static int __devinit
  116. rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
  117. {
  118. struct net_device *dev;
  119. struct netdev_private *np;
  120. static int card_idx;
  121. int chip_idx = ent->driver_data;
  122. int err, irq;
  123. long ioaddr;
  124. static int version_printed;
  125. void *ring_space;
  126. dma_addr_t ring_dma;
  127. if (!version_printed++)
  128. printk ("%s", version);
  129. err = pci_enable_device (pdev);
  130. if (err)
  131. return err;
  132. irq = pdev->irq;
  133. err = pci_request_regions (pdev, "dl2k");
  134. if (err)
  135. goto err_out_disable;
  136. pci_set_master (pdev);
  137. dev = alloc_etherdev (sizeof (*np));
  138. if (!dev) {
  139. err = -ENOMEM;
  140. goto err_out_res;
  141. }
  142. SET_MODULE_OWNER (dev);
  143. SET_NETDEV_DEV(dev, &pdev->dev);
  144. #ifdef MEM_MAPPING
  145. ioaddr = pci_resource_start (pdev, 1);
  146. ioaddr = (long) ioremap (ioaddr, RIO_IO_SIZE);
  147. if (!ioaddr) {
  148. err = -ENOMEM;
  149. goto err_out_dev;
  150. }
  151. #else
  152. ioaddr = pci_resource_start (pdev, 0);
  153. #endif
  154. dev->base_addr = ioaddr;
  155. dev->irq = irq;
  156. np = netdev_priv(dev);
  157. np->chip_id = chip_idx;
  158. np->pdev = pdev;
  159. spin_lock_init (&np->tx_lock);
  160. spin_lock_init (&np->rx_lock);
  161. /* Parse manual configuration */
  162. np->an_enable = 1;
  163. np->tx_coalesce = 1;
  164. if (card_idx < MAX_UNITS) {
  165. if (media[card_idx] != NULL) {
  166. np->an_enable = 0;
  167. if (strcmp (media[card_idx], "auto") == 0 ||
  168. strcmp (media[card_idx], "autosense") == 0 ||
  169. strcmp (media[card_idx], "0") == 0 ) {
  170. np->an_enable = 2;
  171. } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
  172. strcmp (media[card_idx], "4") == 0) {
  173. np->speed = 100;
  174. np->full_duplex = 1;
  175. } else if (strcmp (media[card_idx], "100mbps_hd") == 0
  176. || strcmp (media[card_idx], "3") == 0) {
  177. np->speed = 100;
  178. np->full_duplex = 0;
  179. } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
  180. strcmp (media[card_idx], "2") == 0) {
  181. np->speed = 10;
  182. np->full_duplex = 1;
  183. } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
  184. strcmp (media[card_idx], "1") == 0) {
  185. np->speed = 10;
  186. np->full_duplex = 0;
  187. } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
  188. strcmp (media[card_idx], "6") == 0) {
  189. np->speed=1000;
  190. np->full_duplex=1;
  191. } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
  192. strcmp (media[card_idx], "5") == 0) {
  193. np->speed = 1000;
  194. np->full_duplex = 0;
  195. } else {
  196. np->an_enable = 1;
  197. }
  198. }
  199. if (jumbo[card_idx] != 0) {
  200. np->jumbo = 1;
  201. dev->mtu = MAX_JUMBO;
  202. } else {
  203. np->jumbo = 0;
  204. if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
  205. dev->mtu = mtu[card_idx];
  206. }
  207. np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
  208. vlan[card_idx] : 0;
  209. if (rx_coalesce > 0 && rx_timeout > 0) {
  210. np->rx_coalesce = rx_coalesce;
  211. np->rx_timeout = rx_timeout;
  212. np->coalesce = 1;
  213. }
  214. np->tx_flow = (tx_flow == 0) ? 0 : 1;
  215. np->rx_flow = (rx_flow == 0) ? 0 : 1;
  216. if (tx_coalesce < 1)
  217. tx_coalesce = 1;
  218. else if (tx_coalesce > TX_RING_SIZE-1)
  219. tx_coalesce = TX_RING_SIZE - 1;
  220. }
  221. dev->open = &rio_open;
  222. dev->hard_start_xmit = &start_xmit;
  223. dev->stop = &rio_close;
  224. dev->get_stats = &get_stats;
  225. dev->set_multicast_list = &set_multicast;
  226. dev->do_ioctl = &rio_ioctl;
  227. dev->tx_timeout = &rio_tx_timeout;
  228. dev->watchdog_timeo = TX_TIMEOUT;
  229. dev->change_mtu = &change_mtu;
  230. SET_ETHTOOL_OPS(dev, &ethtool_ops);
  231. #if 0
  232. dev->features = NETIF_F_IP_CSUM;
  233. #endif
  234. pci_set_drvdata (pdev, dev);
  235. ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
  236. if (!ring_space)
  237. goto err_out_iounmap;
  238. np->tx_ring = (struct netdev_desc *) ring_space;
  239. np->tx_ring_dma = ring_dma;
  240. ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
  241. if (!ring_space)
  242. goto err_out_unmap_tx;
  243. np->rx_ring = (struct netdev_desc *) ring_space;
  244. np->rx_ring_dma = ring_dma;
  245. /* Parse eeprom data */
  246. parse_eeprom (dev);
  247. /* Find PHY address */
  248. err = find_miiphy (dev);
  249. if (err)
  250. goto err_out_unmap_rx;
  251. /* Fiber device? */
  252. np->phy_media = (readw(ioaddr + ASICCtrl) & PhyMedia) ? 1 : 0;
  253. np->link_status = 0;
  254. /* Set media and reset PHY */
  255. if (np->phy_media) {
  256. /* default Auto-Negotiation for fiber deivices */
  257. if (np->an_enable == 2) {
  258. np->an_enable = 1;
  259. }
  260. mii_set_media_pcs (dev);
  261. } else {
  262. /* Auto-Negotiation is mandatory for 1000BASE-T,
  263. IEEE 802.3ab Annex 28D page 14 */
  264. if (np->speed == 1000)
  265. np->an_enable = 1;
  266. mii_set_media (dev);
  267. }
  268. pci_read_config_byte(pdev, PCI_REVISION_ID, &np->pci_rev_id);
  269. err = register_netdev (dev);
  270. if (err)
  271. goto err_out_unmap_rx;
  272. card_idx++;
  273. printk (KERN_INFO "%s: %s, %02x:%02x:%02x:%02x:%02x:%02x, IRQ %d\n",
  274. dev->name, np->name,
  275. dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
  276. dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5], irq);
  277. if (tx_coalesce > 1)
  278. printk(KERN_INFO "tx_coalesce:\t%d packets\n",
  279. tx_coalesce);
  280. if (np->coalesce)
  281. printk(KERN_INFO "rx_coalesce:\t%d packets\n"
  282. KERN_INFO "rx_timeout: \t%d ns\n",
  283. np->rx_coalesce, np->rx_timeout*640);
  284. if (np->vlan)
  285. printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
  286. return 0;
  287. err_out_unmap_rx:
  288. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
  289. err_out_unmap_tx:
  290. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
  291. err_out_iounmap:
  292. #ifdef MEM_MAPPING
  293. iounmap ((void *) ioaddr);
  294. err_out_dev:
  295. #endif
  296. free_netdev (dev);
  297. err_out_res:
  298. pci_release_regions (pdev);
  299. err_out_disable:
  300. pci_disable_device (pdev);
  301. return err;
  302. }
  303. int
  304. find_miiphy (struct net_device *dev)
  305. {
  306. int i, phy_found = 0;
  307. struct netdev_private *np;
  308. long ioaddr;
  309. np = netdev_priv(dev);
  310. ioaddr = dev->base_addr;
  311. np->phy_addr = 1;
  312. for (i = 31; i >= 0; i--) {
  313. int mii_status = mii_read (dev, i, 1);
  314. if (mii_status != 0xffff && mii_status != 0x0000) {
  315. np->phy_addr = i;
  316. phy_found++;
  317. }
  318. }
  319. if (!phy_found) {
  320. printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
  321. return -ENODEV;
  322. }
  323. return 0;
  324. }
  325. int
  326. parse_eeprom (struct net_device *dev)
  327. {
  328. int i, j;
  329. long ioaddr = dev->base_addr;
  330. u8 sromdata[256];
  331. u8 *psib;
  332. u32 crc;
  333. PSROM_t psrom = (PSROM_t) sromdata;
  334. struct netdev_private *np = netdev_priv(dev);
  335. int cid, next;
  336. #ifdef MEM_MAPPING
  337. ioaddr = pci_resource_start (np->pdev, 0);
  338. #endif
  339. /* Read eeprom */
  340. for (i = 0; i < 128; i++) {
  341. ((u16 *) sromdata)[i] = le16_to_cpu (read_eeprom (ioaddr, i));
  342. }
  343. #ifdef MEM_MAPPING
  344. ioaddr = dev->base_addr;
  345. #endif
  346. /* Check CRC */
  347. crc = ~ether_crc_le (256 - 4, sromdata);
  348. if (psrom->crc != crc) {
  349. printk (KERN_ERR "%s: EEPROM data CRC error.\n", dev->name);
  350. return -1;
  351. }
  352. /* Set MAC address */
  353. for (i = 0; i < 6; i++)
  354. dev->dev_addr[i] = psrom->mac_addr[i];
  355. /* Parse Software Infomation Block */
  356. i = 0x30;
  357. psib = (u8 *) sromdata;
  358. do {
  359. cid = psib[i++];
  360. next = psib[i++];
  361. if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
  362. printk (KERN_ERR "Cell data error\n");
  363. return -1;
  364. }
  365. switch (cid) {
  366. case 0: /* Format version */
  367. break;
  368. case 1: /* End of cell */
  369. return 0;
  370. case 2: /* Duplex Polarity */
  371. np->duplex_polarity = psib[i];
  372. writeb (readb (ioaddr + PhyCtrl) | psib[i],
  373. ioaddr + PhyCtrl);
  374. break;
  375. case 3: /* Wake Polarity */
  376. np->wake_polarity = psib[i];
  377. break;
  378. case 9: /* Adapter description */
  379. j = (next - i > 255) ? 255 : next - i;
  380. memcpy (np->name, &(psib[i]), j);
  381. break;
  382. case 4:
  383. case 5:
  384. case 6:
  385. case 7:
  386. case 8: /* Reversed */
  387. break;
  388. default: /* Unknown cell */
  389. return -1;
  390. }
  391. i = next;
  392. } while (1);
  393. return 0;
  394. }
  395. static int
  396. rio_open (struct net_device *dev)
  397. {
  398. struct netdev_private *np = netdev_priv(dev);
  399. long ioaddr = dev->base_addr;
  400. int i;
  401. u16 macctrl;
  402. i = request_irq (dev->irq, &rio_interrupt, SA_SHIRQ, dev->name, dev);
  403. if (i)
  404. return i;
  405. /* Reset all logic functions */
  406. writew (GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset,
  407. ioaddr + ASICCtrl + 2);
  408. mdelay(10);
  409. /* DebugCtrl bit 4, 5, 9 must set */
  410. writel (readl (ioaddr + DebugCtrl) | 0x0230, ioaddr + DebugCtrl);
  411. /* Jumbo frame */
  412. if (np->jumbo != 0)
  413. writew (MAX_JUMBO+14, ioaddr + MaxFrameSize);
  414. alloc_list (dev);
  415. /* Get station address */
  416. for (i = 0; i < 6; i++)
  417. writeb (dev->dev_addr[i], ioaddr + StationAddr0 + i);
  418. set_multicast (dev);
  419. if (np->coalesce) {
  420. writel (np->rx_coalesce | np->rx_timeout << 16,
  421. ioaddr + RxDMAIntCtrl);
  422. }
  423. /* Set RIO to poll every N*320nsec. */
  424. writeb (0x20, ioaddr + RxDMAPollPeriod);
  425. writeb (0xff, ioaddr + TxDMAPollPeriod);
  426. writeb (0x30, ioaddr + RxDMABurstThresh);
  427. writeb (0x30, ioaddr + RxDMAUrgentThresh);
  428. writel (0x0007ffff, ioaddr + RmonStatMask);
  429. /* clear statistics */
  430. clear_stats (dev);
  431. /* VLAN supported */
  432. if (np->vlan) {
  433. /* priority field in RxDMAIntCtrl */
  434. writel (readl(ioaddr + RxDMAIntCtrl) | 0x7 << 10,
  435. ioaddr + RxDMAIntCtrl);
  436. /* VLANId */
  437. writew (np->vlan, ioaddr + VLANId);
  438. /* Length/Type should be 0x8100 */
  439. writel (0x8100 << 16 | np->vlan, ioaddr + VLANTag);
  440. /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
  441. VLAN information tagged by TFC' VID, CFI fields. */
  442. writel (readl (ioaddr + MACCtrl) | AutoVLANuntagging,
  443. ioaddr + MACCtrl);
  444. }
  445. init_timer (&np->timer);
  446. np->timer.expires = jiffies + 1*HZ;
  447. np->timer.data = (unsigned long) dev;
  448. np->timer.function = &rio_timer;
  449. add_timer (&np->timer);
  450. /* Start Tx/Rx */
  451. writel (readl (ioaddr + MACCtrl) | StatsEnable | RxEnable | TxEnable,
  452. ioaddr + MACCtrl);
  453. macctrl = 0;
  454. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  455. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  456. macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
  457. macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
  458. writew(macctrl, ioaddr + MACCtrl);
  459. netif_start_queue (dev);
  460. /* Enable default interrupts */
  461. EnableInt ();
  462. return 0;
  463. }
  464. static void
  465. rio_timer (unsigned long data)
  466. {
  467. struct net_device *dev = (struct net_device *)data;
  468. struct netdev_private *np = netdev_priv(dev);
  469. unsigned int entry;
  470. int next_tick = 1*HZ;
  471. unsigned long flags;
  472. spin_lock_irqsave(&np->rx_lock, flags);
  473. /* Recover rx ring exhausted error */
  474. if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
  475. printk(KERN_INFO "Try to recover rx ring exhausted...\n");
  476. /* Re-allocate skbuffs to fill the descriptor ring */
  477. for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
  478. struct sk_buff *skb;
  479. entry = np->old_rx % RX_RING_SIZE;
  480. /* Dropped packets don't need to re-allocate */
  481. if (np->rx_skbuff[entry] == NULL) {
  482. skb = dev_alloc_skb (np->rx_buf_sz);
  483. if (skb == NULL) {
  484. np->rx_ring[entry].fraginfo = 0;
  485. printk (KERN_INFO
  486. "%s: Still unable to re-allocate Rx skbuff.#%d\n",
  487. dev->name, entry);
  488. break;
  489. }
  490. np->rx_skbuff[entry] = skb;
  491. skb->dev = dev;
  492. /* 16 byte align the IP header */
  493. skb_reserve (skb, 2);
  494. np->rx_ring[entry].fraginfo =
  495. cpu_to_le64 (pci_map_single
  496. (np->pdev, skb->data, np->rx_buf_sz,
  497. PCI_DMA_FROMDEVICE));
  498. }
  499. np->rx_ring[entry].fraginfo |=
  500. cpu_to_le64 (np->rx_buf_sz) << 48;
  501. np->rx_ring[entry].status = 0;
  502. } /* end for */
  503. } /* end if */
  504. spin_unlock_irqrestore (&np->rx_lock, flags);
  505. np->timer.expires = jiffies + next_tick;
  506. add_timer(&np->timer);
  507. }
  508. static void
  509. rio_tx_timeout (struct net_device *dev)
  510. {
  511. long ioaddr = dev->base_addr;
  512. printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
  513. dev->name, readl (ioaddr + TxStatus));
  514. rio_free_tx(dev, 0);
  515. dev->if_port = 0;
  516. dev->trans_start = jiffies;
  517. }
  518. /* allocate and initialize Tx and Rx descriptors */
  519. static void
  520. alloc_list (struct net_device *dev)
  521. {
  522. struct netdev_private *np = netdev_priv(dev);
  523. int i;
  524. np->cur_rx = np->cur_tx = 0;
  525. np->old_rx = np->old_tx = 0;
  526. np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
  527. /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
  528. for (i = 0; i < TX_RING_SIZE; i++) {
  529. np->tx_skbuff[i] = NULL;
  530. np->tx_ring[i].status = cpu_to_le64 (TFDDone);
  531. np->tx_ring[i].next_desc = cpu_to_le64 (np->tx_ring_dma +
  532. ((i+1)%TX_RING_SIZE) *
  533. sizeof (struct netdev_desc));
  534. }
  535. /* Initialize Rx descriptors */
  536. for (i = 0; i < RX_RING_SIZE; i++) {
  537. np->rx_ring[i].next_desc = cpu_to_le64 (np->rx_ring_dma +
  538. ((i + 1) % RX_RING_SIZE) *
  539. sizeof (struct netdev_desc));
  540. np->rx_ring[i].status = 0;
  541. np->rx_ring[i].fraginfo = 0;
  542. np->rx_skbuff[i] = NULL;
  543. }
  544. /* Allocate the rx buffers */
  545. for (i = 0; i < RX_RING_SIZE; i++) {
  546. /* Allocated fixed size of skbuff */
  547. struct sk_buff *skb = dev_alloc_skb (np->rx_buf_sz);
  548. np->rx_skbuff[i] = skb;
  549. if (skb == NULL) {
  550. printk (KERN_ERR
  551. "%s: alloc_list: allocate Rx buffer error! ",
  552. dev->name);
  553. break;
  554. }
  555. skb->dev = dev; /* Mark as being used by this device. */
  556. skb_reserve (skb, 2); /* 16 byte align the IP header. */
  557. /* Rubicon now supports 40 bits of addressing space. */
  558. np->rx_ring[i].fraginfo =
  559. cpu_to_le64 ( pci_map_single (
  560. np->pdev, skb->data, np->rx_buf_sz,
  561. PCI_DMA_FROMDEVICE));
  562. np->rx_ring[i].fraginfo |= cpu_to_le64 (np->rx_buf_sz) << 48;
  563. }
  564. /* Set RFDListPtr */
  565. writel (cpu_to_le32 (np->rx_ring_dma), dev->base_addr + RFDListPtr0);
  566. writel (0, dev->base_addr + RFDListPtr1);
  567. return;
  568. }
  569. static int
  570. start_xmit (struct sk_buff *skb, struct net_device *dev)
  571. {
  572. struct netdev_private *np = netdev_priv(dev);
  573. struct netdev_desc *txdesc;
  574. unsigned entry;
  575. u32 ioaddr;
  576. u64 tfc_vlan_tag = 0;
  577. if (np->link_status == 0) { /* Link Down */
  578. dev_kfree_skb(skb);
  579. return 0;
  580. }
  581. ioaddr = dev->base_addr;
  582. entry = np->cur_tx % TX_RING_SIZE;
  583. np->tx_skbuff[entry] = skb;
  584. txdesc = &np->tx_ring[entry];
  585. #if 0
  586. if (skb->ip_summed == CHECKSUM_HW) {
  587. txdesc->status |=
  588. cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
  589. IPChecksumEnable);
  590. }
  591. #endif
  592. if (np->vlan) {
  593. tfc_vlan_tag =
  594. cpu_to_le64 (VLANTagInsert) |
  595. (cpu_to_le64 (np->vlan) << 32) |
  596. (cpu_to_le64 (skb->priority) << 45);
  597. }
  598. txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
  599. skb->len,
  600. PCI_DMA_TODEVICE));
  601. txdesc->fraginfo |= cpu_to_le64 (skb->len) << 48;
  602. /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
  603. * Work around: Always use 1 descriptor in 10Mbps mode */
  604. if (entry % np->tx_coalesce == 0 || np->speed == 10)
  605. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  606. WordAlignDisable |
  607. TxDMAIndicate |
  608. (1 << FragCountShift));
  609. else
  610. txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
  611. WordAlignDisable |
  612. (1 << FragCountShift));
  613. /* TxDMAPollNow */
  614. writel (readl (ioaddr + DMACtrl) | 0x00001000, ioaddr + DMACtrl);
  615. /* Schedule ISR */
  616. writel(10000, ioaddr + CountDown);
  617. np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
  618. if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  619. < TX_QUEUE_LEN - 1 && np->speed != 10) {
  620. /* do nothing */
  621. } else if (!netif_queue_stopped(dev)) {
  622. netif_stop_queue (dev);
  623. }
  624. /* The first TFDListPtr */
  625. if (readl (dev->base_addr + TFDListPtr0) == 0) {
  626. writel (np->tx_ring_dma + entry * sizeof (struct netdev_desc),
  627. dev->base_addr + TFDListPtr0);
  628. writel (0, dev->base_addr + TFDListPtr1);
  629. }
  630. /* NETDEV WATCHDOG timer */
  631. dev->trans_start = jiffies;
  632. return 0;
  633. }
  634. static irqreturn_t
  635. rio_interrupt (int irq, void *dev_instance, struct pt_regs *rgs)
  636. {
  637. struct net_device *dev = dev_instance;
  638. struct netdev_private *np;
  639. unsigned int_status;
  640. long ioaddr;
  641. int cnt = max_intrloop;
  642. int handled = 0;
  643. ioaddr = dev->base_addr;
  644. np = netdev_priv(dev);
  645. while (1) {
  646. int_status = readw (ioaddr + IntStatus);
  647. writew (int_status, ioaddr + IntStatus);
  648. int_status &= DEFAULT_INTR;
  649. if (int_status == 0 || --cnt < 0)
  650. break;
  651. handled = 1;
  652. /* Processing received packets */
  653. if (int_status & RxDMAComplete)
  654. receive_packet (dev);
  655. /* TxDMAComplete interrupt */
  656. if ((int_status & (TxDMAComplete|IntRequested))) {
  657. int tx_status;
  658. tx_status = readl (ioaddr + TxStatus);
  659. if (tx_status & 0x01)
  660. tx_error (dev, tx_status);
  661. /* Free used tx skbuffs */
  662. rio_free_tx (dev, 1);
  663. }
  664. /* Handle uncommon events */
  665. if (int_status &
  666. (HostError | LinkEvent | UpdateStats))
  667. rio_error (dev, int_status);
  668. }
  669. if (np->cur_tx != np->old_tx)
  670. writel (100, ioaddr + CountDown);
  671. return IRQ_RETVAL(handled);
  672. }
  673. static void
  674. rio_free_tx (struct net_device *dev, int irq)
  675. {
  676. struct netdev_private *np = netdev_priv(dev);
  677. int entry = np->old_tx % TX_RING_SIZE;
  678. int tx_use = 0;
  679. unsigned long flag = 0;
  680. if (irq)
  681. spin_lock(&np->tx_lock);
  682. else
  683. spin_lock_irqsave(&np->tx_lock, flag);
  684. /* Free used tx skbuffs */
  685. while (entry != np->cur_tx) {
  686. struct sk_buff *skb;
  687. if (!(np->tx_ring[entry].status & TFDDone))
  688. break;
  689. skb = np->tx_skbuff[entry];
  690. pci_unmap_single (np->pdev,
  691. np->tx_ring[entry].fraginfo & 0xffffffffffff,
  692. skb->len, PCI_DMA_TODEVICE);
  693. if (irq)
  694. dev_kfree_skb_irq (skb);
  695. else
  696. dev_kfree_skb (skb);
  697. np->tx_skbuff[entry] = NULL;
  698. entry = (entry + 1) % TX_RING_SIZE;
  699. tx_use++;
  700. }
  701. if (irq)
  702. spin_unlock(&np->tx_lock);
  703. else
  704. spin_unlock_irqrestore(&np->tx_lock, flag);
  705. np->old_tx = entry;
  706. /* If the ring is no longer full, clear tx_full and
  707. call netif_wake_queue() */
  708. if (netif_queue_stopped(dev) &&
  709. ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
  710. < TX_QUEUE_LEN - 1 || np->speed == 10)) {
  711. netif_wake_queue (dev);
  712. }
  713. }
  714. static void
  715. tx_error (struct net_device *dev, int tx_status)
  716. {
  717. struct netdev_private *np;
  718. long ioaddr = dev->base_addr;
  719. int frame_id;
  720. int i;
  721. np = netdev_priv(dev);
  722. frame_id = (tx_status & 0xffff0000);
  723. printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
  724. dev->name, tx_status, frame_id);
  725. np->stats.tx_errors++;
  726. /* Ttransmit Underrun */
  727. if (tx_status & 0x10) {
  728. np->stats.tx_fifo_errors++;
  729. writew (readw (ioaddr + TxStartThresh) + 0x10,
  730. ioaddr + TxStartThresh);
  731. /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
  732. writew (TxReset | DMAReset | FIFOReset | NetworkReset,
  733. ioaddr + ASICCtrl + 2);
  734. /* Wait for ResetBusy bit clear */
  735. for (i = 50; i > 0; i--) {
  736. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  737. break;
  738. mdelay (1);
  739. }
  740. rio_free_tx (dev, 1);
  741. /* Reset TFDListPtr */
  742. writel (np->tx_ring_dma +
  743. np->old_tx * sizeof (struct netdev_desc),
  744. dev->base_addr + TFDListPtr0);
  745. writel (0, dev->base_addr + TFDListPtr1);
  746. /* Let TxStartThresh stay default value */
  747. }
  748. /* Late Collision */
  749. if (tx_status & 0x04) {
  750. np->stats.tx_fifo_errors++;
  751. /* TxReset and clear FIFO */
  752. writew (TxReset | FIFOReset, ioaddr + ASICCtrl + 2);
  753. /* Wait reset done */
  754. for (i = 50; i > 0; i--) {
  755. if ((readw (ioaddr + ASICCtrl + 2) & ResetBusy) == 0)
  756. break;
  757. mdelay (1);
  758. }
  759. /* Let TxStartThresh stay default value */
  760. }
  761. /* Maximum Collisions */
  762. #ifdef ETHER_STATS
  763. if (tx_status & 0x08)
  764. np->stats.collisions16++;
  765. #else
  766. if (tx_status & 0x08)
  767. np->stats.collisions++;
  768. #endif
  769. /* Restart the Tx */
  770. writel (readw (dev->base_addr + MACCtrl) | TxEnable, ioaddr + MACCtrl);
  771. }
  772. static int
  773. receive_packet (struct net_device *dev)
  774. {
  775. struct netdev_private *np = netdev_priv(dev);
  776. int entry = np->cur_rx % RX_RING_SIZE;
  777. int cnt = 30;
  778. /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
  779. while (1) {
  780. struct netdev_desc *desc = &np->rx_ring[entry];
  781. int pkt_len;
  782. u64 frame_status;
  783. if (!(desc->status & RFDDone) ||
  784. !(desc->status & FrameStart) || !(desc->status & FrameEnd))
  785. break;
  786. /* Chip omits the CRC. */
  787. pkt_len = le64_to_cpu (desc->status & 0xffff);
  788. frame_status = le64_to_cpu (desc->status);
  789. if (--cnt < 0)
  790. break;
  791. /* Update rx error statistics, drop packet. */
  792. if (frame_status & RFS_Errors) {
  793. np->stats.rx_errors++;
  794. if (frame_status & (RxRuntFrame | RxLengthError))
  795. np->stats.rx_length_errors++;
  796. if (frame_status & RxFCSError)
  797. np->stats.rx_crc_errors++;
  798. if (frame_status & RxAlignmentError && np->speed != 1000)
  799. np->stats.rx_frame_errors++;
  800. if (frame_status & RxFIFOOverrun)
  801. np->stats.rx_fifo_errors++;
  802. } else {
  803. struct sk_buff *skb;
  804. /* Small skbuffs for short packets */
  805. if (pkt_len > copy_thresh) {
  806. pci_unmap_single (np->pdev,
  807. desc->fraginfo & 0xffffffffffff,
  808. np->rx_buf_sz,
  809. PCI_DMA_FROMDEVICE);
  810. skb_put (skb = np->rx_skbuff[entry], pkt_len);
  811. np->rx_skbuff[entry] = NULL;
  812. } else if ((skb = dev_alloc_skb (pkt_len + 2)) != NULL) {
  813. pci_dma_sync_single_for_cpu(np->pdev,
  814. desc->fraginfo &
  815. 0xffffffffffff,
  816. np->rx_buf_sz,
  817. PCI_DMA_FROMDEVICE);
  818. skb->dev = dev;
  819. /* 16 byte align the IP header */
  820. skb_reserve (skb, 2);
  821. eth_copy_and_sum (skb,
  822. np->rx_skbuff[entry]->data,
  823. pkt_len, 0);
  824. skb_put (skb, pkt_len);
  825. pci_dma_sync_single_for_device(np->pdev,
  826. desc->fraginfo &
  827. 0xffffffffffff,
  828. np->rx_buf_sz,
  829. PCI_DMA_FROMDEVICE);
  830. }
  831. skb->protocol = eth_type_trans (skb, dev);
  832. #if 0
  833. /* Checksum done by hw, but csum value unavailable. */
  834. if (np->pci_rev_id >= 0x0c &&
  835. !(frame_status & (TCPError | UDPError | IPError))) {
  836. skb->ip_summed = CHECKSUM_UNNECESSARY;
  837. }
  838. #endif
  839. netif_rx (skb);
  840. dev->last_rx = jiffies;
  841. }
  842. entry = (entry + 1) % RX_RING_SIZE;
  843. }
  844. spin_lock(&np->rx_lock);
  845. np->cur_rx = entry;
  846. /* Re-allocate skbuffs to fill the descriptor ring */
  847. entry = np->old_rx;
  848. while (entry != np->cur_rx) {
  849. struct sk_buff *skb;
  850. /* Dropped packets don't need to re-allocate */
  851. if (np->rx_skbuff[entry] == NULL) {
  852. skb = dev_alloc_skb (np->rx_buf_sz);
  853. if (skb == NULL) {
  854. np->rx_ring[entry].fraginfo = 0;
  855. printk (KERN_INFO
  856. "%s: receive_packet: "
  857. "Unable to re-allocate Rx skbuff.#%d\n",
  858. dev->name, entry);
  859. break;
  860. }
  861. np->rx_skbuff[entry] = skb;
  862. skb->dev = dev;
  863. /* 16 byte align the IP header */
  864. skb_reserve (skb, 2);
  865. np->rx_ring[entry].fraginfo =
  866. cpu_to_le64 (pci_map_single
  867. (np->pdev, skb->data, np->rx_buf_sz,
  868. PCI_DMA_FROMDEVICE));
  869. }
  870. np->rx_ring[entry].fraginfo |=
  871. cpu_to_le64 (np->rx_buf_sz) << 48;
  872. np->rx_ring[entry].status = 0;
  873. entry = (entry + 1) % RX_RING_SIZE;
  874. }
  875. np->old_rx = entry;
  876. spin_unlock(&np->rx_lock);
  877. return 0;
  878. }
  879. static void
  880. rio_error (struct net_device *dev, int int_status)
  881. {
  882. long ioaddr = dev->base_addr;
  883. struct netdev_private *np = netdev_priv(dev);
  884. u16 macctrl;
  885. /* Link change event */
  886. if (int_status & LinkEvent) {
  887. if (mii_wait_link (dev, 10) == 0) {
  888. printk (KERN_INFO "%s: Link up\n", dev->name);
  889. if (np->phy_media)
  890. mii_get_media_pcs (dev);
  891. else
  892. mii_get_media (dev);
  893. if (np->speed == 1000)
  894. np->tx_coalesce = tx_coalesce;
  895. else
  896. np->tx_coalesce = 1;
  897. macctrl = 0;
  898. macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
  899. macctrl |= (np->full_duplex) ? DuplexSelect : 0;
  900. macctrl |= (np->tx_flow) ?
  901. TxFlowControlEnable : 0;
  902. macctrl |= (np->rx_flow) ?
  903. RxFlowControlEnable : 0;
  904. writew(macctrl, ioaddr + MACCtrl);
  905. np->link_status = 1;
  906. netif_carrier_on(dev);
  907. } else {
  908. printk (KERN_INFO "%s: Link off\n", dev->name);
  909. np->link_status = 0;
  910. netif_carrier_off(dev);
  911. }
  912. }
  913. /* UpdateStats statistics registers */
  914. if (int_status & UpdateStats) {
  915. get_stats (dev);
  916. }
  917. /* PCI Error, a catastronphic error related to the bus interface
  918. occurs, set GlobalReset and HostReset to reset. */
  919. if (int_status & HostError) {
  920. printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
  921. dev->name, int_status);
  922. writew (GlobalReset | HostReset, ioaddr + ASICCtrl + 2);
  923. mdelay (500);
  924. }
  925. }
  926. static struct net_device_stats *
  927. get_stats (struct net_device *dev)
  928. {
  929. long ioaddr = dev->base_addr;
  930. struct netdev_private *np = netdev_priv(dev);
  931. #ifdef MEM_MAPPING
  932. int i;
  933. #endif
  934. unsigned int stat_reg;
  935. /* All statistics registers need to be acknowledged,
  936. else statistic overflow could cause problems */
  937. np->stats.rx_packets += readl (ioaddr + FramesRcvOk);
  938. np->stats.tx_packets += readl (ioaddr + FramesXmtOk);
  939. np->stats.rx_bytes += readl (ioaddr + OctetRcvOk);
  940. np->stats.tx_bytes += readl (ioaddr + OctetXmtOk);
  941. np->stats.multicast = readl (ioaddr + McstFramesRcvdOk);
  942. np->stats.collisions += readl (ioaddr + SingleColFrames)
  943. + readl (ioaddr + MultiColFrames);
  944. /* detailed tx errors */
  945. stat_reg = readw (ioaddr + FramesAbortXSColls);
  946. np->stats.tx_aborted_errors += stat_reg;
  947. np->stats.tx_errors += stat_reg;
  948. stat_reg = readw (ioaddr + CarrierSenseErrors);
  949. np->stats.tx_carrier_errors += stat_reg;
  950. np->stats.tx_errors += stat_reg;
  951. /* Clear all other statistic register. */
  952. readl (ioaddr + McstOctetXmtOk);
  953. readw (ioaddr + BcstFramesXmtdOk);
  954. readl (ioaddr + McstFramesXmtdOk);
  955. readw (ioaddr + BcstFramesRcvdOk);
  956. readw (ioaddr + MacControlFramesRcvd);
  957. readw (ioaddr + FrameTooLongErrors);
  958. readw (ioaddr + InRangeLengthErrors);
  959. readw (ioaddr + FramesCheckSeqErrors);
  960. readw (ioaddr + FramesLostRxErrors);
  961. readl (ioaddr + McstOctetXmtOk);
  962. readl (ioaddr + BcstOctetXmtOk);
  963. readl (ioaddr + McstFramesXmtdOk);
  964. readl (ioaddr + FramesWDeferredXmt);
  965. readl (ioaddr + LateCollisions);
  966. readw (ioaddr + BcstFramesXmtdOk);
  967. readw (ioaddr + MacControlFramesXmtd);
  968. readw (ioaddr + FramesWEXDeferal);
  969. #ifdef MEM_MAPPING
  970. for (i = 0x100; i <= 0x150; i += 4)
  971. readl (ioaddr + i);
  972. #endif
  973. readw (ioaddr + TxJumboFrames);
  974. readw (ioaddr + RxJumboFrames);
  975. readw (ioaddr + TCPCheckSumErrors);
  976. readw (ioaddr + UDPCheckSumErrors);
  977. readw (ioaddr + IPCheckSumErrors);
  978. return &np->stats;
  979. }
  980. static int
  981. clear_stats (struct net_device *dev)
  982. {
  983. long ioaddr = dev->base_addr;
  984. #ifdef MEM_MAPPING
  985. int i;
  986. #endif
  987. /* All statistics registers need to be acknowledged,
  988. else statistic overflow could cause problems */
  989. readl (ioaddr + FramesRcvOk);
  990. readl (ioaddr + FramesXmtOk);
  991. readl (ioaddr + OctetRcvOk);
  992. readl (ioaddr + OctetXmtOk);
  993. readl (ioaddr + McstFramesRcvdOk);
  994. readl (ioaddr + SingleColFrames);
  995. readl (ioaddr + MultiColFrames);
  996. readl (ioaddr + LateCollisions);
  997. /* detailed rx errors */
  998. readw (ioaddr + FrameTooLongErrors);
  999. readw (ioaddr + InRangeLengthErrors);
  1000. readw (ioaddr + FramesCheckSeqErrors);
  1001. readw (ioaddr + FramesLostRxErrors);
  1002. /* detailed tx errors */
  1003. readw (ioaddr + FramesAbortXSColls);
  1004. readw (ioaddr + CarrierSenseErrors);
  1005. /* Clear all other statistic register. */
  1006. readl (ioaddr + McstOctetXmtOk);
  1007. readw (ioaddr + BcstFramesXmtdOk);
  1008. readl (ioaddr + McstFramesXmtdOk);
  1009. readw (ioaddr + BcstFramesRcvdOk);
  1010. readw (ioaddr + MacControlFramesRcvd);
  1011. readl (ioaddr + McstOctetXmtOk);
  1012. readl (ioaddr + BcstOctetXmtOk);
  1013. readl (ioaddr + McstFramesXmtdOk);
  1014. readl (ioaddr + FramesWDeferredXmt);
  1015. readw (ioaddr + BcstFramesXmtdOk);
  1016. readw (ioaddr + MacControlFramesXmtd);
  1017. readw (ioaddr + FramesWEXDeferal);
  1018. #ifdef MEM_MAPPING
  1019. for (i = 0x100; i <= 0x150; i += 4)
  1020. readl (ioaddr + i);
  1021. #endif
  1022. readw (ioaddr + TxJumboFrames);
  1023. readw (ioaddr + RxJumboFrames);
  1024. readw (ioaddr + TCPCheckSumErrors);
  1025. readw (ioaddr + UDPCheckSumErrors);
  1026. readw (ioaddr + IPCheckSumErrors);
  1027. return 0;
  1028. }
  1029. int
  1030. change_mtu (struct net_device *dev, int new_mtu)
  1031. {
  1032. struct netdev_private *np = netdev_priv(dev);
  1033. int max = (np->jumbo) ? MAX_JUMBO : 1536;
  1034. if ((new_mtu < 68) || (new_mtu > max)) {
  1035. return -EINVAL;
  1036. }
  1037. dev->mtu = new_mtu;
  1038. return 0;
  1039. }
  1040. static void
  1041. set_multicast (struct net_device *dev)
  1042. {
  1043. long ioaddr = dev->base_addr;
  1044. u32 hash_table[2];
  1045. u16 rx_mode = 0;
  1046. struct netdev_private *np = netdev_priv(dev);
  1047. hash_table[0] = hash_table[1] = 0;
  1048. /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
  1049. hash_table[1] |= cpu_to_le32(0x02000000);
  1050. if (dev->flags & IFF_PROMISC) {
  1051. /* Receive all frames promiscuously. */
  1052. rx_mode = ReceiveAllFrames;
  1053. } else if ((dev->flags & IFF_ALLMULTI) ||
  1054. (dev->mc_count > multicast_filter_limit)) {
  1055. /* Receive broadcast and multicast frames */
  1056. rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
  1057. } else if (dev->mc_count > 0) {
  1058. int i;
  1059. struct dev_mc_list *mclist;
  1060. /* Receive broadcast frames and multicast frames filtering
  1061. by Hashtable */
  1062. rx_mode =
  1063. ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
  1064. for (i=0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  1065. i++, mclist=mclist->next)
  1066. {
  1067. int bit, index = 0;
  1068. int crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
  1069. /* The inverted high significant 6 bits of CRC are
  1070. used as an index to hashtable */
  1071. for (bit = 0; bit < 6; bit++)
  1072. if (crc & (1 << (31 - bit)))
  1073. index |= (1 << bit);
  1074. hash_table[index / 32] |= (1 << (index % 32));
  1075. }
  1076. } else {
  1077. rx_mode = ReceiveBroadcast | ReceiveUnicast;
  1078. }
  1079. if (np->vlan) {
  1080. /* ReceiveVLANMatch field in ReceiveMode */
  1081. rx_mode |= ReceiveVLANMatch;
  1082. }
  1083. writel (hash_table[0], ioaddr + HashTable0);
  1084. writel (hash_table[1], ioaddr + HashTable1);
  1085. writew (rx_mode, ioaddr + ReceiveMode);
  1086. }
  1087. static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  1088. {
  1089. struct netdev_private *np = netdev_priv(dev);
  1090. strcpy(info->driver, "dl2k");
  1091. strcpy(info->version, DRV_VERSION);
  1092. strcpy(info->bus_info, pci_name(np->pdev));
  1093. }
  1094. static int rio_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1095. {
  1096. struct netdev_private *np = netdev_priv(dev);
  1097. if (np->phy_media) {
  1098. /* fiber device */
  1099. cmd->supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
  1100. cmd->advertising= ADVERTISED_Autoneg | ADVERTISED_FIBRE;
  1101. cmd->port = PORT_FIBRE;
  1102. cmd->transceiver = XCVR_INTERNAL;
  1103. } else {
  1104. /* copper device */
  1105. cmd->supported = SUPPORTED_10baseT_Half |
  1106. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
  1107. | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
  1108. SUPPORTED_Autoneg | SUPPORTED_MII;
  1109. cmd->advertising = ADVERTISED_10baseT_Half |
  1110. ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
  1111. ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full|
  1112. ADVERTISED_Autoneg | ADVERTISED_MII;
  1113. cmd->port = PORT_MII;
  1114. cmd->transceiver = XCVR_INTERNAL;
  1115. }
  1116. if ( np->link_status ) {
  1117. cmd->speed = np->speed;
  1118. cmd->duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
  1119. } else {
  1120. cmd->speed = -1;
  1121. cmd->duplex = -1;
  1122. }
  1123. if ( np->an_enable)
  1124. cmd->autoneg = AUTONEG_ENABLE;
  1125. else
  1126. cmd->autoneg = AUTONEG_DISABLE;
  1127. cmd->phy_address = np->phy_addr;
  1128. return 0;
  1129. }
  1130. static int rio_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  1131. {
  1132. struct netdev_private *np = netdev_priv(dev);
  1133. netif_carrier_off(dev);
  1134. if (cmd->autoneg == AUTONEG_ENABLE) {
  1135. if (np->an_enable)
  1136. return 0;
  1137. else {
  1138. np->an_enable = 1;
  1139. mii_set_media(dev);
  1140. return 0;
  1141. }
  1142. } else {
  1143. np->an_enable = 0;
  1144. if (np->speed == 1000) {
  1145. cmd->speed = SPEED_100;
  1146. cmd->duplex = DUPLEX_FULL;
  1147. printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
  1148. }
  1149. switch(cmd->speed + cmd->duplex) {
  1150. case SPEED_10 + DUPLEX_HALF:
  1151. np->speed = 10;
  1152. np->full_duplex = 0;
  1153. break;
  1154. case SPEED_10 + DUPLEX_FULL:
  1155. np->speed = 10;
  1156. np->full_duplex = 1;
  1157. break;
  1158. case SPEED_100 + DUPLEX_HALF:
  1159. np->speed = 100;
  1160. np->full_duplex = 0;
  1161. break;
  1162. case SPEED_100 + DUPLEX_FULL:
  1163. np->speed = 100;
  1164. np->full_duplex = 1;
  1165. break;
  1166. case SPEED_1000 + DUPLEX_HALF:/* not supported */
  1167. case SPEED_1000 + DUPLEX_FULL:/* not supported */
  1168. default:
  1169. return -EINVAL;
  1170. }
  1171. mii_set_media(dev);
  1172. }
  1173. return 0;
  1174. }
  1175. static u32 rio_get_link(struct net_device *dev)
  1176. {
  1177. struct netdev_private *np = netdev_priv(dev);
  1178. return np->link_status;
  1179. }
  1180. static struct ethtool_ops ethtool_ops = {
  1181. .get_drvinfo = rio_get_drvinfo,
  1182. .get_settings = rio_get_settings,
  1183. .set_settings = rio_set_settings,
  1184. .get_link = rio_get_link,
  1185. };
  1186. static int
  1187. rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
  1188. {
  1189. int phy_addr;
  1190. struct netdev_private *np = netdev_priv(dev);
  1191. struct mii_data *miidata = (struct mii_data *) &rq->ifr_ifru;
  1192. struct netdev_desc *desc;
  1193. int i;
  1194. phy_addr = np->phy_addr;
  1195. switch (cmd) {
  1196. case SIOCDEVPRIVATE:
  1197. break;
  1198. case SIOCDEVPRIVATE + 1:
  1199. miidata->out_value = mii_read (dev, phy_addr, miidata->reg_num);
  1200. break;
  1201. case SIOCDEVPRIVATE + 2:
  1202. mii_write (dev, phy_addr, miidata->reg_num, miidata->in_value);
  1203. break;
  1204. case SIOCDEVPRIVATE + 3:
  1205. break;
  1206. case SIOCDEVPRIVATE + 4:
  1207. break;
  1208. case SIOCDEVPRIVATE + 5:
  1209. netif_stop_queue (dev);
  1210. break;
  1211. case SIOCDEVPRIVATE + 6:
  1212. netif_wake_queue (dev);
  1213. break;
  1214. case SIOCDEVPRIVATE + 7:
  1215. printk
  1216. ("tx_full=%x cur_tx=%lx old_tx=%lx cur_rx=%lx old_rx=%lx\n",
  1217. netif_queue_stopped(dev), np->cur_tx, np->old_tx, np->cur_rx,
  1218. np->old_rx);
  1219. break;
  1220. case SIOCDEVPRIVATE + 8:
  1221. printk("TX ring:\n");
  1222. for (i = 0; i < TX_RING_SIZE; i++) {
  1223. desc = &np->tx_ring[i];
  1224. printk
  1225. ("%02x:cur:%08x next:%08x status:%08x frag1:%08x frag0:%08x",
  1226. i,
  1227. (u32) (np->tx_ring_dma + i * sizeof (*desc)),
  1228. (u32) desc->next_desc,
  1229. (u32) desc->status, (u32) (desc->fraginfo >> 32),
  1230. (u32) desc->fraginfo);
  1231. printk ("\n");
  1232. }
  1233. printk ("\n");
  1234. break;
  1235. default:
  1236. return -EOPNOTSUPP;
  1237. }
  1238. return 0;
  1239. }
  1240. #define EEP_READ 0x0200
  1241. #define EEP_BUSY 0x8000
  1242. /* Read the EEPROM word */
  1243. /* We use I/O instruction to read/write eeprom to avoid fail on some machines */
  1244. int
  1245. read_eeprom (long ioaddr, int eep_addr)
  1246. {
  1247. int i = 1000;
  1248. outw (EEP_READ | (eep_addr & 0xff), ioaddr + EepromCtrl);
  1249. while (i-- > 0) {
  1250. if (!(inw (ioaddr + EepromCtrl) & EEP_BUSY)) {
  1251. return inw (ioaddr + EepromData);
  1252. }
  1253. }
  1254. return 0;
  1255. }
  1256. enum phy_ctrl_bits {
  1257. MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
  1258. MII_DUPLEX = 0x08,
  1259. };
  1260. #define mii_delay() readb(ioaddr)
  1261. static void
  1262. mii_sendbit (struct net_device *dev, u32 data)
  1263. {
  1264. long ioaddr = dev->base_addr + PhyCtrl;
  1265. data = (data) ? MII_DATA1 : 0;
  1266. data |= MII_WRITE;
  1267. data |= (readb (ioaddr) & 0xf8) | MII_WRITE;
  1268. writeb (data, ioaddr);
  1269. mii_delay ();
  1270. writeb (data | MII_CLK, ioaddr);
  1271. mii_delay ();
  1272. }
  1273. static int
  1274. mii_getbit (struct net_device *dev)
  1275. {
  1276. long ioaddr = dev->base_addr + PhyCtrl;
  1277. u8 data;
  1278. data = (readb (ioaddr) & 0xf8) | MII_READ;
  1279. writeb (data, ioaddr);
  1280. mii_delay ();
  1281. writeb (data | MII_CLK, ioaddr);
  1282. mii_delay ();
  1283. return ((readb (ioaddr) >> 1) & 1);
  1284. }
  1285. static void
  1286. mii_send_bits (struct net_device *dev, u32 data, int len)
  1287. {
  1288. int i;
  1289. for (i = len - 1; i >= 0; i--) {
  1290. mii_sendbit (dev, data & (1 << i));
  1291. }
  1292. }
  1293. static int
  1294. mii_read (struct net_device *dev, int phy_addr, int reg_num)
  1295. {
  1296. u32 cmd;
  1297. int i;
  1298. u32 retval = 0;
  1299. /* Preamble */
  1300. mii_send_bits (dev, 0xffffffff, 32);
  1301. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1302. /* ST,OP = 0110'b for read operation */
  1303. cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
  1304. mii_send_bits (dev, cmd, 14);
  1305. /* Turnaround */
  1306. if (mii_getbit (dev))
  1307. goto err_out;
  1308. /* Read data */
  1309. for (i = 0; i < 16; i++) {
  1310. retval |= mii_getbit (dev);
  1311. retval <<= 1;
  1312. }
  1313. /* End cycle */
  1314. mii_getbit (dev);
  1315. return (retval >> 1) & 0xffff;
  1316. err_out:
  1317. return 0;
  1318. }
  1319. static int
  1320. mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
  1321. {
  1322. u32 cmd;
  1323. /* Preamble */
  1324. mii_send_bits (dev, 0xffffffff, 32);
  1325. /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
  1326. /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
  1327. cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
  1328. mii_send_bits (dev, cmd, 32);
  1329. /* End cycle */
  1330. mii_getbit (dev);
  1331. return 0;
  1332. }
  1333. static int
  1334. mii_wait_link (struct net_device *dev, int wait)
  1335. {
  1336. BMSR_t bmsr;
  1337. int phy_addr;
  1338. struct netdev_private *np;
  1339. np = netdev_priv(dev);
  1340. phy_addr = np->phy_addr;
  1341. do {
  1342. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1343. if (bmsr.bits.link_status)
  1344. return 0;
  1345. mdelay (1);
  1346. } while (--wait > 0);
  1347. return -1;
  1348. }
  1349. static int
  1350. mii_get_media (struct net_device *dev)
  1351. {
  1352. ANAR_t negotiate;
  1353. BMSR_t bmsr;
  1354. BMCR_t bmcr;
  1355. MSCR_t mscr;
  1356. MSSR_t mssr;
  1357. int phy_addr;
  1358. struct netdev_private *np;
  1359. np = netdev_priv(dev);
  1360. phy_addr = np->phy_addr;
  1361. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1362. if (np->an_enable) {
  1363. if (!bmsr.bits.an_complete) {
  1364. /* Auto-Negotiation not completed */
  1365. return -1;
  1366. }
  1367. negotiate.image = mii_read (dev, phy_addr, MII_ANAR) &
  1368. mii_read (dev, phy_addr, MII_ANLPAR);
  1369. mscr.image = mii_read (dev, phy_addr, MII_MSCR);
  1370. mssr.image = mii_read (dev, phy_addr, MII_MSSR);
  1371. if (mscr.bits.media_1000BT_FD & mssr.bits.lp_1000BT_FD) {
  1372. np->speed = 1000;
  1373. np->full_duplex = 1;
  1374. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1375. } else if (mscr.bits.media_1000BT_HD & mssr.bits.lp_1000BT_HD) {
  1376. np->speed = 1000;
  1377. np->full_duplex = 0;
  1378. printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
  1379. } else if (negotiate.bits.media_100BX_FD) {
  1380. np->speed = 100;
  1381. np->full_duplex = 1;
  1382. printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
  1383. } else if (negotiate.bits.media_100BX_HD) {
  1384. np->speed = 100;
  1385. np->full_duplex = 0;
  1386. printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
  1387. } else if (negotiate.bits.media_10BT_FD) {
  1388. np->speed = 10;
  1389. np->full_duplex = 1;
  1390. printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
  1391. } else if (negotiate.bits.media_10BT_HD) {
  1392. np->speed = 10;
  1393. np->full_duplex = 0;
  1394. printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
  1395. }
  1396. if (negotiate.bits.pause) {
  1397. np->tx_flow &= 1;
  1398. np->rx_flow &= 1;
  1399. } else if (negotiate.bits.asymmetric) {
  1400. np->tx_flow = 0;
  1401. np->rx_flow &= 1;
  1402. }
  1403. /* else tx_flow, rx_flow = user select */
  1404. } else {
  1405. bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
  1406. if (bmcr.bits.speed100 == 1 && bmcr.bits.speed1000 == 0) {
  1407. printk (KERN_INFO "Operating at 100 Mbps, ");
  1408. } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 0) {
  1409. printk (KERN_INFO "Operating at 10 Mbps, ");
  1410. } else if (bmcr.bits.speed100 == 0 && bmcr.bits.speed1000 == 1) {
  1411. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1412. }
  1413. if (bmcr.bits.duplex_mode) {
  1414. printk ("Full duplex\n");
  1415. } else {
  1416. printk ("Half duplex\n");
  1417. }
  1418. }
  1419. if (np->tx_flow)
  1420. printk(KERN_INFO "Enable Tx Flow Control\n");
  1421. else
  1422. printk(KERN_INFO "Disable Tx Flow Control\n");
  1423. if (np->rx_flow)
  1424. printk(KERN_INFO "Enable Rx Flow Control\n");
  1425. else
  1426. printk(KERN_INFO "Disable Rx Flow Control\n");
  1427. return 0;
  1428. }
  1429. static int
  1430. mii_set_media (struct net_device *dev)
  1431. {
  1432. PHY_SCR_t pscr;
  1433. BMCR_t bmcr;
  1434. BMSR_t bmsr;
  1435. ANAR_t anar;
  1436. int phy_addr;
  1437. struct netdev_private *np;
  1438. np = netdev_priv(dev);
  1439. phy_addr = np->phy_addr;
  1440. /* Does user set speed? */
  1441. if (np->an_enable) {
  1442. /* Advertise capabilities */
  1443. bmsr.image = mii_read (dev, phy_addr, MII_BMSR);
  1444. anar.image = mii_read (dev, phy_addr, MII_ANAR);
  1445. anar.bits.media_100BX_FD = bmsr.bits.media_100BX_FD;
  1446. anar.bits.media_100BX_HD = bmsr.bits.media_100BX_HD;
  1447. anar.bits.media_100BT4 = bmsr.bits.media_100BT4;
  1448. anar.bits.media_10BT_FD = bmsr.bits.media_10BT_FD;
  1449. anar.bits.media_10BT_HD = bmsr.bits.media_10BT_HD;
  1450. anar.bits.pause = 1;
  1451. anar.bits.asymmetric = 1;
  1452. mii_write (dev, phy_addr, MII_ANAR, anar.image);
  1453. /* Enable Auto crossover */
  1454. pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
  1455. pscr.bits.mdi_crossover_mode = 3; /* 11'b */
  1456. mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
  1457. /* Soft reset PHY */
  1458. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1459. bmcr.image = 0;
  1460. bmcr.bits.an_enable = 1;
  1461. bmcr.bits.restart_an = 1;
  1462. bmcr.bits.reset = 1;
  1463. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1464. mdelay(1);
  1465. } else {
  1466. /* Force speed setting */
  1467. /* 1) Disable Auto crossover */
  1468. pscr.image = mii_read (dev, phy_addr, MII_PHY_SCR);
  1469. pscr.bits.mdi_crossover_mode = 0;
  1470. mii_write (dev, phy_addr, MII_PHY_SCR, pscr.image);
  1471. /* 2) PHY Reset */
  1472. bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
  1473. bmcr.bits.reset = 1;
  1474. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1475. /* 3) Power Down */
  1476. bmcr.image = 0x1940; /* must be 0x1940 */
  1477. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1478. mdelay (100); /* wait a certain time */
  1479. /* 4) Advertise nothing */
  1480. mii_write (dev, phy_addr, MII_ANAR, 0);
  1481. /* 5) Set media and Power Up */
  1482. bmcr.image = 0;
  1483. bmcr.bits.power_down = 1;
  1484. if (np->speed == 100) {
  1485. bmcr.bits.speed100 = 1;
  1486. bmcr.bits.speed1000 = 0;
  1487. printk (KERN_INFO "Manual 100 Mbps, ");
  1488. } else if (np->speed == 10) {
  1489. bmcr.bits.speed100 = 0;
  1490. bmcr.bits.speed1000 = 0;
  1491. printk (KERN_INFO "Manual 10 Mbps, ");
  1492. }
  1493. if (np->full_duplex) {
  1494. bmcr.bits.duplex_mode = 1;
  1495. printk ("Full duplex\n");
  1496. } else {
  1497. bmcr.bits.duplex_mode = 0;
  1498. printk ("Half duplex\n");
  1499. }
  1500. #if 0
  1501. /* Set 1000BaseT Master/Slave setting */
  1502. mscr.image = mii_read (dev, phy_addr, MII_MSCR);
  1503. mscr.bits.cfg_enable = 1;
  1504. mscr.bits.cfg_value = 0;
  1505. #endif
  1506. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1507. mdelay(10);
  1508. }
  1509. return 0;
  1510. }
  1511. static int
  1512. mii_get_media_pcs (struct net_device *dev)
  1513. {
  1514. ANAR_PCS_t negotiate;
  1515. BMSR_t bmsr;
  1516. BMCR_t bmcr;
  1517. int phy_addr;
  1518. struct netdev_private *np;
  1519. np = netdev_priv(dev);
  1520. phy_addr = np->phy_addr;
  1521. bmsr.image = mii_read (dev, phy_addr, PCS_BMSR);
  1522. if (np->an_enable) {
  1523. if (!bmsr.bits.an_complete) {
  1524. /* Auto-Negotiation not completed */
  1525. return -1;
  1526. }
  1527. negotiate.image = mii_read (dev, phy_addr, PCS_ANAR) &
  1528. mii_read (dev, phy_addr, PCS_ANLPAR);
  1529. np->speed = 1000;
  1530. if (negotiate.bits.full_duplex) {
  1531. printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
  1532. np->full_duplex = 1;
  1533. } else {
  1534. printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
  1535. np->full_duplex = 0;
  1536. }
  1537. if (negotiate.bits.pause) {
  1538. np->tx_flow &= 1;
  1539. np->rx_flow &= 1;
  1540. } else if (negotiate.bits.asymmetric) {
  1541. np->tx_flow = 0;
  1542. np->rx_flow &= 1;
  1543. }
  1544. /* else tx_flow, rx_flow = user select */
  1545. } else {
  1546. bmcr.image = mii_read (dev, phy_addr, PCS_BMCR);
  1547. printk (KERN_INFO "Operating at 1000 Mbps, ");
  1548. if (bmcr.bits.duplex_mode) {
  1549. printk ("Full duplex\n");
  1550. } else {
  1551. printk ("Half duplex\n");
  1552. }
  1553. }
  1554. if (np->tx_flow)
  1555. printk(KERN_INFO "Enable Tx Flow Control\n");
  1556. else
  1557. printk(KERN_INFO "Disable Tx Flow Control\n");
  1558. if (np->rx_flow)
  1559. printk(KERN_INFO "Enable Rx Flow Control\n");
  1560. else
  1561. printk(KERN_INFO "Disable Rx Flow Control\n");
  1562. return 0;
  1563. }
  1564. static int
  1565. mii_set_media_pcs (struct net_device *dev)
  1566. {
  1567. BMCR_t bmcr;
  1568. ESR_t esr;
  1569. ANAR_PCS_t anar;
  1570. int phy_addr;
  1571. struct netdev_private *np;
  1572. np = netdev_priv(dev);
  1573. phy_addr = np->phy_addr;
  1574. /* Auto-Negotiation? */
  1575. if (np->an_enable) {
  1576. /* Advertise capabilities */
  1577. esr.image = mii_read (dev, phy_addr, PCS_ESR);
  1578. anar.image = mii_read (dev, phy_addr, MII_ANAR);
  1579. anar.bits.half_duplex =
  1580. esr.bits.media_1000BT_HD | esr.bits.media_1000BX_HD;
  1581. anar.bits.full_duplex =
  1582. esr.bits.media_1000BT_FD | esr.bits.media_1000BX_FD;
  1583. anar.bits.pause = 1;
  1584. anar.bits.asymmetric = 1;
  1585. mii_write (dev, phy_addr, MII_ANAR, anar.image);
  1586. /* Soft reset PHY */
  1587. mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
  1588. bmcr.image = 0;
  1589. bmcr.bits.an_enable = 1;
  1590. bmcr.bits.restart_an = 1;
  1591. bmcr.bits.reset = 1;
  1592. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1593. mdelay(1);
  1594. } else {
  1595. /* Force speed setting */
  1596. /* PHY Reset */
  1597. bmcr.image = 0;
  1598. bmcr.bits.reset = 1;
  1599. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1600. mdelay(10);
  1601. bmcr.image = 0;
  1602. bmcr.bits.an_enable = 0;
  1603. if (np->full_duplex) {
  1604. bmcr.bits.duplex_mode = 1;
  1605. printk (KERN_INFO "Manual full duplex\n");
  1606. } else {
  1607. bmcr.bits.duplex_mode = 0;
  1608. printk (KERN_INFO "Manual half duplex\n");
  1609. }
  1610. mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
  1611. mdelay(10);
  1612. /* Advertise nothing */
  1613. mii_write (dev, phy_addr, MII_ANAR, 0);
  1614. }
  1615. return 0;
  1616. }
  1617. static int
  1618. rio_close (struct net_device *dev)
  1619. {
  1620. long ioaddr = dev->base_addr;
  1621. struct netdev_private *np = netdev_priv(dev);
  1622. struct sk_buff *skb;
  1623. int i;
  1624. netif_stop_queue (dev);
  1625. /* Disable interrupts */
  1626. writew (0, ioaddr + IntEnable);
  1627. /* Stop Tx and Rx logics */
  1628. writel (TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl);
  1629. synchronize_irq (dev->irq);
  1630. free_irq (dev->irq, dev);
  1631. del_timer_sync (&np->timer);
  1632. /* Free all the skbuffs in the queue. */
  1633. for (i = 0; i < RX_RING_SIZE; i++) {
  1634. np->rx_ring[i].status = 0;
  1635. np->rx_ring[i].fraginfo = 0;
  1636. skb = np->rx_skbuff[i];
  1637. if (skb) {
  1638. pci_unmap_single(np->pdev,
  1639. np->rx_ring[i].fraginfo & 0xffffffffffff,
  1640. skb->len, PCI_DMA_FROMDEVICE);
  1641. dev_kfree_skb (skb);
  1642. np->rx_skbuff[i] = NULL;
  1643. }
  1644. }
  1645. for (i = 0; i < TX_RING_SIZE; i++) {
  1646. skb = np->tx_skbuff[i];
  1647. if (skb) {
  1648. pci_unmap_single(np->pdev,
  1649. np->tx_ring[i].fraginfo & 0xffffffffffff,
  1650. skb->len, PCI_DMA_TODEVICE);
  1651. dev_kfree_skb (skb);
  1652. np->tx_skbuff[i] = NULL;
  1653. }
  1654. }
  1655. return 0;
  1656. }
  1657. static void __devexit
  1658. rio_remove1 (struct pci_dev *pdev)
  1659. {
  1660. struct net_device *dev = pci_get_drvdata (pdev);
  1661. if (dev) {
  1662. struct netdev_private *np = netdev_priv(dev);
  1663. unregister_netdev (dev);
  1664. pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
  1665. np->rx_ring_dma);
  1666. pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
  1667. np->tx_ring_dma);
  1668. #ifdef MEM_MAPPING
  1669. iounmap ((char *) (dev->base_addr));
  1670. #endif
  1671. free_netdev (dev);
  1672. pci_release_regions (pdev);
  1673. pci_disable_device (pdev);
  1674. }
  1675. pci_set_drvdata (pdev, NULL);
  1676. }
  1677. static struct pci_driver rio_driver = {
  1678. .name = "dl2k",
  1679. .id_table = rio_pci_tbl,
  1680. .probe = rio_probe1,
  1681. .remove = __devexit_p(rio_remove1),
  1682. };
  1683. static int __init
  1684. rio_init (void)
  1685. {
  1686. return pci_module_init (&rio_driver);
  1687. }
  1688. static void __exit
  1689. rio_exit (void)
  1690. {
  1691. pci_unregister_driver (&rio_driver);
  1692. }
  1693. module_init (rio_init);
  1694. module_exit (rio_exit);
  1695. /*
  1696. Compile command:
  1697. gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
  1698. Read Documentation/networking/dl2k.txt for details.
  1699. */